GT3200

GT3200 (64-PIN TQFP PACKAGES) USB3250 (56-PIN QFN PACKAGE) USB2.0 PHY IC PRODUCT FEATURES USB-IF "Hi-Speed" certified to USB2.0 electrical specification Interface compliant with the UTMI specification (60MHz 8-bit unidirectional interface or 30MHz 16-bit bidirectional interface) Supports 480Mbps High Speed (HS) and 12Mbps Full Speed (FS) serial data transmission rates Integrated 45Ω and 1.5kΩ termination resistors reduce external component count Internal short circuit protection of DP and DM lines On-chip oscillator operates with low cost 12MHz crystal Robust and low power digital clock and data recovery circuit SYNC and EOP generation on transmit packets and detection on receive packets Datasheet NRZI encoding and decoding Bit stuffing and unstuffing with error detection Supports the USB suspend state, HS detection, HS Chirp, Reset and Resume Support for all test modes defined in the USB2.0 specification Draws 72mA (185mW) maximum current consumption in HS mode - ideal for bus powered functions On-die decoupling capacitance and isolation for immunity to digital switching noise Available in three 64-pin TQFP packages (GT3200) or a 56-pin QFN package (USB3250) Full industrial operating temperature range from -40oC to +85oC (ambient) SMSC GT3200, SMSC USB3250 DATASHEET Revision 1.5 (03-24-06) USB2.0 PHY IC Datasheet ORDER NUMBER(S): GT3200-JD FOR 64 PIN 10 X 10 X 1.4MM TQFP PACKAGE GT3200-JN FOR 64 PIN 7 X 7 X 1.4MM TQFP PACKAGE GT3200-JV FOR 64 PIN 7 X 7 X 1.4MM TQFP PACKAGE (GREEN, LEAD-FREE) USB3250-ABZJ FOR 56 PIN 8 X 8 X 0.85MM QFN PACKAGE (GREEN, LEAD-FREE) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 1.5 (03-24-06) DATASHEET 2 SMSC GT3200, SMSC USB3250 USB2.0 PHY IC Datasheet Table of Contents Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 4 Interface Signal Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chapter 5 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 6.2 Driver Characteristics of Full-Speed Drivers in High-Speed Capable Transceivers . . . . . . . . . . . . 18 High-speed Signaling Eye Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Chapter 7 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Data Recovery Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FS/HS RX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FS/HS TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 24 25 26 27 31 31 31 31 Chapter 8 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 Linestate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPMODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SE0 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suspend Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Detection Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Detection Handshake - FS Downstream Facing Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Detection Handshake - HS Downstream Facing Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Detection Handshake - Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assertion of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detection of Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS Device Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 33 33 33 34 34 35 36 38 40 42 43 43 45 Chapter 9 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SMSC GT3200, SMSC USB3250 DATASHEET 3 Revision 1.5 (03-24-06) USB2.0 PHY IC Datasheet List of Figures Figure 2.1 Figure 3.1 Figure 3.2 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 7.6 Figure 7.7 Figure 7.8 Figure 7.9 Figure 7.10 Figure 7.11 Figure 7.12 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Figure 8.9 Figure 8.10 Figure 9.1 Figure 9.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 64 pin GT3200 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 56 pin USB3250 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver . . . . . . . . 18 Full-Speed Driver VOL/IOL Characteristics for High-speed Capable Transceiver. . . . . . . . . 19 Eye Pattern Measurement Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Eye Pattern for Transmit Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . 21 Eye Pattern for Receive Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . . 22 Bidirectional 16-bit interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 FS CLK Relationship to Transmit Data and Control Signals (8-bit mode) . . . . . . . . . . . . . . . 25 FS CLK Relationship to Receive Data and Control Signals (8-bit mode) . . . . . . . . . . . . . . . 25 Transmit Timing for a Data Packet (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Transmit Timing for 16-bit Data, Even Byte Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Transmit Timing for 16-bit Data, Odd Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Receive Timing for Data with Unstuffed Bits (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Receive Timing for 16-bit Data, Even Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Receive Timing for 16-bit Data, Odd Byte Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Receive Timing for Data (with CRC-16 in 8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Receive Timing for Setup Packet (8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Receive Timing for Data Packet with CRC-16 (8-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . 31 Reset Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Suspend Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 HS Detection Handshake Timing Behavior (FS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chirp K-J-K-J-K-J Sequence Detection State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 HS Detection Handshake Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 HS Detection Handshake Timing Behavior from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Resume Timing Behavior (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Application Diagram for 64-pin TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Application Diagram for 56-pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 GT3200 TQFP Package Outline and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 USB3250 QFN Package Outline and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Revision 1.5 (03-24-06) DATASHEET 4 SMSC GT3200, SMSC USB3250 USB2.0 PHY IC Datasheet List of Tables Table 4.1 System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.2 Data Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.3 USB I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.4 Biasing and Clock Oscillator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.5 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.1 Electrical Characteristics: Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.2 DC Electrical Characteristics: Logic Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.4 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.5 Dynamic Characteristics: Digital UTMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.6 Eye Pattern for Transmit Waveform and Eye Pattern Definition . . . . . . . . . . . . . . . . . . . . . . . Table 6.7 Eye Pattern for Receive Waveform and Eye Pattern Definition. . . . . . . . . . . . . . . . . . . . . . . . Table 8.1 Linestate States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.2 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.3 USB2.0 Test Mode to Macrocell Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.4 Reset Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.5 Suspend Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.6 HS Detection Handshake Timing Values (FS Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.7 Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.8 HS Detection Handshake Timing Values from Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.9 Resume Timing Values (HS Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8.10 Attach and Reset Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 11 12 12 12 13 13 13 14 15 15 16 17 21 22 32 33 33 34 35 37 39 41 42 44 SMSC GT3200, SMSC USB3250 DATASHEET 5 Revision 1.5 (03-24-06) USB2.0 PHY IC Datasheet Chapter 1 General Description The GT3200 and USB3250 provide the Physical Layer (PHY) interface to a USB2.0 Device Controller. The IC is available in a 64 pin lead TQFP (GT3200) or a 56 pin QFN (USB3250). 1.1 Applications The Universal Serial Bus (USB) is the preferred interface to connect high-speed PC peripherals. Scanners Printers External Storage and System Backup Still and Video Cameras PDAs CD-RW Gaming Devices 1.2 Product Description The GT3200 and USB3250 are USB2.0 physical layer transceiver (PHY) integrated circuits. SMSC's proprietary technology results in low power dissipation, which is ideal for building a bus powered USB2.0 peripheral. The PHY can be configured for either an 8-bit unidirectional or a 16-bit bidirectional parallel interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1 legacy protocol at 12Mbps. All required termination for the USB2.0 Transceiver is internal. Internal 5.25V short circuit protection of DP and DM lines is provided for USB compliance. While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding. Revision 1.5 (03-24-06) DATASHEET 6 SMSC GT3200, SMSC USB3250 USB2.0 PHY IC Datasheet Chapter 2 Functional Block Diagram VDD3.3 PWR CONTROL TX LOGIC TX State Machine DATABUS16_8 RESET SUSPENDN XCVRSELECT TERMSELECT OPMODE[1:0] VDD1.8 Parallel to Serial Conversion Bit Stuff NRZI Encode XO PLL and XTAL OSC HS_DRIVE_ENABLE HS_CS_ENABLE HS TX XI System Clocking TX RPU_EN 1.5kΩ VPO VMO OEB HS_DATA FS TX DP LINESTATE[1:0] CLKOUT RX DM UTMI Interface RX LOGIC RX State Machine Serial to Parallel Conversion Bit Unstuff VP VM FS SE+ DATA[15:0] * TXVALID TXREADY VALIDH FS SE- Clock Recovery Unit Clock and Data Recovery Elasticity Buffer FS RX MUX RXVALID RXACTIVE RXERROR NRZI Decode HS RX BIASING Bandgap Voltage Reference Current Reference HS SQ Figure 2.1 Block Diagram Note: See Section 7.1, "Modes of Operation," on page 23 for a description of the digital interface. SMSC GT3200, SMSC USB3250 RBIAS DATASHEET 7 Revision 1.5 (03-24-06) USB2.0 PHY IC Datasheet Chapter 3 Pinout DATABUS16_8 RXACTIVE RXERROR TXREADY RXVALID TXVALID 51 CLKOUT DATA[0] 50 VALIDH VDD1.8 64 63 62 61 60 59 58 57 56 55 54 53 52 49 VDD3.3 VSS VSS VSS VSS VSS NC VSSA NC DM DP VDDA3.3 VSSA RBIAS VDDA3.3 VSSA XI XO VDDA1.8 NC SUSPENDN VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 29 30 31 25 26 27 21 22 23 17 18 19 20 24 28 32 48 47 46 45 VSS DATA[1] DATA[2] DATA[3] DATA[4] VDD1.8 DATA[5] DATA[6] DATA[7] DATA[8] VSS DATA[9] DATA[10] DATA[11] DATA[12] VSS USB2.0 GT3200 PHY IC 44 43 42 41 40 39 38 37 36 35 34 33 OPMODE[1] OPMODE[0] DATA[15] DATA[14] LINESTATE[1] LINESTATE[0] DATA[13] VDD3.3 XCVRSELECT Figure 3.1 64 pin GT3200 Pinout Revision 1.5 (03-24-06) TERMSELECT DATASHEET 8 VDD3.3 VDD1.8 VDD1.8 VSS VSS RESET SMSC GT3200, SMSC USB3250 USB2.0 PHY IC Datasheet DATABUS16_8 RXACTIVE RXERROR TXREADY RXVALID CLKOUT TXVALID 45 DATA[0] 44 VALIDH VDD1.8 VSS VSS 48 VSS 47 46 56 55 54 53 52 51 50 49 43 VDD3.3 VSSA DM DP VDDA3.3 VSSA RBIAS VDDA3.3 VSSA VSSA XI XO VDDA1.8 SUSPENDN VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 DATA[1] DATA[2] DATA[3] DATA[4] VDD1.8 DATA[5] DATA[6] DATA[7] DATA[8] VSS DATA[9] DATA[10] DATA[11] DATA[12] USB2.0 USB3250 PHY IC 39 38 37 36 35 34 33 32 31 30 29 OPMODE[1] OPMODE[0] DATA[15] DATA[14] LINESTATE[1] LINESTATE[0] XCVRSELECT TERMSELECT DATA[13] RESET VDD3.3 VDD1.8 Figure 3.2 56 pin USB3250 Pinout SMSC GT3200, SMSC USB3250 DATASHEET 9 VDD1.8 VDD3.3 Revision 1.5 (03-24-06) USB2.0 PHY IC Datasheet Chapter 4 Interface Signal Definition Table 4.1 System Interface Signals ACTIVE LEVEL High NAME RESET DIRECTION Input DESCRIPTION Reset. Reset all state machines. After coming out of reset, must wait 5 rising edges of clock before asserting TXValid for transmit. Assertion of Reset: May be asynchronous to CLKOUT De-assertion of Reset: Must be synchronous to CLKOUT Transceiver Select. This signal selects between the FS and HS transceivers: 0: HS transceiver enabled 1: FS transceiver enabled. Termination Select. This signal selects between the FS and HS terminations: 0: HS termination enabled 1: FS termination enabled Suspend. Places the transceiver in a mode that draws minimal power from supplies. Shuts down all blocks not necessary for Suspend/Resume operation. While suspended, TERMSELECT must always be in FS mode to ensure that the 1.5k Ω pull-up on DP remains powered. 0: Transceiver circuitry drawing suspend current 1: Transceiver circuitry drawing normal current System Clock. This output is used for clocking receive and transmit parallel data at 60MHz (8-bit mode) or 30MHz (16-bit mode). When in 8-bit mode, this specification refers to CLKOUT as CLK60. When in 16-bit mode, CLKOUT is referred to as CLK30. Operational Mode. These signals select between the various operational modes: [1] [0] Description 0 0 0: Normal Operation 0 1 1: Non-driving (all terminations removed) 1 0 2: Disable bit stuffing and NRZI encoding 1 1 3: Reserved Line State. These signals reflect the current state of the USB data bus in FS mode, with [0] reflecting the state of DP and [1] reflecting the state of DM. When the device is suspended or resuming from a suspended state, the signals are combinatorial. Otherwise, the signals are synchronized to CLKOUT. [1] [0] Description 0 0 0: SE0 0 1 1: J State 1 0 2: K State 1 1 3: SE1 Databus Select. Selects between 8-bit and 16-bit data transfers. 0: 8-bit data path enabled. VALIDH is undefined. CLKOUT = 60MHz. 1: 16-bit data path enabled. CLKOUT = 30MHz. XCVRSELECT Input N/A TERMSELECT Input N/A SUSPENDN Input Low CLKOUT Output Rising Edge OPMODE[1:0] Input N/A LINESTATE[1:0] Output N/A DATABUS16_8 Input N/A Revision 1.5 (03-24-06) DATASHEET 10 SMSC GT3200, SMSC USB3250 USB2.0 PHY IC Datasheet Table 4.2 Data Interface Signals ACTIVE LEVEL N/A NAME DATA[15:0] DIRECTION Bidir DESCRIPTION DATA BUS. 16-BIT BIDIRECTIONAL MODE. TXVALID 0 0 RXVALID 0 1 VALIDH X 0 DATA[15:0] Not used DATA[7:0] output is valid for receive VALIDH is an output DATA[15:0] output is valid for receive VALIDH is an output DATA[7:0] input is valid for transmit VALIDH is an input DATA[15:0] input is valid for transmit VALIDH is an input 0 1 1 1 X 0 1 X 1 DATA BUS. 8-BIT UNIDIRECTIONAL MODE. TXVALID 0 0 1 TXVALID Input High RXVALID 0 1 X DATA[15:0] Not used DATA[15:8] output is valid for receive DATA[7:0] input is valid for transmit Transmit Valid. Indicates that the TXDATA bus is valid for transmit. The assertion of TXVALID initiates the transmission of SYNC on the USB bus. The negation of TXVALID initiates EOP on the USB. Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT) must not be changed on the de-assertion or assertion of TXVALID. The PHY must be in a quiescent state when these inputs are changed. TXREADY Output High Transmit Data Ready. If TXVALID is asserted, the SIE must always have data available for clocking into the TX Holding Register on the rising edge of CLKOUT. TXREADY is an acknowledgement to the SIE that the transceiver has clocked the data from the bus and is ready for the next transfer on the bus. If TXVALID is negated, TXREADY can be ignored by the SIE. Transmit/Receive High Data Bit Valid (used in 16-bit mode only). When TXVALID = 1, the 16-bit data bus direction is changed to inputs, and VALIDH is an input. If VALIDH is asserted, DATA[15:0] is valid for transmission. If deasserted, only DATA[7:0] is valid for transmission. The DATA bus is driven by the SIE. When TXVALID = 0 and RXVALID = 1, the 16-bit data bus direction is changed to outputs, and VALIDH is an output. If VALIDH is asserted, the DATA[15:0] outputs are valid for receive. If deasseted, only DATA[7:0] is valid for receive. The DATA bus is read by the SIE. VALIDH Bidir N/A RXVALID Output High Receive Data Valid. Indicates that the RXDATA bus has received valid data. The Receive Data Holding Register is full and ready to be unloaded. The SIE is expected to latch the RXDATA bus on the rising edge of CLKOUT. Receive Active. Indicates that the receive state machine has detected Start of Packet and is active. Receive Error. 0: Indicates no error. 1: Indicates a receive error has been detected. This output is clocked with the same timing as the RXDATA lines and can occur at anytime during a transfer. RXACTIVE RXERROR Output Output High High SMSC GT3200, SMSC USB3250 DATASHEET 11 Revision 1.5 (03-24-06) USB2.0 PHY IC Datasheet Table 4.3 USB I/O Signals ACTIVE LEVEL N/A N/A USB Positive Data Pin. USB Negative Data Pin. NAME DP DM DIRECTION I/O I/O DESCRIPTION Table 4.4 Biasing and Clock Oscillator Signals ACTIVE LEVEL N/A NAME RBIAS DIRECTION Input DESCRIPTION External 1% bias resistor. Requires a 12KΩ resistor to ground. Used for setting HS transmit current level and on-chip termination impedance. External crystal. 12MHz crystal connected from XI to XO. XI/XO Input N/A Table 4.5 Power and Ground Signals ACTIVE LEVEL N/A N/A N/A N/A N/A N/A NAME VDD3.3 VDD1.8 VSS VDDA3.3 VDDA1.8 VSSA DIRECTION N/A N/A N/A N/A N/A N/A Note 4.1 DESCRIPTION 3.3V Digital Supply. Powers digital pads. See Note 4.1 1.8V Digital Supply. Powers digital core. Digital Ground. See Note 4.2 3.3V Analog Supply. Powers analog I/O and 3.3V analog circuitry. 1.8V Analog Supply. Powers 1.8V analog circuitry. See Note 4.1 Analog Ground. See Note 4.2 A Ferrite Bead (with DC resistance