LAN9118-MD

LAN9118 High Performance Single-Chip 10/100 NonPCI Ethernet Controller PRODUCT FEATURES Highlights ■ ■ Datasheet Reduced Power Modes — — — — — ■ ■ ■ ■ ■ ■ Optimized for the highest data-rate applications such as high-definition video and multi-media applications Efficient architecture with low CPU overhead; Easily interfaces to most 32-bit and 16-bit embedded CPU’s Integrated PHY Supports audio & video streaming over Ethernet: multiple high-definition (HD) MPEG2 streams Pin compatible with other members of LAN9118 family (LAN9117, LAN9116 and LAN9115) Numerous power management modes Wake on LAN* Magic packet wakeup* Wakeup indicator event signal Link Status Change Fully compliant with IEEE 802.3/802.3u standards Integrated Ethernet MAC and PHY 10BASE-T and 100BASE-TX support Full- and Half-duplex support Full-duplex flow control Backpressure for half-duplex flow control Preamble generation and removal Automatic 32-bit CRC generation and checking Automatic payload padding and pad removal Loop-back modes One 48-bit perfect address 64 hash-filtered multicast addresses Pass all multicast Promiscuous mode Inverse filtering Pass all incoming with status report Disable reception of broadcast packets Single chip Ethernet controller — — — — — — — — — — Target Applications ■ ■ ■ ■ ■ ■ Video distribution systems, multi-room PVR High-end Cable, satellite, and IP set-top boxes Digital video recorders High definition televisions Digital media clients/servers Home gateways ■ Flexible address filtering modes — — — — — — — Key Benefits ■ ■ Integrated Ethernet PHY — Auto-negotiation — Automatic polarity detection and correction Supports highest performance applications — Highest performing non-PCI Ethernet controller in the market — 32-bit interface with fast bus cycle times — Burst-mode read support ■ High-Performance host bus interface — Simple, SRAM-like interface — 32/16-bit data bus — Large, 16Kbyte FIFO memory that can be allocated to RX or TX functions — One configurable host interrupt ■ Eliminates dropped packets — Internal buffer memory can store over 200 packets — Supports automatic or host-triggered PAUSE and backpressure flow control ■ Miscellaneous features — Low profile 100-pin TQFP package; green, lead free package also availaible — Integral 1.8V regulator — General Purpose Timer — Support for optional EEPROM — Support for 3 status LEDs multiplexed with Programmable GPIO signals ■ Minimizes CPU overhead — Supports Slave-DMA — Interrupt Pin with Programmable Hold-off timer ■ Reduces system cost and increases design flexibility — SRAM-like interface easily interfaces to most embedded CPU’s or SoC’s — Low-cost, low--pin count non-PCI interface for embedded designs ■ ■ 3.3V Power Supply with 5V tolerant I/O 0 to 70°C * Third-party brands and names are the property of their respective owners. SMSC LAN9118 DATASHEET Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet ORDER NUMBER(S): LAN9118-MD FOR 100 PIN, TQFP PACKAGE LAN9118-MT FOR 100 PIN, TQFP PACKAGE (GREEN, LEAD-FREE) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © SMSC 2005. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 1.1 (05-17-05) DATASHEET 2 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table of Contents Chapter 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 11 11 11 12 12 12 12 12 12 12 Internal Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100 Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/100 Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive and Transmit FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Bus Interface (SRAM Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 2 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Chapter 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 3.2 10/100 Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Full-Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Half-Duplex Flow Control (Backpressure) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Virtual Local Area Network (VLAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Filtering Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filtering Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Perfect Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Hash Only Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-up Frame Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Magic Packet Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-bit vs. 16-bit Host Bus Width Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 16-bit Bus Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.2 16-bit Bus Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Big and Little Endian Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Timer (GP Timer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.1 MAC Address Auto-Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9.2 EEPROM Host Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.3 Internal PHY Power-Down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.2 Hardware Reset Input (nRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.3 Resume Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.4 Soft Reset (SRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11.5 PHY Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX Data Path Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.1 TX Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.2 TX Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.3 TX Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.4 TX Status Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.5 Calculating Actual TX Data FIFO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 21 22 22 22 22 25 25 25 25 26 28 29 29 29 29 30 30 30 31 37 37 37 39 40 41 41 41 41 41 42 44 44 46 47 48 SMSC LAN9118 DATASHEET Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.13 3.12.6 Transmit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.7 TX Data FIFO Underrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.8 Transmitter Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12.9 Stopping and Starting the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX Data Path Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.1 RX Slave PIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.2 RX Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.3 RX Status Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.4 Stopping and Starting the Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13.5 Receiver Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 51 51 51 51 52 54 55 56 56 Chapter 4 Internal Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.1 4.2 Top Level Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Base-TX Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 4B/5B Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Scrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 NRZI and MLT3 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 100M Transmit Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 100M Phase Lock Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Base-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 100M Receive Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery . . . . . . . . . . . . . 4.3.3 NRZI and MLT-3 Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 Descrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 5B/4B Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Base-T Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 10M Transmit Data across the internal MII bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Manchester Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 10M Transmit Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Base-T Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 10M Receive Input and Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 Manchester Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3 Jabber Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1 Re-starting Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.2 Disabling Auto-negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.3 Half vs. Full-Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 57 57 59 59 59 59 60 60 60 60 61 61 61 61 61 61 62 62 62 62 62 62 64 64 64 64 4.3 4.4 4.5 4.6 4.7 Chapter 5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.1 5.2 5.3 Register Nomenclature and Access Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX and TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 RX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 ID_REV—Chip ID and Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 IRQ_CFG—Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 INT_STS—Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 INT_EN—Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 BYTE_TEST—Byte Order Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.6 FIFO_INT—FIFO Level Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.7 RX_CFG—Receive Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.8 TX_CFG—Transmit Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.9 HW_CFG—Hardware Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 66 66 67 67 68 69 70 71 72 73 73 74 75 Revision 1.1 (05-17-05) DATASHEET 4 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4 5.5 5.3.10 RX_DP_CTRL—Receive Datapath Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.11 RX_FIFO_INF—Receive FIFO Information Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.12 TX_FIFO_INF—Transmit FIFO Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.13 PMT_CTRL— Power Management Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.14 GPIO_CFG—General Purpose IO Configuration Register . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.15 GPT_CFG-General Purpose Timer Configuration Register . . . . . . . . . . . . . . . . . . . . . . 83 5.3.16 GPT_CNT-General Purpose Timer Current Count Register . . . . . . . . . . . . . . . . . . . . . . 84 5.3.17 ENDIAN—Endian Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3.18 FREE_RUN—Free-Run 25MHz Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.19 RX_DROP– Receiver Dropped Frames Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.3.20 MAC_CSR_CMD – MAC CSR Synchronizer Command Register . . . . . . . . . . . . . . . . . 86 5.3.21 MAC_CSR_DATA – MAC CSR Synchronizer Data Register . . . . . . . . . . . . . . . . . . . . . 86 5.3.22 AFC_CFG – Automatic Flow Control Configuration Register . . . . . . . . . . . . . . . . . . . . . 87 5.3.23 E2P_CMD – EEPROM Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.24 E2P_DATA – EEPROM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 MAC Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.4.1 MAC_CR—MAC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.4.2 ADDRH—MAC Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.4.3 ADDRL—MAC Address Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.4.4 HASHH—Multicast Hash Table High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.4.5 HASHL—Multicast Hash Table Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.4.6 MII_ACC—MII Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.4.7 MII_DATA—MII Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.4.8 FLOW—Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.4.9 VLAN1—VLAN1 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.4.10 VLAN2—VLAN2 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.4.11 WUFF—Wake-up Frame Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.4.12 WUCSR—Wake-up Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.5.1 Basic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.5.2 Basic Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.5.3 PHY Identifier 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.5.4 PHY Identifier 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.5.5 Auto-negotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.5.6 Auto-negotiation Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.5.7 Auto-negotiation Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.5.8 Mode Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.5.9 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.5.10 Special Control/Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.5.11 Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.5.13 PHY Special Control/Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Special Restrictions on Back-to-Back Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIO Burst Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX Data FIFO Direct PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RX Data FIFO Direct PIO Burst Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TX Data FIFO Direct PIO Writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 110 111 112 113 114 115 117 118 119 119 SMSC LAN9118 DATASHEET 5 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 7 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.1 7.2 7.3 7.4 7.5 Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption Device Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption Device and System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 121 122 123 124 Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Revision 1.1 (05-17-05) DATASHEET 6 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet List of Figures Figure 1.1 Figure 1.2 Figure 2.1 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7 Figure 3.8 Figure 3.9 Figure 3.10 Figure 3.11 Figure 3.12 Figure 3.13 Figure 3.14 Figure 3.15 Figure 3.16 Figure 3.17 Figure 3.18 Figure 4.1 Figure 4.2 Figure 5.1 Figure 5.2 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Figure 8.1 System Block Diagram Utilizing the SMSC LAN9118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VLAN Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VLAN Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 EEPROM Access Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 EEPROM ERASE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 EEPROM ERAL Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 EEPROM EWDS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 EEPROM EWEN Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 EEPROM READ Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 EEPROM WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 EEPROM WRAL Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PME and PME_INT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Simplified Host TX Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TX Buffer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 TX Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 TX Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Host Receive Routine Using Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Host Receive Routine with Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 RX Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 100Base-TX Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 LAN9118 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Example ADDRL, ADDRH and EEPROM Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 LAN9118 PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 LAN9118 PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 RX Data FIFO Direct PIO Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 RX Data FIFO Direct PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 TX Data FIFO Direct PIO Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 100 Pin TQFP Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SMSC LAN9118 DATASHEET 7 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet List of Tables Table 2.1 Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2.2 Default Ethernet Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2.3 LAN Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2.4 Serial EEPROM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 2.5 System and Power Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 2.6 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 3.1 Address Filtering Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 3.2 Wake-Up Frame Filter Register Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 3.3 Filter i Byte Mask Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 3.4 Filter i Command Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 3.5 Filter i Offset Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 3.6 Filter i CRC-16 Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 3.7 Byte Lane Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 3.8 Required EECLK Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 3.9 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 3.10 PHY Reset Sources and Effected Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 3.11 TX Command 'A' Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 3.12 TX Command 'B' Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 3.13 TX DATA Start Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 4.1 4B/5B Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 5.1 LAN9118 Direct Address Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 5.2 RX Alignment Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 5.3 Valid TX/RX FIFO Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 5.4 EEPROM Enable Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 5.5 Backpressure Duration Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 5.6 LAN9118 MAC CSR Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 5.8 LAN9118 PHY Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 5.9 MODE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 6.1 Read After Write Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 6.2 Read After Read Timing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 6.3 PIO Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 6.4 PIO Burst Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 6.5 RX Data FIFO Direct PIO Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 6.7 PIO Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 6.8 TX Data FIFO Direct PIO Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 6.9 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 6.10 EEPROM Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 7.1 Power Consumption Device Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 7.2 Power Consumption Device and System Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 7.3 I/O Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 7.4 100BASE-TX Tranceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 7.5 10BASE-T Tranceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 7.6 LAN9118 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 7.7 LAN9118 Recommended Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 8.1 100 Pin TQFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Revision 1.1 (05-17-05) DATASHEET 8 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 1 General Description The LAN9118 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9118 has been specifically architected to provide the highest performance possible for any given architecture. The LAN9118 is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant. The LAN9118 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit and 32-bit microprocessors and microcontrollers. The LAN9118 includes large transmit and receive data FIFOs with a high-speed host bus interface to accommodate high bandwidth, high latency applications. In addition, the LAN9118 memory buffer architecture allows the most efficient use of memory resources by optimizing packet granularity. Applications The LAN9118 is well suited for many high-performance embedded applications, including: ■ ■ ■ ■ ■ ■ ■ High-end cable, satellite and IP set-top boxes Video distribution systems Multi-room PVR (Personal Video Recorder) Digital video recorders High-definition televisions Digital media clients/servers Home gateways The LAN9118 also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the LAN9118 can automatically generate flow control packets to the remote node, or assert back-pressure on the remote node by generating network collisions. The LAN9118 supports numerous power management and wakeup features. The LAN9118 can be placed in a reduced power mode and can be programmed to issue an external wake signal via several methods, including “Magic Packet”, “Wake on LAN” and “Link Status Change”. This signal is ideal for triggering system power-up using remote Ethernet wakeup events. The device can be removed from the low power state via a host processor command. SMSC LAN9118 DATASHEET 9 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet System Memory System Memory System Peripherals Microprocessor/ Microcontroller Magnetics System Bus Ethernet LAN9118 LEDS/GPIO 25MHz XTAL EEPROM (Optional) Figure 1.1 System Block Diagram Utilizing the SMSC LAN9118 The SMSC LAN9118 integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller into Ethernet packets. The LAN9118 Ethernet MAC/PHY controller is designed and optimized to function in an embedded environment. All communication is performed with programmed I/O transactions using the simple SRAM-like host interface bus. The diagram shown above, describes a typical system configuration of the LAN9118 in a typical embedded environment. The LAN9118 is a general purpose, platform independent, Ethernet controller. The LAN9118 consists of four major functional blocks. The four blocks are: ■ ■ ■ ■ 10/100 Ethernet PHY 10/100 Ethernet MAC RX/TX FIFOs Host Bus Interface (HBI) Revision 1.1 (05-17-05) DATASHEET 10 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 1.1 Internal Block Overview This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal Block Diagram". 25MHz +3.3V EEPROM (Optional) PME Wakup Indicator Power Management 3.3V to 1.8V Regulator PLL EEPROM Controller Host Bus Interface (HBI) 2kB to 14kB Configurable TX FIFO TX Status FIFO SRAM I/F PIO Controller RX Status FIFO IRQ FIFO_SEL Interrupt Controller GP Timer 10/100 Ethernet MAC MIL - RX Elastic Buffer - 128 bytes MIL - TX Elastic Buffer - 2K bytes 10/100 Ethernet PHY LAN 2kB to 14kB Configurable RX FIFO Figure 1.2 Internal Block Diagram 1.2 10/100 Ethernet PHY The LAN9118 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in either full or half duplex configurations. The PHY block includes auto-negotiation. Minimal external components are required for the utilization of the Integrated PHY. 1.3 10/100 Ethernet MAC The transmit and receive data paths are separate within the MAC allowing the highest performance especially in full duplex mode. The data paths connect to the PIO interface Function via separate busses to increase performance. Payload data as well as transmit and receive status is passed on these busses. A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is accessible from the host through the PIO interface function. On the backend, the MAC interfaces with the internal 10/100 PHY through a the MII (Media Independent Interface) port internal to the LAN9118. The MAC CSR's also provides a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus. The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly accessible from the host interface. The differentiation between the TX/RX FIFO memory buffers and the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working SMSC LAN9118 DATASHEET 11 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first to the RX FIFOs for the host to access the data. 1.4 Receive and Transmit FIFOs The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between the host interface and the MAC through which all transmitted and received data and status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks thus reducing or minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data paths. In addition, the RX and TX FIFOs are configurable in size, allowing increased flexibility. 1.5 Interrupt Controller The LAN9118 supports a single programmable interrupt. The programmable nature of this interrupt allows the user the ability to optimize performance dependent upon the application requirement. Both the polarity and buffer type of the interrupt pin are configurable for the external interrupt processing. The interrupt line can be configured as an open-drain output to facilitate the sharing of interrupts with other devices. In addition, a programmable interrupt de-assertion interval is provided. 1.6 GPIO Interface A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the LAN9118. It is accessible through the host bus interface via the CSRs. The GPIO signals can function as inputs, push-pull outputs and open drain outputs. The GPIO’s (GPO’s are not configurable) can also be configured to trigger interrupts with programmable polarity. 1.7 Serial EEPROM Interface A serial EEPROM interface is included in the LAN9118. The serial EEPROM is optional and can be programmed with the LAN9118 MAC address. The LAN9118 can optionally load the MAC address automatically after power-on. 1.8 Power Management Controls The LAN9118 supports comprehensive array of power management modes to allow use in power sensitive applications. Wake on LAN, Link Status Change and Magic Packet detection are supported by the LAN9118. An external PME (Power Management Event) interrupt is provided to indicate detection of a wakeup event. 1.9 General Purpose Timer The general-purpose timer has no dedicated function within the LAN9118 and may be programmed to issue a timed interrupt. 1.10 Host Bus Interface (SRAM Interface) The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for the LAN9118 Control and Status Registers (CSR’s). The host bus interface is the primary bus for connection to the embedded host system. This interface models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are supported. Revision 1.1 (05-17-05) DATASHEET 12 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet The LAN9118 host bus interface supports 32-bit and 16-bit bus transfers; internally, all data paths are 32-bits wide. The LAN9118 can be interfaced to either Big-Endian or Little-Endian processors in either 32-bit or 16-bit external bus width modes of operation. The host bus data Interface is responsible for host address decoding and data bus steering. The host bus interface handles the 16 to 32-bit conversion when the LAN9118 is configured with a 16-bit host interface. Additionally, when Big Endian mode is selected, the data path to the internal controller registers will be reorganized accordingly. SMSC LAN9118 DATASHEET 13 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 2 Pin Description and Configuration GPIO2/nLED3** GPIO1/nLED2** GPIO0/nLED1** 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 FIFO_SEL nRESET EXRES1 GND_IO VDD_IO VDD_A VDD_A VDD_A VSS_A VSS_A VSS_A VSS_A TPO+ TPO- NC*1 NC*2 nWR TPI+ nRD nCS TPI- NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 VDD_IO VDD_IO VDD_IO GND_IO GND_IO GND_IO **Denotes a m ultifunction pin *1 This NC pin can also be tied to VDD_A for backw ard com patibility *2 This NC pin can also be tied to VSS_A for backw ard compatibility Figure 2.1 Pin Configuration Revision 1.1 (05-17-05) DATASHEET 14 GND_IO VDD_IO D10 50 GND_CORE VREG VDD_CORE VSS_PLL XTAL2 XTAL1 VDD_PLL VDD_REF ATEST RBIAS VSS_REF A7 A6 A5 A4 A3 A2 A1 GND_IO VDD_IO D31 D30 D29 D28 D27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SMSC LAN9118 100 PIN TQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC SPEED_SEL NC IRQ NC PM E EECLK** EECS EEDIO** GND_CORE VDD_CORE D0 D1 D2 VDD_IO GND_IO D3 D4 D5 D6 VDD_IO GND_IO D7 D8 D9 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.1 Host Bus Interface Signals PIN NO. 21-26,2933,36-40 NAME Host Data High SYMBOL D[31:16] BUFFER TYPE I/O8 (PD) # PINS 16 DESCRIPTION Bi-directional data port. Supports Big/Little Endian Byte ordering. Note that Pull-down’s are disabled in 32 bit mode. Bi-directional data port. Supports Big/Little Endian Byte ordering. 7-bit Address Port. Used to select Internal CSR’s and TX and RX FIFOs. Active low strobe to indicate a read cycle. Active low strobe to indicate a write cycle. This signal, qualified with nCS, is also used to wakeup the LAN9118 when it is in a reduced power state. Active low signal used to qualify read and write operations. This signal qualified with nWR is also used to wakeup the LAN9118 when it is in a reduced power state. Programmable Interrupt request. Programmable polarity, source and buffer types. No Connect This signal functions as a configuration input on power-up and is used to select the default Ethernet settings. Upon deassertion of reset, the value of the input is latched. This signal functions as shown in Table 2.2, "Default Ethernet Settings", below. When driven high all accesses to the LAN9118 are to the RX or TX Data FIFOs. In this mode, the A[7:3] upper address inputs are ignored. 43-46,4953,56-59,6264 12-18 92 93 Host Data Low D[15:0] I/O8 16 Host Address Read Strobe Write Strobe A[7:1] nRD nWR IS IS IS 7 1 1 94 Chip Select nCS IS 1 72 Interrupt Request Reserved 10/100 Selector IRQ O8/OD8 1 71,73,75,84, 90,91 74 Reserved SPEED_SEL I (PU) 5 1 76 FIFO Select FIFO_SEL IS 1 Table 2.2 Default Ethernet Settings DEFAULT ETHERNET SETTINGS SPEED_SEL 0 1 SPEED 10MBPS 100MBPS DUPLEX HALF-DUPLEX HALF-DUPLEX AUTO NEG. DISABLED ENABLED SMSC LAN9118 DATASHEET 15 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.3 LAN Interface Signals PIN NO. 79 78 83 82 87 NAME TXP TXN RXP RXN PHY External Bias Resistor SYMBOL TPO+ TPOTPI+ TPIEXRES1 BUFFER TYPE AO AO AI AI AI NUM PINS 1 1 1 1 1 DESCRIPTION Twisted Pair Transmit Output, Positive Twisted Pair Transmit Output, Negative Twisted Pair Receive Input, Positive Twisted Pair Receive Input, Negative Must be connected to ground through a 12.4K ohm 1% resistor. Table 2.4 Serial EEPROM Interface Signals PIN NO. 67 NAME EEPROM Data, GPO3, TX_EN, TX_CLK, D32/nD16 SYMBOL EEDIO/GPO3/ TX_EN/TX_CLK BUFFER TYPE I/O8 NUM PINS 1 DESCRIPTION EEPROM Data: This bi-directional pin can be connected to a serial EEPROM DIO. This is optional. General Purpose Output 3: This pin can also function as a general purpose output, or it can be configured to monitor the TX_EN or TX_CLK signals on the internal MII port. When configured as a GPO signal, or as a TX_EN/TX_CLK monitor, the EECS pin is deasserted so as to never unintentionally access the serial EEPROM. This signal cannot function as a generalpurpose input. Data Bus Width Select: This signal also functions as a configuration input on power-up and is used to select the host bus data width. Upon deassertion of reset, the value of the input is latched. When high, a 32-bit data bus is utilized. When low, a 16bit interface is utilized. 68 EEPROM Chip Select nEECS O8 1 Serial EEPROM chip select. (D32/nD16) Revision 1.1 (05-17-05) DATASHEET 16 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.4 Serial EEPROM Interface Signals (continued) PIN NO. 69 NAME EEPROM Clock, GPO4 RX_DV, RX_CLK SYMBOL EECLK/GPO4/ RX_DV/RX_CLK BUFFER TYPE O8 NUM PINS 1 DESCRIPTION EEPROM Clock: Serial EEPROM Clock pin. General Purpose Output 4: This pin can also function as a generalpurpose output, or it can be configured to monitor the RX_DV or RX_CLK signals on the internal MII port. When configured as a GPO signal, or as an RX_DV/RX_CLK monitor, the EECS pin is deasserted so as to never unintentionally access the serial EEPROM. This signal cannot function as a generalpurpose input. Table 2.5 System and Power Signals PIN NO. 6 NAME Crystal 1 SYMBOL XTAL1 BUFFER TYPE lclk NUM PINS 1 DESCRIPTION External 25MHz Crystal Input. Can also be connected to singleended TTL oscillator. If this method is implemented, XTAL2 should be left unconnected. External 25MHz Crystal output. 5 95 Crystal 2 Reset XTAL2 nRESET Oclk IS (PU) 1 1 Active-low reset input. Resets all logic and registers within the LAN9118 This signal is pulled high with a weak internal pull-up resistor. If nRESET is left unconnected, the LAN9118 will rely on its internal power-on reset circuitry Note: The LAN9118 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. See Section 3.11, "Detailed Reset Description," on page 40 for additional information SMSC LAN9118 DATASHEET 17 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.5 System and Power Signals (continued) PIN NO. 70 NAME Wakeup Indicator SYMBOL PME BUFFER TYPE O8/OD8 NUM PINS 1 DESCRIPTION When programmed to do so, is asserted when the LAN9118 detects a wake event and is requesting the system to wake up from the associated sleep state. The polarity and buffer type of this signal is programmable. Note: Detection of a Power Management Event, and assertion of the PME signal will not wakeup the LAN9118. The LAN9118 will only wake up when it detects a host write cycle (assertion of nCS and nWR). Although any write to the LAN9118, regardless of the data written, will wakeup the device when it is in a power-saving mode, it is required that the BYTE_TEST register be used for this purpose. 100,99 ,98 General Purpose I/O data, nLED1 (Speed Indicator), nLED2 (Link & Activity Indicator), GPIO[2:0]/ LED[3:1] IS/O12/ OD12 3 nLED3 (FullDuplex Indicator). General Purpose I/O data: These three general-purpose signals are fully programmable as either pushpull output, open-drain output or input by writing the GPIO_CFG configuration register in the CSR’s. They are also multiplexed as GP LED connections. GPIO signals are Schmitt-triggered inputs. When configured as LED outputs these signals are open-drain. nLED1 (Speed Indicator). This signal is driven low when the operating speed is 100Mbs, during auto-negotiation and when the cable is disconnected. This signal is driven high only during 10Mbs operation. nLED2 (Link & Activity Indicator). This signal is driven low (LED on) when the LAN9118 detects a valid link. This signal is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected. This signal is then driven low again for a minimum of 80mS, after which time it will repeat the process if TX or RX activity is detected. Effectively, LED2 is activated solid for a link. When transmit or receive activity is sensed LED2 will flash as an activity indicator. nLED3 (Full-Duplex Indicator). This signal is driven low when the link is operating in full-duplex mode. Revision 1.1 (05-17-05) DATASHEET 18 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 2.5 System and Power Signals (continued) PIN NO. NAME SYMBOL BUFFER TYPE NUM PINS DESCRIPTION PLL Bias: Connect to an external 12.0K ohm 1.0% resistor to ground. Used for the PLL Bias circuit. This pin must be connected to VDD for normal operation. 3.3V input for internal voltage regulator +3.3V I/O logic power supply pins 10 RBIAS RBIAS AI 1 9 2 20,28, 35, 42,48, 55,61, 97 19,27, 34,41, 47,54, 60,96 81,85, 89 77,80, 86,88 3,65 Test Pin Internal Regulator Power +3.3V I/O Power ATEST VREG VDD_IO I P P 1 1 8 I/O Ground GND_IO P 8 Ground for I/O pins +3.3V Analog Power Analog Ground Core Voltage Decoupling VDD_A VSS_A VDD_CORE P P P 3 4 2 +3.3V Analog power supply pins. See Note 2.1 Ground for analog circuitry 1.8 V from internal core regulator. Both pins must be connected together externally and then tied to a 10uF 0.1-Ohm ESR capacitor, in parallel with a 0.01uF capacitor to Ground next to each pin. See Note 2.1 Ground for internal digital logic 1.8V Power from the internal PLL regulator. This external pin must be connected to a 10uF 0.1-Ohm ESR capacitor, in parallel with a 0.01uF capacitor to Ground. See Note 2.1 GND for the PLL Connected to 3.3v power and used as the reference voltage for the internal PLL Ground for internal PLL reference voltage 1,66 7 Core Ground PLL Power GND_CORE VDD_PLL P P 2 1 4 8 PLL Ground Reference Power VSS_PLL VDD_REF P P 1 1 11 Reference Ground Note 2.1 VSS_REF P 1 Please refer to the SMSC application note AN 12.5 titled “Designing with the LAN9118 Getting Started”. It is also important to note that this application note applies to the whole SMSC LAN9118 family of Ethernet controllers. However, subtle differences may apply. SMSC LAN9118 DATASHEET 19 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 2.1 Buffer Types Table 2.6 Buffer Types TYPE I IS O12 OD12 IO8 OD8 O8 PU PD AI AO AIO ICLK OCLK Input pin Schmitt triggered Input Output with 12mA sink and 12mA source Open-drain output with 12mA sink I/O with 8mA symmetrical drive Open-drain output with 8mA sink Output 8mA symmetrical drive 30uA internal pull-up 30uA internal pull-down Analog input Analog output Analog bi-directional Crystal oscillator input pin Crystal oscillator output pin DESCRIPTION Revision 1.1 (05-17-05) DATASHEET 20 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 3 Functional Description 3.1 10/100 Ethernet MAC The Ethernet Media Access controller (MAC) incorporates the essential protocol requirements for operating an Ethernet/IEEE 802.3-compliant node and provides an interface between the host subsystem and the internal Ethernet PHY. The MAC can operate in either 100-Mbps or 10-Mbps mode. The MAC operates in both half-duplex and full-duplex modes. When operating in half-duplex mode, the MAC complies fully with Section 4 of ISO/IEC 8802-3 (ANSI/IEEE standard) and ANSI/IEEE 802.3 standards. When operating in full-duplex mode, the MAC complies with IEEE 802.3x full-duplex operation standard. The MAC provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. These features include the ability to disable retries after a collision, dynamic FCS (Frame Check Sequence) generation on a frame-by-frame basis, automatic pad field insertion and deletion to enforce minimum frame size attributes, and automatic retransmission and detection of collision frames. The MAC can sustain transmission or reception of minimally-sized back-to-back packets at full line speed with an interpacket gap (IPG) of 9.6 microseconds for 10 Mbps and 0.96 microseconds for 100 Mbps. The primary attributes of the MAC Function are: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Transmit and receive message data encapsulation Framing (frame boundary delimitation, frame synchronization) Error detection (physical medium transmission errors) Media access management Medium allocation (collision detection, except in full-duplex operation) Contention resolution (collision handling, except in full-duplex operation) Flow control during full-duplex mode Decoding of control frames (PAUSE command) and disabling the transmitter Generation of control frames Interface to the internal PHYl The transmit and receive data paths are separate within the LAN9118 from the MAC to host interface allowing the highest performance, especially in full duplex mode. Payload data as well as transmit and receive status are passed on these busses. A third internal bus is used to access the MAC’s “Control and Status Registers” (CSR’s). This bus is also accessible from the host. On the backend, the MAC interfaces with the 10/100 PHY through an internal MII (Media Independent Interface) port, internal to the LAN9118. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus. The receive and transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between the host interface and the MAC through which all transmitted and received data and status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks reducing and minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data paths. The LAN9118 can store up to 250 Ethernet packets utuilizing FIFOs, totaling 16K bytes, with a packet granularity of 4 bytes. This memory is shared by the RX and TX blocks and is configurable in terms of allocation. This depth of buffer storage minimizes or eliminates receive overruns. SMSC LAN9118 21 Revision 1.1 (05-17-05) DATASHEET High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.2 Flow Control The LAN9118 Ethernet MAC supports full-duplex flow control using the pause operation and control frame. It also supports half-duplex flow control using back pressure. 3.2.1 Full-Duplex Flow Control The pause operation inhibits data transmission of data frames for a specified period of time. A Pause operation consists of a frame containing the globally assigned multicast address (01-80-C2-00-00-01), the PAUSE opcode, and a parameter indicating the quantum of slot time (512 bit times) to inhibit data transmissions. The PAUSE parameter may range from 0 to 65,535 slot times. The Ethernet MAC logic, on receiving a frame with the reserved multicast address and PAUSE opcode, inhibits data frame transmissions for the length of time indicated. If a Pause request is received while a transmission is in progress, then the pause will take effect after the transmission is complete. Control frames are received and processed by the MAC and are passed on. The MAC also transmits control frames (pause command) via both hardware and software control. The software driver requests the MAC to transmit a control frame and gives the value of the PAUSE time to be used in the control frame. The MAC Function constructs a control frame with the appropriate values set in all the different fields (as defined in the 802.3x specification) and transmits the frame to the MII interface. The transmission of the control frame is not affected by the current state of the Pause timer value that is set because of a recently received control frame. 3.2.2 Half-Duplex Flow Control (Backpressure) In half-duplex mode, back pressure is used for flow control. Whenever the receive buffer/FIFO becomes full or crosses a certain threshold level, the MAC starts sending a Jam signal. The MAC transmit logic enters a state at the end of current transmission (if any), where it waits for the beginning of a received frame. Once a new frame starts, the MAC starts sending the Jam signal, which will result in a collision. After sensing the collision, the remote station will back off its transmission. The MAC continues sending the jam to make other stations defer transmission. The MAC only generates this collision-based back pressure when it receives a new frame, in order to avoid any late collisions. 3.2.3 Virtual Local Area Network (VLAN) VLAN is a means to form a “broadcast domain” without restriction on the physical or geographical location on the members of that domain. VLAN can be implemented in any number of different factors, such as: ■ ■ ■ ■ ■ Physical port MAC address Layer-3 unicast address Multicast address Date/time in combination with MAC address, etc. An example of a VLAN is depicted in Figure 3.1, "VLAN Topology". It demonstrates the freedom from physical constraint on the network, and the ability to divide a single switched network into a smaller broadcast domain. Moreover, VLAN offers a number of other advantages, such as: Configurability: Changes to an existing VLAN can be made on the network administrative level, rather than on the hardware level. A member of a VLAN can thus change its MAC address or its port and still be a member of the same VLAN. Extra routing is not necessary. Security: VLAN can improve security by demanding a predefined authentication before admitting a new member to the domain. Revision 1.1 (05-17-05) DATASHEET 22 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Network efficiency: Allows shielding one system resource from traffic not meant for that resource. A workstation in one VLAN is shielded from traffic on another VLAN, increasing that workstation’s efficiency. Broadcast containment: Leakage of broadcast frames from one VLAN to another is prevented. VLAN 3 CCC DDD VLAN 2 EEE AAA BBB FFF LAN Switch #1 GGG VLAN 1 HHH LAN Switch #2 VLAN Config Data Address AAA BBB CCC DDD EEE FFF GGG HHH VLAN # VLAN 3 VLAN 3 VLAN 3 VLAN 2 VLAN 2 VLAN 2 VLAN 1 VLAN 1 LAN Switch #3 Figure 3.1 VLAN Topology When the members of a VLAN are not located on the same physical medium, the VLAN uses a tag to help it determine how to forward the frame from one member to another. The tag structure was proprietary until the IEEE released a supplement to 802.3 defining the VLAN frame structure, including the tag. This new frame structure for VLAN is depicted in Figure 3.2, "VLAN Frame". SMSC LAN9118 DATASHEET 23 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Figure 3.2 VLAN Frame The MAC Function recognizes transmitted and received frames tagged with either one-level or twolevel VLAN IDs. The MAC compares the thirteenth and fourteenth bytes of transmit and receive frames to the contents of both the one-level VLAN tag register and the two-level VLAN tag register. If a match is found, the MAC Function identifies the frame as either a one- or two-level VLAN frame, depending on where the match was found. Upon recognizing that a frame has a VLAN tag, counter thresholds are adjusted to account for the extra bytes that the VLAN tag adds to the frame. The maximum length of the good packet is thus changed from 1518 bytes to 1522 bytes. Revision 1.1 (05-17-05) DATASHEET 24 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.3 Address Filtering Functional Description The Ethernet address fields of an Ethernet Packet, consists of two 6-byte fields: one for the destination address and one for the source address. The first bit of the destination address signifies whether it is a physical address or a multicast address. The LAN9118 address check logic filters the frame based on the Ethernet receive filter mode that has been enabled. Filter modes are specified based on the state of the control bits in Table 3.1, "Address Filtering Modes", which shows the various filtering modes used by the Ethernet MAC Function. These bits are defined in more detail in the “MAC Control Register”. Please refer to Section 5.4.1, "MAC_CR—MAC Control Register," on page 92 for more information on this register. If the frame fails the filter, the Ethernet MAC function does not receive the packet. The host has the option of accepting or ignoring the packet. Table 3.1 Address Filtering Modes MCPAS 0 0 PRMS 0 0 INVFILT 0 0 HO 0 0 HPFILT 0 1 DESCRIPTION MAC address perfect filtering only for all addresses. MAC address perfect filtering for physical address and hash filtering for multicast addresses Hash Filtering for physical and multicast addresses Inverse Filtering Promiscuous Pass all multicast frames. Frames with physical addresses are perfect-filtered Pass all multicast frames. Frames with physical addresses are hashfiltered 0 0 X 1 0 0 1 0 0 1 0 0 1 0 X 0 1 0 X X 1 0 0 1 1 3.4 3.4.1 Filtering Modes Perfect Filtering This filtering mode passes only incoming frames whose destination address field exactly matches the value programmed into the MAC Address High register and the MAC address low register. The MAC address is formed by the concatenation of the above two registers in the MAC CSR Function. 3.4.2 Hash Only Filtering This type of filtering checks for incoming Receive packets with either multicast or physical destination addresses, and executes an imperfect address filtering against the hash table. During imperfect hash filtering, the destination address in the incoming frame is passed through the CRC logic and the upper six bits of the CRC register are used to index the contents of the hash table. The hash table is formed by merging the register’s multicast hash table high and multicast hash table low in the MAC CSR Function to form a 64-bit hash table. The most significant bit determines the register to be used (High/Low), while the other five bits determine the bit within the register. A value of 00000 selects Bit 0 of the multicast hash table low register and a value of 11111 selects Bit 31 of the multicast hash table high register. SMSC LAN9118 DATASHEET 25 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.4.2.1 Hash Perfect Filtering In hash perfect filtering, if the received frame is a physical address, the LAN9118 Packet Filter block perfect-filters the incoming frame’s destination field with the value programmed into the MAC Address High register and the MAC Address Low register. If the incoming frame is a multicast frame, however, the LAN9118 packet filter function performs an imperfect address filtering against the hash table. The imperfect filtering against the hash table is the same imperfect filtering process described in the “Hash Only Filtering” section above. 3.4.2.2 Inverse Filtering In inverse filtering, the LAN9118 Packet Filter Block accepts incoming frames with a destination address not matching the perfect address (i.e., the value programmed into the MAC Address High register and the MAC Address Low register in the CRC block and rejects frames with destination addresses matching the perfect address. For all filtering modes, when MCPAS is set, all multicast frames are accepted. When the PRMS bit is set, all frames are accepted regardless of their destination address. This includes all broadcast frames as well. 3.5 Wake-up Frame Detection Setting the Wake-Up Frame Enable bit (WUEN) in the “WUCSR—Wake-up Control and Status Register”, places the LAN9118 MAC in the wake-up frame detection mode. In this mode, normal data reception is disabled, and detection logic within the MAC examines receive data for the preprogrammed wake-up frame patterns. The LAN9118 can be programmed to notify the host of the wakeup frame detection with the assertion of the host interrupt (IRQ) or assertion of the power managment event signal (PME). Upon detection, the Wake-Up Frame Received bit (WUFR) in the WUCSR is set. When the host clears the WUEN bit the LAN9118 will resume normal receive operation. Before putting the MAC into the wake-up frame detection state, the host must provide the detection logic with a list of sample frames and their corresponding byte masks. This information is written into the Wake-up Frame Filter register (WUFF). Please refer to Section 5.4.11, "WUFF—Wake-up Frame Filter," on page 100 for additional information on this register. The MAC supports four programmable filters that support many different receive packet patterns. If remote wake-up mode is enabled, the remote wake-up function receives all frames addressed to the MAC. It then checks each frame against the enabled filter and recognizes the frame as a remote wakeup frame if it passes the wakeup frame filter register’s address filtering and CRC value match. In order to determine which bytes of the frames should be checked by the CRC module, the MAC uses a programmable byte mask and a programmable pattern offset for each of the four supported filters. The pattern’s offset defines the location of the first byte that should be checked in the frame. Since the destination address is checked by the address filtering Function, the pattern offset is always greater than 12. The byte mask is a 31-bit field that specifies whether or not each of the 31 contiguous bytes within the frame, beginning in the pattern offset, should be checked. If bit j in the byte mask is set, the detection logic checks byte offset +j in the frame. In order to load the Wake-up Frame Filter register, the host LAN driver software must perform eight writes to the Wake-up Frame Filter register (WUFF). The Diagram shown in Table 3.2, "Wake-Up Frame Filter Register Structure" below, shows the wakeup frame filter register’s structure. Note 3.1 Note 3.2 Wake-up frame detection can be performed when LAN9118 is in the D0 or D1 power states. In the D0 state, wake-up frame detection is enabled when the WUEN bit is set. Wake-up frame detection, as well as Magic Packet detection, is always enabled and cannot be disabled when the device enters the D1 state. Revision 1.1 (05-17-05) DATASHEET 26 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 3.2 Wake-Up Frame Filter Register Structure Filter 0 Byte Mask Filter 1 Byte Mask Filter 2 Byte Mask Filter 3 Byte Mask Reserved Filter 3 Command Reserved Filter 2 Command Reserved Filter 1 Command Reserved Filter 0 Command Filter 3 Offset Filter 2 Offset Filter 1Offset Filter 0 Offset Filter 0 CRC-16 Filter 2 CRC-16 Filter 1 CRC-16 Filter 3 CRC-16 The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether or not this is a wake-up frame. Table 3.3, describes the byte mask’s bit fields. Table 3.3 Filter i Byte Mask Bit Definitions FILTER I BYTE MASK DESCRIPTION FIELD 31 30:0 DESCRIPTION Must be zero (0) Byte Mask: If bit j of the byte mask is set, the CRC machine processes byte number pattern - (offset + j) of the incoming frame. Otherwise, byte pattern - (offset + j) is ignored. The Filter i command register controls Filter i operation. Table 3.4 shows the Filter I command register. Table 3.4 Filter i Command Bit Definitions FILTER i COMMANDS FIELD 3 DESCRIPTION Address Type: Defines the destination address type of the pattern. When bit is set, the pattern applies only to multicast frames. When bit is cleared, the pattern applies only to unicast frames. RESERVED Enable Filter: When bit is set, Filter i is enabled, otherwise, Filter i is disabled. The Filter i Offset register defines the offset in the frame’s destination address field from which the frames are examined by Filter i. Table 3.5 describes the Filter i Offset bit fields. 2:1 0 SMSC LAN9118 DATASHEET 27 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 3.5 Filter i Offset Bit Definitions FILTER I OFFSET DESCRIPTION FIELD 7:0 DESCRIPTION Pattern Offset: The offset of the first byte in the frame on which CRC is checked for wake-up frame recognition. The minimum value of this field must be 12 since there should be no CRC check for the destination address and the source address fields. The MAC checks the first offset byte of the frame for CRC and checks to determine whether the frame is a wake-up frame. Offset 0 is the first byte of the incoming frame's destination address. The Filter i CRC-16 register contains the CRC-16 result of the frame that should pass Filter i. Table 3.6 describes the Filter i CRC-16 bit fields. Table 3.6 Filter i CRC-16 Bit Definitions FILTER I CRC-16 DESCRIPTION FIELD 15:0 DESCRIPTION Pattern CRC-16: This field contains the 16-bit CRC value from the pattern and the byte mask programmed to the wake-up filter register Function. This value is compared against the CRC calculated on the incoming frame, and a match indicates the reception of a wakeup frame. 3.5.1 Magic Packet Detection Setting the Magic Packet Enable bit (MPEN) in the “WUCSR—Wake-up Control and Status Register”, places the LAN9118 MAC in the “Magic Packet” detection mode. In this mode, normal data reception is disabled, and detection logic within the MAC examines receive data for a Magic Packet. The LAN9118 can be programmed to notify the host of the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or assertion of the power managment event signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the WUCSR is set. When the host clears the MPEN bit the LAN9118 will resume normal receive operation. Please refer to Section 5.4.12, "WUCSR—Wake-up Control and Status Register," on page 101 for additional information on this register In Magic Packet mode, the Power Management Logic constantly monitors each frame addressed to the node for a specific Magic Packet pattern. It checks only packets with the MAC’s address or a broadcast address to meet the Magic Packet requirement. The Power Management Logic checks each received frame for the pattern 48h FF_FF_FF_FF_FF_FF after the destination and source address field. Then the Function looks in the frame for 16 repetitions of the MAC address without any breaks or interruptions. In case of a break in the 16 address repetitions, the PMT Function scans for the 48'hFF_FF_FF_FF_FF_FF pattern again in the incoming frame. The 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream. The device will also accept a multicast frame, as long as it detects the 16 duplications of the MAC address. If the MAC address of a node is 00h 11h 22h 33h 44h 55h, then the MAC scans for the following data sequence in an Ethernet: Frame. Revision 1.1 (05-17-05) DATASHEET 28 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Destination Address Source Address ……………FF FF FF FF FF FF 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 …CRC It should be noted that Magic Packet detection can be performed when LAN9118 is in the D0 or D1 power states. In the D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the D1 state, Magic Packet detection, as well as wake-up frame detection, are automatically enabled when the device enters the D1 state. 3.6 32-bit vs. 16-bit Host Bus Width Operation The LAN9118 can be configured to communicate with the host bus via either a 32-bit or a 16-bit bus. An external strap is used to select between the two modes. 32-bit mode is the native environment for the LAN9118 Ethernet controller and no special requirements exist for communication in this mode. However, when this part is used in the 16-bit mode, two writes or reads must be performed back to back to properly communicate. The bus width is set by strapping the EEDIO pin; this setting can be read from bit 2 of the “Hardware Configuration Register”. Please refer to Section 5.3.9, "HW_CFG—Hardware Configuration Register," on page 75 for additional information on this register. 3.6.1 16-bit Bus Writes The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot change during a sixteen bit write). No ordering requirements exist. The processor can access either the low or high word first, as long as the next write is performed to the other word. If a write to the same word is performed, the LAN9118 disregards the transfer. 3.6.2 16-bit Bus Reads The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD transfer. This DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot change during a sixteen bit read). No ordering requirements exist. The processor can access either the low or high word first, as long as the next read is performed from the other word. If a read to the same word is performed, the data read is invalid and should be re-read. This is not a fatal error. The LAN9118 will reset its read counters and restart a new cycle on the next read. The Upper 16 data pins (D[31:16]) are not driven by the LAN9118 in 16-bit mode. These pins have internal pull-down’s and the signals are left in a high-impedance state. 3.7 Big and Little Endian Support The SMSC LAN9118 supports “Big-” or “Little-Endian” processors in either 16 or 32-bit bus width modes. To support big-endian processors, the hardware designer must explicitly invert the layout of the byte lanes. In addition, for a 16-bit interface, the big-endian register must be set correctly following Table 3.7, "Byte Lane Mapping". The host bus interface can be selected via an external strap to translate the data bus into either mode. Please refer to Table 2.4, “Serial EEPROM Interface Signals,” on page 16, for information on multiplexed signal D32/nD16 for more information on data bus width selection. Additionally, please refer to Section 5.3.17, "ENDIAN—Endian Control," on page 84 for additional information on status indication on Endian modes. SMSC LAN9118 DATASHEET 29 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 3.7 Byte Lane Mapping MODE OF OPERATION 32-bit DATA PINS D[31:24] Byte 3 (MSB) D[23:16] Byte 2 D[15:8] Byte 1 D[7:0] Byte 0 (LSB) DESCRIPTION This is the native mode of the LAN9118. Endianess does not matter when both WORD lanes are in operation. Mode 0 (Big Endian Register equal to 0xFFFFFFFF)h A1 = 0 A1 = 1 ----Byte 3 Byte 1 Byte 2 Byte 0 Note: This mode can be used by 32bit processors operating with an external 16-bit bus. Mode 1 (Big Endian Register not equal to 0xFFFFFFFF)h A1 = 0 A1 = 1 ----Byte 1 Byte 3 Byte 0 Byte 2 Note: This mode can also be used by native 16-bit processors. 3.8 General Purpose Timer (GP Timer) The General Purpose Timer is a programmable block that can be used to generate periodic host interrupts. The resolution of this timer is 100uS. The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting down when the TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from set ‘1’ to cleared ‘0,’ the GPT_CNT field is initialized to FFFFh. The GPT_CNT register is also initialized to FFFFh on a reset. Software can write the pre-load value into the GPT_LOAD field at any time; e.g., before or after the TIMER_EN bit is asserted. The GPT Enable bit TIMER_EN is located in the GPT_CFG register. Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is written to the GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT interrupt status bit and the IRQ signal if the GPT_INT_EN bit is set, and continues counting. The GPT interrupt status bit is in the INT_STS Register. The GPT_INT hardware interrupt can only be set if the GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT bit is set, it can only be cleared by writing a ‘1’ to the bit. 3.9 EEPROM Interface LAN9118 can optionally load its MAC address from an external serial EEPROM. If a properly configured EEPROM is detected by LAN9118 at power-up, hard reset or soft reset, the ADDRH and ADDRL registers will be loaded with the contents of the EEPROM. If a properly configured EEPROM is not detected, it is the responsibility of the host LAN Driver to set the IEEE addresses. The LAN9118 EEPROM controller also allows the host system to read, write and erase the contents of the Serial EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for 128 x 8-bit operation. 3.9.1 MAC Address Auto-Load On power-up, hard reset or soft reset, the EEPROM controller attempts to read the first byte of data from the EEPROM (address 00h). If the value A5h is read from the first address, then the EEPROM Revision 1.1 (05-17-05) DATASHEET 30 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet controller will assume that an external Serial EEPROM is present. The EEPROM controller will then access the next EEPROM byte and send it to the MAC Address register byte 0 (ADDRL[7:0]). This process will be repeated for the next five bytes of the MAC Address, thus fully programming the 48bit MAC address. Once all six bytes have been programmed, the “MAC Address Loaded” bit is set in the E2P_CMD register. A detailed explanation of the EEPROM byte ordering with respect to the MAC address is given in Section 5.4.3, "ADDRL—MAC Address Low Register," on page 95. If an 0xA5h is not read from the first address, the EEPROM controller will end initialization. It is then the responsibility of the host LAN driver software to set the IEEE address by writing to the MAC’s ADDRH and ADDRL registers. The host can initiate a reload of the MAC address from the EEPROM by issuing the RELOAD command via the E2P command (E2P_CMD) register. If the first byte read from the EEPROM is not A5h, it is assumed that the EEPROM is not present, or not programmed, and the MAC address reload will fail. The “MAC Address Loaded” bit indicates a successful reload of the MAC address. 3.9.2 EEPROM Host Operations After the EEPROM controller has finished reading (or attempting to read) the MAC after power-on, hard reset or soft reset, the host is free to perform other EEPROM operations. EEPROM operations are performed using the E2P_CMD and E2P data (E2P_DATA) registers. Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 89 provides an explanation of the supported EEPROM operations. If the EEPROM operation is the “write location” (WRITE) or “write all” (WRAL) commands, the host must first write the desired data into the E2P_DATA register. The host must then issue the WRITE or WRAL command using the E2P_CMD register by setting the EPC_CMD field appropriately. If the operation is a WRITE, the EPC_ADDR field in E2P_CMD must also be set to the desired location. The command is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared. If the EEPROM operation is the “read location” (READ) operation, the host must issue the READ command using the E2P_CMD with the EPC_ADDR set to the desired location. The command is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared, at which time the data from the EEPROM may be read from the E2P_DATA register. Other EEPROM operations are performed by writing the appropriate command to the EPC_CMD register. The command is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared. In all cases the host must wait for EPC_BSY to clear before modifying the E2P_CMD register. Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM the host must first issue the EWEN command. If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9118 will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set. Figure 3.3, "EEPROM Access Flow Diagram" illustrates the host accesses required to perform an EEPROM Read or Write operation. SMSC LAN9118 DATASHEET 31 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet EEPROM Write EEPROM Read Idle Idle Write Data Register Write Command Register Write Command Register Read Command Register Busy Bit = 0 Busy Bit = 0 Read Command Register Read Data Register Figure 3.3 EEPROM Access Flow Diagram The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used to monitor internal MII signals. 3.9.2.1 Supported EEPROM Operations The EEPROM controller supports the following EEPROM operations under host control via the E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A description and functional timing diagram is provided below for each operation. Please refer to the E2P_CMD register description in Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 89 for E2P_CMD field settings for each command. ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within 30ms. Revision 1.1 (05-17-05) DATASHEET 32 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet tCSL EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) 1 1 1 A6 A0 Figure 3.4 EEPROM ERASE Cycle ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. tCSL EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) 1 0 0 1 0 Figure 3.5 EEPROM ERAL Cycle SMSC LAN9118 DATASHEET 33 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet EWDS (Erase/Write Disable): After issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations issue the EWEN command. tCSL EECS EECLK EEDIO (OUTPUT) 1 0 0 0 0 EEDIO (INPUT) Figure 3.6 EEPROM EWDS Cycle EWEN (Erase/Write Enable): Enables the EEPROM for erase and write operations. The EEPROM will allow erase and write operations until the “Erase/Write Disable” command is sent, or until power is cycled. Note: The EEPROM device will power-up in the erase/write-disabled state. Any erase or write operations will fail until an Erase/Write Enable command is issued. tCSL EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) 1 0 0 1 1 Figure 3.7 EEPROM EWEN Cycle Revision 1.1 (05-17-05) DATASHEET 34 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet READ (Read Location): This command will cause a read of the EEPROM location pointed to by EPC Address (EPC_ADDR). The result of the read is available in the E2P_DATA register. tCSL EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) 1 1 0 A6 A0 D7 D0 Figure 3.8 EEPROM READ Cycle WRITE (Write Location): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the E2P_DATA register to be written to the EEPROM location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within 30ms. tCSL EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) 1 0 1 A6 A0 D7 D0 Figure 3.9 EEPROM WRITE Cycle SMSC LAN9118 DATASHEET 35 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit is set if the EEPROM does not respond within 30ms. tCSL EECS EECLK EEDIO (OUTPUT) 1 0 0 0 1 D7 D0 EEDIO (INPUT) Figure 3.10 EEPROM WRAL Cycle Table 3.8, "Required EECLK Cycles", shown below, shows the number of EECLK cycles required for each EEPROM operation. Table 3.8 Required EECLK Cycles OPERATION ERASE ERAL EWDS EWEN READ WRITE WRAL REQUIRED EECLK CYCLES 10 10 10 10 18 18 18 3.9.2.2 MAC Address Reload The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register. If a value of 0xA5h is not found in the first address of the EEPROM, the EEPROM is assumed to be un-programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates a successful load of the MAC address. The EPC_LOAD bit is set after a successful reload of the MAC address. 3.9.2.3 EEPROM Command and Data Registers Refer to Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 89 and Section 5.3.24, "E2P_DATA – EEPROM Data Register," on page 91 for a detailed description of these registers. Supported EEPROM operations are described in these sections. 3.9.2.4 EEPROM Timing Refer to Section 6.9, "EEPROM Timing," on page 119 for detailed EEPROM timing specifications. Revision 1.1 (05-17-05) DATASHEET 36 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.10 Power Management LAN9118 supports power-down modes to allow applications to minimize power consumption. The following sections describe these modes. 3.10.1 System Description Power is reduced to various modules by disabling the clocks as outlined in Table 3.9, “Power Management States,” on page 38. All configuration data is saved when in either of the two low power states. Register contents are not affected unless specifically indicated in the register description. 3.10.2 Functional Description There is one normal operating power state, D0 and there are two power saving states: D1, and D2. Upon entry into either of the two power saving states, only the PMT_CTRL register is accessible for read operations. In either of the power saving states the READY bit in the PMT_CTRL register will be cleared. Reads of any other addresses are forbidden until the READY bit is set. All writes, with the exception of the wakeup write to BYTE_TEST, are also forbidden until the READY bit is set. Only when in the D0 (Normal) state, when the READY bit is set, can the rest of the device be accessed. Note 3.3 The LAN9118 must always be read at least once after power-up, reset, or upon return from a power-saving state, otherwise write operations will not function. In system configurations where the PME signal is shared amongst multiple devices, the WUPS field within the PMT_CTRL register can be read to determine which LAN9118 device is driving the PME signal. When the LAN9118 is in a power saving state (D1 or D2), a write cycle to the BYTE_TEST register will return the LAN9118 to the D0 state. Table 7.1, “Power Consumption Device Only,” on page 121 and Table 7.2, “Power Consumption Device and System Components,” on page 122, shows the power consumption values for each power state. Note 3.4 When the LAN9118 is in a power saving state, a write of any data to the BYTE_TEST register will wake-up the device. DO NOT PERFORM WRITES TO OTHER ADDRRESSES while the READY bit in the PMT_CTRL register is cleared. 3.10.2.1 D1 Sleep Power consumption is reduced in this state by disabling clocks to portions of the internal logic as shown in Table 3.9. In this mode the clock to the internal PHY and portions of the MAC are still operational. This state is entered when the host writes a '01' to the PM_MODE bits in the Power Management (PMT_CTRL) register. The READY bit in PMT_CTRL is cleared when entering the D1 state. Wake-up frame and Magic Packet detection are automatically enabled in the D1 state. If properly enabled via the WOL_EN and PME_EN bits, the LAN9118 will assert the PME hardware signal upon the detection of the wake-up frame or magic packet. The LAN9118 can also assert the host interrupt (IRQ) on detection of a wake-up frame or magic packet. Upon detection, the WUPS field in PMT_CTRL will be set to a 10b. Note 3.5 Note 3.6 The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the setting of PME_EN. Wake-up frame and Magic Packet detection is automatically enabled when entering the D1 state. For wake-up frame detection, the wake-up frame filter must be programmed before entering the D1 state (see Section 3.5, "Wake-up Frame Detection," on page 26). If used, the host interrupt and PME signal must be enabled prior to entering the D1 state. A write to the BYTE_TEST register, regardless of whether a wake-up frame or Magic Packet was detected, will return LAN9118 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY bit and verify that it is set before attempting any other reads or writes of the device. SMSC LAN9118 DATASHEET 37 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Note 3.7 The host must do only read accesses prior to the ready bit being set. Once the READY bit is set, the LAN9118 is ready to resume normal operation. At this time the WUPS field can be cleared. 3.10.2.2 D2 Sleep In this state, as shown in Table 3.9, all clocks to the MAC and host bus are disabled, and the PHY is placed in a reduced power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY (Mode Control/Status register) must be set. This places the PHY in the Energy Detect mode. The PM_MODE bits in the PMT_CTRL register must then be set to 10b. Upon setting the PM_MODE bits, the LAN9118 will enter the D2 sleep state. The READY bit in PMT_CTRL is cleared when entering the D2 state. Note 3.8 If carrier is present when this state is entered detection will occur immediately. If properly enabled via the ED_EN and PME_EN bits, LAN9118 will assert the PME hardware signal upon detection of a valid carrier. Upon detection, the WUPS field in PMT_CTRL will be set to a 01b. Note 3.9 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the setting of PME_EN. A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return LAN9118 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY bit and verify that it is set before attempting any other reads or writes of the device. Before LAN9118 is fully awake from this state the EDPWRDOWN bit in register 17 of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the EDPWRDOWN bit until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9118 is ready to resume normal operation. At this time the WUPS field can be cleared. Table 3.9 Power Management States LAN9118 BLOCK PHY MAC Power Management MAC and Host Interface Internal Clock D0 (NORMAL OPERATION) Full ON Full ON Full ON Full ON D1 (WOL) Full ON RX Power Mgmt. Block On OFF Full ON D2 (ENERGY DETECT) Energy Detect Power-Down OFF OFF OFF KEY CLOCK ON BLOCK DISABLED – CLOCK ON FULL OFF Revision 1.1 (05-17-05) DATASHEET 38 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.10.2.3 Power Managment Event Indicators Figure 3.11 is a simplified block diagram of the logic that controls the external PME, and internal pme_interrupt signals. The pme_interrupt signal is used to set the PME_INT status bit in the INT_STS register, which, if enabled, will generate a host interrupt upon detection of a power management event. The PME_INT status bit in INT_STS will remain set until the internal pme_interrupt signal is cleared by clearing the WUPS bits, or by clearing the corresponding WOL_EN or ED_EN bit. After clearing the internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a ‘1’ to this bit in the INT_STS register. It should be noted that the LAN9118 can generate a host interrupt regardless of the state of the PME_EN bit, or the external PME signal. The external PME signal can be setup for pulsed, or static operation. When the PME_IND bit in the PMT_CTRL register is set to a ‘1’, the external PME signal will be driven active for 50ms upon detection of a wake-up event. When the PME_IND bit is cleared, the PME signal will be driven continously upon detection of a wake-up event. The PME signal is deactivated by clearing the WUPS bits, or by clearing the corresponding WOL_EN or ED_EN bit. The PME signal can also be deactivated by clearing the PME_EN bit. WUFR WOL_EN WUEN WUPS MPR MPEN ED_EN WUPS phy_int Other System Interrupts PME_INT Denotes a level-triggered "sticky" status bit PME_INT_EN IRQ_EN IRQ PME_EN PME_IND PME_POL PME_TYPE 50ms LOGIC PME Figure 3.11 PME and PME_INT Signal Generation 3.10.3 Internal PHY Power-Down modes There are 2 power-down modes for the internal Phy: 3.10.3.1 General Power-Down This power-down is controlled by register 0, bit 11. In this mode the internal PHY, except the management interface, is powered-down and stays in that condition as long as Phy register bit 0.11 is HIGH. When bit 0.11 is cleared, the PHY powers up and is automatically reset. Please refer to Section 5.5.1, "Basic Control Register," on page 102 for additional information on this register. SMSC LAN9118 DATASHEET 39 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.10.3.2 Energy Detect Power-Down This power-down mode is activated by setting the Phy register bit 17.13 to 1. Please refer to Section 5.5.8, "Mode Control/Status," on page 106 for additional information on this register. In this mode when no energy is present on the line, the PHY is powered down, with th exception of the management interface, the SQUELCH circuit and the ENERGYON logic. The ENERGYON logic is used to detect the presence of valid energy from 100Base-TX, 10Base-T, or Auto-negotiation signals In this mode, when the ENERGYON signal is low, the PHY is powered-down, and nothing is transmitted. When energy is received - link pulses or packets - the ENERGYON signal goes high, and the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts the INT7.1 bit of the register defined in Section 5.5.11, "Interrupt Source Flag," on page 108. If the ENERGYON interrupt is enabled, this event will cause an interrupt to the host. The first and possibly the second packet to activate ENERGYON may be lost. When 17.13 is low, energy detect power-down is disabled. 3.11 Detailed Reset Description The LAN9118 has five reset sources: ■ ■ ■ ■ ■ Power-On Reset (POR) Hardware Reset Input Pin (nRESET) Soft Reset (SRST) PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST) PHY Soft Reset via PHY Basic Control Register (PHY REG 0.15) Table 3.10 shows the effect of the various reset sources on the LAN9118's circuitry. Table 3.10 PHY Reset Sources and Effected Circuitry HBI Note 3.12 X X X NASR REGISTERS Note 3.12 X X EEPROM MAC ADDR. RELOAD Note 3.11 X X X X X CONFIG. STRAPS LATCHED X X RESET SOURCE POR nRESET SRST PHY_RST PHY REG 0.15 PLL X X MIL X X X MAC X X X PHY Note 3.10 X X Note 3.10 After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic Status Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data. Note 3.11 After a POR, nRESET or SRST, the LAN9118 will automatically check for the presence of an external EEPROM. After any of these resets the application must verify that the EPC Busy Bit (E2P_CMD, bit 31) is cleared before attempting to access the EEPROM, or change the function of the GPO/GPIO signals, or before modifying the ADDRH or ADDRL registers in the MAC. Note 3.12 HBI - “Host Bus Interface”, NASR - Not affected by software reset Revision 1.1 (05-17-05) DATASHEET 40 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.11.1 Power-On Reset (POR) A Power-On reset occurs whenever power is initially applied to the LAN9118, or if power is removed and reapplied to the LAN9118. A timer within the LAN9118 will assert the internal reset for approximately 22ms. The READY bit in the PMT_CTRL register can be read from the host interface and will read back a ‘0’ until the POR is complete. Upon completion of the POR, the READY bit in PMT_CTRL is set high, and the LAN9118 can be configured via its control registers. APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) after an internal reset (22ms). If the software driver polls this bit and it is not set within 100ms, then an error condition occurred. 3.11.2 Hardware Reset Input (nRESET) A hardware reset will occur when the nRESET input signal is driven low. The READY bit in the PMT_CTRL register can be read from the host interface, and will read back a ‘0’ until the hardware reset is complete. Upon completion of the hardware reset, the READY bit in PMT_CTRL is set high. After the “READY” bit is set, the LAN9118 can be configured via its control registers. The nRESET signal is pulled-high internally by the LAN9118 and can be left unconnected if unused. If used, nRESET must be driven low for a minimum period as defined in Section 6.8, "Reset Timing," on page 119. APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately. If the software driver polls this bit and it is not set within 100ms, then an error condition occurred. 3.11.3 Resume Reset Timing After issuing a write to the BYTE_TEST register to wake the LAN9118 from a power-down state, the READY bit in PMT_CTRL will assert (set High) within 2ms. APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) within 2 ms. If the software driver polls this bit and it is not set within 100ms, then an error condition occurred. 3.11.4 Soft Reset (SRST) Soft reset is initiated by writing a ‘1’ to bit 0 of the HW_CFG register (SRST). This self-clearing bit will return to ‘0’ after approximately 2 µs, at which time the Soft Reset is complete. Soft reset does not clear control register bits marked as NASR. APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately, (within 2µs). If the software driver polls this bit and it is not set within 100ms, then an error condition occurred. 3.11.5 PHY Reset Timing The following sections and tables specify the operation and time required for the internal PHY to become operational after various resets or when returning from the reduced power state. 3.11.5.1 PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST) The PHY soft reset is initiated by writing a ‘1’ to bit 10 of the PMT_CTRL register (PHY_RST). This self-clearing bit will return to ‘0’ after approximately 100 µs, at which time the PHY reset is complete. 3.11.5.2 PHY Soft Reset via PHY Basic Control Register (PHY Reg. 0.15) The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register. This self-clearing bit will return to ‘0’ at which time the PHY reset is complete. SMSC LAN9118 DATASHEET 41 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.12 TX Data Path Operation Data is queued for transmission by writing it into the TX data FIFO. Each packet to be transmitted may be divided among multiple buffers. Each buffer starts with a two DWORD TX command (TX command ‘A’ and TX command ‘B’). The TX command instructs the LAN9118 on the handling of the associated buffer. Packet boundaries are delineated using control bits within the TX command. The host provides a 16-bit Packet Tag field in the TX command. The Packet Tag value is appended to the corresponding TX status DWORD. All Packet Tag fields must have the same value for all buffers in a given packet. If tags differ between buffers in the same packet the TXE error will be asserted. Any value may be chosen for a Packet Tag as long as all tags in the same Packet are identical. Packet Tags also provide a method of synchronization between transmitted packets and their associated status. Software can use unique Packet Tags to assist with validating matching status completions. Note 3.13 The use of packet tags is not required by the hardware. This is a software LAN driver only application example for use of this field. A Packet Length field in the TX command specifies the number of bytes in the associated packet. All Packet Length fields must have the same value for all buffers in a given packet. Hardware compares the Packet Length field and the actual amount of data received by the Ethernet controller. If the actual packet length count does not match the Packet Length field as defined in the TX command, the Transmitter Error (TXE) flag is asserted. The LAN9118 can be programmed to start payload transmission of a buffer on a byte boundary by setting the “Data Start Offset” field in the TX command. The “Data Start Offset” field points to the actual start of the payload data within the first 8 DWORDs of the buffer. Data before the “Data Start Offset” pointer will be ignored. When a packet is split into multiple buffers, each successive buffer may begin on any arbitrary byte. The LAN9118 can be programmed to strip padding from the end of a transmit packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9118 is operating in a system that always performs multi-word bursts. In such cases the LAN9118 must guarantee that it can accept data in multiples of the Burst length regardless of the actual packet length. When configured to do so, the LAN9118 will accept extra data at the end of the packet and will remove the extra padding before transmitting the packet. The LAN9118 automatically removes data up to the boundary specified in the Buffer End Alignment field specified in each TX command. The host can instruct the LAN9118 to issue an interrupt when the buffer has been fully loaded into the TX FIFO contained in the LAN9118 and transmitted. This feature is enabled through the TX command ‘Interrupt on Completion’ field. Upon completion of transmission, irrespective of success or failure, the status of the transmission is written to the TX status FIFO. TX status is available to the host and may be read using PIO operations. An interrupt can be optionally enabled by the host to indicate the availability of a programmable number TX status DWORDS. Before writing the TX command and payload data to the TX FIFO, the host must check the available TX FIFO space by performing a PIO read of the TX_FIFO_INF register. The host must ensure that it does not overfill the TX FIFO or the TX Error (TXE) flag will be asserted. The host proceeds to write the TX command by first writing TX command ‘A’, then TX command ‘B’. After writing the command, the host can then move the payload data into the TX FIFO. TX status DWORD’s are stored in the TX status FIFO to be read by the host at a later time upon completion of the data transmission onto the wire. Revision 1.1 (05-17-05) DATASHEET 42 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet init Idle TX Status Available Read TX Status (optional) Check available FIFO space Write TX Command Write Start Padding (optional) Last Buffer in Packet Write Buffer Not Last Buffer Figure 3.12 Simplified Host TX Flow Diagram SMSC LAN9118 DATASHEET 43 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.12.1 TX Buffer Format TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer before moving the Ethernet packet data. The TX command A and command B are 32bit values that are used by the LAN9118 in the handling and processing of the associated Ethernet packet data buffer. Buffer alignment, segmentation and other packet processing parameters are included in the command structure. The following diagram illustrates the buffer format. Host Write 31 Order 1st 2nd 3rd 0 TX Command 'A' TX Command 'B' Optional offset DWORD0 . . . Optional offset DWORDn Offset + Data DWORD0 . . . . . Last Data & PAD Optional Pad DWORD0 . . . Last Optional Pad DWORDn Figure 3.13 TX Buffer Format Note 3.14 Figure 3.13, "TX Buffer Format", shows the TX Buffer as it is written into the LAN9118. It should be noted that not all of the data shown in this diagram is actually stored in the TX data FIFO. This must be taken into account when calculating the actual TX data FIFO usage. Please refer to Section 3.12.5, "Calculating Actual TX Data FIFO Usage," on page 48 for a detailed explanation on calculating the actual TX data FIFO usage. 3.12.2 TX Command Format The TX command instructs the TX FIFO controller on handling the subsequent buffer. The command precedes the data to be transmitted. The TX command is divided into two, 32-bit words; TX command ‘A’ and TX command ‘B’. There is a 16-bit packet tag in the TX command ‘B’ command word. Packet tags may, if host software desires, be unique for each packet (i.e., an incrementing count). The value of the tag will be returned in the RX status word for the associated packet. The Packet tag can be used by host software to uniquely identify each status word as it is returned to the host. Revision 1.1 (05-17-05) DATASHEET 44 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do not match, the Ethernet controller will assert the Transmitter Error (TXE) flag. TX COMMAND ‘A’ Table 3.11 TX Command 'A' Format BITS 31 30:26 25:24 DESCRIPTION Interrupt on Completion. When set, the TXDONE flag will be asserted when the current buffer has been fully loaded into the TX FIFO. This flag may be optionally mapped to a host interrupt. Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility. Buffer End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The host will add extra DWORDs of data up to the alignment specified in the table below. The LAN9118 will remove the extra DWORDs. This mechanism can be used to maintain cache line alignment on host processors. [25] 0 0 1 1 [24] 0 1 0 1 End Alignment 4-byte alignment 16-byte alignment 32-byte alignment Reserved 23:21 20:16 15:14 13 12 11 10:0 Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility Data Start Offset (bytes). This field specifies the offset of the first byte of TX data. The offset value can be anywhere from 0 bytes to 31 a Byte offset. Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility First Segment. When set, this bit indicates that the associated buffer is the first segment of the packet. Last Segment. When set, this bit indicates that the associated buffer is the last segment of the packet Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility. Buffer Size (bytes). This field indicates the number of bytes contained in the buffer following this command. This value, along with the Buffer End Alignment field, is read and checked by the LAN9118 and used to determine how many extra DWORD’s were added to the end of the Buffer. A running count is also maintained in the LAN9118 of the cumulative buffer sizes for a given packet. This cumulative value is compared against the Packet Length field in the TX command ‘B’ word and if they do not correlate, the TXE flag is set. Note: The buffer size specified does not include the buffer end alignment padding or data start offset added to a buffer. SMSC LAN9118 DATASHEET 45 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet TX COMMAND ‘B’ Table 3.12 TX Command 'B' Format BITS 31:16 DESCRIPTION Packet Tag. The host should write a unique packet identifier to this field. This identifier is added to the corresponding TX status word and can be used by the host to correlate TX status words with their corresponding packets. Note: 15:14 13 12 The use of packet tags is not required by the hardware. This field can be used by the LAN software driver for any application. Packet Tags is one application example. Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility. Add CRC Disable. When set, the automatic addition of the CRC is disabled. Disable Ethernet Frame Padding. When set, this bit prevents the automatic addition of padding to an Ethernet frame of less than 64 bytes. The CRC field is also added despite the state of the Add CRC Disable field. Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility. Packet Length (bytes). This field indicates the total number of bytes in the current packet. This length does not include the offset or padding. If the Packet Length field does not match the actual number of bytes in the packet the Transmitter Error (TXE) flag will be set. 11 10:0 3.12.3 TX Data Format The TX data section begins at the third DWORD in the TX buffer (after TX command ‘A’ and TX command ‘B’). The location of the first byte of valid buffer data to be transmitted is specified in the “Data Start Offset” field of the TX command ‘A’ word. Table 3.13, "TX DATA Start Offset", shows the correlation between the setting of the LSB’s in the “Data Start Offset” field and the byte location of the first valid data byte. Additionally, transmit buffer data can be offset by up to 7 additional DWORDS as indicated by the upper three MSB’s (5:2) in the “Data Start Offset” field. Table 3.13 TX DATA Start Offset Data Start Offset [1:0]: First TX Data Byte: 11 D[31:24] 10 D[23:16] 01 D[15:8] 00 D[7:0] TX data is contiguous until the end of the buffer. The buffer may end on a byte boundary. Unused bytes at the end of the packet will not be sent to the MIL for transmission. The Buffer End Alignment field in TX command ‘A’ specifies the alignment that must be maintained for the associated buffer. End alignment may be specified as 4-, 16-, or 32-byte. The host processor is responsible for adding the additional data to the end of the buffer. The hardware will automatically remove this extra data. 3.12.3.1 TX Buffer Fragmentation Rules Transmit buffers must adhere to the following rules: ■ ■ ■ Each buffer can start and end on any arbitrary byte alignment The first buffer of any transmit packet can be any length Middle buffers (i.e., those with First Segment = Last Segment = 0) must be greater than, or equal to 4 bytes in length The final buffer of any transmit packet can be any length ■ Revision 1.1 (05-17-05) DATASHEET 46 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Additionally, The LAN9118 has specific rules regarding the use of transmit buffers when in Store-andForward mode (i.e., HW_CFG[SF] = 1). When this mode is enabled, the total space consumed in the TX FIFO (MIL) must be limited to no more than 2KB - 3 DWORDs (2,036 bytes total). Any transmit packet that is so highly fragmented that it takes more space than this must be un-fragmented (by copying to a Driver-supplied buffer) before the transmit packet can be sent to the LAN9118. One approach to determine whether a packet is too fragmented is to calculate the actual amount of space that it will consume, and check it against 2,036 bytes. Another approach is to check the number of buffers against a worst-case limit of 86 (see explanation below). 3.12.3.2 Calculating Worst-Case TX FIFO (MIL) Usage The actual space consumed by a buffer consists only of any partial DWORD offsets in the first/last DWORD of the buffer, plus all of the whole DWORDs in between. Any whole DWORD offsets and/or alignments are stripped off before the buffer even gets into the TX data FIFO, and TX command words are stripped off before the buffer is written to the TX FIFO, so none of those DWORDs count as space consumed. The worst-case overhead for a TX buffer is 6 bytes, which assumes that it started on the high byte of a DWORD and ended on the low byte of a DWORD. A TX packet consisting of 86 such fragments would have an overhead of 516 bytes (6 * 86) which, when added to a 1514-byte max-size transmit packet (1516 bytes, rounded up to the next whole DWORD), would give a total space consumption of 2,032 bytes, leaving 4 bytes to spare; this is the basis for the "86 fragment" rule mentioned above. 3.12.4 TX Status Format TX status is passed to the host CPU through a separate FIFO mechanism. A status word is returned for each packet transmitted. Data transmission is suspended if the TX status FIFO becomes full. Data transmission will resume when the host reads the TX status and there is room in the FIFO for more “TX Status” data. The host can optionally choose to not read the TX status. The host can optionally ignore the TX status by setting the “TX Status Discard Allow Overrun Enable” (TXSAO) bit in the TX Configuration Register (TX_CFG). If this option is chosen TX status will not be written to the FIFO. Setting this bit high allows the transmitter to continue operation with a full TX status FIFO. In this mode the status information is still available in the TX status FIFO, and TX status interrupts still function. In the case of an overrun, the TXSUSED counter will stay at zero and no further TX status will be written to the TX status FIFO until the host frees space by reading TX status. If TXSAO is enabled, a TXE error will not be generated if the TX status FIFO overruns. In this mode the host is responsible for re-synchronizing TX status in the case of an overrun. BITS 31:16 15 14:12 11 10 9 8 DESCRIPTION Packet TAG. Unique identifier written by the host into the Packet Tag field of the TX command ‘B’ word. This field can be used by the host to correlate TX status words with the associated TX packets. Error Status (ES). ). When set, this bit indicates that the Ethernet controller has reported an error. This bit is the logical OR of bits 11, 10, 9, 8, 2, 1 in this status word. Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility. Loss of Carrier. When set, this bit indicates the loss of carrier during transmission. No Carrier. When set, this bit indicates that the carrier signal from the transceiver was not present during transmission. Late Collision. When set, indicates that the packet transmission was aborted after the collision window of 64 bytes. Excessive Collisions. When set, this bit indicates that the transmission was aborted after 16 collisions while attempting to transmit the current packet. SMSC LAN9118 DATASHEET 47 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 7 6:3 2 DESCRIPTION Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility. Collision Count. This counter indicates the number of collisions that occurred before the packet was transmitted. It is not valid when excessive collisions (bit 8) is also set. Excessive Deferral. If the deferred bit is set in the control register, the setting of the excessive deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times during transmission. Underrun Error. When set, this bit indicates that the transmitter aborted the associated frame because of an underrun condition of the TX data FIFO. TX Underrun will cause the assertion of the TXE error flag. Deferred. When set, this bit indicates that the current packet transmission was deferred. 1 0 3.12.5 Calculating Actual TX Data FIFO Usage The following rules are used to calculate the actual TX data FIFO space consumed by a TX Packet: ■ ■ TX command 'A' is stored in the TX data FIFO for every TX buffer TX command 'B' is written into the TX data FIFO when the First Segment (FS) bit is set in TX command 'A' Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before the data is written to the TX data FIFO. Any data that is less than 1 DWORD is passed to the TX data FIFO. Payload from each buffer within a Packet is written into the TX data FIFO. Any DWORD-long data added as part of the End Padding is removed from each buffer before the data is written to the TX data FIFO. Any end padding that is less than 1 DWORD is passed to the TX data FIFO ■ ■ ■ 3.12.6 3.12.6.1 Transmit Examples TX Example 1 In this example a single, 111-Byte Ethernet packet will be transmitted. This packet is divided into three buffers. The three buffers are as follows: Buffer 0: ■ ■ ■ 7-Byte “Data Start Offset” 79-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 1: ■ ■ ■ 0-Byte “Data Start Offset” 15-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 2: ■ ■ ■ 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” Note 3.15 Figure 3.14, "TX Example 1" illustrates the TX command structure for this example, and also shows how data is passed to the TX data FIFO. Revision 1.1 (05-17-05) DATASHEET 48 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Data W ritten to the Ethernet Controller 31 TX Com m and 'A' Buff er End Alignment = 1 Data Start Of fset = 7 First Segment = 1 Last Segment = 0 Buff er Size = 79 TX Com m and 'B' Packet Length = 111 0 TX Command 'A' TX Command 'B' 7-Byte Data Start Offset Data Passed to the TX Data FIFO TX Command 'A' TX Command 'B' 79-Byte Payload 79-Byte Payload Pad DW ORD 1 10-Byte End Padding TX Command 'A' 31 TX Com m and 'A' Buff er End Alignment = 1 Data Start Of fset = 0 First Segment = 0 Last Segment = 0 Buff er Size = 15 TX Com m and 'B' Packet Length = 111 0 TX Command 'A' TX Command 'B' 15-Byte Payload TX Command 'A' 15-Byte Payload 1B 17-Byte Payload 31 0 TX Com m and 'A' Buff er End Alignment = 1 Data Start Of fset = 10 First Segment = 0 Last Segment = 1 Buff er Size = 17 TX Com m and 'B' Packet Length = 111 10-Byte TX Command 'A' End OffsetPadding TX Command 'B' 10-Byte Data Start Offset NOTE: Extra bytes betw een buff ers are not transmitted 17-Byte Payload Data 5-Byte End Padding Figure 3.14 TX Example 1 SMSC LAN9118 DATASHEET 49 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.12.6.2 TX Example 2 In this example, a single 183-Byte Ethernet packet will be transmitted. This packet is in a single buffer as follows: ■ ■ ■ 2-Byte “Data Start Offset” 183-Bytes of payload data 4-Byte “Buffer End Alignment” Figure 3.15, "TX Example 2" illustrates the TX command structure for this example, and also shows how data is passed to the TX data FIFO. Note that the packet resides in a single TX Buffer, therefore both the FS and LS bits are set in TX command ‘A’. Data Written to the Ethernet Controller TX Command 'A' Buffer End Alignment = 0 Data Start Offset = 6 First Segment = 1 Last Segment = 1 Buffer Size =183 TX Command 'B' Packet Length = 183 31 0 Data Passed to the TX Data FIFO TX Command 'A' TX Command 'B' TX Command 'A' TX Command 'B' 6-Byte Data Start Offset 183-Byte Payload Data 183-Byte Payload Data 3B End Padding NOTE: Extra bytes between buffers are not transmitted Figure 3.15 TX Example 2 Revision 1.1 (05-17-05) DATASHEET 50 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 3.12.7 TX Data FIFO Underrun If the MIL is not operating in store and forward mode, and the host is unable supply data at the Ethernet line rate, the TX data FIFO can underrun. If a TX underrun occurs, any further data written to the TX data FIFO for the offending frame (the frame being transmitted during the underrun) will automatically be discarded and no further data for that frame will be transmitted. TX data FIFO underrun is not an error condition, and data transmission will resume with the next valid TX command. In the case of a TX data FIFO underrun, the (TDFU) flag is set and can be used to generate a host interrupt. A TX data FIFO underrun is also indicated in the TX status word for the underrun frame. In the case of a TX underrun, the host is still required to write the remainder of the current TX packet to the LAN9118. Any remaining data from the underrun frame that is written to the LAN9118 will backup in the TX data FIFO (no more data is read until the next TX SOF [start of frame]). As the data backs up in the TX data FIFO, it will be visible in the TX_FIFO_INF register. In typical Driver usage, software will write the entire transmit packet to the LAN9118 and check INT_STS and see (from TDFU) that the underrun has occurred. Eventually, the driver will recognize the underrun. A '1' must then be written to the TXD_DUMP bit in the TX_CFG to flush the remaining data in the TX data FIFO (note that TX_ON may be kept on while flushing the remaining TX data FIFO contents). Once the leftover data from the underrun frame is purged, the LAN9118 is ready to send new transmit packets. It is advisable to clear the TDFU bit prior to transmitting any more data (assuming that SF=0) so that subsequent underruns can be detected, but this is not required by the hardware. 3.12.8 Transmitter Errors If the Transmitter Error (TXE) flag is asserted for any reason, the transmitter will continue operation. TX Error (TXE) will be asserted under the following conditions: ■ If the actual packet length count does not match the Packet Length field as defined in the TX command. Both TX command ‘A’ and TX command ‘B’ are required for each buffer in a given packet. TX command ‘B’ must be identical for every buffer in a given packet. If the TX command ‘B’ words do not match, the Ethernet controller will assert the Transmitter Error (TXE) flag. Host overrun of the TX data FIFO. Overrun of the TX status FIFO (unless TXSAO is enabled) ■ ■ ■ 3.12.9 Stopping and Starting the Transmitter To halt the transmitter, the host must set the TX_STOP bit in the TX_CFG register. The transmitter will finish sending the current frame (if there is a frame transmission in progress). When the transmitter has received the TX status for this frame, it will clear the TX_STOP and TX_ON bits, and will pulse the TXSTOP_INT. Once stopped, the host can optionally clear the TX status and TX data FIFOs. The host must re-enable the transmitter by setting the TX_ON bit. If the there are frames pending in the TX data FIFO (i.e., TX data FIFO was not purged), the transmission will resume with this data. 3.13 RX Data Path Operation When an Ethernet Packet is received, the MIL first begins to transfer the RX data. This data is loaded into the RX data FIFO. The RX data FIFO pointers are updated as data is written into the FIFO. The last transfer from the MIL is the RX status word. The LAN9118 implements a separate FIFO for the RX status words. The total available RX data and status queued in the RX FIFO can be read from the RX_FIFO_INF register. The host may read any number of available RX status words before reading the RX data FIFO. SMSC LAN9118 DATASHEET 51 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet The host must use caution when reading the RX data and status. The host must never read more data than what is available in the FIFOs. If this is attempted an underrun condition will occur. If this error occurs, the Ethernet controller will assert the Receiver Error (RXE) interrupt. If an underrun condition occurs, a soft reset is required to regain host synchronization. A configurable beginning offset is supported in the LAN9118. The RX data Offset field in the RX_CFG register controls the number of bytes that the beginning of the RX data buffer is shifted. The host can set an offset from 0-31 bytes. The offset may be changed in between RX packets, but it must not be changed during an RX packet read. The LAN9118 can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9118 is operating in a system that always performs multi-DWORD bursts. In such cases the LAN9118 must guarantee that it can transfer data in multiples of the Burst length regardless of the actual packet length. When configured to do so, the LAN9118 will add extra data at the end of the packet to allow the host to perform the necessary number of reads so that the Burst length is not cut short. Once a packet has been padded by the H/W, it is the responsibility of the host to interrogate the Packet length field in the RX status and determine how much padding to discard at the end of the Packet. It is possible to read multiple packets out of the RX data FIFO in one continuous stream. It should be noted that the programmed Offset and Padding will be added to each individual packet in the stream, since packet boundaries are maintained. 3.13.1 RX Slave PIO Operation Using PIO mode, the host can either implement a polling or interrupt scheme to empty the received packet out of the RX data FIFO. The host will remain in the idle state until it receives an indication (interrupt or polling) that data is available in the RX data FIFO. The host will then read the RX status FIFO to get the packet status, which will contain the packet length and any other status information. The host should perform the proper number of reads, as indicated by the packet length plus the start offset and the amount of optional padding added to the end of the frame, from the RX data FIFO. Revision 1.1 (05-17-05) DATASHEET 52 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet init Idle RX Interrupt Read RX Status DWORD Not Last Packet Last Packet Read RX Packet Figure 3.16 Host Receive Routine Using Interrupts init Read RX_FIFO_ INf Valid Status DWORD Read RX Status DWORD Not Last Packet Last Packet Read RX Packet Figure 3.17 Host Receive Routine with Polling 3.13.1.1 Receive Data FIFO Fast Forward The RX data path implements an automatic data discard function. Using the RX data FIFO Fast Forward bit (RX_FFWD) in the RX_DP_CTRL register, the host can instruct the LAN9118 to skip the packet at the head of the RX data FIFO. The RX data FIFO pointers are automatically incremented to the beginning of the next RX packet. SMSC LAN9118 DATASHEET 53 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet When performing a fast-forward, there must be at least 4 DWORDs of data in the RX data FIFO for the packet being discarded. For less than 4 DWORDs do not use RX_FFWD. In this case data must be read from the RX data FIFO and discarded using standard PIO read operations. After initiating a fast-forward operation, do not perform any reads of the RX data FIFO until the RX_FFWD bit is cleared. Other resources can be accessed during this time (i.e., any registers and/or the other three FIFOs). Also note that the RX_FFWD will only fast-forward the RX data FIFO, not the RX status FIFO. After an RX fast-forward operation the RX status must still be read from the RX status FIFO. The receiver does not have to be stopped to perform a fast-forward operation. 3.13.1.2 Force Receiver Discard (Receiver Dump) In addition to the Receive data Fast Forward feature, LAN9118 also implements a receiver "dump" feature. This feature allows the host processor to flush the entire contents of the RX data and RX status FIFOs. When activated, the read and write pointers for the RX data and status FIFOs will be returned to their reset state. To perform a receiver dump, the LAN9118 receiver must be halted. Once the receiver stop completion is confirmed, the RX_DUMP bit can be set in the RX_CFG register. The RX_DUMP bit is cleared when the dump is complete. For more information on stopping the receiver, please refer to Section 3.13.4, "Stopping and Starting the Receiver," on page 56. For more information on the RX_DUMP bit, please refer to Section 5.3.7, "RX_CFG—Receive Configuration Register," on page 73. 3.13.2 RX Packet Format The RX status words can be read from the RX status FIFO port, while the RX data packets can be read from the RX data FIFO. RX data packets are formatted in a specific manner before the host can read them. It is assumed that the host has previously read the associated status word from the RX status FIFO, to ascertain the data size and any error conditions. Revision 1.1 (05-17-05) DATASHEET 54 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Host Read Order 1st 2nd 31 0 Optional offset DWORD0 . . Optional offset DWORDn ofs + First Data DWORD . . . . Last Data DWORD Optional Pad DWORD0 . . Last Optional Pad DWORDn Figure 3.18 RX Packet Format 3.13.3 RX Status Format BITS 31 30 29:16 15 14 13 12 11 Reserved. This bit is reserved. Reads 0. DESCRIPTION Filtering Fail. When set, this bit indicates that the associated frame failed the address recognizing filtering. Packet Length. The size, in bytes, of the corresponding received frame. Error Status (ES). When set this bit indicates that the MIL has reported an error. This bit is the Internal logical “or” of bits 11,7,6 and 1. Reserved. These bits are reserved. Reads 0. Broadcast Frame. When set, this bit indicates that the received frame has a Broadcast address. Length Error (LE). When set, this bit indicates that the actual length does not match with the length/type field of the received frame. Runt Frame. When set, this bit indicates that frame was prematurely terminated before the collision window (64 bytes). Runt frames are passed on to the host only if the Pass Bad Frames bit MAC_CR Bit [16] is set. Multicast Frame. When set, this bit indicates that the received frame has a Multicast address. 10 SMSC LAN9118 DATASHEET 55 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 9:8 7 DESCRIPTION Reserved. These bits are reserved. Reads 0. Frame Too Long. When set, this bit indicates that the frame length exceeds the maximum Ethernet specification of 1518 bytes. This is only a frame too long indication and will not cause the frame reception to be truncated. Collision Seen. When set, this bit indicates that the frame has seen a collision after the collision window. This indicates that a late collision has occurred. Frame Type. When set, this bit indicates that the frame is an Ethernet-type frame (Length/Type field in the frame is greater than 1500). When reset, it indicates the incoming frame was an 802.3 type frame. This bit is not set for Runt frames less than 14 bytes. Receive Watchdog time-out. When set, this bit indicates that the incoming frame is greater than 2048 bytes through 2560 bytes, therefore expiring the Receive Watchdog Timer. MII Error. When set, this bit indicates that a receive error (RX_ER asserted) was detected during frame reception. Dribbling Bit. When set, this bit indicates that the frame contained a non-integer multiple of 8 bits. This error is reported only if the number of dribbling bits in the last byte is 4 in the MII operating mode, or at least 3 in the 10 Mbps operating mode. This bit will not be set when the collision seen bit[6] is set. If set and the CRC error bit is [1] reset, then the packet is considered to be valid. CRC Error. When set, this bit indicates that a CRC error was detected. This bit is also set when the RX_ER pin is asserted during the reception of a frame even though the CRC may be correct. This bit is not valid if the received frame is a Runt frame, or a late collision was detected or when the Watchdog Time-out occurs. Reserved. These bits are reserved. Reads 0 6 5 4 3 2 1 0 3.13.4 Stopping and Starting the Receiver To stop the receiver, the host must clear the RXEN bit in the MAC Control Register. When the receiver is halted, the RXSTOP_INT will be pulsed. Once stopped, the host can optionally clear the RX status and RX data FIFOs. The host must re-enable the receiver by setting the RXEN bit. 3.13.5 Receiver Errors If the Receiver Error (RXE) flag is asserted for any reason, the receiver will continue operation. RX Error (RXE) will be asserted under the following conditions: ■ ■ ■ A host underrun of RX data FIFO A host underrun of the RX status FIFO An overrun of the RX status FIFO It is the duty of the host to identify and resolve any error conditions. Revision 1.1 (05-17-05) DATASHEET 56 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 4 Internal Ethernet PHY 4.1 Top Level Functional Description Functionally, the internal PHY can be divided into the following sections: ■ ■ ■ ■ ■ 100Base-TX transmit and receive 10Base-T transmit and receive Internal MII interface to the Ethernet Media Access Controller Auto-negotiation to automatically determine the best speed and duplex possible Management Control to read status registers and write control registers 100M PLL TX_CLK MAC Internal MII 25 MHz by 4 bits MII 25MHz by 4 bits 4B/5B Encoder 25MHz by 5 bits Scrambler and PISO 125 Mbps Serial NRZI Converter NRZI MLT-3 Converter MLT-3 MLT-3 Tx Driver MLT-3 Magnetics RJ45 MLT-3 CAT-5 Figure 4.1 100Base-TX Data Path 4.2 4.2.1 100Base-TX Transmit The data path of the 100Base-TX is shown in Figure 4.1. Each major block is explained below. 4B/5B Encoding The transmit data passes from the MII block to the 4B/5B encoder. This block encodes the data from 4-bit nibbles to 5-bit symbols (known as “code-groups”) according to Table 4.1. Each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for control information or are not valid. The first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through F. The remaining code-groups are given letter designations with slashes on either side. For example, an IDLE code-group is /I/, a transmit error code-group is /H/, etc. The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is bypassed the 5th transmit data bit is equivalent to TX_ER. SMSC LAN9118 DATASHEET 57 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 4.1 4B/5B Code Table CODE GROUP 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 SYM 0 1 2 3 4 5 6 7 8 9 A B C D E F I J K T IDLE First nibble of SSD, translated to “0101” following IDLE, else RX_ER Second nibble of SSD, translated to “0101” following J, else RX_ER First nibble of ESD, causes de-assertion of CRS if followed by /R/, else assertion of RX_ER Second nibble of ESD, causes deassertion of CRS if following /T/, else assertion of RX_ER Transmit Error Symbol INVALID, RX_ER if during RX_DV INVALID, RX_ER if during RX_DV INVALID, RX_ER if during RX_DV INVALID, RX_ER if during RX_DV INVALID, RX_ER if during RX_DV INVALID, RX_ER if during RX_DV INVALID, RX_ER if during RX_DV 58 RECEIVER INTERPRETATION 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DATA 0 1 2 3 4 5 6 7 8 9 A B C D E F TRANSMITTER INTERPRETATION 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DATA Sent after /T/R until TX_EN Sent for rising TX_EN Sent for rising TX_EN Sent for falling TX_EN 00111 R Sent for falling TX_EN 00100 00110 11001 00000 00001 00010 00011 00101 Revision 1.1 (05-17-05) H V V V V V V V Sent for rising TX_ER INVALID INVALID INVALID INVALID INVALID INVALID INVALID SMSC LAN9118 DATASHEET High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 4.1 4B/5B Code Table (continued) CODE GROUP 01000 01100 10000 SYM V V V RECEIVER INTERPRETATION INVALID, RX_ER if during RX_DV INVALID, RX_ER if during RX_DV INVALID, RX_ER if during RX_DV INVALID INVALID INVALID TRANSMITTER INTERPRETATION 4.2.2 Scrambling Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being radiated by the physical wiring. The scrambler also performs the Parallel In Serial Out conversion (PISO) of the data. 4.2.3 NRZI and MLT3 Encoding The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”. 4.2.4 100M Transmit Driver The MLT3 data is then passed to the analog transmitter, which launches the differential MLT-3 signal, on outputs TXP and TXN, to the twisted pair media via a 1:1 ratio isolation transformer. The 10BaseT and 100Base-TX signals pass through the same transformer so that common “magnetics” can be used for both. The transmitter drives into the 100Ω impedance of the CAT-5 cable. Cable termination and impedance matching require external components. 4.2.5 100M Phase Lock Loop (PLL) The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. SMSC LAN9118 DATASHEET 59 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet RX_CLK 100M PLL MAC Internal MII 25MHz by 4 bits MII 25MHz by 4 bits 125 Mbps Serial 4B/5B Decoder 25MHz by 5 bits Descrambler and SIPO NRZI Converter NRZI MLT-3 Converter MLT-3 DSP: Timing recovery, Equalizer and BLW Correction A/D Converter MLT-3 Magnetics MLT-3 RJ45 MLT-3 CAT-5 6 bit Data Figure 4.2 Receive Data Path 4.3 4.3.1 100Base-TX Receive The receive data path is shown in Figure 4.2. Detailed descriptions are given below. 100M Receive Input The MLT-3 from the cable is fed into the PHY (on inputs RXP and RXN) via a 1:1 ratio transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64level quanitizer it generates 6 digital bits to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC can be used. 4.3.2 Equalizer, Baseline Wander Correction and Clock and Data Recovery The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m and 150m. If the DC content of the signal is such that the low-frequency components fall below the low frequency pole of the isolation transformer, then the droop characteristics of the transformer will become significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the received data, the PHY corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD defined “killer packet” with no bit errors. The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing unit of the DSP, selects the optimum phase for sampling the data. This is used as the received recovered clock. This clock is used to extract the serial data from the received signal. 4.3.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. Revision 1.1 (05-17-05) DATASHEET 60 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 4.3.4 Descrambling The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. During reception of IDLE (/I/) symbols. the descrambler synchronizes its descrambler key to the incoming stream. Once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data. Special logic in the descrambler ensures synchronization with the remote PHY by searching for IDLE symbols within a window of 4000 bytes (40us). This window ensures that a maximum packet size of 1514 bytes, allowed by the IEEE 802.3 standard, can be received with no interference. If no IDLEsymbols are detected within this time-period, receive operation is aborted and the descrambler re-starts the synchronization process. The descrambler can be bypassed by setting bit 0 of register 31. 4.3.5 Alignment The de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /J/K/ Start-of-Stream Delimiter (SSD) pair at the start of a packet. Once the code-word alignment is determined, it is stored and utilized until the next start of frame. 4.3.6 5B/4B Decoding The 5-bit code-groups are translated into 4-bit data nibbles according to the 4B/5B table. The SSD, /J/K/, is translated to “0101 0101” as the first 2 nibbles of the MAC preamble. Reception of the SSD causes the PHY to assert the internal RX_DV signal, indicating that valid data is available on the Internal RXD bus. Successive valid code-groups are translated to data nibbles. Reception of either the End of Stream Delimiter (ESD) consisting of the /T/R/ symbols, or at least two /I/ symbols causes the PHY to de-assert the internal carrier sense and RX_DV. These symbols are not translated into data. 4.4 10Base-T Transmit Data to be transmitted comes from the MAC layer controller. The 10Base-T transmitter receives 4-bit nibbles from the MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream. The data stream is then Manchester-encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. The 10M transmitter uses the following blocks: ■ ■ ■ ■ MII (digital) TX 10M (digital) 10M Transmitter (analog) 10M PLL (analog) 4.4.1 10M Transmit Data across the internal MII bus The MAC controller drives the transmit data onto the internal TXD BUS. When the controller has driven TX_EN high to indicate valid data, the data is latched by the MII block on the rising edge of TX_CLK. The data is in the form of 4-bit wide 2.5MHz data. 4.4.2 Manchester Encoding The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz clock. This is used to Manchester encode the NRZ data stream. When no data is being transmitted SMSC LAN9118 DATASHEET 61 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet (TX_EN is low), the TX10M block outputs Normal Link Pulses (NLPs) to maintain communications with the remote link partner. 4.4.3 10M Transmit Drivers The Manchester encoded data is sent to the analog transmitter where it is shaped and filtered before being driven out as a differential signal across the TXP and TXN outputs. 4.5 10Base-T Receive The 10Base-T receiver gets the Manchester- encoded analog signal from the cable via the magnetics. It recovers the receive clock from the signal and uses this clock to recover the NRZI data stream. This 10M serial data is converted to 4-bit data nibbles which are passed to the controller across the MII at a rate of 2.5MHz. This 10M receiver uses the following blocks: ■ ■ ■ ■ Filter and SQUELCH (analog) 10M PLL (analog) RX 10M (digital) MII (digital) 4.5.1 10M Receive Input and Squelch The Manchester signal from the cable is fed into the PHY (on inputs RXP and RXN) via 1:1 ratio magnetics. It is first filtered to reduce any out-of-band noise. It then passes through a SQUELCH circuit. The SQUELCH is a set of amplitude and timing comparators that normally reject differential voltage levels below 300mV and detect and recognize differential voltages above 585mV. 4.5.2 Manchester Decoding The output of the SQUELCH goes to the RX10M block where it is validated as Manchester encoded data. The polarity of the signal is also checked. If the polarity is reversed (local RXP is connected to RXN of the remote partner and vice versa), then this is identified and corrected. The reversed condition is indicated by the flag “XPOL“, bit 4 in register 27. The 10M PLL is locked onto the received Manchester signal and from this, generates the received 20MHz clock. Using this clock, the Manchester encoded data is extracted and converted to a 10MHz NRZI data stream. It is then converted from serial to 4-bit wide parallel data. The RX10M block also detects valid 10Base-T IDLE signals - Normal Link Pulses (NLPs) - to maintain the link. 4.5.3 Jabber Detection Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition, that results in holding the TX_EN input for a long period. Special logic is used to detect the jabber state and abort the transmission to the line, within 45ms. Once TX_EN is deasserted, the logic resets the jabber condition. 4.6 Auto-negotiation The purpose of the Auto-negotiation function is to automatically configure the PHY to the optimum link parameters based on the capabilities of its link partner. Auto-negotiation is a mechanism for exchanging configuration information between two link-partners and automatically selecting the highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification. Revision 1.1 (05-17-05) DATASHEET 62 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Once auto-negotiation has completed, information about the resolved link can be passed back to the controller via the internal Serial Management Interface (SMI). The results of the negotiation process are reflected in the Speed Indication bits in register 31, as well as the Link Partner Ability Register (Register 5). The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC controller. The advertised capabilities of the PHY are stored in register 4 of the SMI registers. The default advertised by the PHY is determined by user-defined on-chip signal options. The following blocks are activated during an Auto-negotiation session: ■ ■ ■ ■ ■ ■ ■ Auto-negotiation (digital) 100M ADC (analog) 100M PLL (analog) 100M equalizer/BLW/clock recovery (DSP) 10M SQUELCH (analog) 10M PLL (analog) 10M Transmitter (analog) When enabled, auto-negotiation is started by the occurrence of one of the following events: ■ ■ ■ ■ ■ Hardware reset Software reset Power-down reset Link status down Setting register 0, bit 9 high (auto-negotiation restart) On detection of one of these events, the PHY begins auto-negotiation by transmitting bursts of Fast Link Pulses (FLP). These are bursts of link pulses from the 10M transmitter. They are shaped as Normal Link Pulses and can pass uncorrupted down CAT-3 or CAT-5 cable. A Fast Link Pulse Burst consists of up to 33 pulses. The 17 odd-numbered pulses, which are always present, frame the FLP burst. The 16 even-numbered pulses, which may be present or absent, contain the data word being transmitted. Presence of a data pulse represents a “1”, while absence represents a “0”. The data transmitted by an FLP burst is known as a “Link Code Word.” These are defined fully in IEEE 802.3 clause 28. In summary, the PHY advertises 802.3 compliance in its selector field (the first 5 bits of the Link Code Word). It advertises its technology ability according to the bits set in register 4 of the SMI registers. There are 4 possible matches of the technology abilities. In the order of priority these are: ■ ■ ■ ■ 100M full-duplex (Highest priority) 100M half-duplex 10M full-duplex 10M half-duplex If the full capabilities of the PHY are advertised (100M, full-duplex), and if the link partner is capable of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode. If the link partner is capable of half and full-duplex modes, then auto-negotiation selects full-duplex as the highest performance operation. Once a capability match has been determined, the link code words are repeated with the acknowledge bit set. Any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received. Writing register 4 bits [8:5] allows software control of the capabilities advertised by the PHY. Writing register 4 does not automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new SMSC LAN9118 DATASHEET 63 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet abilities will be advertised. Auto-negotiation can also be disabled via software by clearing register 0, bit 12. The LAN9118 does not support “Next Page" capability. 4.7 Parallel Detection If the LAN9118 is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE standard. This ability is known as “Parallel Detection. This feature ensures inter operability with legacy link partners. If a link is formed via parallel detection, then bit 0 in register 6 is cleared to indicate that the Link Partner is not capable of auto-negotiation. The Ethernet MAC has access to this information via the management interface. If a fault occurs during parallel detection, bit 4 of register 6 is set. Register 5 is used to store the Link Partner Ability information, which is coded in the received FLPs. If the Link Partner is not auto-negotiation capable, then register 5 is updated after completion of parallel detection to reflect the speed capability of the Link Partner. 4.7.1 Re-starting Auto-negotiation Auto-negotiation can be re-started at any time by setting register 0, bit 9. Auto-negotiation will also restart if the link is broken at any time. A broken link is caused by signal loss. This may occur because of a cable break, or because of an interruption in the signal transmitted by the Link Partner. Autonegotiation resumes in an attempt to determine the new link configuration. If the management entity re-starts Auto-negotiation by writing to bit 9 of the control register, the LAN9118 will respond by stopping all transmission/receiving operations. Once the break_link_timer is done, in the Auto-negotiation state-machine (approximately 1200ms) the auto-negotiation will re-start. The Link Partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negotiation. 4.7.2 Disabling Auto-negotiation Auto-negotiation can be disabled by setting register 0, bit 12 to zero. The device will then force its speed of operation to reflect the information in register 0, bit 13 (speed) and register 0, bit 8 (duplex). The speed and duplex bits in register 0 should be ignored when auto-negotiation is enabled. 4.7.3 Half vs. Full-Duplex half-duplex operation relies on the CSMA/CD (Carrier Sense Multiple Access / Collision Detect) protocol to handle network traffic and collisions. In this mode, the carrier sense signal, CRS, responds to both transmit and receive activity. In this mode, If data is received while the PHY is transmitting, a collision results. In full-duplex mode, the PHY is able to transmit and receive data simultaneously. In this mode, CRS responds only to receive activity. The CSMA/CD protocol does not apply and collision detection is disabled. Revision 1.1 (05-17-05) DATASHEET 64 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 5 Register Description The following section describes all LAN9118 registers and data ports. FCh RESERVED B4h B0h ACh A8h A4h A0h EEPROM Port MAC CSRPort 50h 4Ch 48h 44h 40h 3Ch TX Status TX Status RX Status RX Status FIFO PEEK FIFO Port FIFO PEEK FIFO Port TX Data FIFO Alias Ports 24h 20h 1Ch TX Data FIFO Port RX Data FIFO Alias Ports 04h Base + 00h RX Data FIFO Port Figure 5.1 LAN9118 Memory Map SMSC LAN9118 DATASHEET 65 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.1 SYMBOL RO WO R/W R/WC RC LL LH SC NASR Reserved Bits Reserved Registers Register Nomenclature and Access Attributes DESCRIPTION Read Only: If a register is read only, writes to this register have no effect. Write Only: If a register is write only, reads always return 0. Read/Write: A register with this attribute can be read and written Read/Write Clear: A register bit with this attribute can be read and written. However, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. Read to Clear: A register bit with this attribute is cleared when read. Latch Low: Clear on read of register Latch High: Clear on read of register Self-Clearing Not Affected by Software Reset Unless otherwise stated, reserved fields must be written with zeros to ensure future compatibility. The value of reserved bits is not guaranteed on a read. In addition to reserved bits within a register, the LAN9118 contains address locations in the configuration space that are marked “Reserved. When a “Reserved” register location is read, a random value can be returned. Registers that are marked as “Reserved” must not be modified by system software. Writes to “Reserved” registers may cause system failure. Upon a Reset (System reset, Software Reset, or POR), the LAN9118 sets its internal configuration registers to predetermined default states. The default state represents the minimum functionality feature set required to successfully bring up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software to properly determine the operating parameters and optional system features that are applicable, and to program the LAN9118 registers accordingly. Default Value Upon Reset 5.2 RX and TX FIFO Ports The LAN9118 contains four host-accessible FIFOs: the RX Status, RX data, TX Status, and TX data FIFOs. The sizes of the RX and TX data FIFOs, as well as the RX Status FIFO are configurable through the CSRs. 5.2.1 RX FIFO Ports The RX data Path consists of two Read-Only FIFOs; the RX Status and data. The RX Status FIFO can be read from two locations. The RX Status FIFO Port will perform a destructive read, thus “Popping” the data from the RX Status FIFO. There is also the RX Status FIFO PEEK location. This location allows a non-destructive read of the top (oldest) location of the FIFO. The RX data FIFO only allows destructive reads. It is aliased in 8 DWORD locations (16 WORD locations in 16-bit mode) from the 00h offset to 1Ch offset. The host may access any of the 8(16) locations since they all contain the same data and perform the same function. Revision 1.1 (05-17-05) DATASHEET 66 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.2.2 TX FIFO Ports The TX data Path consists of two FIFOs, the TX status and data. The TX Status FIFO can be read from two locations. The TX Status FIFO Port will perform a destructive read, thus “Popping” the data from the TX Status FIFO. There is also the TX Status FIFO PEEK location. This location allows a nondestructive read of the top (oldest) location of the FIFO. The TX data FIFO is Write Only. It is aliased in 8 DWORD locations (16 WORD locations in 16-bit mode) from the 20h offset to 3Ch offset. The host may write to any of the 8(16) locations since they all access the same TX data FIFO location and perform the same function. 5.3 System Control and Status Registers Table 5.1, "LAN9118 Direct Address Register Map", lists the registers that are directly addressable by the host bus. Table 5.1 LAN9118 Direct Address Register Map CONTROL AND STATUS REGISTERS BASE ADDRESS + OFFSET 50h SYMBOL ID_REV REGISTER NAME Chip ID and Revision. DEFAULT See “ID_REV— Chip ID and Revision” on page 68. 00000000h 00000000h 00000000h 87654321h 48000000h 00000000h 00000000h 00000800h 00000000h 00000000h 00001200h 00000000h 00000000h 0000FFFFh 0000FFFFh 00000000h Revision 1.1 (05-17-05) 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h SMSC LAN9118 IRQ_CFG INT_STS INT_EN RESERVED BYTE_TEST FIFO_INT RX_CFG TX_CFG HW_CFG RX_DP_CTL RX_FIFO_INF TX_FIFO_INF PMT_CTRL GPIO_CFG GPT_CFG GPT_CNT RESERVED ENDIAN Main Interrupt Configuration Interrupt Status Interrupt Enable Register Reserved for future use Read-only byte order testing register FIFO Level Interrupts Receive Configuration Transmit Configuration Hardware Configuration RX Datapath Control Receive FIFO Information Transmit FIFO Information Power Management Control General Purpose IO Configuration General Purpose Timer Configuration General Purpose Timer Count Reserved for future use ENDIAN 67 DATASHEET High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 5.1 LAN9118 Direct Address Register Map (continued) CONTROL AND STATUS REGISTERS BASE ADDRESS + OFFSET 9Ch A0h A4h A8h ACh B0h B4h B8h - FCh SYMBOL FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG E2P_CMD E2P_DATA RESERVED REGISTER NAME Free Run Counter RX Dropped Frames Counter MAC CSR Synchronizer Command (MAC CSR’s are indexed through this register) MAC CSR Synchronizer Data Automatic Flow Control Configuration EEPROM command (The EEPROM is indexed through this register) EEPROM Data Reserved for future use DEFAULT 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h - 5.3.1 ID_REV—Chip ID and Revision Offset: 50h Size: 32 bits This register contains the ID and Revision fields for this design. BITS 31-16 15-0 DESCRIPTION Chip ID. This read-only field identifies this design Chip Revision. This is the current revision of the chip. TYPE RO RO DEFAULT 0118h 0001h Revision 1.1 (05-17-05) DATASHEET 68 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.2 IRQ_CFG—Interrupt Configuration Register Offset: 54h Size: 32 bits This register configures and indicates the state of the IRQ signal. BITS 31:24 DESCRIPTION Interrupt Deassertion Interval (INT_DEAS). This field determines the Interrupt Deassertion Interval for the Interrupt Request in multiples of 10 microseconds. Writing zeros to this field disables the INT_DEAS Interval and resets the interval counter. Any pending interrupts are then issued. If a new, nonzero value is written to the INT_DEAS field, any subsequent interrupts will obey the new setting. Note: 23-15 14 The Interrupt Deassertion interval does not apply to the PME interrupt. RO TYPE R/W DEFAULT 0 Reserved Interrupt Deassertion Interval Clear (INT_DEAS_CLR). Writing a one to this register clears the de-assertion counter in the IRQ Controller, thus causing a new de-assertion interval to begin (regardless of whether or not the IRQ Controller is currently in an active de-assertion interval). Interrupt Deassertion Status (INT_DEAS_STS). When set, this bit indicates that the INT_DEAS is currently in a deassertion interval, and any interrupts (as indicated by the IRQ_INT and INT_EN bits) will not be delivered to the IRQ pin. When cleared, the INT_DEAS is currently not in a deassertion interval, and enabled interrupts will be delivered to the IRQ pin. Master Interrupt (IRQ_INT). This read-only bit indicates the state of the internal IRQ line. When set high, one of the enabled interrupts is currently active. This bit will respond to the associated interrupts regardless of the IRQ_EN field. This bit is not affected by the setting of the INT_DEAS field. Reserved IRQ Enable (IRQ_EN) – This bit controls the final interrupt output to the IRQ pin. When cleared, the IRQ output is disabled and will be permanently deasserted. This bit only controls the external IRQ signal, and has no effect on any of the internal interrupt status bits. Reserved IRQ Polarity (IRQ_POL) – When cleared, enables the IRQ line to function as an active low output. When set, the IRQ output is active high. When IRQ is configured as an open-drain output this field is ignored, and the interrupt output is always active low. Reserved IRQ Buffer Type (IRQ_TYPE) – When cleared, enables IRQ to function as an open-drain buffer for use in a Wired-Or Interrupt configuration. When set, the IRQ output is a Push-Pull driver. When configured as an open-drain output the IRQ_POL field is ignored, and the interrupt output is always active low. 13 SC 0 12 RO 0 11-9 8 RO R/W 0 7-5 4 RO R/W NASR 0 3-1 0 RO R/W NASR 0 SMSC LAN9118 DATASHEET 69 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.3 INT_STS—Interrupt Status Register Offset: 58h Size: 32 bits This register contains the current status of the generated interrupts. Writing a 1 to the corresponding bits acknowledges and clears the interrupt. BITS 31 30-26 25 24 23 DESCRIPTION Software Interrupt (SW_INT). This interrupt is generated when the SW_INT_EN bit is set high. Writing a one clears this interrupt. Reserved TX Stopped (TXSTOP_INT). This interrupt is issued when STOP_TX bit in TX_CFG is set, and the transmitter is halted. RX Stopped (RXSTOP_INT). This interrupt is issued when the receiver is halted. RX Dropped Frame Counter Halfway (RXDFH_INT). This interrupt is issued when the RX Dropped Frames Counter counts past its halfway point (7FFFFFFFh to 80000000h). Reserved TX IOC Interrupt (TX_IOC). When a buffer with the IOC flag set has finished being loaded into the TX FIFO, this interrupt is generated. RX DMA Interrupt (RXD_INT). This interrupt is issued when the amount of data programmed in the RX DMA Count (RX_DMA_CNT) field of the RX_CFG register has been transferred out of the RX FIFO. GP Timer (GPT_INT). This interrupt is issued when the General Purpose timer wraps past zero to FFFFh. PHY (PHY_INT). Indicates a PHY Interrupt event. Power Management Event Interrupt (PME_INT). This interrupt is issued when a Power Management Event is detected as configured in the PMT_CTRL register. This interrupt functions independent of the PME signal, and will still function if the PME signal is disabled. Writing a '1' clears this bit regardless of the state of the PME hardware signal. Notes: ■ Detection of a Power Management Event, and assertion of the PME signal will not wakeup the LAN9118. The LAN9118 will only wake up when it detects a host write cycle of any data to the BYTE_TEST register. ■ The Interrupt Deassertion interval does not apply to the PME interrupt. FIFO overflows. TYPE R/WC RO R/WC R/WC R/WC DEFAULT 0 0 0 0 22 21 20 RO R/WC R/WC 0 0 0 19 18 17 R/WC RO R/WC 0 0 0 16 15 14 TX Status FIFO Overflow (TXSO). Generated when the TX Status Receive Watchdog Time-out (RWT). Interrupt is generated when a packet larger than 2048 bytes has been received. R/WC R/WC R/WC 0 0 0 Receiver Error (RXE). Indicates that the receiver has encountered an error. Please refer to Section 3.13.5, "Receiver Errors," on page 56 for a description of the conditions that will cause an RXE. 13 Transmitter Error (TXE). When generated, indicates that the transmitter has encountered an error. Please refer to Section 3.12.8, "Transmitter Errors," on page 51, for a description of the conditions that will cause a TXE. R/WC 0 Revision 1.1 (05-17-05) DATASHEET 70 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 12 11 10 9 8 7 6 5 4 3 2-0 Reserved DESCRIPTION TYPE RO R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC DEFAULT 0 0 0 0 0 0 0 0 0 000 TX Data FIFO Underrun Interrupt (TDFU). Generated when the TX data FIFO underruns. TX Data FIFO Overrun Interrupt (TDFO). Generated when the TX data FIFO is full, and another write is attempted. TX Data FIFO Available Interrupt (TDFA). Generated when the TX data FIFO available space is greater than the programmed level. TX Status FIFO Full Interrupt (TSFF). Generated when the TX Status FIFO is full. TX Status FIFO Level Interrupt (TSFL). Generated when the TX Status FIFO reaches the programmed level. RX Dropped Frame Interrupt (RXDF_INT). This interrupt is issued whenever a receive frame is dropped. RX Data FIFO Level Interrupt (RDFL). Generated when the RX FIFO reaches the programmed level. RX Status FIFO Full Interrupt (RSFF). Generated when the RX Status FIFO is full. RX Status FIFO Level Interrupt (RSFL). Generated when the RX Status FIFO reaches the programmed level. GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These interrupts are configured through the GPIO_CFG register. 5.3.4 INT_EN—Interrupt Enable Register Offset: 5Ch Size: 32 bits This register contains the interrupt masks for IRQ. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ. Bits in the INT_STS register will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this register. BITS 31 30:26 25 24 23 22 21 20 19 DESCRIPTION Software Interrupt (SW_INT_EN) Reserved TX Stopped Interrupt Enable (TXSTOP_INT_EN) RX Stopped Interrupt Enable (RXSTOP_INT_EN) RX Dropped Frame Counter Halfway Interrupt Enable (RXDFH_INT_EN). Reserved TX IOC Interrupt Enable (TIOC_INT_EN) RX DMA Interrupt (RXD_INT). GP Timer (GPT_INT_EN) 71 TYPE R/W RO R/W R/W R/W RO R/W R/W R/W DEFAULT 0 0 0 0 0 0 0 0 SMSC LAN9118 DATASHEET Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2-0 DESCRIPTION PHY (PHY_INT_EN) Power Management Event Interrupt Enable (PME_INT_EN) TX Status FIFO Overflow (TXSO_EN) Receive Watchdog Time-out Interrupt (RWT_INT_EN) Receiver Error Interrupt (RXE_INT_EN) Transmitter Error Interrupt (TXE_INT_EN) Reserved TX Data FIFO Underrun Interrupt (TDFU_INT_EN) TX Data FIFO Overrun Interrupt (TDFO_INT_EN) TX Data FIFO Available Interrupt (TDFA_INT_EN) TX Status FIFO Full Interrupt (TSFF_INT_EN) TX Status FIFO Level Interrupt (TSFL_INT_EN) RX Dropped Frame Interrupt Enable (RXDF_INT_EN) RX Data FIFO Level Interrupt (RDFL_INT_EN) RX Status FIFO Full Interrupt (RSFF_INT_EN) RX Status FIFO Level Interrupt (RSFL_INT_EN) GPIO [2:0] (GPIOx_INT_EN). TYPE R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 5.3.5 BYTE_TEST—Byte Order Test Register Offset: 64h Size: 32 bits This register can be used to determine the byte ordering of the current configuration BITS 31:0 DESCRIPTION Byte Test TYPE RO DEFAULT 87654321h Revision 1.1 (05-17-05) DATASHEET 72 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.6 FIFO_INT—FIFO Level Interrupts Offset: 68h Size: 32 bits This register configures the limits where the FIFO Controllers will generate system interrupts. BITS 31-24 DESCRIPTION TX Data Available Level. The value in this field sets the level, in number of 64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be generated. When the TX data FIFO free space is greater than this value a TX FIFO Available interrupt (TDFA) will be generated. TX Status Level. The value in this field sets the level, in number of DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be generated. When the TX Status FIFO used space is greater than this value an TX Status FIFO Level interrupt (TSFL) will be generated. RX Space Available Level. The value in this field sets the level, in number of 64 Byte blocks, at which the RX data FIFO Level interrupt (RDFL) will be generated. When the RX data FIFO free space is less than this value an RX data FIFO Level interrupt (RDFL) will be generated. RX Status Level. The value in this field sets the level, in number of DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be generated. When the RX Status FIFO used space is greater than this value an RX Status FIFO Level interrupt (RSFL) will be generated. TYPE R/W DEFAULT 48h 23-16 R/W 00h 15-8 R/W 00h 7-0 R/W 00h 5.3.7 RX_CFG—Receive Configuration Register Offset: 6Ch Size: 32 bits This register controls the LAN9118 receive engine. BITS 31:30 DESCRIPTION RX End Alignment. This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9118 will add extra DWORDs of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORDs. This mechanism can be used to maintain cache line alignment on host processors. Please refer to Table 5.2 for bit definitions Note: The desired RX End Alignment must be set before reading a packet. The RX end alignment can be changed between reading receive packets, but must not be changed if the packet is partially read. RO R/W 000h TYPE R/W DEFAULT 00b 29-28 27-16 Reserved RX DMA Count (RX_DMA_CNT). This 12-bit field indicates the amount of data, in DWORDS, to be transferred out of the RX data FIFO before asserting the RXD_INT. After being set, this field is decremented for each DWORD of data that is read from the RX data FIFO. This field can be overwritten with a new value before it reaches zero. SMSC LAN9118 DATASHEET 73 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 15 DESCRIPTION Force RX Discard (RX_DUMP). This self-clearing bit clears the RX data and status FIFOs of all pending data. When a ‘1’ is written, the RX data and status pointers are cleared to zero. Note: Please refer to section “Force Receiver Discard (Receiver Dump)” on page 54 for a detailed description regarding the use of RX_DUMP. TYPE SC DEFAULT 0 14-13 12-8 Reserved RX Data Offset (RXDOFF). This field controls the offset value, in bytes, that is added to the beginning of an RX data packet. The start of the valid data will be shifted by the number of bytes specified in this field. An offset of 0-31 bytes is a valid number of offset bytes. Note: The two LSBs of this field (D[9:8]) must not be modified while the RX is running. The receiver must be halted, and all data purged before these two bits can be modified. The upper three bits (DWORD offset) may be modified while the receiver is running. Modifications to the upper bits will take affect on the next DWORD read. RO R/W 00000 7-0 Reserved RO - Table 5.2 RX Alignment Bit Definitions [31] 0 0 1 1 [30] 0 1 0 1 End Alignment 4-byte alignment 16-byte alignment 32-byte alignment Reserved 5.3.8 TX_CFG—Transmit Configuration Register Offset: 70h Size: 32 bits This register controls the transmit functions on the LAN9118 Ethernet Controller. BITS 31-16 15 DESCRIPTION Reserved. Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX status pointers are cleared to zero. Force TX Data Discard (TXD_DUMP). This self-clearing bit clears the TX data FIFO of all pending data. When a ‘1’ is written, the TX data pointers are cleared to zero. Reserved TYPE RO SC DEFAULT 0 14 SC 0 13-3 RO - Revision 1.1 (05-17-05) DATASHEET 74 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 2 DESCRIPTION TX Status Allow Overrun (TXSAO). When this bit is cleared, data transmission is suspended if the TX Status FIFO becomes full. Setting this bit high allows the transmitter to continue operation with a full TX Status FIFO. Note: This bit does not affect the operation of the TX Status FIFO Full interrupt. TYPE R/W DEFAULT 0 1 Transmitter Enable (TX_ON). When this bit is set (1), the transmitter is enabled. Any data in the TX FIFO will be sent. This bit is cleared automatically when STOP_TX is set and the transmitter is halted. Stop Transmitter (STOP_TX). When this bit is set (1), the transmitter will finish the current frame, and will then stop transmitting. When the transmitter has stopped this bit will clear. All writes to this bit are ignored while this bit is high. R/W 0 0 SC 0 5.3.9 HW_CFG—Hardware Configuration Register Offset: 74h Size: 32 bits This register controls the hardware configuration of the LAN9118 Ethernet Controller BITS 31-22 21 DESCRIPTION Reserved Transmit Threshold Mode (TTM). This bit is used to control the transmit threshold the MIL uses as shown in the two tables in the TR field of this register. This bit is ignored when the SF bit is set (1). This bit should be set to '1' when operating in 10Mbps mode, and cleared to '0' when operating in 100Mbps mode if the SF bit cleared. TYPE RO R/W DEFAULT 0 20 Store and Forward (SF). When set, this bit instructs the MIL to store a frame of transmit data in the MIL buffer before forwarding to its final destination. If this bit is set, the MIL buffers the entire frame before transmitting. TTM and TR (see bits 21,13, and 12) are treated as Don’t Cares once the SF mode is selected. If this bit is reset, the MAC initiates transmission before it receives the entire frame from the HBI (Host Bus Interface). TTM and TR (see bit 21,13, and 12) determine when the MIL initiates the transmission. If the host cannot keep up with the MAC transmitting the Ethernet Packet, there is a risk of an Underrun Error. R/W 0 16-19 TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values to a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the space allocated by TX_FIF_SIZ, and the TX data FIFO consumes the remaining space specified by TX_FIF_SZ. The minimum size of the TX FIFOs is 2KB (TX data and status combined). The TX data FIFO is used for both TX data and TX commands. The RX status and data FIFOs consume the remaining space, which is equal to 16KB – TX_FIF_SIZ. See section 5.3.9.1 Allowable settings for Configurable FIFO Memory Allocationon page 77 for more information. R/W 5h SMSC LAN9118 DATASHEET 75 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 15-14 13-12 DESCRIPTION Reserved Threshold Control Bits (TR). These control the transmit threshold values the MIL should use. These bits are used when the SF bit is reset. The host can program the Transmit threshold by setting these bits. The intent is to allow the MIL to transfer data to the final destination only after the threshold value is met. In 10Mbps mode (TTM = 1) the threshold is set as follows: TYPE RO R/W DEFAULT 00 [13] 0 [12] Threshold (DWORDS) 0 1 0 1 012h 018h 020h 028h 0 1 1 In 100Mbps mode (TTM = 0) the threshold is set by as follows: [13] 0 [12] Threshold (DWORDS) 0 1 0 1 020h 040h 080h 100h 0 1 1 11-3 2 Reserved 32/16-bit Mode. When set, the LAN9118 is set for 32-bit operation. When clear, it is configured for 16-bit operation. This field is the value of the D32/nD16 strap. Soft Reset Time-out (SRST_TO). If a software reset is attempted when the internal PHY is not in the operational state (RX_CLK and TX_CLK running), the reset will not complete and the soft reset operation will time-out and this bit will be set to a ‘1’. The host processor must correct the problem and issue another soft reset. Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset generates a full reset of the MAC CSR’s. The SCSR’s (system command and status registers) are reset except for any NASR bits. Soft reset also clears any TX or RX errors (TXE/RXE). This bit is self-clearing. Notes: ■ Do not attempt a soft reset unless the internal PHY is fully awake and operational. After a PHY reset, or when returning from a reduced power state, the PHY must be given adequate time to return to the operational state before a soft reset can be issued. The internal RX_CLK and TX_CLK signals must be running for a proper software reset. Please refer to Section 6.8, "Reset Timing," on page 119 for details on PHY reset timing. ■ The LAN9118 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. RO RO - 1 RO 0 0 SC 0 Revision 1.1 (05-17-05) DATASHEET 76 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.9.1 Allowable settings for Configurable FIFO Memory Allocation TX and RX FIFO space is configurable through the CSR - HW_CFG register defined above. The user must select the FIFO allocation by setting the TX FIFO Size (TX_FIF_SZ) field in the hardware configuration (HW_CFG) register. The TX_FIF_SZ field selects the total allocation for the TX data path, including the TX Status FIFO size. The TX Status FIFO size is fixed at 512 Bytes (128 TX Status DWORDs). The TX Status FIFO length is subtracted from the total TX FIFO size with the remainder being the TX data FIFO Size. Note that TX data FIFO space includes both commands and payload data. RX FIFO Size is the remainder of the unallocated FIFO space (16384 bytes – TX FIFO Size). The RX Status FIFO size is always equal to 1/16 of the RX FIFO Size. The RX Status FIFO length is subtracted from the total RX FIFO size with the remainder being the RX data FIFO Size. For example, if TX_FIF_SZ = 6 then: Total TX FIFO Size = 6144 Bytes (6KB) TX Status FIFO Size = 512 Bytes (Fixed) TX Data FIFO Size = 6144 – 512 = 5632 Bytes RX FIFO Size = 16384 – 6144 = 10240 Bytes (10KB) RX Status FIFO Size = 10240 / 16 = 640 Bytes (160 RX Status DWORDs) RX Data FIFO Size = 10240 – 640 = 9600 Bytes Table 5.3 shows every valid setting for the TX_FIF_SZ field. Note that settings not shown in this table are reserved and should not be used. Note: The RX data FIFO is considered full 4 DWORDs before the length that is specified in the HW_CFG register. Table 5.3 Valid TX/RX FIFO Allocations TX_FIF_SZ 2 3 4 5 6 7 8 9 10 11 12 13 14 SMSC LAN9118 TX DATA FIFO SIZE (BYTES) 1536 2560 3584 4608 5632 6656 7680 8704 9728 10752 11776 12800 13824 TX STATUS FIFO SIZE (BYTES) 512 512 512 512 512 512 512 512 512 512 512 512 512 RX DATA FIFO SIZE (BYTES) 13440 12480 11520 10560 9600 8640 7680 6720 5760 4800 3840 2880 1920 RX STATUS FIFO SIZE (BYTES) 896 832 768 704 640 576 512 448 384 320 256 192 128 Revision 1.1 (05-17-05) DATASHEET 77 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K bytes of TX, and 128 bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by the host. As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO. Depending on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data that may be queued in the TX data FIFO. Conversely, as data is received by the LAN9118, it is moved from the MAC to the RX MIL FIFO, and then into the RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO. If the RX MIL FIFO fills up and overruns, subsequent RX frames will be lost until room is made in the RX data FIFO. For each frame of data that is lost, the RX Dropped Frames Counter (RX_DROP) is incremented. RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate independent of the TX adatand RX data and status FIFOs. FIFO levels set for the RX and TX data and Status FIFOs do not take into consideration the MIL FIFOs. 5.3.10 RX_DP_CTRL—Receive Datapath Control Register Offset: 78h Size: 32 bits This register is used to discard unwanted receive frames. BITS 31 DESCRIPTION RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes the RX data FIFO to fast-forward to the start of the next frame. This bit will remain high until the RX data FIFO fast-forward operation has completed. No reads should be issued to the RX data FIFO while this bit is high. Note: Please refer to section “Receive Data FIFO Fast Forward” on page 53 for detailed information regarding the use of RX_FFWD. TYPE R/W DEFAULT 0h 30-0 Reserved RO - 5.3.11 RX_FIFO_INF—Receive FIFO Information Register Offset: 7Ch Size: 32 bits This register contains the used space in the receive FIFOs of the LAN9118 Ethernet Controller. BITS 31-24 23-16 DESCRIPTION Reserved RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in DWORDs, used in the RX Status FIFO. TYPE RO RO DEFAULT 00h Revision 1.1 (05-17-05) DATASHEET 78 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 15-0 DESCRIPTION RX Data FIFO Used Space (RXDUSED).). Reads the amount of space in bytes, used in the RX data FIFO. For each receive frame, this field is incremented by the length of the receive data rounded up to the nearest DWORD (if the payload does not end on a DWORD boundary). TYPE RO DEFAULT 0000h 5.3.12 TX_FIFO_INF—Transmit FIFO Information Register Offset: 80h Size: 32 bits This register contains the free space in the transmit data FIFO and the used space in the transmit status FIFO in the LAN9118. BITS 31-24 23-16 15-0 DESCRIPTION Reserved TX Status FIFO Used Space (TXSUSED). Indicates the amount of space in DWORDS used in the TX Status FIFO. TX Data FIFO Free Space (TDFREE). Reads the amount of space in bytes, available in the TX data FIFO. The application should never write more data than is available, as indicated by this value. TYPE RO RO RO DEFAULT 00h 1200h 5.3.13 PMT_CTRL— Power Management Control Register Offset: 84h Size: 32 bits This register controls the Power Management features. This register can be read while the LAN9118 is in a power saving mode. Note: The LAN9118 must always be read at least once after power-up, reset, or upon return from a power-saving state or write operations will not function. SMSC LAN9118 DATASHEET 79 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 31:14 13-12 DESCRIPTION RESERVED Power Management Mode (PM_MODE) – These bits set the LAN9118 into the appropriate Power Management mode. Special care must be taken when modifying these bits. Encoding: 00b – D0 (normal operation) 01b – D1 (wake-up frame and magic packet detection are enabled) 10b – D2 (can perform energy detect) 11b – RESERVED - Do not set in this mode Note: When the LAN9118 is in a any of the reduced power modes, a write of any data to the BYTE_TEST register will wake-up the device. DO NOT PERFORM WRITES TO OTHER ADDRRESSES while the READY bit in this register is cleared. TYPE RO SC DEFAULT 00b 11 10 RESERVED PHY Reset (PHY_RST) – Writing a ‘1’ to this bit resets the PHY. The internal logic automatically holds the PHY reset for a minimum of 100us. When the PHY is released from reset, this bit is automatically cleared. All writes to this bit are ignored while this bit is high. Wake-On-Lan Enable (WOL_EN) – When set, the PME signal (if enabled with PME_EN) will be asserted in accordance with the PME_IND bit upon a WOL event. When set, the PME_INT will also be asserted upon a WOL event, regardless of the setting of the PME_EN bit. Energy-Detect Enable (ED_EN) - When set, the PME signal (if enabled with PME_EN) will be asserted in accordance with the PME_IND bit upon an Energy-Detect event. When set, the PME_INT will also be asserted upon an Energy Detect event, regardless of the setting of the PME_EN bit. RESERVED PME Buffer Type (PME_TYPE) – When cleared, enables PME to function as an open-drain buffer for use in a Wired-Or configuration. When set, the PME output is a Push-Pull driver. When configured as an open-drain output the PME_POL field is ignored, and the output is always active low. WAKE-UP Status (WUPS) – This field indicates the cause of a wake-up event detection as follows 00b -- No wake-up event detected 01b -- Energy detected 10b -- Wake-up frame or magic packet detected 11b -- Indicates multiple events occurred WUPS bits are cleared by writing a ‘1’ to the appropriate bit. The device must return to the D0 state (READY bit set) before these bits can be cleared. Note: In order to clear this bit, it is required that all event sources be cleared as well. The event sources are decribed in Figure 3.11 PME and PME_INT Signal Generationon page 39. RO SC 0b 9 R/W 0b 8 R/W 0b 7 6 RO R/W NASR 0b 5-4 R/WC 00 Revision 1.1 (05-17-05) DATASHEET 80 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 3 DESCRIPTION PME indication (PME_IND). The PME signal can be configured as a pulsed output or a static signal, which is asserted upon detection of a wake-up event. When set, the PME signal will pulse active for 50mS upon detection of a wake-up event. When clear, the PME signal is driven continously upon detection of a wakeup event. The PME signal can be deactivated by clearing the WUPS bits, or by clearing the appropriate enable (refer to Section 3.10.2.3, "Power Managment Event Indicators," on page 39). TYPE R/W DEFAULT 0b 2 PME Polarity (PME_POL). This bit controls the polarity of the PME signal. When set, the PME output is an active high signal. When reset, it is active low. When PME is configured as an open-drain output this field is ignored, and the output is always active low. PME Enable (PME_EN). When set, this bit enables the external PME signal. This bit does not affect the PME interrupt (PME_INT). Device Ready (READY). When set, this bit indicates that LAN9118 is ready to be accessed. This register can be read when LAN9118 is in any power management mode. Upon waking from any power management mode, including power-up, the host processor can interrogate this field as an indication when LAN9118 has stabilized and is fully alive. Reads and writes of any other address are invalid until this bit is set. Note: With the exception of HW_CFG and PMT_CTRL, read access to any internal resources is forbidden while the READY bit is cleared. R/W NASR 0b 1 0 R/W RO 0b - SMSC LAN9118 DATASHEET 81 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.14 GPIO_CFG—General Purpose IO Configuration Register Offset: 88h Size: 32 bits This register configures the GPIO and LED functions. Bits 31 30:28 Reserved Description Type RO R/W Default 000 LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED output. When cleared low, the pin functions as a GPIO signal. LED1/GPIO0 – bit 28 LED2/GPIO1 – bit 29 LED3/GPIO2 – bit 30 Reserved GPIO Interrupt Polarity 0-2 (GPIO_INT_POL). When set high, a high logic level on the corresponding GPIO pin will set the corresponding INT_STS register bit. When cleared low, a low logic level on the corresponding GPIO pin will set the corresponding INT_STS register bit. GPIO Interrupts must also be enabled in GPIOx_INT_EN in the INT_EN register. GPIO0 – bit 24 GPIO1 – bit 25 GPIO2 – bit 26 Note: GPIO inputs must be active for greater than 40nS to be recognized as interrupt inputs. 27 26:24 RO R/W 000 23 22:20 Reserved EEPROM Enable (EEPR_EN). The value of this field determines the function of the external EEDIO and EECLK: Please refer to Table 5.4 for the EEPROM Enable bit function definitions. Note: The host must not change the function of the EEDIO and EECLK pins when an EEPROM read or write cycle is in progress. Do not use reserved settings. RO R/W 000 19 18:16 Reserved GPIO Buffer Type 0-2 (GPIOBUFn). When set, the output buffer for the corresponding GPIO signal is configured as a push/pull driver. When cleared, the corresponding GPIO set configured as an open-drain driver. GPIO0 – bit 16 GPIO1 – bit 17 GPIO2 – bit 18 Reserved GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO as output. When cleared the GPIO is enabled as an input. GPIO0 – bit 8 GPIO1 – bit 9 GPIO2 – bit 10 Reserved GPO Data 3-4 (GPODn). The value written is reflected on GPOn. GPO3 – bit 3 GPO4 – bit 4 RO R/W 000 15:11 10:8 RO R/W 0000 7:5 4:3 RO R/W 00 Revision 1.1 (05-17-05) DATASHEET 82 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Bits 2:0 Description GPIO Data 0-2 (GPIODn). When enabled as an output, the value written is reflected on GPIOn. When read, GPIOn reflects the current state of the corresponding GPIO pin. GPIO0 – bit 0 GPIO1 – bit 1 GPIO2 – bit 2 Type R/W Default 000 Table 5.4 EEPROM Enable Bit Definitions [22] 0 0 0 0 1 1 1 1 [21] 0 0 1 1 0 0 1 1 [20] 0 1 0 1 0 1 0 1 TX_EN TX_EN TX_CLK GPO3 Reserved GPO4 RX_DV RX_CLK EEDIO FUNCTION EEDIO GPO3 Reserved RX_DV EECLK FUNCTION EECLK GPO4 5.3.15 GPT_CFG-General Purpose Timer Configuration Register Offset: 8Ch Size: 32 bits This register configures the General Purpose timer. The GP Timer can be configured to generate host interrupts at intervals defined in this register. BITS 31-30 29 DESCRIPTION Reserved GP Timer Enable (TIMER_EN). When a one is written to this bit the GP Timer is put into the run state. When cleared, the GP Timer is halted. On the 1 to 0 transition of this bit the GPT_LOAD field will be preset to FFFFh. Reserved General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded into the GP-Timer. TYPE RO R/W DEFAULT 0 28-16 15-0 RO R/W FFFFh SMSC LAN9118 DATASHEET 83 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.16 GPT_CNT-General Purpose Timer Current Count Register Offset: 90h Size: 32 bits This register reflects the current value of the GP Timer. BITS 31-16 15-0 DESCRIPTION Reserved General Purpose Timer Current Count (GPT_CNT). This 16-bit field reflects the current value of the GP Timer. TYPE RO RO DEFAULT FFFFh 5.3.17 ENDIAN—Endian Control Offset: 98h Size: 32 bits This register controls the Endianess of the LAN9118. BITS 31:0 DESCRIPTION Endian. If this field is set to 0xFFFFFFFFh, the LAN9118 is configured to operate with most 32-bit host big-endian processors using a 16-bit interface. If this field is set to anything else, the LAN9118 is configured to operate with native 16-bit Little-Endian processors. Notes: ■ Please refer to Section 3.6, "32-bit vs. 16-bit Host Bus Width Operation" for additional information. ■ The value of this field is only significant when configured for 16-bit operation. TYPE R/W NASR DEFAULT 00000000h Revision 1.1 (05-17-05) DATASHEET 84 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.18 FREE_RUN—Free-Run 25MHz Counter Offset: 9Ch Size: 32 bits This register reflects the value of the free-running 25MHz counter. BITS 31:0 DESCRIPTION Free Running SCLK Counter (FR_CNT): Note: This field reflects the value of a free-running 32-bit counter. At reset the counter starts at zero and is incremented for every 25MHz cycle. When the maximum count has been reached the counter will rollover. When read in 16-bit mode the count value is latched on the first read. The FREE_RUN counter can take up to 160nS to clear after a reset event. This counter will run regardless of the power management states D0, D1 or D2. TYPE RO DEFAULT - Note: 5.3.19 RX_DROP– Receiver Dropped Frames Counter Offset: A0h Size: 32 bits This register indicates the number of receive frames that have been dropped. BITS 31-0 DESCRIPTION RX Dropped Frame Counter (RX_DFC). This counter is incremented every time a receive frame is dropped. RX_DFC is cleared on any read of this register. An interrupt can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). TYPE RC DEFAULT 00000000h SMSC LAN9118 DATASHEET 85 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.20 MAC_CSR_CMD – MAC CSR Synchronizer Command Register Offset: A4h Size: 32 bits This register is used to control the read and write operations with the MAC CSR’s BITS 31 DESCRIPTION CSR Busy. When a 1 is written into this bit, the read or write operation is performed to the specified MAC CSR. This bit will remain set until the operation is complete. In the case of a read this means that the host can read valid data from the data register. The MAC_CSR_CMD and MAC_CSR_DATA registers should not be modified until this bit is cleared. R/nW. When set, this bit indicates that the host is requesting a read operation. When clear, the host is performing a write. Reserved. CSR Address. The 8-bit value in this field selects which MAC CSR will be accessed with the read or write operation. TYPE SC DEFAULT 0 30 29-8 7-0 R/W RO R/W 0 00h 5.3.21 MAC_CSR_DATA – MAC CSR Synchronizer Data Register Offset: A8h Size: 32 bits This register is used in conjunction with the MAC_CSR_CMD register to perform read and write operations with the MAC CSR’s BITS 31-0 DESCRIPTION MAC CSR Data. Value read from or written to the MAC CSR’s. TYPE R/W DEFAULT 00000000h Revision 1.1 (05-17-05) DATASHEET 86 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.22 AFC_CFG – Automatic Flow Control Configuration Register Offset: ACh Size: 32 bits This register configures the mechanism that controls both the automatic, and software-initiated transmission of pause frames and back pressure. Note: The LAN9118 will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31:24 23:16 DESCRIPTION Reserved Automatic Flow Control High Level (AFC_HI). Specifies, in multiples of 64 bytes, the level at which flow control will trigger. When this limit is reached the chip will apply back pressure or will transmit a pause frame as programmed in bits [3:0] of this register. During full-duplex operation only a single pause frame is transmitted when this level is reached. The pause time transmitted in this frame is programmed in the FCPT field of the FLOW register in the MAC CSR space. During half-duplex operation each incoming frame that matches the criteria in bits [3:0] of this register will be jammed for the period set in the BACK_DUR field. TYPE RO R/W DEFAULT 00h 15:8 Automatic Flow Control Low Level (AFC_LO). Specifies, in multiples of 64 bytes, the level at which a pause frame is transmitted with a pause time setting of zero. When the amount of data in the RX data FIFO falls below this level the pause frame is transmitted. A pause time value of zero instructs the other transmitting device to immediately resume transmission. The zero time pause frame will only be transmitted if the RX data FIFO had reached the AFC_HI level and a pause frame was sent. A zero pause time frame is sent whenever automatic flow control in enabled in bits [3:0] of this register. Note: When automatic flow control is enabled the AFC_LO setting must always be less than the AFC_HI setting. R/W 00h 7:4 Backpressure Duration (BACK_DUR). When the LAN9118 automatically asserts back pressure, it will be asserted for this period of time. This field has no function and is not used in full-duplex mode. Please refer to Table 5.5, describing Backpressure Duration bit mapping for more information. Flow Control on Multicast Frame (FCMULT). When this bit is set, the LAN9118 will assert back pressure when the AFC level is reached and a multicast frame is received. This field has no function in full-duplex mode. Flow Control on Broadcast Frame (FCBRD). When this bit is set, the LAN9118 will assert back pressure when the AFC level is reached and a broadcast frame is received. This field has no function in full-duplex mode. Flow Control on Address Decode (FCADD). When this bit is set, the LAN9118 will assert back pressure when the AFC level is reached and a frame addressed to the LAN9118 is received. This field has no function in full-duplex mode. R/W 0h 3 R/W 0 2 R/W 0 1 R/W 0 SMSC LAN9118 DATASHEET 87 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 0 DESCRIPTION Flow Control on Any Frame (FCANY). When this bit is set, the LAN9118 will assert back pressure, or transmit a pause frame when the AFC level is reached and any frame is received. Setting this bit enables full-duplex flow control when the LAN9118 is operating in full-duplex mode. When this mode is enabled during half-duplex operation, the Flow Controller does not decode the MAC address and will send a pause frame upon receipt of a valid preamble (i.e., immediately at the beginning of the next frame after the RX data FIFO level is reached). When this mode is enabled during full-duplex operation, the Flow Controller will immediately instruct the MAC to send a pause frame when the RX data FIFO level is reached. The MAC will queue the pause frame transmission for the next available window. Setting this bit overrides bits [3:1] of this register. TYPE R/W DEFAULT 0 Table 5.5 Backpressure Duration Bit Mapping BACKPRESSURE DURATION [19:16] 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 100Mbs Mode 5uS 10uS 15uS 25uS 50uS 100uS 150uS 200uS 250uS 300uS 350uS 400uS 450uS 500uS 550uS 600uS 10Mbs Mode 7.2uS 12.2uS 17.2uS 27.2uS 52.2uS 102.2uS 152.2uS 202.2uS 252.2uS 302.2uS 352.2uS 402.2uS 452.2uS 502.2uS 552.2uS 602.2uS Revision 1.1 (05-17-05) DATASHEET 88 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.3.23 E2P_CMD – EEPROM Command Register Offset: B0h Size: 32 bits This register is used to control the read and write operations with the Serial EEPROM. BITS 31 DESCRIPTION EPC Busy: When a 1 is written into this bit, the operation specified in the EPC command field is performed at the specified EEPROM address. This bit will remain set until the operation is complete. In the case of a read this means that the host can read valid data from the E2P data register. The E2P_CMD and E2P_DATA registers should not be modified until this bit is cleared. In the case where a write is attempted and an EEPROM is not present, the EPC Busy remains busy until the EPC Time-out occurs. At that time the busy bit is cleared. Note: EPC busy will be high immediately following power-up or reset. After the EEPROM controller has finished reading (or attempting to read) the MAC address from the EEPROM the EPC Busy bit is cleared. TYPE SC DEFAULT 0 SMSC LAN9118 DATASHEET 89 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 30-28 DESCRIPTION EPC command. This field is used to issue commands to the EEPROM controller. The EPC will execute commands when the EPC Busy bit is set. A new command must not be issued until the previous command completes. This field is encoded as follows: TYPE R/W DEFAULT 0 [30] 0 [29] [28] OPERATION 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 READ EWDS EWEN WRITE WRAL ERASE ERAL Reload 0 0 0 1 1 1 1 READ (Read Location): This command will cause a read of the EEPROM location pointed to by EPC Address. The result of the read is available in the E2P_DATA register. EWDS (Erase/Write Disable): After issued, the EEPROM will ignore erase and write commands. To re-enable erase/write operations issue the EWEN command. EWEN (Erase/Write Enable): Enables the EEPROM for erase and write operations. The EEPROM will allow erase and write operations until the Erase/Write Disable command is sent, or until power is cycled. Note: The EEPROM device will power-up in the erase/write-disabled state. Any erase or write operations will fail until an Erase/Write Enable command is issued. WRITE (Write Location): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the E2P_DATA register to be written to the EEPROM location selected by the EPC Address field. WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the E2P_DATA register to be written to every EEPROM memory location. ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will erase the location selected by the EPC Address field. ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM. RELOAD (MAC Address Reload): Instructs the EEPROM controller to reload the MAC address from the EEPROM. If a value of 0xA5 is not found in the first address of the EEPROM, the EEPROM is assumed to be unprogrammed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates a successful load of the MAC address. 27-10 Reserved. RO - Revision 1.1 (05-17-05) DATASHEET 90 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 9 DESCRIPTION TYPE R/WC DEFAULT 0 EPC Time-out. If an EEPROM operation is performed, and there is no response from the EEPROM within 30mS, the EEPROM controller will timeout and return to its idle state. This bit is set when a time-out occurs indicating that the last operation was unsuccessful. Note: If the EEDIO signal pin is externally pulled-high, EPC commands will not time out if the EEPROM device is missing. In this case the EPC Busy bit will be cleared as soon as the command sequence is complete. It should also be noted that the ERASE, ERAL, WRITE and WRAL commands are the only EPC commands that will time-out if an EEPROM device is not present -and- the EEDIO signal is pulled low 8 MAC Address Loaded. When set, this bit indicates that a valid EEPROM was found, and that the MAC address programming has completed normally. This bit is set after a successful load of the MAC address after power-up, or after a RELOAD command has completed RO - 7-0 EPC Address. The 8-bit value in this field is used by the EEPROM R/W 00h Controller to address the specific memory location in the Serial EEPROM. This is a Byte aligned address. 5.3.24 E2P_DATA – EEPROM Data Register Offset: B4h Size: 32 bits This register is used in conjunction with the E2P_CMD register to perform read and write operations with the Serial EEPROM BITS 31-8 7:0 DESCRIPTION Reserved. EEPROM Data. Value read from or written to the EEPROM. TYPE RO R/W DEFAULT 00h 5.4 MAC Control and Status Registers These registers are located in the MAC module and are accessed indirectly through the MAC-CSR synchronizer port. Table 5.6, "LAN9118 MAC CSR Register Map", shown below, lists the MAC registers that are accessible through the indexing method using the MAC_CSR_CMD and MAC_CSR_DATA registers (see sections MAC_CSR_CMD – MAC CSR Synchronizer Command Register and MAC_CSR_DATA – MAC CSR Synchronizer Data Register). SMSC LAN9118 DATASHEET 91 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 5.6 LAN9118 MAC CSR Register Map MAC CONTROL AND STATUS REGISTERS INDEX 1 2 3 4 5 6 7 8 9 A B C SYMBOL MAC_CR ADDRH ADDRL HASHH HASHL MII_ACC MII_DATA FLOW VLAN1 VLAN2 WUFF WUCSR REGISTER NAME MAC Control Register MAC Address High MAC Address Low Multicast Hash Table High Multicast Hash Table Low MII Access MII Data Flow Control VLAN1 Tag VLAN2 Tag Wake-up Frame Filter Wake-up Control and Status DEFAULT 00040000h 0000FFFFh FFFFFFFFh 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 5.4.1 MAC_CR—MAC Control Register Offset: Default Value: 1 00040000h Attribute: Size: R/W 32 bits This register establishes the RX and TX operation modes and controls for address filtering and packet filtering. BITS 31 DESCRIPTION Receive All Mode (RXALL). When set, all incoming packets will be received and passed on to the address filtering Function for processing of the selected filtering mode on the received frame. Address filtering then occurs and is reported in Receive Status. When reset, only frames that pass Destination Address filtering will be sent to the Application. Reserved Disable Receive Own (RCVOWN). When set, the MAC disables the reception of frames when TXEN is asserted. The MAC blocks the transmitted frame on the receive path. When reset, the MAC receives all packets the PHY gives, including those transmitted by the MAC.This bit should be reset when the Full Duplex Mode bit is set. Reserved 30-24 23 22 Revision 1.1 (05-17-05) DATASHEET 92 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 21 DESCRIPTION Loopback operation Mode (LOOPBK). Selects the loop back operation modes for the MAC. This is only for full duplex mode 1’b0: Normal: No feedback 1’b1: Internal: Through MII In internal loopback mode, the TX frame is received by the Internal MII interface, and sent back to the MAC without being sent to the PHY. Note: When enabling or disabling the loopback mode it can take up to 10µs for the mode change to occur. The transmitter and receiver must be stopped and disabled when modifying the LOOPBK bit. The transmitter or receiver should not be enabled within10µs of modifying the LOOPBK bit. 20 Full Duplex Mode (FDPX). When set, the MAC operates in Full-Duplex mode, in which it can transmit and receive simultaneously. In Full-Duplex mode, the heartbeat check is disabled and the heartbeat fail status should thus be ignored. Pass All Multicast (MCPAS). When set, indicates that all incoming frames with a Multicast destination address (first bit in the destination address field is 1) are received. Incoming frames with physical address (Individual Address/Unicast) destinations are filtered and received only if the address matches the MAC Address. Promiscuous Mode (PRMS). When set, indicates that any incoming frame is received regardless of its destination address. Inverse filtering (INVFILT). When set, the address check Function operates in Inverse filtering mode. This is valid only during Perfect filtering mode. Pass Bad Frames (PASSBAD). When set, all incoming frames that passed address filtering are received, including runt frames, collided frames or truncated frames caused by buffer underrun. Hash Only Filtering mode (HO). When set, the address check Function operates in the Imperfect Address Filtering mode both for physical and multicast addresses Reserved Hash/Perfect Filtering Mode (HPFILT). When reset (0), the LAN9118 will implement a perfect address filter on incoming frames according the address specified in the MAC address register. When set (1), the address check Function does imperfect address filtering of multicast incoming frames according to the hash table specified in the multicast hash table register. If the Hash Only Filtering mode (HO) bit is set (1), then the physical (IA) are imperfect filtered too. If the Hash Only Filtering mode (HO) bit is reset (0), then the IA addresses are perfect address filtered according to the MAC Address register 19 18 17 16 15 14 13 12 Late Collision Control (LCOLL). When set, enables retransmission of the collided frame even after the collision period (late collision). When reset, the MAC disables frame transmission on a late collision. In any case, the Late Collision status is appropriately updated in the Transmit Packet status. Disable Broadcast Frames (BCAST). When set, disables the reception of broadcast frames. When reset, forwards all broadcast frames to the application. Disable Retry (DISRTY). When set, the MAC attempts only one transmission. When a collision is seen on the bus, the MAC ignores the current frame and goes to the next frame and a retry error is reported in the Transmit status. When reset, the MAC attempts 16 transmissions before signaling a retry error. Reserved Automatic Pad Stripping (PADSTR). When set, the MAC strips the pad field on all incoming frames, if the length field is less than 46 bytes. The FCS field is also stripped, since it is computed at the transmitting station based on the data and pad field characters, and is invalid for a received frame that has had the pad characters stripped. Receive frames with a 46-byte or greater length field are passed to the Application unmodified (FCS is not stripped). When reset, the MAC passes all incoming frames to the host unmodified. 11 10 9 8 SMSC LAN9118 DATASHEET 93 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 7-6 DESCRIPTION BackOff Limit (BOLMT). The BOLMT bits allow the user to set its back-off limit in a relaxed or aggressive mode. According to IEEE 802.3, the MAC has to wait for a random number [r] of slottimes** after it detects a collision, where: (eq.1)0 < r < 2K The exponent K is dependent on how many times the current frame to be transmitted has been retried, as follows: (eq.2)K = min (n, 10) where n is the current number of retries. If a frame has been retried three times, then K = 3 and r= 8 slot-times maximum. If it has been retried 12 times, then K = 10, and r = 1024 slot-times maximum. An LFSR (linear feedback shift register) 20-bit counter emulates a 20bit random number generator, from which r is obtained. Once a collision is detected, the number of the current retry of the current frame is used to obtain K (eq.2). This value of K translates into the number of bits to use from the LFSR counter. If the value of K is 3, the MAC takes the value in the first three bits of the LFSR counter and uses it to count down to zero on every slot-time. This effectively causes the MAC to wait eight slot-times. To give the user more flexibility, the BOLMT value forces the number of bits to be used from the LFSR counter to a predetermined value as in the table below. BOLMT Value 2’b00 # Bits Used from LFSR Counter 10 8 4 1 2’b01 2’b10 2’b11 Thus, if the value of K = 10, the MAC will look at the BOLMT if it is 00, then use the lower ten bits of the LFSR counter for the wait countdown. If the BOLMT is 10, then it will only use the value in the first four bits for the wait countdown, etc. **Slot-time = 512 bit times. (See IEEE 802.3 Spec., Secs. 4.2.3.25 and 4.4.2.1) 5 Deferral Check (DFCHK). When set, enables the deferral check in the MAC. The MAC will abort the transmission attempt if it has deferred for more than 24,288 bit times. Deferral starts when the transmitter is ready to transmit, but is prevented from doing so because the CRS is active. Defer time is not cumulative. If the transmitter defers for 10,000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. When reset, the deferral check is disabled in the MAC and the MAC defers indefinitely. Reserved Transmitter enable (TXEN). When set, the MAC’s transmitter is enabled and it will transmit frames from the buffer onto the cable. When reset, the MAC’s transmitter is disabled and will not transmit any frames. Receiver Enable (RXEN). When set (1), the MAC’s receiver is enabled and will receive frames from the internal PHY. When reset, the MAC’s receiver is disabled and will not receive any frames from the internal PHY. Reserved 4 3 2 1-0 5.4.2 ADDRH—MAC Address High Register Offset: Default Value: 2 0000FFFFh Attribute: Size: R/W 32 bits The MAC Address High register contains the upper 16-bits of the physical address of the MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0]) Revision 1.1 (05-17-05) DATASHEET 94 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet is loaded from address 0x05 of the EEPROM. The second byte (bits [15:8]) is loaded from address 0x06 of the EEPROM. Please refer to Section 4.6 for more information on the EEPROM. Section 5.4.3 details the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the Ethernet physical address. BITS 31-16 15-0 Reserved DESCRIPTION Physical Address [47:32]. This field contains the upper 16-bits (47:32) of the Physical Address of the LAN9118 device. The content of this field is undefined until loaded from the EEPROM at poweron. The host can update the contents of this field after the initialization process has completed. 5.4.3 ADDRL—MAC Address Low Register Offset: Default Value: 3 FFFFFFFFh Attribute: Size: R/W 32 bits The MAC Address Low register contains the lower 32 bits of the physical address of the MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Controller if a programmed EEPROM is detected. The least significant byte of this register (bits [7:0]) is loaded from address 0x01 of the EEPROM. The most significant byte of this register is loaded from address 0x04 of the EEPROM. Please refer to Section 4.6 for more information on the EEPROM. BITS 31-0 DESCRIPTION Physical Address [31:0]. This field contains the lower 32 bits (31:0) of the Physical Address of the LAN9118 device. The content of this field is undefined until loaded from the EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. Table 5.7 below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the Ethernet physical address. Also shown is the correlation between the EEPROM addresses and ADDRL and ADDRH registers. Table 5.7 ADDRL, ADDRH and EEPROM Byte Ordering EEPROM ADDRESS 0x01 0x02 0x03 0x04 0x05 0x06 ADDRN ADDRL[7:0] ADDRL[15:8] ADDRL[23:16] ADDRL[31:24] ADDRH[7:0] ADDRH[15:8] ORDER OF RECEPTION ON ETHERNET 1st 2nd 3rd 4th 5th 6th SMSC LAN9118 DATASHEET 95 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and ADDRH registers would be programmed as shown in Figure 5.2. The values required to automatically load this configuration from the EEPROM are also shown. 31 xx 24 23 xx 16 15 0xBC 87 0x9A 0 0x06 0x05 0x04 0x03 0xBC 0x9A 0x78 0x56 0x34 0x12 0xA5 EEPROM ADDRH 31 0x78 24 23 16 15 0x34 87 0x12 0 0x02 0x01 0x00 0x56 ADDRL Figure 5.2 Example ADDRL, ADDRH and EEPROM Setup Note: By convention, the left most byte of the Ethernet address (in this example 0x12) is the most significant byte and is transmitted/received first. 5.4.4 HASHH—Multicast Hash Table High Register Offset: Default Value: 4 00000000h Attribute: Size: R/W 32 bits The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the Hash table. The most significant bit determines the register to be used (Hi/Low), while the other five bits determine the bit within the register. A value of 00000 selects Bit 0 of the Multicast Hash Table Lo register and a value of 11111 selects the Bit 31 of the Multicast Hash Table Hi register. If the corresponding bit is 1, then the multicast frame is accepted. Otherwise, it is rejected. If the “Pass All Multicast” (MCPAS) bit is set (1), then all multicast frames are accepted regardless of the multicast hash values. The Multicast Hash Table Hi register contains the higher 32 bits of the hash table and the Multicast Hash Table Low register contains the lower 32 bits of the hash table. BITS 31-0 Upper 32 bits of the 64-bit Hash Table DESCRIPTION Revision 1.1 (05-17-05) DATASHEET 96 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.5 HASHL—Multicast Hash Table Low Register Offset: Default Value: 5 00000000h Attribute: Size: R/W 32 bits This register defines the lower 32-bits of the Multicast Hash Table. Please refer to Table 5.4.4, "HASHH—Multicast Hash Table High Register" for further details. BITS 31-0 Lower 32 bits of the 64-bit Hash Table DESCRIPTION 5.4.6 MII_ACC—MII Access Register Offset: Default Value: 6 00000000h Attribute: Size: R/W 32 bits This register is used to control the Management cycles to the PHY. BITS 31-16 15-11 10-6 5-2 1 0 Reserved DESCRIPTION PHY Address: For every access to this register, this field must be set to 00001b. MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY. Reserved MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data register. If this bit is not set, this will be a read operation, packing the data in the MII data register. MII Busy (MIIBZY): This bit must be polled to determine when the MII register accesss is complete. This bit must read a logical 0 before writing to this register and MII data register. The LAN driver software must set (1) this bit in order for the LAN9118 to read or write any of the MII PHY registers. During a MII register access, this bit will be set, signifying a read or write access is in progress. The MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The MII data register is invalid until the MAC has cleared this bit during a PHY read operation. SMSC LAN9118 DATASHEET 97 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.7 MII_DATA—MII Data Register Offset: Default Value: 7 00000000h Attribute: Size: R/W 32 bits This register contains either the data to be written to the PHY register specified in the MII Access Register, or the read data from the PHY register whose index is specified in the MII Access Register. BITS 31-16 15-0 Reserved DESCRIPTION MII Data. This contains the 16-bit value read from the PHY read operation or the 16-bit data value to be written to the PHY before an MII write operation. 5.4.8 FLOW—Flow Control Register Offset: Default Value: 8 00000000h Attribute: Size: R/W 32 bits This register controls the generation and reception of the Control (Pause command) frames by the MAC’s flow control block. The control frame fields are selected as specified in the 802.3x Specification and the Pause-Time value from this register is used in the “Pause Time” field of the control frame. In full-duplex mode the FCBSY bit is set until the control frame is transferred onto the cable. In halfduplex mode FCBSY is set while back pressure is being asserted. The host has to make sure that the Busy bit is cleared before writing the register. The Pass Control Frame bit (FCPASS) does not affect the sending of the frames, including Control Frames, to the Application Interface. The Flow Control Enable (FCEN) bit enables the receive portion of the Flow Control block. This register is used in conjunction with the AFC_CFG register in the Slave CSRs to configure flow control. Software flow control is initiated using the AFC_CFG register. Note: The LAN9118 will not transmit pause frames or assert back pressure if the transmitter is disabled. BITS 31-16 15-3 DESCRIPTION Pause Time (FCPT). This field indicates the value to be used in the PAUSE TIME field in the control frame. This field must be initialized before full-duplex automatic flow control is enabled. Reserved Revision 1.1 (05-17-05) DATASHEET 98 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 2 DESCRIPTION Pass Control Frames (FCPASS). When set, the MAC sets the Packet Filter bit in the Receive packet status to indicate to the Application that a valid Pause frame has been received. The Application must accept or discard a received frame based on the Packet Filter control bit. The MAC receives, decodes and performs the Pause function when a valid Pause frame is received in Full-Duplex mode and when flow control is enabled (FCE bit set). When reset, the MAC resets the Packet Filter bit in the Receive packet status. The MAC always passes the data of all frames it receives (including Flow Control frames) to the Application. Frames that do not pass Address filtering, as well as frames with errors, are passed to the Application. The Application must discard or retain the received frame’s data based on the received frame’s STATUS field. Filtering modes (Promiscuous mode, for example) take precedence over the FCPASS bit. Flow Control Enable (FCEN). When set, enables the MAC Flow Control function. The MAC decodes all incoming frames for control frames; if it receives a valid control frame (PAUSE command), it disables the transmitter for a specified time (Decoded pause time x slot time). When reset, the MAC flow control function is disabled; the MAC does not decode frames for control frames. Note: Flow Control is applicable when the MAC is set in Full Duplex Mode. In Half-Duplex mode, this bit enables the Backpressure function to control the flow of received frames to the MAC. 1 0 Flow Control Busy (FCBSY). This bit is set high whenever a pause frame or back pressure is being transmitted. This bit should read logical 0 before writing to the Flow Control (FLOW) register. During a transfer of Control Frame, this bit continues to be set, signifying that a frame transmission is in progress. After the PAUSE control frame’s transmission is complete, the MAC resets to 0. Notes: ■ When writing this register the FCBSY bit must always be zero. ■ Applications must always write a zero to this bit 5.4.9 VLAN1—VLAN1 Tag Register Offset: Default Value: 9 00000000h Attribute: Size: R/W 32 bits This register contains the VLAN tag field to identify VLAN1 frames. For VLAN frames the legal frame length is increased from 1518 bytes to 1522 bytes. BITS 31-16 15-0 Reserved DESCRIPTION VLAN1 Tag Identifier (VTI1). This contains the VLAN Tag field to identify the VLAN1 frames. This field is compared with the 13th and 14th bytes of the incoming frames for VLAN1 frame detection. If used, this register must be set to 0x8100. SMSC LAN9118 DATASHEET 99 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.10 VLAN2—VLAN2 Tag Register Offset: Default Value: A 00000000h Attribute: Size: R/W 32 bits This register contains the VLAN tag field to identify VLAN2 frames. For VLAN frames the legal frame length is increased from 1518 bytes to 1522 bytes. BITS 31-16 15-0 Reserved DESCRIPTION VLAN2 Tag Identifier (VTI2). This contains the VLAN Tag field to identify the VLAN2 frames. This field is compared with the 13th and 14th bytes of the incoming frames for VLAN2 frame detection.If used, this register must be set to 0x8100. 5.4.11 WUFF—Wake-up Frame Filter Offset: Default Value: B 00000000h Attribute: Size: WO 32 bits This register is used to configure the wake up frame filter. BITS 31-0 DESCRIPTION Wake-Up Frame Filter (WFF). Wake-Up Frame Filter (WFF). The Wake-up frame filter is configured through this register using an indexing mechanism. After power-on reset, hardware reset, or soft reset, the MAC loads the first value written to this location to the first DWORD in the Wake-up frame filter (filter 0 byte mask). The second value written to this location is loaded to the second DWORD in the wake-up frame filter (filter 1 byte mask) and so on. Once all eight DWORDs have been written, the internal pointer will once again point to the first entry and the filter entries can be modified in the same manner. Note: This is a write-only register. Revision 1.1 (05-17-05) DATASHEET 100 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.4.12 WUCSR—Wake-up Control and Status Register Offset: Default Value: C 00000000h Attribute: Size: R/W 32 bits This register contains data pertaining to the MAC’s remote wake-up status and capabilities. BITS 31-10 9 8-7 6 5 4-3 2 1 0 Reserved DESCRIPTION Global Unicast Enable (GUE). When set, the MAC wakes up from power-saving mode on receipt of a global unicast frame. A global unicast frame has the MAC Address [1:0] bit set to 0. Reserved Remote Wake-Up Frame Received (WUFR). The MAC, upon receiving a valid Remote Wake-up frame, sets this bit.. Magic Packet Received (MPR). Tthe MAC, upon receiving a valid Magic Packet, sets this bit. Reserved Wake-Up Frame enabled (WUEN). When set, Remote Wake-Up mode is enabled and the MAC is capable of detecting wake-up frames as programmed in the wake-up frame filter. Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled. Reserved 5.5 PHY Registers The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII_ACC and MII_DATA registers. An index must be used to access individual PHY registers. PHY Register Indexes are shown in Table 5.8, "LAN9118 PHY Control and Status Register"below. Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic Control Register (Reset) is set. Table 5.8 LAN9118 PHY Control and Status Register PHY CONTROL AND STATUS REGISTERS INDEX (IN DECIMAL) 0 1 2 3 SMSC LAN9118 REGISTER NAME Basic Control Register Basic Status Register PHY Identifier 1 PHY Identifier 2 101 Revision 1.1 (05-17-05) DATASHEET High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 5.8 LAN9118 PHY Control and Status Register (continued) PHY CONTROL AND STATUS REGISTERS INDEX (IN DECIMAL) 4 5 6 17 18 27 29 30 31 REGISTER NAME Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Mode Control/Status Register Special Modes Register Special Control/Status Indications Interrupt Source Register Interrupt Mask Register PHY Special Control/Status Register 5.5.1 Basic Control Register Index (In Decimal): 0 Size: 16-bits BITS 15 14 13 12 11 DESCRIPTION Reset. 1 = software reset. Bit is self-clearing. For best results, when setting this bit do not set other bits in this register. Loopback. 1 = loopback mode, 0 = normal operation Speed Select. 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is enabled (0.12 = 1). Auto-Negotiation Enable. 1 = enable auto-negotiate process (overrides 0.13 and 0.8) 0 = disable auto-negotiate process. Power Down. 1 = General power down-mode, 0 = normal operation. Note: After this bit is cleared, the PHY may auto-negotiate with it's partner station. This process may take a few seconds to complete. Once auto-negotiation is complete, bit 5 of the PHY's Basic Status Register will be set. TYPE RW/SC RW RW RW RW DEFAULT 0 0 See Note 5.1 See Note 5.1 0 10 9 8 7 Reserved Restart Auto-Negotiate. 1 = restart auto-negotiate process 0 = normal operation. Bit is self-clearing. Duplex Mode. 1 = full duplex, 0 = half duplex. Ignored if Auto Negotiation is enabled (0.12 = 1). Collision Test. 1 = enable COL test, 0 = disable COL test 102 RO RW/SC RW RW 0 0 0 0 SMSC LAN9118 Revision 1.1 (05-17-05) DATASHEET High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 6-0 DESCRIPTION Reserved Note 5.1 TYPE RO DEFAULT 0 This default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the pin description section for more details 5.5.2 Basic Status Register Index (In Decimal): 1 Size: 16-bits BITS 15 14 13 12 11 10-6 5 4 3 2 1 0 DESCRIPTION 100Base-T4. 1 = T4 able, 0 = no T4 ability 100Base-TX Full Duplex. 1 = TX with full duplex, 0 = no TX full duplex ability. 100Base-TX Half Duplex. 1 = TX with half duplex, 0 = no TX half duplex ability. 10Base-T Full Duplex. 1 = 10Mbps with full duplex 0 = no 10Mbps with full duplex ability 10Base-T Half Duplex. 1 = 10Mbps with half duplex 0 = no 10Mbps with half duplex ability Reserved Auto-Negotiate Complete. 1 = auto-negotiate process completed 0 = autonegotiate process not completed Remote Fault. 1 = remote fault condition detected 0 = no remote fault Auto-Negotiate Ability. 1 = able to perform auto-negotiation function 0 = unable to perform auto-negotiation function Link Status. 1 = link is up, 0 = link is down Jabber Detect. 1 = jabber condition detected 0 = no jabber condition detected Extended Capabilities. 1 = supports extended capabilities registers 0 = does not support extended capabilities registers. TYPE RO RO RO RO RO RO RO RO/LH RO RO/LL RO/LH RO DEFAULT 0 1 1 1 1 0 0 0 1 0 0 1 SMSC LAN9118 DATASHEET 103 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.3 PHY Identifier 1 Index (In Decimal): 2 Size: 16-bits BITS 15-0 DESCRIPTION PHY ID Number. Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. TYPE RO DEFAULT 0x0007h 5.5.4 PHY Identifier 2 Index (In Decimal): 3 Size: 16-bits BITS 15-10 9-4 3-0 DESCRIPTION PHY ID Number b. Assigned to the 19th through 24th bits of the OUI. Model Number. Six-bit manufacturer’s model number. Revision Number. Four-bit manufacturer’s revision number. TYPE RO RO RO DEFAULT 0xC0D1h 5.5.5 Auto-negotiation Advertisement Index (In Decimal): 4 Size: 16-bits BITS 15 14 13 12 11-10 DESCRIPTION Next Page. 1 = next page capable, 0 = no next page ability. This device does not support next page ability. Reserved Remote Fault. 1 = remote fault detected, 0 = no remote fault Reserved Pause Operation. 00 No PAUSE 01 Symmetric PAUSE 10 Asymmetric PAUSE 11 Both Symmetric PAUSE and Asymmetric PAUSE 100Base-T4. 1 = T4 able, 0 = no T4 ability This device does not support 100Base-T4. TYPE RO RO R/W R/W R/W DEFAULT 0 0 0 0 00 9 RO 0 Revision 1.1 (05-17-05) DATASHEET 104 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet BITS 8 7 6 DESCRIPTION 100Base-TX Full Duplex. 1 = TX with full duplex, 0 = no TX full duplex ability 100Base-TX. 1 = TX able, 0 = no TX ability 10Base-T Full Duplex. 1 = 10Mbps with full duplex 0 = no 10Mbps with full duplex ability 10Base-T. 1 = 10Mbps able, 0 = no 10Mbps ability Selector Field. [00001] = IEEE 802.3 Note 5.2 TYPE R/W R/W R/W DEFAULT See Note 5.2 1 See Note 5.2 See Note 5.2 00001 5 4:0 R/W R/W This default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the pin description section for more details. 5.5.6 Auto-negotiation Link Partner Ability Index (In Decimal): 5 Size: 16-bits BITS 15 14 DESCRIPTION Next Page. 1 = next page capable, 0 = no next page ability. This device does not support next page ability. Acknowledge. 1 = link code word received from partner 0 = link code word not yet received Note: This bit will always read 0 TYPE RO RO DEFAULT 0 0 13 12 11-10 Remote Fault. 1 = remote fault detected, 0 = no remote fault Reserved Pause Operation. 00 No PAUSE supported by partner station 01 Symmetric PAUSE supported by partner station 10 Asymmetric PAUSE supported by partner station 11 Both Symmetric PAUSE and Asymmetric PAUSE supported by partner station 100Base-T4. 1 = T4 able, 0 = no T4 ability 100Base-TX Full Duplex. 1 = TX with full duplex, 0 = no TX full duplex ability 100Base-TX. 1 = TX able, 0 = no TX ability 10Base-T Full Duplex. 1 = 10Mbps with full duplex 0 = no 10Mbps with full duplex ability 10Base-T. 1 = 10Mbps able, 0 = no 10Mbps ability Selector Field. [00001] = IEEE 802.3 105 RO RO RO 0 0 00 9 8 7 6 RO RO RO RO 0 0 0 0 5 4:0 RO RO 0 00001 SMSC LAN9118 DATASHEET Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.7 Auto-negotiation Expansion Index (In Decimal): 6 Size: 16-bits BITS 15:5 4 DESCRIPTION Reserved Parallel Detection Fault. 1 = fault detected by parallel detection logic 0 = no fault detected by parallel detection logic Link Partner Next Page Able. 1 = link partner has next page ability 0 = link partner does not have next page ability Next Page Able. 1 = local device has next page ability 0 = local device does not have next page ability Page Received. 1 = new page received 0 = new page not yet received Link Partner Auto-Negotiation Able. 1 = link partner has auto-negotiation ability 0 = link partner does not have auto-negotiation ability TYPE RO RO/LH DEFAULT 0 0 3 RO 0 2 RO 0 1 RO/LH 0 0 RO 0 5.5.8 Mode Control/Status Index (In Decimal): 17 Size: 16-bits BITS 15-14 13 DESCRIPTION Reserved. Write as 0; ignore on read. EDPWRDOWN. Enable the Energy Detect Power-Down mode: 0=Energy Detect Power-Down is disabled 1=Energy Detect Power-Down is enabled Reserved. Write as 0, ignore on read ENERGYON. Indicates whether energy is detected This bit goes to a “0” if no valid energy is detected within 256ms. Reset to “1” by hardware reset, unaffected by SW reset. Reserved. Write as “0”. Ignore on read. TYPE RW RW DEFAULT 0 0 12-2 1 RW RO 0 1 0 RW 0 Revision 1.1 (05-17-05) DATASHEET 106 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.9 Special Modes Index (In Decimal): 18 Size: 16-bits ADDRESS 15-8 7:5 4:0 Reserved DESCRIPTION TYPE RW, NASR RW, NASR RW, NASR DEFAULT MODE: PHY Mode of operation. Refer to Table 5.9 for more details. PHYAD: PHY Address: The PHY Address is used for the SMI address. See Table 5.9 00001b Table 5.9 MODE Control DEFAULT REGISTER BIT VALUES MODE MODE DEFINITIONS REGISTER 0 [13,12,10,8] 000 001 010 011 100 10Base-T Half Duplex. Auto-negotiation disabled. 10Base-T Full Duplex. Auto-negotiation disabled. 100Base-TX Half Duplex. Auto-negotiation disabled. CRS is active during Transmit & Receive. 100Base-TX Full Duplex. Auto-negotiation disabled. CRS is active during Receive. 100ase-TX Half Duplex is advertised. Autonegotiation enabled. CRS is active during Transmit & Receive. Repeater mode. Auto-negotiation enabled. 100Base-TX Half Duplex is advertised. CRS is active during Receive. Reserved - Do not set the LAN9118 in this mode. All capable. Auto-negotiation enabled. 0000 0001 1000 1001 1100 REGISTER 4 [8,7,6,5] N/A N/A N/A N/A 0100 101 1100 0100 110 111 N/A X10X N/A 1111 SMSC LAN9118 DATASHEET 107 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.10 Special Control/Status Indications Index (In Decimal): 27 Size: 16-bits ADDRESS 15:11 10 DESCRIPTION Reserved: Write as 0. Ignore on read. VCOOFF_LP: Forces the Receive PLL 10M to lock on the reference clock at all times: 0 - Receive PLL 10M can lock on reference or line as needed (normal operation) 1 - Receive PLL 10M is locked on the reference clock. In this mode 10M data packets cannot be received. Reserved: Write as 0. Ignore on read. XPOL: Polarity state of the 10Base-T: 0 - Normal polarity 1 - Reversed polarity Reserved: Read only - Writing to these bits have no effect. MODE RW RW, NASR DEFAULT 0 0 9-5 4 RW RO 0 0 3:0 RO 1011b 5.5.11 Interrupt Source Flag Index (In Decimal): 29 Size: 16-bits BITS 15-8 7 6 5 4 3 2 1 0 DESCRIPTION Reserved. Ignore on read. INT7. 1= ENERGYON generated, 0= not source of interrupt INT6. 1= Auto-Negotiation complete, 0= not source of interrupt INT5. 1= Remote Fault Detected, 0= not source of interrupt INT4. 1= Link Down (link status negated), 0= not source of interrupt INT3. 1= Auto-Negotiation LP Acknowledge, 0= not source of interrupt INT2. 1= Parallel Detection Fault, 0= not source of interrupt INT1. 1= Auto-Negotiation Page Received, 0= not source of interrupt Reserved. TYPE RO/LH RO/LH RO/LH RO/LH RO/LH RO/LH RO/LH RO/LH RO/LH DEFAULT 0 0 0 0 0 0 0 0 0 Revision 1.1 (05-17-05) DATASHEET 108 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 5.5.12 Interrupt Mask Index (In Decimal): 30 Size: 16-bits BITS 15-8 7-0 DESCRIPTION Reserved. Write as 0; ignore on read. Mask Bits. 1 = interrupt source is enabled 0 = interrupt source is masked TYPE RO RW DEFAULT 0 0 5.5.13 PHY Special Control/Status Index (In Decimal): 31 Size: 16-bits BITS 15 - 13 12 DESCRIPTION Reserved. Autodone. Auto-negotiation done indication: 0 = Auto-negotiation is not done or disabled (or not active) 1 = Auto-negotiation is done Reserved. Write as 0000010b, ignore on Read. Speed Indication. HCDSPEED value: [001]=10Mbps half-duplex [101]=10Mbps full-duplex [010]=100Base-TX half-duplex [110]=100Base-TX full-duplex Reserved. Write as 0; ignore on Read Note 5.3 TYPE RO RO DEFAULT 000b 0b 11-5 4-2 RW RO 0000010b See Note 5.3 1-0 RO 00b See Table 2.2, “Default Ethernet Settings,” on page 15, for default settings. SMSC LAN9118 DATASHEET 109 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 6 Timing Diagrams 6.1 Host Interface Timing The LAN9118 supports the following host cycles: Read Cycles: ■ ■ ■ ■ PIO Reads (nCS or nRD controlled) PIO Burst Reads (nCS or nRD controlled) RX Data FIFO Direct PIO Reads (nCS or nRD controlled) RX Data FIFO Direct PIO Burst Reads (nCS or nRD controlled) Write Cycles: ■ ■ PIO writes (nCS and nWR controlled) TX Data FIFO direct PIO writes (nCS or nWR controlled) 6.1.1 Special Restrictions on Back-to-Back Write/Read Cycles It is important to note that there are specific restrictions on the timing of back-to-back write-read operations. These restrictions concern reading the control registers after any write cycle to the LAN9118 device. In many cases there is a required minimum delay between writing to the LAN9118, and the subsequent side effect (change in the control register value). For example, when writing to the TX Data FIFO, it takes up to 135ns for the level indication to change in the TX_FIFO_INF register. In order to prevent the host from reading stale data after a write operation, minimum wait periods must be enforced. These periods are specified in Table 6.1, "Read After Write Timing Rules". The host processor is required to wait the specified period of time after any write to the LAN9118 before reading the resource specified in the table. These wait periods are for read operations that immediately follow any write cycle. Note that the required wait period is dependant upon the register being read after the write. Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the minimum write-to-read timing restriction is met. Table 6.1 also shows the number of dummy reads that are required before reading the register indicated. The number of BYTE_TEST reads in this table is based on the minimum timing for Tcycle (45ns). For microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the table. Note that dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met. Table 6.1 Read After Write Timing Rules MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) 0 135 90 45 0 45 110 REGISTER NAME ID_REV IRQ_CFG INT_STS INT_EN BYTE_TEST FIFO_INT Revision 1.1 (05-17-05) NUMBER OF BYTE_TEST READS (ASSUMING TCYCLE OF 45NS) 0 3 2 1 0 1 SMSC LAN9118 DATASHEET High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 6.1 Read After Write Timing Rules (continued) MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) 45 45 45 45 0 135 315 45 45 135 45 180 0 45 45 45 45 45 NUMBER OF BYTE_TEST READS (ASSUMING TCYCLE OF 45NS) 1 1 1 1 0 3 7 1 1 3 1 4 0 1 1 1 1 1 REGISTER NAME RX_CFG TX_CFG HW_CFG RX_DP_CTRL RX_FIFO_INF TX_FIFO_INF PMT_CTRL GPIO_CFG GPT_CFG GPT_CNT ENDIAN FREE_RUN RX_DROP MAC_CSR_CMD MAC_CSR_DATA AFC_CFG E2P_CMD E2P_DATA 6.1.2 Special Restrictions on Back-to-Back Read Cycles There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific registers after reading resources that have side effects. In many cases there is a delay between reading the LAN9118, and the subsequent indication of the expected change in the control register values. In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been established. These periods are specified in Table 6.2, "Read After Read Timing Rules". The host processor is required to wait the specified period of time between read operations of specific combinations of resources. The wait period is dependant upon the combination of registers being read. Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the minimum wait time restriction is met. Table 6.2 also shows the number of dummy reads that are required for back-to-back read operations. The number of BYTE_TEST reads in this table is based on the minimum timing for Tcycle (45ns). For microprocessors with slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time specified in the table. Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met. SMSC LAN9118 DATASHEET 111 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 6.2 Read After Read Timing Rules AFTER READING... RX Data FIFO RX Status FIFO TX Status FIFO RX_DROP WAIT FOR THIS MANY NS… 135 135 135 180 OR PERFORM THIS MANY READS OF BYTE_TEST… (ASSUMING Tcycle OF 45NS) 3 3 3 4 BEFORE READING... RX_FIFO_INF RX_FIFO_INF TX_FIFO_INF RX_DROP 6.2 PIO Reads PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing diagram. PIO reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between cycles for the period specified. PIO reads are supported for both 16- and 32-bit access. Timing for 16-bit and 32-bit PIO Read cycles is identical with the exception that D[31:16] are not driven during a 16-bit read. Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read cycles. A[7:1] nCS, nRD Data Bus Figure 6.1 LAN9118 PIO Read Cycle Timing Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths Revision 1.1 (05-17-05) DATASHEET 112 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 6.3 PIO Read Timing SYMBOL tcycle tcsl tcsh tcsdv tasu tah tdon tdoff tdoh DESCRIPTION Read Cycle Time nCS, nRD Assertion Time nCS, nRD Deassertion Time nCS, nRD Valid to Data Valid Address Setup to nCS, nRD Valid Address Hold Time Data Buffer Turn On Time Data Buffer Turn Off Time Data Output Hold Time 0 0 0 0 7 MIN 45 32 13 30 TYP MAX UNITS ns ns ns ns ns ns ns ns ns Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. 6.3 PIO Burst Reads In this mode, performance is improved by allowing up to 8, DWORD read cycles, or 16, WORD read cycles back-to-back. PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between bursts for the period specified. Timing for 16-bit and 32-bit PIO Burst Mode Read cycles is identical, with the exception that D[31:16] are not driven during a 16-bit burst. A[7:5] A[4:1] nCS, nRD Data Bus Figure 6.2 LAN9118 PIO Burst Read Cycle Timing SMSC LAN9118 113 Revision 1.1 (05-17-05) DATASHEET High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths Table 6.4 PIO Burst Read Timing SYMBOL tcsh tcsdv tacyc tasu tadv tah tdon tdoff tdoh DESCRIPTION nCS, nRD Deassertion Time nCS, nRD Valid to Data Valid Address Cycle Time Address Setup to nCS, nRD valid Address Stable to Data Valid Address Hold Time Data Buffer Turn On Time Data Buffer Turn Off Time Data Output Hold Time 0 0 0 7 45 0 40 ns ns ns ns ns MIN 13 30 TYP MAX UNITS ns ns Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. 6.4 RX Data FIFO Direct PIO Reads In this mode the upper address inputs are not decoded, and any read of the LAN9118 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9118. Timing is identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address lines. Timing for 16-bit and 32-bit Direct PIO Read cycles is identical with the exception that D[31:16] is not driven during a 16-bit read. Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored. Revision 1.1 (05-17-05) DATASHEET 114 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet FIFO_SEL A[2:1] nCS, nRD Data Bus Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths Table 6.5 RX Data FIFO Direct PIO Read Timing SYMBOL tcycle tcsl tcsh tcsdv tasu tah tdon tdoff tdoh DESCRIPTION Read Cycle Time nCS, nRD Assertion Time nCS, nRD Deassertion Time nCS, nRD Valid to Data Valid Address, FIFO_SEL Setup to nCS, nRD Valid Address, FIFO_SEL Hold Time Data Buffer Turn On Time Data Buffer Turn Off Time Data Output Hold Time 0 0 0 0 7 MIN 45 32 13 30 TYP MAX UNITS ns ns ns ns ns ns ns ns ns Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and deasserted in any order. 6.5 RX Data FIFO Direct PIO Burst Reads In this mode the upper address inputs are not decoded, and any burst read of the LAN9118 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9118. Timing SMSC LAN9118 DATASHEET 115 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the address lines. In this mode, performance is improved by allowing an unlimited number of back-to-back DWORD or WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). When either or both of these control signals go high, they must remain high for the period specified. Timing for 16-bit and 32-bit RX Data FIFO Direct PIO Burst Reads is identical with the exception that D[31:16] are not driven during a 16-bit burst. Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored. FIFO_SEL A[2:1] nCS, nRD Data Bus Figure 6.4 RX Data FIFO Direct PIO Burst Read Cycle Timing Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing SYMBOL tcsh tcsdv tacyc tasu tadv tah tdon tdoff tdoh DESCRIPTION nCS, nRD Deassertion Time nCS, nRD Valid to Data Valid Address Cycle Time Address, FIFO_SEL Setup to nCS, nRD Valid Address Stable to Data Valid Address, FIFO_SEL Hold Time Data Buffer Turn On Time Data Buffer Turn Off Time Data Output Hold Time 0 0 0 7 45 0 40 ns ns ns ns ns MIN 13 30 TYP MAX UNITS ns ns Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. Revision 1.1 (05-17-05) DATASHEET 116 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.6 PIO Writes PIO writes are used for all LAN9118 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). Either or both of these control signals must go high between cycles for the period specified. PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are identical with the exception that D[31:16] are ignored during a 16-bit write. A[7:1] nCS, nRD Data Bus Figure 6.5 PIO Write Cycle Timing Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths Table 6.7 PIO Write Cycle Timing SYMBOL tcycle tcsl tcsh tasu tah tdsu tdh DESCRIPTION Write Cycle Time nCS, nWR Assertion Time nCS, nWR Deassertion Time Address Setup to nCS, nWR Assertion Address Hold Time Data Setup to nCS, nWR Deassertion Data Hold Time MIN 45 32 13 0 0 7 0 TYP MAX UNITS ns ns ns ns ns ns ns Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are deasserted. They may be asserted and deasserted in any order. SMSC LAN9118 DATASHEET 117 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.7 TX Data FIFO Direct PIO Writes In this mode the upper address inputs are not decoded, and any write to the LAN9118 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9118. Timing is identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address lines. Timing for 16-bit and 32-bit cycles is identical with the exception that D[31:16] is ignored during a 16bit write. Note that address lines A[2:1] are still used when the LAN9118 is operating in 32-bit and 16bit mode. Address bits A[7:3] are ignored. FIFO_SEL A[2:1] nCS, nRD Data Bus Figure 6.6 TX Data FIFO Direct PIO Write Timing Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths Table 6.8 TX Data FIFO Direct PIO Write Timing SYMBOL tcycle tcsl tcsh tasu tah tdsu tdh DESCRIPTION Write Cycle Time nCS, nWR Assertion Time nCS, nWR Deassertion Time Address, FIFO_SEL Setup to nCS, nWR Assertion Address, FIFO_SEL Hold Time Data Setup to nCS, nWR Deassertion Data Hold Time MIN 45 32 13 0 0 7 0 TYP MAX UNITS ns ns ns ns ns ns ns Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are deasserted. They may be asserted and deasserted in any order. Revision 1.1 (05-17-05) DATASHEET 118 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 6.8 Reset Timing T6.1 nRST T6.2 Configuration signals T6.4 Output drive T6.3 Table 6.9 Reset Timing PARAMETER T6.1 T6.2 T6.3 T6.4 DESCRIPTION Reset Pulse Width Configuration input setup to nRST rising Configuration input hold after nRST rising Output Drive after nRST rising MIN 200 200 10 16 TYP MAX UNITS us ns ns ns NOTES 6.9 EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9118 Figure 6.7 EEPROM Timing SMSC LAN9118 DATASHEET 119 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 6.10 EEPROM Timing Values SYMBOL tCKCYC tCKH tCKL tCSHCKH tCKLCSL tDVCKH tCKHDIS tDSCKH tDHCKH tCKLDIS tCSHDV tDHCSL tCSL DESCRIPTION EECLK Cycle time EECLK High time EECLK Low time EECS high before rising edge of EECLK EECLK falling edge to EECS low EEDIO valid before rising edge of EECLK (OUTPUT) EEDIO disable after rising edge EECLK (OUTPUT) EEDIO setup to rising edge of EECLK (INPUT) EEDIO hold after rising edge of EECLK (INPUT) EECLK low to data disable (OUTPUT) EEDIO valid after EECS high (VERIFY) EEDIO hold after EECS low (VERIFY) EECS low 0 1070 MIN 1110 550 550 1070 30 550 550 90 0 580 600 TYP MAX 1130 570 570 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns Revision 1.1 (05-17-05) DATASHEET 120 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 7 Operational Characteristics 7.1 Absolute Maximum Ratings* Supply Voltage ................................................................................................................... +3.3V +/- 10% Operating Temperature ..........................................................................................................0°C to 70°C Storage Temperature.........................................................................................................-65°C to 150°C Positive Voltage on any pin, with respect to Ground ........................................................................ 5.5V Negative Voltage on any pin, with respect to Ground ..................................................................... -0.3V Note: These maximum ratings do not apply to the following analog pins - ATEST, RBIAS, EXRES1, TPO +/-, TPI +/* Stresses exceeding those listed above could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. 7.2 Power Consumption Device Only Power measurements taken under the following conditions: Temperature: .................................................................................................................................. +25° C Device VDD:..................................................................................................................................+3.30 V Table 7.1 Power Consumption Device Only MODE 10BASE-T Operation D0, 10BASE-T /w traffic D0, Idle D1, 10BASE-T /w traffic D1, Idle D2, Energy Detect Power Down D2, General Power Down 100BASE-TX Operation D0, 100BASE-TX /w traffic D0, Idle D1, 100BASE-T /w traffic 422 367 262 121 Revision 1.1 (05-17-05) TOTAL POWER - TYPICAL (MW) 244 225 120 120 35 11 SMSC LAN9118 DATASHEET High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 7.1 Power Consumption Device Only (continued) MODE D1, Idle D2, Energy Detect Power Down (Cable disconnected) D2, General Power Down Note 7.1 Note 7.2 TOTAL POWER - TYPICAL (MW) 262 35 11 Each LED indicator in use adds approximately 4 mA to the Digital power supply. D0 = Normal Operation, D1 = WOL (Wake On LAN mode), D2= Low Power Energy Detect. 7.3 Power Consumption Device and System Components This section describes typical power consumption values of a total Ethernet LAN connectivity solution, which includes external components supporting the SMSC Ethernet controller. The values below should be used as comparision measurements only for power provisioning. Please refer to application note “AN 12-5 Designing with the LAN9118 - Getting Started”, that can be found on SMSC’s web site www.smsc.com, which details the magnetics and other components used. Power measurements taken under the following conditions: Temperature: .................................................................................................................................. +25° C Device VDD:..................................................................................................................................+3.30 V Table 7.2 Power Consumption Device and System Components MODE 10BASE-T Operation D0, 10BASE-T /w traffic D0, Idle D1, 10BASE-T /w traffic D1, Idle D2, Energy Detect Power Down D2, General Power Down 100BASE-TX Operation D0, 100BASE-TX /w traffic D0, Idle D1, 100BASE-T /w traffic D1, Idle D2, Energy Detect Power Down D2, General Power Down Note 7.3 Revision 1.1 (05-17-05) TOTAL POWER - TYPICAL (MW) 614 637 513 513 56 32 518 576 414 414 56 32 Each LED indicator in use adds approximately 4 mA to the Digital power supply. DATASHEET 122 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet 7.4 DC Electrical Specifications Table 7.3 I/O Buffer Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS NOTES I Type Input Buffer Low Input Level High Input Level IS Type Input Buffer Negative-Going Threshold Positive-Going Threshold Schmitt Trigger Hysteresis (VIHT - VILT) O12 Type Buffer Low Output Level High Output Level OD12 Type Buffer Low Output Level IO8 Type Buffer Low Input Level High Input Level Low Output Level High Output Level OD8 Type Buffer Low Output Level O8 Type Buffer Low Output Level High Output Level ICLK Input Buffer Low Input Level High Input Level VILCK VIHCK 1.4 0.5 V V VOL VOH 0.4 VDD - 0.4 V V IOL = 8mA IOH = -8mA VOL 0.4 V IOL = 8mA VILI VIHI VOL VOH -0.3 2.0 0.4 VDD - 0.4 0.8 5.5 V V V V IOL = 8mA IOH = -8mA VOL 0.4 V IOL = 12mA VOL VOH 0.4 VDD - 0.4 V V IOL = 12mA IOH = -12mA VILT VIHT VHYS 1.05 1.3 198 1.26 1.53 264 1.47 1.71 300 V V mV Schmitt Trigger Schmitt Trigger VILI VIHI -0.3 2.0 0.8 5.5 V V SMSC LAN9118 DATASHEET 123 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 7.4 100BASE-TX Tranceiver Characteristics PARAMETER Peak Differential Output Voltage High Peak Differential Output Voltage Low Signal Amplitude Symmetry Signal Rise & Fall Time Rise & Fall Time Symmetry Duty Cycle Distortion Overshoot & Undershoot Jitter Note 7.4 Note 7.5 Note 7.6 SYMBOL VPPH VPPL VSS TRF TRFS DCD VOS MIN 950 -950 98 3.0 35 TYP 50 MAX 1050 -1050 102 5.0 0.5 65 5 1.4 UNITS mVpk mVpk % nS nS % % nS Note 7.6 NOTES Note 7.4 Note 7.4 Note 7.4 Note 7.4 Note 7.4 Note 7.5 Measured at the line side of the transformer, line replaced by 100Ω (+/- 1%) resistor. Offset from16 nS pulse width at 50% of pulse peak Measured differentially. Table 7.5 10BASE-T Tranceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Note 7.7 SYMBOL VOUT VDS MIN 2.2 300 TYP 2.5 420 MAX 2.8 585 UNITS V mV NOTES Note 7.7 Measured at the line side of the transformer, line replaced by 100Ω (+/- 1%) resistor. 7.5 Clock Circuit The LAN9118 can accept either a 25MHz crystal (preferred) or a 25 MHz clock oscillator (±50 PPM) input. The LAN9118 shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1/CLKIN (pin 6). The Input Clock Duty Cycle is 40% minimum, 50% typical and 60% maximum. It is recommended that a crystal utilizing matching parallel load capacitors be used for the LAN9118 crystal input/output signals (XTAL1, XTAL2). See Table 7.6, "LAN9118 Crystal Specifications" for crystal specifications. Revision 1.1 (05-17-05) DATASHEET 124 SMSC LAN9118 High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Table 7.6 LAN9118 Crystal Specifications Frequency Tolerance @ 25° C Frequency Stability Over Temp Operating Temp Range Shunt Capacitance Load Capacitance Drive Level ±50 PPM ±50 PPM 0° C to 70° C 7.0 pF 20 pF ~ Parallel 0.5 mW Table 7.7 LAN9118 Recommended Crystals Fox Electronics FOXS/250F-20 Additionally, SMSC recommends a series resistor for the crystal circuit. Further details are provided in SMSC Application Note AN10.7 - “Parallel Crystal Circuit Input Voltage Control” and in the LAN9118 Reference Schematic. SMSC LAN9118 DATASHEET 125 Revision 1.1 (05-17-05) High Performance Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet Chapter 8 Package Outline Figure 8.1 100 Pin TQFP Package Definition Table 8.1 100 Pin TQFP Package Parameters A A1 A2 D D1 E E1 H L L1 e q W R1 R2 ccc MIN ~ 0.05 1.35 15.80 13.90 15.80 13.90 0.09 0.45 ~ 0o 0.17 0.08 0.08 ~ NOMINAL ~ ~ ~ ~ ~ ~ ~ ~ 0.60 1.00 0.50 Basic ~ 0.22 ~ ~ ~ MAX 1.60 0.15 1.45 16.20 14.10 16.20 14.10 0.20 0.75 ~ 7o 0.27 ~ 0.20 0.08 REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity Notes: 1. Controlling Unit: millimeter. 2. Tolerance on the true position of the leads is ± 0.04 mm maximum. 3. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. Revision 1.1 (05-17-05) 126 SMSC LAN9118 DATASHEET