LAN9512i

LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller PRODUCT FEATURES Highlights Two downstream ports, one upstream port — Two integrated downstream USB 2.0 PHYs — One integrated upstream USB 2.0 PHY — — — — — — — — — — Datasheet High-Performance 10/100 Ethernet Controller Fully compliant with IEEE802.3/802.3u Integrated Ethernet MAC and PHY 10BASE-T and 100BASE-TX support Full- and half-duplex support with flow control Preamble generation and removal Automatic 32-bit CRC generation and checking Automatic payload padding and pad removal Loop-back modes TCP/UDP checksum offload support Flexible address filtering modes – One 48-bit perfect address – 64 hash-filtered multicast addresses – Pass all multicast – Promiscuous mode – Inverse filtering – Pass all incoming with status report — Wakeup packet support — Integrated Ethernet PHY – Auto-negotiation, HP Auto-MDIX – Automatic polarity detection and correction – Energy Detect Integrated 10/100 Ethernet MAC with full-duplex support Integrated 10/100 Ethernet PHY with HP Auto-MDIX Implements Reduced Power Operating Modes Minimized BOM Cost — Single 25 MHz crystal (Eliminates cost of separate crystals for USB and Ethernet) — Built-in Power-On-Reset (POR) circuit (Eliminates requirement for external passive or active reset) Target Applications Desktop PCs Notebook PCs Printers Game Consoles Embedded Systems Docking Stations Power and I/Os — — — — — Three PHY LEDs Eight GPIOs Supports bus-powered and self-powered operation Internal 1.8v core supply regulator External 3.3v I/O supply Key Features USB Hub — Fully compliant with Universal Serial Bus Specification Revision 2.0 — HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) compatible — Two downstream ports, one upstream port — Port mapping and disable support — Port Swap: Programmable USB diff-pair pin location — PHY Boost: Programmable USB signal drive strength — Select presence of a permanently hardwired USB peripheral device on a port by port basis — Advanced power saving features — Downstream PHY goes into low power mode when port power to the port is disabled — Full Power Management with individual or ganged power control of each downstream port. — Integrated USB termination Pull-up/Pull-down resistors — Internal short circuit protection of USB differential signal pins SMSC LAN9512/LAN9512i Miscellaneous features — Optional EEPROM — Optional 24MHz reference clock output for partner hub — IEEE 1149.1 (JTAG) Boundary Scan Software — — — — — Windows 2000/XP/Vista Driver Linux Driver Win CE Driver MAC OS Driver EEPROM Utility Packaging — 64-pin QFN, lead-free RoHS compliant Environmental — — — — — Commercial Temperature Range (0°C to +70°C) Industrial Temperature Range (-40°C to +85°C) ±8kV HBM without External Protection Devices ±8kV contact mode (IEC61000-4-2) ±15kV air-gap discharge mode (IEC61000-4-2) Revision 1.0 (11-24-09) DATASHEET USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Order Numbers: LAN9512-JZX for 64-pin, QFN lead-free RoHS compliant package (0 to +70°C temp range) LAN9512i-JZX for 64-pin, QFN lead-free RoHS compliant package (-40 to +85°C temp range) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.com/rohs 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 1.0 (11-24-09) DATASHEET 2 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table of Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.2 USB Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.3 Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.4 EEPROM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.5 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 7 7 7 7 Chapter 2 Pin Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 2.2 Port Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.1 Port Power Control Using a USB Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Port Power Control Using a Poly Fuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 19 Chapter 3 EEPROM Controller (EPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 3.2 3.3 3.4 EEPROM Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Hub Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Auto-Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . An Example of EEPROM Format Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 23 32 32 33 Chapter 4 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1 4.2 4.3 4.4 4.5 Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Operational Current Consumption & Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.4 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 38 39 39 40 42 42 42 43 44 45 4.6 Chapter 5 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.1 64-QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Chapter 6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SMSC LAN9512/LAN9512i DATASHEET 3 Revision 1.0 (11-24-09) USB 2.0 Hub and 10/100 Ethernet Controller Datasheet List of Figures Figure 1.1 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 4.1 Figure 4.1 Figure 4.2 Figure 5.1 Figure 5.2 Internal Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 LAN9512/LAN9512i 64-QFN Pin Assignments (TOP VIEW). . . . . . . . . . . . . . . . . . . . . . . . . . 9 Port Power Control with USB Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Port Power Control with Poly Fuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Port Power with Ganged Control with Poly Fuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 LAN9512/LAN9512i 64-QFN Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 LAN9512/LAN9512i Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Revision 1.0 (11-24-09) DATASHEET 4 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet List of Tables Table 2.1 EEPROM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.2 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.3 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.4 USB Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.5 Ethernet PHY Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.6 I/O Power Pins, Core Power Pins, and Ground Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.7 No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.8 64-QFN Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.9 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.1 EEPROM Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.2 Configuration Flags Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.3 Hub Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.4 Config Data Byte 1 Register (CFG1) Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.5 Config Data Byte 2 Register (CFG2) Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.6 Config Data Byte 3 Register (CFG3) Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.7 Boost_Up Register (BOOSTUP) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.8 Boost_3:2 Register (BOOST32) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.9 Status/Command Register (STCD) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.10 EEPROM Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.11 Dump of EEPROM Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.12 EEPROM Example - 256 Byte EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.1 Operational Current Consumption & Power Dissipation (VDD33IO = VDD33A = 3.3V) . . . . . Table 4.2 I/O Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.3 100BASE-TX Transceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.4 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.5 EEPROM Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.6 JTAG Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.7 LAN9512/LAN9512i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.1 LAN9512/LAN9512i 64-QFN Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 10 12 13 14 14 15 19 20 22 23 28 29 30 30 30 31 32 33 34 39 40 41 41 43 44 45 46 48 SMSC LAN9512/LAN9512i DATASHEET 5 Revision 1.0 (11-24-09) USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Chapter 1 Introduction 1.1 Block Diagram LAN9512/LAN9512i JTAG TAP Controller Upstream USB PHY USB DP/DM USB 2.0 Hub 10/100 Ethernet Controller EEPROM Controller Ethernet PHY EEPROM Ethernet Downstream USB PHY USB DP/DM Downstream USB PHY USB DP/DM Figure 1.1 Internal Block Diagram 1.1.1 Overview The LAN9512/LAN9512i is a high performance Hi-Speed USB 2.0 hub with a 10/100 Ethernet controller. With applications ranging from embedded systems, desktop PCs, notebook PCs, printers, game consoles, and docking stations, the LAN9512/LAN9512i is targeted as a high performance, low cost USB/Ethernet and USB/USB connectivity solution. The LAN9512/LAN9512i contains an integrated USB 2.0 hub, two integrated downstream USB 2.0 PHYs, an integrated upstream USB 2.0 PHY, a 10/100 Ethernet PHY, a 10/100 Ethernet Controller, a TAP controller, and a EEPROM controller. A block diagram of the LAN9512/LAN9512i is provided in Figure 1.1. The LAN9512/LAN9512i hub provides over 30 programmable features, including: PortMap ( also referred to as port remap) which provides flexible port mapping and disabling sequences. The downstream ports of the LAN9512/LAN9512i hub can be reordered or disabled in any sequence to support multiple platform designs’ with minimum effort. For any port that is disabled, the LAN9512/LAN9512i automatically reorders the remaining ports to match the USB host controller’s port numbering scheme. PortSwap which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment of USB signals (D+/D-) to connectors avoiding uneven trace length or crossing of the USB differential signals on the PCB. PHYBoost which enables four programmable levels of USB signal drive strength in USB port transceivers. PHYBoost attempts to restore USB signal integrity that has been compromised by system level variables such as poor PCB layout, long cables, etc.. Revision 1.0 (11-24-09) DATASHEET 6 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet 1.1.2 USB Hub The integrated USB hub is fully compliant with the USB 2.0 Specification and will attach to a USB host as a Full-Speed Hub or as a Full-/High-Speed Hub. The hub supports Low-Speed, Full-Speed, and High-Speed (if operating as a High-Speed hub) downstream devices on all of the enabled downstream ports. A dedicated Transaction Translator (TT) is available for each downstream facing port. This architecture ensures maximum USB throughput for each connected device when operating with mixed-speed peripherals. The hub works with an external USB power distributed switch device to control VBUS switching to downstream ports, and to limit current and sense over-current conditions. All required resistors on the USB ports are integrated into the hub. This includes all series termination resistors on D+ and D- pins and all required pull-down and pull-up resistors on D+ and D- pins. The over-current sense inputs for the downstream facing ports have internal pull-up resistors. Two external ports are available for general USB device connectivity. 1.1.3 Ethernet Controller The 10/100 Ethernet controller provides an integrated Ethernet MAC and PHY which are fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant. The 10/100 Ethernet controller also supports numerous power management wakeup features, including “Magic Packet”, “Wake on LAN” and “Link Status Change”. These wakeup events can be programmed to initiate a USB remote wakeup. The 10/100 Ethernet PHY integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY block includes support for auto-negotiation, full or half-duplex configuration, auto-polarity correction and Auto-MDIX. Minimal external components are required for the utilization of the integrated PHY. The Ethernet controller implements four USB endpoints: Control, Interrupt, Bulk-in, and Bulk-out. The Bulk-in and Bulk-out Endpoints allow for Ethernet reception and transmission respectively. Implementation of vendor-specific commands allows for efficient statistics gathering and access to the Ethernet controller’s system control and status registers. 1.1.4 EEPROM Controller The LAN9512/LAN9512i contains an EEPROM controller for connection to an external EEPROM. This allows for the automatic loading of static configuration data upon power-on reset, pin reset, or software reset. The EEPROM can be configured to load USB descriptors, USB device configuration, and the MAC address. 1.1.5 Peripherals The LAN9512/LAN9512i also contains a TAP controller, and provides three PHY LED indicators, as well as eight general purpose I/O pins. All GPIOs can serve as remote wakeup events when LAN9512/LAN9512i is in a suspended state. The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG. 1.1.6 Power Management The LAN9512/LAN9512i features three variations of USB suspend: SUSPEND0, SUSPEND1, and SUSPEND2. These modes allow the application to select the ideal balance of remote wakeup functionality and power consumption. SUSPEND0: Supports GPIO, “Wake On LAN”, and “Magic Packet” remote wakeup events. This suspend state reduces power by stopping the clocks of the MAC and other internal modules. SMSC LAN9512/LAN9512i DATASHEET 7 Revision 1.0 (11-24-09) USB 2.0 Hub and 10/100 Ethernet Controller Datasheet SUSPEND1: Supports GPIO and “Link Status Change” for remote wakeup events. This suspend state consumes less power than SUSPEND0. SUSPEND2: Supports only GPIO assertion for a remote wakeup event. This is the default suspend mode for the LAN9512/LAN9512i. Revision 1.0 (11-24-09) DATASHEET 8 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Chapter 2 Pin Description and Configuration VDD18ETHPLL AUTOMDIX_EN VDD18CORE CLK24_OUT CLK24_EN VDD33IO VDD33IO 48 47 46 45 44 43 GPIO7 42 41 40 39 38 37 36 35 34 VDD33A EXRES VDD33A RXP RXN VDD33A TXP TXN VDD33A USBDM0 USBDP0 XO XI VDD18USBPLL USBRBIAS VDD33A 33 VDD33IO TEST3 TEST4 TEST2 GPIO5 GPIO4 GPIO3 GPIO6 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TCK TDO TDI TMS nTRST VDD33IO EEDI EEDO EECS EECLK nSPD_LED/GPIO2 nLNKA_LED/GPIO1 nFDX_LED/GPIO0 VDD33IO NC NC SMSC LAN9512/LAN9512i 64 PIN QFN (TOP VIEW) VSS 1 2 3 4 5 6 7 8 USBDP2 9 VBUS_DET NC NC NC VDD33A NC USBDM2 USBDM3 USBDP3 VDD33A nRESET TEST1 VDD18CORE PRTCTL2 NOTE: When HP Auto-MDIX is activated, the TXN/TXP pins can function as RXN/RXP and vice-versa NOTE: Exposed pad (VSS) on bottom of package must be connected to ground Figure 2.1 LAN9512/LAN9512i 64-QFN Pin Assignments (TOP VIEW) SMSC LAN9512/LAN9512i DATASHEET 9 PRTCTL3 Revision 1.0 (11-24-09) USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 2.1 EEPROM Pins NUM PINS 1 1 1 1 BUFFER TYPE IS (PD) O8 O8 O8 NAME EEPROM Data In EEPROM Data Out EEPROM Chip Select EEPROM Clock SYMBOL EEDI EEDO EECS EECLK DESCRIPTION This pin is driven by the EEDO output of the external EEPROM. This pin drives the EEDI input of the external EEPROM. This pin drives the chip select output of the external EEPROM. This pin drives the EEPROM clock of the external EEPROM. Table 2.2 JTAG Pins NUM PINS BUFFER TYPE IS NAME JTAG Test Port Reset SYMBOL nTRST DESCRIPTION This active low pin functions as the JTAG test port reset input. Note: This pin should be tied high if it is not used. 1 1 1 1 1 JTAG Test Mode Select JTAG Test Data Input JTAG Test Data Out JTAG Test Clock TMS TDI TDO TCK IS IS O12 IS This pin functions as the JTAG test mode select. This pin functions as the JTAG data input. This pin functions as the JTAG data output. This pin functions as the JTAG test clock. Table 2.3 Miscellaneous Pins NUM PINS BUFFER TYPE IS NAME System Reset SYMBOL nRESET DESCRIPTION This active low pin allows external hardware to reset the device. Note: This pin should be tied high if it is not used. 1 1 Ethernet Full-Duplex Indicator LED General Purpose I/O 0 nFDX_LED OD12 (PU) IS/O12/ OD12 (PU) This pin is driven low (LED on) when the Ethernet link is operating in full-duplex mode. This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. GPIO0 Revision 1.0 (11-24-09) DATASHEET 10 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 2.3 Miscellaneous Pins (continued) NUM PINS BUFFER TYPE OD12 (PU) NAME Ethernet Link Activity Indicator LED SYMBOL nLNKA_LED DESCRIPTION This pin is driven low (LED on) when a valid link is detected. This pin is pulsed high (LED off) for 80mS whenever transmit or receive activity is detected. This pin is then driven low again for a minimum of 80mS, after which time it will repeat the process if TX or RX activity is detected. Effectively, LED2 is activated solid for a link. When transmit or receive activity is sensed, LED2 will function as an activity indicator. This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. This pin is driven low (LED on) when the Ethernet operating speed is 100Mbs, or during autonegotiation. This pin is driven high during 10Mbs operation, or during line isolation. This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. This General Purpose I/O pin is fully programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. This pin detects the state of the upstream bus power. The Hub monitors VBUS_DET to determine when to assert the USBDP0 pin's internal pull-up resistor (signaling a connect event). For bus powered hubs, this pin must be tied to VDD33IO. For self powered hubs where the device is permanently attached to a host, VBUS_DET should be pulled to VDD33IO. For other self powered applications, refer to the device reference schematic for additional connection information. 1 General Purpose I/O 1 Ethernet Speed Indicator LED 1 General Purpose I/O 2 General Purpose I/O 3 General Purpose I/O 4 General Purpose I/O 5 General Purpose I/O 6 General Purpose I/O 7 Detect Upstream VBUS Power GPIO1 IS/O12/ OD12 (PU) OD12 (PU) nSPD_LED GPIO2 IS/O12/ OD12 (PU) IS/O8/ OD8 (PU) IS/O8/ OD8 (PU) IS/O8/ OD8 (PU) IS/O8/ OD8 (PU) IS/O8/ OD8 (PU) IS_5V 1 GPIO3 1 GPIO4 1 GPIO5 1 GPIO6 1 GPIO7 VBUS_DET 1 1 Auto-MDIX Enable AUTOMDIX_EN IS Determines the default Auto-MDIX setting. 0 = Auto-MDIX is disabled. 1 = Auto-MDIX is enabled. SMSC LAN9512/LAN9512i DATASHEET 11 Revision 1.0 (11-24-09) USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 2.3 Miscellaneous Pins (continued) NUM PINS 1 BUFFER TYPE - NAME Test 1 SYMBOL TEST1 DESCRIPTION Used for factory testing, this pin must always be left unconnected. Used for factory testing, this pin must always be connected to VSS for proper operation. Used for factory testing, this pin must always be connected to VDD33IO for proper operation. This pin enables the generation of the 24 MHz clock on the CLK_24_OUT pin. This pin outputs a 24 MHz clock that can be used a reference clock for a partner hub. Used for factory testing, this pin must always be left unconnected. 1 Test 2 Test 3 TEST2 TEST3 - 1 1 1 1 24 MHz Clock Enable 24 MHz Clock Test 4 CLK24_EN CLK24_OUT TEST4 IS 08 - Table 2.4 USB Pins NUM PINS 1 1 1 1 1 1 BUFFER TYPE AIO AIO NAME Upstream USB DMINUS 0 Upstream USB DPLUS 0 Downstream USB DMINUS 2 Downstream USB DPLUS 2 Downstream USB DMINUS 3 Downstream USB DPLUS 3 USB Port Power Control 2 SYMBOL USBDM0 USBDP0 DESCRIPTION Upstream USB DMINUS signal. Upstream USB DPLUS signal. USBDM2 USBDP2 USBDM3 USBDP3 PRTCTL2 AIO AIO AIO AIO IS/OD12 (PU) Downstream USB peripheral 2 DMINUS signal. Downstream USB peripheral 2 DPLUS signal. Downstream USB peripheral 3 DMINUS signal. Downstream USB peripheral 3 DPLUS signal. When used as an output, this pin enables power to downstream USB peripheral 2. When used as an input, this pin is used to sample the output signal from an external current monitor for downstream USB peripheral 2. An overcurrent condition is indicated when the signal is low. Refer to Section 2.1 for additional information. 1 Revision 1.0 (11-24-09) DATASHEET 12 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 2.4 USB Pins (continued) NUM PINS BUFFER TYPE IS/OD12 (PU) NAME USB Port Power Control 3 SYMBOL PRTCTL3 DESCRIPTION When used as an output, this pin enables power to downstream USB peripheral 3. When used as an input, this pin is used to sample the output signal from an external current monitor for downstream USB peripheral 3. An overcurrent condition is indicated when the signal is low. Refer to Section 2.1 for additional information. 1 1 External USB Bias Resistor USB PLL +1.8V Power Supply Crystal Input USBRBIAS AI Used for setting HS transmit current level and onchip termination impedance. Connect to an external 12K 1.0% resistor to ground. Refer to the LAN9512/LAN9512i reference schematics for additional connection information. External 25 MHz crystal input. Note: This pin can also be driven by a singleended clock oscillator. When this method is used, XO should be left unconnected 1 VDD18USBPLL P XI ICLK 1 1 Crystal Output XO OCLK External 25 MHz crystal output. Table 2.5 Ethernet PHY Pins NUM PINS BUFFER TYPE AIO NAME Ethernet TX Data Out Negative Ethernet TX Data Out Positive Ethernet RX Data In Negative Ethernet RX Data In Positive +3.3V Analog Power Supply External PHY Bias Resistor Ethernet PLL +1.8V Power Supply SYMBOL TXN DESCRIPTION Negative output of the Ethernet transmitter. The transmit data outputs may be swapped internally with receive data inputs when Auto-MDIX is enabled. Positive output of the Ethernet transmitter. The transmit data outputs may be swapped internally with receive data inputs when Auto-MDIX is enabled. Negative input of the Ethernet receiver. The receive data inputs may be swapped internally with transmit data outputs when Auto-MDIX is enabled. Positive input of the Ethernet receiver. The receive data inputs may be swapped internally with transmit data outputs when Auto-MDIX is enabled. Refer to the LAN9512/LAN9512i reference schematics for connection information. Used for the internal bias circuits. Connect to an external 12.4K 1.0% resistor to ground. Refer to the LAN9512/LAN9512i reference schematics for additional connection information. 1 TXP AIO 1 1 RXN AIO 1 RXP AIO 7 VDD33A P 1 EXRES VDD18ETHPLL AI P 1 SMSC LAN9512/LAN9512i DATASHEET 13 Revision 1.0 (11-24-09) USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 2.6 I/O Power Pins, Core Power Pins, and Ground Pad NUM PINS BUFFER TYPE P NAME +3.3V I/O Power SYMBOL VDD33IO DESCRIPTION +3.3V Power Supply for I/O Pins. Refer to the LAN9512/LAN9512i reference schematics for connection information. 5 2 Digital Core +1.8V Power Supply Output VDD18CORE P +1.8 V power from the internal core voltage regulator. All VDD18CORE pins must be tied together for proper operation. Refer to the LAN9512/LAN9512i reference schematics for connection information. 1 Note 2.1 Ground VSS P Ground Note 2.1 Exposed pad on package bottom (Figure 2.1). Table 2.7 No-Connect Pins NUM PINS 6 BUFFER TYPE - NAME No Connect SYMBOL NC DESCRIPTION These pins must be left floating for normal device operation Revision 1.0 (11-24-09) DATASHEET 14 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 2.8 64-QFN Package Pin Assignments PIN NUM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NUM 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN NUM 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PIN NUM 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PIN NAME USBDM2 USBDP2 USBDM3 USBDP3 VDD33A NC NC NC NC VDD33A VBUS_DET nRESET TEST1 PRTCTL2 VDD18CORE PRTCTL3 PIN NAME NC NC VDD33IO nFDX_LED/ GPIO0 nLNKA_LED/ GPIO1 nSPD_LED/ GPIO2 EECLK EECS EEDO EEDI VDD33IO nTRST TMS TDI TDO TCK PIN NAME VDD33IO TEST2 GPIO3 GPIO4 GPIO5 VDD18CORE VDD33IO TEST3 AUTOMDIX_EN GPIO6 GPIO7 CLK24_EN CLK24_OUT VDD33IO TEST4 VDD18ETHPLL PIN NAME VDD33A EXRES VDD33A RXP RXN VDD33A TXP TXN VDD33A USBDM0 USBDP0 XO XI VDD18USBPLL USBRBIAS VDD33A EXPOSED PAD MUST BE CONNECTED TO VSS SMSC LAN9512/LAN9512i DATASHEET 15 Revision 1.0 (11-24-09) USB 2.0 Hub and 10/100 Ethernet Controller Datasheet 2.1 2.1.1 Port Power Control This section details the usage of the port power control pins PRTCTL[3:2]. Port Power Control Using a USB Power Switch The LAN9512/LAN9512i has a single port power control and over-current sense signal for each downstream port. When disabling port power the driver will actively drive a ‘0’. To avoid unnecessary power dissipation, the internal pull-up resistor will be disabled at that time. When port power is enabled, the output driver is disabled and the pull-up resistor is enabled, creating an open drain output. If there is an over-current situation, the USB Power Switch will assert the open drain OCS signal. The schmitt trigger input will recognize this situation as a low. The open drain output does not interfere. The overcurrent sense filter handles the transient conditions, such as low voltage, while the device is powering up. 5V PRTCTL3 OCS USB Power Switch EN LAN9512/ LAN9512i USB Device 5V PRTCTL2 OCS USB Power Switch EN USB Device Figure 2.2 Port Power Control with USB Power Switch Revision 1.0 (11-24-09) DATASHEET 16 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet 2.1.2 Port Power Control Using a Poly Fuse When using the LAN9512/LAN9512i with a poly fuse, an external diode must be used (See Figure 2.3). When disabling port power, the driver will drive a ‘0’. This procedure will have no effect since the external diode will isolate the pin from the load. When port power is enabled, the output driver is disabled and the pull-up resistor is enabled, which creates an open drain output. This means that the pull-up resistor is providing 3.3 volts to the anode of the diode. If there is an over-current situation, the poly fuse will open. This will cause the cathode of the diode to go to 0 volts. The anode of the diode will be at 0.7 volts, and the Schmidt trigger input will register this as a low, resulting in an overcurrent detection. The open drain output does not interfere. 5V Poly Fuse PRTCTL3 USB Device LAN9512/ LAN9512i 5V Poly Fuse PRTCTL2 USB Device Figure 2.3 Port Power Control with Poly Fuse SMSC LAN9512/LAN9512i DATASHEET 17 Revision 1.0 (11-24-09) USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Many customers use a single poly fuse to power all their devices. For the ganged situation, all power control pins must be tied together. 5V PRTCTL3 Poly Fuse LAN9512/ LAN9512i PRTCTL2 USB Device USB Device Figure 2.4 Port Power with Ganged Control with Poly Fuse Revision 1.0 (11-24-09) DATASHEET 18 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet 2.2 Buffer Types Table 2.9 Buffer Types BUFFER TYPE IS IS_5V O8 OD8 O12 OD12 PU Schmitt-triggered Input 5V Tolerant Schmitt-triggered Input DESCRIPTION Output with 8mA sink and 8mA source Open-drain output with 8mA sink Output with 12mA sink and 12mA source Open-drain output with 12mA sink 50uA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pullups are always enabled. Note: Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to LAN9512/LAN9512i. When connected to a load that must be pulled high, an external resistor must be added. PD 50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always enabled. Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to LAN9512/LAN9512i. When connected to a load that must be pulled low, an external resistor must be added. AI AIO ICLK OCLK P Analog input Analog bi-directional Crystal oscillator input pin Crystal oscillator output pin Power pin SMSC LAN9512/LAN9512i DATASHEET 19 Revision 1.0 (11-24-09) USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Chapter 3 EEPROM Controller (EPC) LAN9512/LAN9512i may use an external EEPROM to store the default values for the USB descriptors and the MAC address. The EEPROM controller supports most “93C46” type EEPROMs. A total of nine address bits are used to support 256/512 byte EEPROMs. Note: A 3-wire style 2K/4K EEPROM that is organized for 256/512 x 8-bit operation must be used. The MAC address is used as the default Ethernet MAC address and is loaded into the MAC’s ADDRH and ADDRL registers. If a properly configured EEPROM is not detected, it is the responsibility of the Host LAN Driver to set the IEEE addresses. After a system-level reset occurs, the device will load the default values from a properly configured EEPROM. The device will not accept USB transactions from the Host until this process is completed. The EEPROM controller also allows the Host system to read, write and erase the contents of the Serial EEPROM. 3.1 EEPROM Format Table 3.1 illustrates the format in which data is stored inside of the EEPROM. Note the EEPROM offsets are given in units of 16-bit word offsets. A length field with a value of zero indicates that the field does not exist in the EEPROM. The device will use the field’s HW default value in this case. Note: For Device Descriptors, the only valid values for the length are 0 and 18. Note: For Configuration and Interface Descriptors, the only valid values for the length are 0 and 18. Note: The EEPROM programmer must ensure that if a String Descriptor does not exist in the EEPROM, the referencing descriptor must contain 00h for the respective string index field. Note: If no Configuration Descriptor is present in the EEPROM, then the Configuration Flags affect the values of bmAttributes and bMaxPower in the Ethernet Controller Configuration Descriptor. Note: If all String Descriptor lengths are zero, then a Language ID will not be supported. Table 3.1 EEPROM Format EEPROM ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 0xA5 MAC Address [7:0] MAC Address [15:8] MAC Address [23:16] MAC Address [31:24] MAC Address [39:32] MAC Address [47:40] EEPROM CONTENTS Full-Speed Polling Interval for Interrupt Endpoint Hi-Speed Polling Interval for Interrupt Endpoint Revision 1.0 (11-24-09) DATASHEET 20 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 3.1 EEPROM Format (continued) 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh-1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh SMSC LAN9512/LAN9512i Configuration Flags Language ID Descriptor [7:0] Language ID Descriptor [15:8] Manufacturer ID String Descriptor Length (bytes) Manufacturer ID String Descriptor EEPROM Word Offset Product Name String Descriptor Length (bytes) Product Name String Descriptor EEPROM Word Offset Serial Number String Descriptor Length (bytes) Serial Number String Descriptor EEPROM Word Offset Configuration String Descriptor Length (bytes) Configuration String Descriptor Word Offset Interface String Descriptor Length (bytes) Interface String Descriptor Word Offset Hi-Speed Device Descriptor Length (bytes) Hi-Speed Device Descriptor Word Offset Hi-Speed Configuration and Interface Descriptor Length (bytes) Hi-Speed Configuration and Interface Descriptor Word Offset Full-Speed Device Descriptor Length (bytes) Full-Speed Device Descriptor Word Offset Full-Speed Configuration and Interface Descriptor Length (bytes) Full-Speed Configuration and Interface Descriptor Word Offset RESERVED Vendor ID LSB Register (VIDL) Vendor ID MSB Register (VIDM) Product ID LSB Register (PIDL) Product ID MSB Register (PIDM) Device ID LSB Register (DIDL) Device ID MSB Register (DIDM) Config Data Byte 1 Register (CFG1) Config Data Byte 2 Register (CFG2) Config Data Byte 3 Register (CFG3) Non-Removable Devices Register (NRD) Port Disable (Self) Register (PDS) Port Disable (Bus) Register (PDB) 21 Revision 1.0 (11-24-09) DATASHEET USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 3.1 EEPROM Format (continued) 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h Max Power (Self) Register (MAXPS) Max Power (Bus) Register (MAXPB) Hub Controller Max Current (Self) Register (HCMCS) Hub Controller Max Current (Bus) Register (HCMCB) Power-on Time Register (PWRT) Boost_Up Register (BOOSTUP) RESERVED Boost_3:2 Register (BOOST32) RESERVED Port Swap Register (PRTSP) Port Remap 12 Register (PRTR12) Port Remap 3 Register (PRTR3) RESERVED Status/Command Register (STCD) Note: EEPROM byte addresses past 39h can be used to store data for any purpose. Table 3.2 describes the Configuration Flags Table 3.2 Configuration Flags Description BIT 7:3 2 1 0 NAME RESERVED Remote Wakeup Support RESERVED Power Method 00000b 0 = The device does not support remote wakeup. 1 = The device supports remote wakeup. 0b 0 = The device Controller is bus powered. 1 = The device Controller is self powered. DESCRIPTION Revision 1.0 (11-24-09) DATASHEET 22 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet 3.1.1 Hub Configuration EEPROM offsets 20h through 39h comprise the Hub Configuration parameters. Table 3.3 describes these parameters and their default ROM values (Values assumed if no valid EEPROM present). Table 3.3 Hub Configuration EEPROM OFFSET 20h DESCRIPTION Vendor ID LSB Register (VIDL) Least Significant Byte of the Vendor ID. This is a 16-bit value that uniquely identifies the Vendor of the user device (assigned by USB-Interface Forum). Vendor ID MSB (VIDM) Most Significant Byte of the Vendor ID. This is a 16-bit value that uniquely identifies the Vendor of the user device (assigned by USB-Interface Forum). Product ID LSB Register (PIDL) Least Significant Byte of the Product ID. This is a 16-bit value that the Vendor can assign that uniquely identifies this particular product (assigned by the OEM). Product ID MSB Register (PIDM) Most Significant Byte of the Product ID. This is a 16-bit value that the Vendor can assign that uniquely identifies this particular product (assigned by the OEM). Device ID LSB Register (DIDL) Least Significant Byte of the Device ID. This is a 16-bit device release number in BCD format (assigned by the OEM). Device ID MSB Register (DIDM) Most Significant Byte of the Device ID. This is a 16-bit device release number in BCD format (assigned by the OEM). Config Data Byte 1 Register (CFG1) Refer to Table 3.4, “Config Data Byte 1 Register (CFG1) Format,” on page 28 for details. Config Data Byte 2 Register (CFG2) Refer to Table 3.5, “Config Data Byte 2 Register (CFG2) Format,” on page 29 for details. Config Data Byte 3 Register (CFG3) Refer to Table 3.6, “Config Data Byte 3 Register (CFG3) Format,” on page 30 for details. Non-Removable Devices Register (NRD) Indicates which port(s) include non-removable devices. 0 = Port is removable 1 = Port is non-removable Informs the host if one of the active ports has a permanent device that is not detachable from the Hub. Note: Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 The device must provide its own descriptor data. DEFAULT 24h 21h 04h 22h 12h 23h 95h 24h 00h 25h Note 3.1 26h 9Bh 27h 18h 28h 00h 29h 02h = RESERVED = RESERVED = RESERVED = RESERVED = 1; Port 3 non-removable = 1; Port 2 non-removable = 1; Port 1 non-removable is RESERVED, always = 0b Bit 1 must be set to 1 by firmware for proper identification of the Ethernet Controller as a non-removable device. 23 Revision 1.0 (11-24-09) Note: SMSC LAN9512/LAN9512i DATASHEET USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 3.3 Hub Configuration (continued) EEPROM OFFSET 2Ah DESCRIPTION Port Disable (Self) Register (PDS) Disables 1 or more ports. 0 = Port is available 1 = Port is disabled During Self-Powered operation, this selects the ports which will be permanently disabled, and are not available to be enabled or enumerated by a host controller. The ports can be disabled in any order, the internal logic will automatically report the correct number of enabled ports to the USB host, and will reorder the active ports in order to ensure proper function. Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 = RESERVED = RESERVED = RESERVED = RESERVED = 1; Port 3 disabled = 1; Port 2 disabled = 1; Port 1 disabled is RESERVED, always = 0b DEFAULT 30h 2Bh Port Disable (Bus) Register (PDB) Disables 1 or more ports. 0 = Port is available 1 = Port is disabled During Bus-Powered operation, this selects the ports which will be permanently disabled, and are not available to be enabled or enumerated by a host controller. The ports can be disabled in any order, the internal logic will automatically report the correct number of enabled ports to the USB host, and will reorder the active ports in order to ensure proper function. Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 = RESERVED = RESERVED = RESERVED = RESERVED = 1; Port 3 disabled = 1; Port 2 disabled = 1; Port 1 disabled is RESERVED, always = 0b 30h 2Ch Max Power (Self) Register (MAXPS) Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a self-powered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0mA in its descriptors. Note: The USB2.0 Specification does not permit this value to exceed 100mA. 01h 2Dh Max Power (Bus) Register (MAXPB) Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a bus-powered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0mA in its descriptors. 00h Revision 1.0 (11-24-09) DATASHEET 24 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 3.3 Hub Configuration (continued) EEPROM OFFSET 2Eh DESCRIPTION Hub Controller Max Current (Self) Register (HCMCS) Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a self-powered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value does NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound device. Note: The USB2.0 Specification does not permit this value to exceed 100mA. DEFAULT 01h 2Fh Hub Controller Max Current (Bus) Register (HCMCB) Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a bus-powered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value does NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound device. Power-on Time Register (PWRT) The length of time that it takes (in 2mS intervals) from the time the host initiated power-on sequence begins on a port until power is good on that port. System software uses this value to determine how long to wait before accessing a powered-on port. Boost_Up Register (BOOSTUP) Refer to Table 3.7, “Boost_Up Register (BOOSTUP) Format,” on page 30 for details. RESERVED Boost_3:2 Register (BOOST32) Refer to Table 3.8, “Boost_3:2 Register (BOOST32) Format,” on page 30 for details. RESERVED Port Swap Register (PRTSP) Swaps the Upstream and Downstream USB DP and DM pins for ease of board routing to devices and connectors. 0 = USB D+ functionality is associated with the DP pin and D- functionality is associated with the DM pin. 1 = USB D+ functionality is associated with the DM pin and D- functionality is associated with the DP pin. Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 = = = = = = = = RESERVED RESERVED RESERVED RESERVED 1; Port 3 DP/DM is swapped 1; Port 2 DP/DM is swapped RESERVED 1; Upstream Port DP/DM is swapped 00h 30h 32h 31h 32h 33h 34h 35h 00h 00h 00h 00h 00h SMSC LAN9512/LAN9512i DATASHEET 25 Revision 1.0 (11-24-09) USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 3.3 Hub Configuration (continued) EEPROM OFFSET 36h DESCRIPTION Port Remap 12 Register (PRTR12) When a hub is enumerated by a USB Host Controller, the hub is only permitted to report how many ports it has. The hub is not permitted to select a numerical range or assignment. The Host Controller will number the downstream ports of the hub starting with the number 1, up to the number of ports that the hub reported having. The host’s port number is referred to as “Logical Port Number” and the physical port on the hub is the “Physical Port Number”. When remapping mode is enabled, (see Port Re-Mapping Enable (PRTMAP_EN) bit in Config Data Byte 3 Register (CFG3) Format) the hub’s downstream port numbers can be remapped to different logical port numbers (assigned by the host). Note: The OEM must ensure that Contiguous Logical Port Numbers are used, starting from #1 up to the maximum number of enabled ports. This ensures that the hub’s ports are numbered in accordance with the way a Host will communicate with the ports. DEFAULT 21h Bit [7:4] = 0000 0001 0010 0011 Physical Port 2 is Disabled Physical Port 2 is mapped to Logical Port 1 Physical Port 2 is mapped to Logical Port 2 Physical Port 2 is mapped to Logical Port 3 All others RESERVED Bit [3:0] = 0000 0001 0010 0011 Physical Port 1 is Disabled Physical Port 1 is mapped to Logical Port 1 Physical Port 1 is mapped to Logical Port 2 Physical Port 1 is mapped to Logical Port 3 All others RESERVED Revision 1.0 (11-24-09) DATASHEET 26 SMSC LAN9512/LAN9512i USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 3.3 Hub Configuration (continued) EEPROM OFFSET 37h DESCRIPTION Port Remap 3 Register (PRTR3) When a hub is enumerated by a USB Host Controller, the hub is only permitted to report how many ports it has. The hub is not permitted to select a numerical range or assignment. The Host Controller will number the downstream ports of the hub starting with the number 1, up to the number of ports that the hub reported having. The host’s port number is referred to as “Logical Port Number” and the physical port on the hub is the “Physical Port Number”. When remapping mode is enabled (see Port Re-Mapping Enable (PRTMAP_EN) bit in Config Data Byte 3 Register (CFG3) Format), the hub’s downstream port numbers can be remapped to different logical port numbers (assigned by the host). Note: The OEM must ensure that Contiguous Logical Port Numbers are used, starting from #1 up to the maximum number of enabled ports, this ensures that the hub’s ports are numbered in accordance with the way a Host will communicate with the ports. DEFAULT 03h Bit [7:4] = Bit [3:0] = 0000 0001 0010 0011 RESERVED Physical Port 3 is Disabled Physical Port 3 is mapped to Logical Port 1 Physical Port 3 is mapped to Logical Port 2 Physical Port 3 is mapped to Logical Port 3 All others RESERVED 38h 39h RESERVED Status/Command Register (STCD) Refer to Table 3.9, “Status/Command Register (STCD) Format,” on page 31 for details. 00h 01h Note 3.1 Default value is dependent on device revision. SMSC LAN9512/LAN9512i DATASHEET 27 Revision 1.0 (11-24-09) USB 2.0 Hub and 10/100 Ethernet Controller Datasheet Table 3.4 Config Data Byte 1 Register (CFG1) Format BITS 7 DESCRIPTION Self or Bus Power (SELF_BUS_PWR) Selects between Self or Bus-Powered operation. 0 = Bus-Powered 1 = Self-Powered The Hub is either Self-Powered (draws less than 2mA of upstream bus power) or Bus-Powered (limited to a 100mA maximum of upstream power prior to being configured by the host controller). When configured as a Bus-Powered device, the SMSC Hub consumes less than 100mA of current prior to being configured. After configuration, the BusPowered SMSC Hub (along with all associated hub circuitry, any embedded devices if part of a compound device, and 100mA per externally available downstream port) must consume no more than 500mA of upstream VBUS current. The current consumption is system dependent, and the OEM must ensure that the USB2.0 specifications are not violated. When configured as a Self-Powered device,