LPC47M102S-MS

LPC47M10x 100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications FEATURES • • • • • • • • • • • • • 3.3 Volt Operation (5 Volt Tolerant) LPC Interface ACPI 1.0 Compliant Fan Control Fan Speed Control Outputs Fan Tachometer Inputs Programmable Wake-up Event Interface PC98, PC99 Compliant Dual Game Port Interface MPU-401 MIDI Support General Purpose Input/Output Pins ISA Plug-and-Play Compatible Register Set Intelligent Auto Power Management System Management Interrupt 2.88MB Super I/O Floppy Disk Controller Licensed CMOS 765B Floppy Disk Controller Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core Supports Two Floppy Drives Directly Configurable Open Drain/Push-Pull Output Drivers Supports Vertical Recording Format 16-Byte Data FIFO 100% IBM Compatibility Detects All Overrun and Underrun Conditions Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption DMA Enable Logic Data Rate and Drive Control Registers 480 Address, Up to Eight IRQ and Three DMA Options Enhanced Digital Data Separator 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates Programmable Precompensation Modes Keyboard Controller 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 256 Bytes of Data RAM Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface Asynchronous Access to Two Data Registers and One Status Register Supports Interrupt and Polling Access 8 Bit Counter Timer Port 92 Support Fast Gate A20 and KRESET Outputs Serial Ports Two Full Function Serial Ports High Speed NS16C550 Compatible UARTs with Send/Receive 16-Byte FIFOs Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control Circuitry 480 Address and 15 IRQ Options Infrared Port Multiprotocol Infrared Interface IrDA 1.0 Compliant SHARP ASK IR 480 Addresses, Up to 15 IRQ Multi-Mode Parallel Port with ChiProtect Standard Mode IBM PC/XT®, PC/AT, and PS/2 Compatible Bidirectional Parallel Port Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) IEEE 1284 Compliant Enhanced Capabilities Port (ECP) ChiProtect Circuitry for Protection 480 Address, Up to 15 IRQ and Three DMA Options LPC Interface Multiplexed Command, Address and Data Bus Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems PME Interface 100 Pin QFP package, lead-free RoHS compliant packages also available - • • • • • • • Page 1 ORDERING INFORMATION LPC47M102S-MC for AMI BIOS in 100 pin QFP package (leaded) LPC47M102S-MS for AMI BIOS in 100 pin QFP lead-free RoHS compliant package LPC47M107S-MC for Phoenix BIOS in 100 pin QFP package (leaded) LPC47M107S-MS for Phoenix BIOS in 100 pin QFP lead-free RoHS compliant package GENERAL DESCRIPTION The LPC47M10x* is a 3.3V (5V tolerant) PC98/PC99 compliant Super I/O controller. The LPC47M10x implements the LPC interface, a pin reduced ISA bus interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. The LPC47M10x provides fan control through two fan speed control output pins and two fan tachometer input pins. It also provides 37 general purpose input/output (GPIO) pins, a dual game port interface and MPU-401 MIDI support. The LPC47M10x incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, two 16C550A compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP, on-chip 12 mA AT bus drivers, one floppy direct drive support, and Intelligent Power Management including PME support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both onchip UARTs are compatible with the NS16C550A. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The LPC47M10x incorporates sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake-up events. The PCC supports multiple low power-down modes. The LPC47M10x supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the recommended functionality to support Windows '95. The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47M10x may be reprogrammed through the internal configuration registers. There are 480 I/O address location options, a Serialized IRQ interface, and three DMA channels. The LPC47M10x does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The LPC47M10x is software and register compatible with SMSC's proprietary 82077AA core. *The “x” in the part number is a designator that changes depending upon the particular BIOS used inside the specific chip. “2” denotes AMI Keyboard BIOS and “7” denotes Phoenix 42i Keyboard BIOS. Page 2 TABLE OF CONTENTS FEATURES..................................................................................................................................................................1 ORDERING INFORMATION ....................................................................................................................................2 GENERAL DESCRIPTION .......................................................................................................................................2 PIN CONFIGURATION.............................................................................................................................................5 DESCRIPTION OF PIN FUNCTIONS.....................................................................................................................6 BUFFER TYPE DESCRIPTIONS .................................................................................................................................10 PINS THAT REQUIRE EXTERNAL PULLUP RESISTORS ............................................................................................11 BLOCK DIAGRAM ...................................................................................................................................................12 REFERENCE DOCUMENTS..................................................................................................................................12 3 VOLT OPERATION / 5 VOLT TOLERANCE ..................................................................................................13 POWER FUNCTIONALITY ...................................................................................................................................13 VCC POWER............................................................................................................................................................13 VTR SUPPORT .........................................................................................................................................................13 INTERNAL PWRGOOD ...........................................................................................................................................13 32.768 KHZ TRICKLE CLOCK INPUT ........................................................................................................................13 INDICATION OF 32KHZ CLOCK .................................................................................................................................14 TRICKLE POWER FUNCTIONALITY ...........................................................................................................................14 VREF PIN ................................................................................................................................................................15 MAXIMUM CURRENT VALUES ..................................................................................................................................15 POWER MANAGEMENT EVENTS (PME/SCI)...........................................................................................................16 FUNCTIONAL DESCRIPTION ...............................................................................................................................16 SUPER I/O REGISTERS ......................................................................................................................................16 HOST PROCESSOR INTERFACE (LPC) .........................................................................................................16 LPC INTERFACE ..................................................................................................................................................17 FLOPPY DISK CONTROLLER .............................................................................................................................21 FDC INTERNAL REGISTERS .............................................................................................................................21 COMMAND SET/DESCRIPTIONS........................................................................................................................36 INSTRUCTION SET .................................................................................................................................................38 SERIAL PORT (UART) ...........................................................................................................................................55 INFRARED INTERFACE........................................................................................................................................66 MPU-401 MIDI UART..............................................................................................................................................67 OVERVIEW ................................................................................................................................................................67 HOST INTERFACE ......................................................................................................................................................68 MPU-401 COMMAND CONTROLLER .........................................................................................................................70 MIDI UART.............................................................................................................................................................71 MPU-401 CONFIGURATION REGISTERS ....................................................................................................................71 Page 3 PARALLEL PORT....................................................................................................................................................72 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES ..................................................................73 EXTENDED CAPABILITIES PARALLEL PORT .................................................................................................78 POWER MANAGEMENT........................................................................................................................................88 SERIAL IRQ..............................................................................................................................................................91 TIMING DIAGRAMS FOR SER_IRQ CYCLE ....................................................................................................91 8042 KEYBOARD CONTROLLER DESCRIPTION ...........................................................................................94 LATCHES ON KEYBOARD AND MOUSE IRQS ..........................................................................................................100 KEYBOARD AND MOUSE PME GENERATION ..........................................................................................................101 GENERAL PURPOSE I/O .....................................................................................................................................102 GPIO PINS .............................................................................................................................................................102 EITHER EDGE TRIGGERED INTERRUPTS ..................................................................................................107 LED FUNCTIONALITY .......................................................................................................................................107 SYSTEM MANAGEMENT INTERRUPT (SMI) ................................................................................................108 PME SUPPORT.......................................................................................................................................................109 ‘WAKE ON SPECIFIC KEY’ OPTION ...............................................................................................................110 FAN SPEED CONTROL AND MONITORING ..................................................................................................111 FAN SPEED CONTROL ...........................................................................................................................................111 FAN TACHOMETER INPUTS ....................................................................................................................................112 SECURITY FEATURE ..........................................................................................................................................115 GPIO DEVICE DISABLE REGISTER CONTROL .......................................................................................................115 DEVICE DISABLE REGISTER ..................................................................................................................................115 GAME PORT LOGIC ............................................................................................................................................115 POWER CONTROL REGISTER ................................................................................................................................117 VREF PIN ..............................................................................................................................................................117 RUNTIME REGISTERS ........................................................................................................................................117 CONFIGURATION ................................................................................................................................................142 OPERATIONAL DESCRIPTION.........................................................................................................................159 MAXIMUM GUARANTEED RATINGS* ............................................................................................................159 DC ELECTRICAL CHARACTERISTICS ..........................................................................................................159 TIMING DIAGRAMS ..............................................................................................................................................162 PACKAGE OUTLINE............................................................................................................................................184 APPENDIX - TEST MODE....................................................................................................................................185 BOARD TEST MODE ...............................................................................................................................................185 Page 4 PIN CONFIGURATION GP57/nDTR2 GP56/nCTS2 GP55/nRTS2 GP54/nDSR2 GP53/TXD2(IRTX) GP52/RXD2(IRRX) GP51/nDCD2 VCC GP50/nRI2 nDCD1 nRI1 nDTR1 nCTS1 nRTS1 nDSR1 TXD1 RXD1 nSTROBE nALF nERROR 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 GP40/DRVDEN0 GP41/DRVDEN1 nMTR0 nDSKCHG nDS0 CLKI32 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA GP42/nIO_PME VTR CLOCKI LAD0 LAD1 LAD2 LAD3 nLFRAME nLDRQ nPCI_RESET nLPCPD GP43/DDRC PCI_CLK SER_IRQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LPC47M10x 100 PIN QFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nACK BUSY PE SLCT VSS PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 nSLCTIN nINIT VCC GP37/A20M GP36/nKBDRST IRTX2/GP35 IRRX2/GP34 VSS MCLK MDAT KCLK KDAT GP33/FAN1 GP32/FAN2 VCC GP31/FAN_TACH1 GP30/FAN_TACH2 VSS GP10/J1B1 GP11/J1B2 GP12/J2B1 GP13/J2B2 GP14/J1X GP15/J1Y GP16/J2X GP17/J2Y AVSS GP20/P17 GP21/P16/nDS1 GP22/P12/nMTR1 VREF GP24/SYSOPT GP25/MIDI_IN GP26/MIDI_OUT GP60/LED1 GP61/LED2 GP27/nIO_SMI Page 5 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DESCRIPTION OF PIN FUNCTIONS PIN No./ QFP BUFFER TYPE BUFFER TYPE PER FUNCTION (NOTE 1) PCI_IO PCI_I PCI_O PCI_I PCI_I PCI_ICLK PCI_IO IS IS (I/O8/OD8)/I (I/O8/OD8)/I (I/O12/OD12)/ (O12/OD12) (I/O12/OD12)/ (O12/OD12) IS/(IS/O8/OD8) O12/(I/O12/ OD12) 5,6 4 4 3 2 NAME TOTAL SYMBOL NOTES 23:20 24 25 26 27 29 30 6 19 51 52 54 55 61 62 53, 65,93 7, 31, 60,76 40 44 18 16 11 10 12 8 9 4 5 PROCESSOR/HOST LPC INTERFACE (10) Multiplexed Command, 4 LAD[3:0] PCI_IO Address, Data [3:0] Frame 1 nLFRAME PCI_I Encoded DMA Request 1 nLDRQ PCI_O PCI Reset 1 nPCI_RESE PCI_I T Power Down 1 nLPCPD PCI_I PCI Clock 1 PCI_CLK PCI_ICL K Serial IRQ 1 SER_IRQ PCI_IO CLOCKS (2) 32.768 Trickle Clock 1 CLOCKI32 IS Input 14.318MHz Clock Input 1 CLOCKI IS FAN CONTROL (4) General Purpose I/O 1 GP30/ IO8 FAN_TACH2 /Fan Tachometer 2 General Purpose I/O 1 GP31/ IO8 FAN_TACH1 /Fan Tachometer 1 General Purpose I/O 1 GP32/FAN2 IO12 /Fan Speed Control 2 General Purpose I/O 1 GP33/FAN1 IO12 /Fan Speed Control 1 INFRARED INTERFACE (2) Infrared Rx 1 IRRX2/GP34 IS/O8 /General Purpose I/O Infrared Tx 1 IRTX2/GP35 IO12 /General Purpose I/O POWER PINS (10) Power 3 VCC Ground Analog Ground Reference Voltage Trickle Voltage Read Disk Data Write Gate Write Disk Data Head Select Step Direction Step Pulse Disk Change Drive Select 0 4 VSS 1 AVSS 1 VREF 1 VTR FDD INTERFACE (14) 1 nRDATA IS 1 nWGATE O12 1 nWDATA O12 1 nHDSEL O12 1 nDIR O12 1 nSTEP O12 1 nDSKCHG IS 1 nDS0 O12 7 IS (O12/OD12) (O12/OD12) (O12/OD12) (O12/OD12) (O12/OD12) IS (O12/OD12) Page 6 DESCRIPTION OF PIN FUNCTIONS PIN No./ QFP BUFFER TYPE BUFFER TYPE PER FUNCTION (NOTE 1) (O12/OD12) IS IS IS (I/O12/OD12)/ (O12/OD12) (I/O12/OD12)/ (O12/OD12) NAME TOTAL SYMBOL NOTES 3 15 14 13 1 2 Motor On 0 Write Protected Track 0 Index Pulse Input General Purpose I/O/Drive Density Select 0 General Purpose I/O/Drive Density Select 1 Receive Serial Data 1 Transmit Serial Data 1 Request to Send 1 1 1 1 1 1 nMTR0 nWRTPRT nTRKO nINDEX GP40/ DRVDEN0 GP41/ DRVDEN1 O12 IS IS IS IO12 1 IO12 84 85 87 88 89 86 91 90 95 96 98 99 100 97 94 92 66 67 68 69 70 71 72 SERIAL PORT 1 INTERFACE (8) 1 RXD1 IS 1 TXD1 O12 1 nRTS1/ O8 SYSOP Clear to Send 1 1 nCTS1 I Data Terminal Ready 1 1 nDTR1 O6 Data Set Ready 1 1 nDSR1 I Data Carrier Detect 1 1 nDCD1 I Ring Indicator 1 1 nRI1 I SERIAL PORT 2 INTERFACE (8) General Purpose I/O 1 GP52/RXD2( IS/O8 IRRX) /Receive Serial Data 2 (Infrared Rx) General Purpose I/O 1 GP53/TXD2( IO12 IRTX) /Transmit Serial Data 2 (Infrared Tx) General Purpose I/O 1 GP55/ IO8 nRTS2 /Request to Send 2 General Purpose I/O 1 GP56/ IO8 /Clear to Send 2 nCTS2 General Purpose I/O 1 GP57/ IO8 /Data Terminal Ready nDTR2 General Purpose I/O 1 GP54/ IO8 /Data Set Ready 2 nDSR2 General Purpose 1 GP51/ IO8 I/O/Data Carrier Detect nDCD2 2 General Purpose 1 GP50/nRI2 IO8 I/O/Ring Indicator 2 PARALLEL PORT INTERFACE (17) Initiate Output 1 nINIT OP14 Printer Select Input 1 nSLCTIN OP14 Port Data 0 1 PD0 IOP14 Port Data 1 1 PD1 IOP14 Port Data 2 1 PD2 IOP14 Port Data 3 1 PD3 IOP14 Port Data 4 1 PD4 IOP14 IS O12 O8 I O6 I I I (IS/O8/OD8) /IS (I/O12/ OD12)/O12 (I/O8/OD8)/ O8 (I/O8/OD8)/I (I/O8/OD8)/ O8 (I/O8/OD8)/I (I/O8/OD8)/I 5 (I/O8/OD8)/I (OD14/OP14) (OD14/OP14) IOP14 IOP14 IOP14 IOP14 IOP14 Page 7 DESCRIPTION OF PIN FUNCTIONS PIN No./ QFP BUFFER TYPE BUFFER TYPE PER FUNCTION (NOTE 1) IOP14 IOP14 IOP14 I/OD12 I I I I (OD14/OP14) (OD14/OP14) IOD16 IOD16 IOD16 IOD16 (I/O8/OD8)/ O8 (I/O8/OD8)/ O8 (IS/O8/OD8)/ IS (IS/O8/OD8)/ IS (IS/O8/OD8)/ IS (IS/O8/OD8)/ IS (I/O12/ OD12)/ IO12 (I/O12/ OD12)/ IO12 (I/O12/ OD12)/IO12 (I/O12/ OD12)/IO12 (I/O8/OD8)/ IO8 (I/O12/OD12)/ IO12/(O12/ OD12) NAME TOTAL SYMBOL NOTES 73 74 75 77 78 79 80 81 82 83 56 57 58 59 63 64 32 33 34 35 36 37 38 39 41 42 43 Port Data 5 1 PD5 IOP14 Port Data 6 1 PD6 IOP14 Port Data 7 1 PD7 IOP14 Printer Selected Status 1 SLCT IO12 Paper End 1 PE I Busy 1 BUSY I Acknowledge 1 nACK I Error 1 nERROR I Autofeed Output 1 nALF OP14 Strobe Output 1 nSTROBE OP14 KEYBOARD/MOUSE INTERFACE (6) Keyboard Data 1 KDAT IOD16 Keyboard Clock 1 KCLK IOD16 Mouse Data 1 MDAT IOD16 Mouse Clock 1 MCLK IOD16 General Purpose I/O 1 GP36/ IO8 nKBDRST /Keyboard Reset General Purpose I/O 1 GP37/A20M IO8 /Gate A20 GENERAL PURPOSE I/O (19) General Purpose I/O 1 GP10/J1B1 IS/O8 /Joystick 1 Button 1 General Purpose I/O 1 GP11/J1B2 IS/O8 /Joystick 1 Button 2 General Purpose I/O 1 GP12/J2B1 IS/O8 /Joystick 2 Button 1 General Purpose I/O 1 GP13/J2B2 IS/O8 /Joystick 2 Button 2 General Purpose I/O 1 GP14/J1X IO12 /Joystick 1 X-Axis General Purpose I/O 1 GP15/J1Y IO12 /Joystick 1 Y-Axis General Purpose I/O 1 GP16/J2X IO12 /Joystick 2 X-Axis General Purpose I/O 1 GP17/J2Y IO12 /Joystick 2 Y-Axis General Purpose I/O / 1 GP20/P17 IO8 P17 General Purpose I/O / 1 GP21 /P16/ IO12 P16 /nDS1 nDS1 General Purpose I/O / P12/nMTR1 General Purpose I/O / System Option General Purpose I/O /MIDI_IN 1 GP22 /P12/ nMTR1 GP24 /SYSOPT GP25 /MIDI_IN IO12 9 9 45 46 1 1 IO8 IO8 (I/O12/ OD12)/IO12/ (O12/OD12) (I/O8/OD8) (I/O8/OD8)/I 8 Page 8 DESCRIPTION OF PIN FUNCTIONS PIN No./ QFP BUFFER TYPE BUFFER TYPE PER FUNCTION (NOTE 1) (I/O12/OD12)/ O12 (I/O12/OD12)/ OD12 (I/O12/OD12)/ O12 (I/O12/OD12)/ O12 (I/O12/OD12)/ OD12 (I/O8/OD8)/I NAME TOTAL SYMBOL NOTES 47 50 48 49 17 28 General Purpose I/O /MIDI_OUT General Purpose I/O /SMI Output General Purpose I/O / LED General Purpose I/O / LED General Purpose I/O / Power Management Event General Purpose I/O /Device Disable Reg. Control 1 1 1 1 1 GP26 /MIDI_OUT GP27 /nIO_SMI GP60 /LED1 GP61 /LED2 GP42 /nIO_PME GP43/DDRC IO12 IO12 IO12 IO12 IO12 10 10 1 IO8 Note: The "n" as the first letter of a signal name indicates an "Active Low" signal. Note 1: Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis represent multiple buffer types for a single pin function. Note 2: The nLPCPD pin may be tied high. The LPC interface will function properly if the nPCI_RESET signal follows the protocol defined for the nLRESET signal in the “Low Pin Count Interface Specification”. Note 3: If the 32kHz input clock is not used the CLKI32 pin must be grounded. There is a bit in the configuration register at 0xF0 in Logical Device A that indicates whether or not the 32kHz clock is connected. This bit determines the clock source for the fan tachometer, LED and “wake on specific key” logic. Set this bit to ‘1’ if the clock is not connected. Note 4. The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and Hard Reset. These pins revert to their non-inverting GPIO output function when VCC is removed from the part. Note 5: The IRTX pins (IRTX2/GP35 and GP53/TXD2 (IRTX)) are driven low when the part is powered by VTR (VCC=0V with VTR=3.3V). These pins will remain low following a power-up (VCC POR) until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block. Note 6: The VCC power-up default for this pin is Logic “0” if the IRTX function is programmed on the GPIO. Note 7: VTR can be connected to VCC if no wakeup functionality is required. Note 8: The GP24 /SYSOPT pin requires an external pulldown resistor to put the base IO address for configuration at 0x02E. An external pullup resistor is required to move the base IO address for configuration to 0x04E. Note 9: External pullups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are inputs after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used, the system must ensure that these pins are high. See Section “Pins That Require External Pullup Resistor”. Note 10: The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR power Page 9 Buffer Type Descriptions Note: The buffer type values are specified at VCC=3.3V IO12 Input/Output, 12mA sink, 6mA source. IS/O12 Input with Schmitt Trigger/Output, 12mA sink, 6mA source. O12 Output, 12mA sink, 6mA source. OD12 Open Drain Output, 12mA sink. O6 Output, 6mA sink, 3mA source. O8 Output, 8mA sink, 4mA source. OD14 Open Drain Output, 14mA sink. OP14 Output, 14mA sink, 14mA source. IOP14 Input/Output, 14mA sink, 14mA source. Backdrive protected. IS/OP14 Input with Schmitt Trigger/Output, 14mA sink, 14mA source, Backdrive Protected. IOD16 Input/Output (Open Drain), 16mA sink. O4 Output, 4mA sink, 2mA source. IO8 Input/Output, 8mA sink, 4mA source. I Input TTL Compatible. IS Input with Schmitt Trigger. PCI_IO Input/Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_O Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_OD Open Drain Output. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_I Input. These pins must meet the PCI 3.3V AC and DC Characteristics. (Note 1) PCI_ICLK Clock Input. These pins must meet the PCI 3.3V AC and DC Characteristics and timing. (Note 2) Note 1. See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. Note 2. See the PCI Local Bus Specification, Revision 2.1, Section 4.2.2. and 4.2.3. Page 10 Pins That Require External Pullup Resistors The following pins require external pullup resistors: • KDAT • KCLK • MDAT • MCLK • GP36/KBDRST if KBDRST function is used • GP37/A20M if A20M function is used • GP20/P17 If P17 function is used • GP21/P16 if P16 function is used • GP22/P12 if P12 function is used • GP27/nIO_SMI if nIO_SMI function is used as Open Collector Output • GP42/nIO_PME if nIO_PME function is used as Open Collector Output • SER_IRQ • GP40/DRVDEN0 if DRVDEN0 function is used as Open Collector • GP41/DRVDEN1 if DRVDEN1 function is used as Open Collector • nMTR0 if used as Open Collector Output • nDS0 if used as Open Collector Output • nDIR if used as Open Collector Output • nSTEP if used as Open Collector Output • nWDATA if used as Open Collector Output • nWGATE if used as Open Collector Output • nHDSEL if used as Open Collector Output • nINDEX • nTRK0 • nWRTPRT • nRDATA • nDSKCHG Page 11 BLOCK DIAGRAM Game Port Signals* (1-Dual) FAN_TACH1* FAN1* FAN2* FAN_TACH2* nIO_SMI nIO_PME SMI PME ... Game Port Fan Control MULTI-MODE PARALLEL PORT MUX PD0-7 BUSY, SLCT, PE, nERROR, nACK nSTB, nSLCTIN, nINIT, nALF GP1[0:7]* GP2[0:2,4:7]* GP3[0:7]*, GP4[0:3]* GP5[0:7]*, GP6[0:1]* TXD1, nCTS1, nRTS1 RXD1 nDSR1, nDCD1, nRI1, nDTR1 DATA BUS SER_IRQ PCI_CLK SERIAL IRQ ADDRESS BUS GENERAL PURPOSE I/O ACPI BLOCK CONFIGURATION REGISTERS LPC Bus Signals 16C550 COMPATIBLE SERIAL PORT 1 LPC BUS INTERFACE CONTROL BUS 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED IRRX2, IRTX2 TXD2(IRTX), nCTS2, nRTS2* RXD2(IRRX) * nDSR2, nDCD2, nRI2, nDTR2* WDATA WCLOCK SMSC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE DIGITAL DATA SEPARATOR WITH WRITE PRECOMPENSATION RCLOCK RDATA CLOCK GEN nINDEX DENSEL nDS0 nTRK0 nDIR nMTR0 nDSKCHG nSTEP DRVDEN0 nWDATA nRDATA nWRPRT * nHDSELDRVDEN1 CLK32 CLOCKI 32KHz 14MHz nWGATE MPU-401 SERIAL PORT MIDI_IN MIDI_OUT 8042 KCLK KDATA MCLK MDATA GATEA20, KRESET VTR Vcc Vss * Denotes Multifunction Pins FIGURE 1 – LPC47M10x BLOCK DIAGRAM REFERENCE DOCUMENTS 1. SMSC Consumer Infrared Communications Controller (CIrCC) V1.X 2. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. 3. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook. 4. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997. 5. Low Pin Count (LPC) Interface Specification, Revision 1.0, September 29, 1997, Intel Document. Page 12 3 VOLT OPERATION / 5 VOLT TOLERANCE The LPC47M10x is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected. The LPC interface pins are 3.3 Volt only. These signals meet PCI DC specifications for 3.3V signaling. These pins are: • LAD[3:0] • nLFRAME • nLDRQ • nLPCPD The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins: • nPCI_RESET • PCI_CLK • SER_IRQ • nIO_PME POWER FUNCTIONALITY The LPC47M10x has three power planes: VCC, VTR and VREF. VCC Power The LPC47M10x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). See the Operational Description Section and the Maximum Current Values sub-section. VTR Support The LPC47M10x requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle Power Functionality and Maximum Current Values sub-sections. If the LPC47M10x is not intended to provide wakeup capabilities on standby current, VTR can be connected to VCC. VTR powers the IR interface, the PME configuration registers and the PME interface. The VTR pin generates a VTR Power-on-Reset signal to initialize these components. Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum potential at least 10 μs before Vcc begins a power-on cycle. When VTR and Vcc are fully powered, the potential difference between the two supplies must not exceed 500mV. Internal PWRGOOD An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as Vcc cycles on and off. When the internal PWRGOOD signal is “1” (active), Vcc > 2.3V (nominal), and the LPC47M10x host interface is active. When the internal PWRGOOD signal is “0” (inactive), Vcc ≤ 2.3V (nominal), and the LPC47M10x host interface is inactive; that is, LPC bus reads and writes will not be decoded. The LPC47M10x device pins nIO_PME, CLOCKI32, KDAT, MDAT, IRRX, nRI1, nRI2, RXD2 and most GPIOs (as input) are part of the PME interface and remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. The IRTX2/GP35, GP53/TXD2(IRTX), GP60/LED1 and GP61/LED2 pins also remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. See Trickle Power Functionality section. The internal PWRGOOD signal is also used to disable the IR Half Duplex Timeout. 32.768 kHz Trickle Clock Input The LPC47M10x utilizes a 32.768 kHz trickle input to supply a clock signal for the fan tachometer logic, LED blink and wake on specific key function. See the following section for more information. Page 13 Indication of 32kHz Clock There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M10x. This bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR POR. Bit[0] (CLK32_PRSN) is defined as follows: 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded). Bit 0 controls the source of the 32kHz (nominal) clock for the fan tachometer logic, the LED blink logic and the “wake on specific key” logic. When the external 32kHz clock is connected, that will be the source for the fan tachometer, LED and “wake on specific key” logic. When the external 32kHz clock is not connected, an internal 32kHz clock source will be derived from the 14MHz clock for the fan tachometer, LED and “wake on specific key” logic. The following functions will not work under VTR power (VCC removed) if the external 32kHz clock is not connected. These functions will work under VCC power even if the external 32kHz clock is not connected. • Wake on specific key • LED blink • Fan Tachometer Trickle Power Functionality When the LPC47M10x is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The following lists the wakeup events: • UART 1 Ring Indicator • UART 2 Ring Indicator • Keyboard data • Mouse data • Wake on Specific Key Logic • Fan Tachometers (Note) • GPIOs for wakeup. See below. Note. The Fan Tachometers can generate a PME when VCC=0. Clear the enable bits for the fan tachometers before removing fan power. The following requirements apply to all I/O pins that are specified to be 5 volt tolerant. I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR. I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present. The GPIOs that are used for PME wakeup as input are GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, GP61. These GPIOs function as follows (with the exception of GP53, GP60 and GP61 see below): • Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins have input buffers into the wakeup logic that are powered by VTR. Page 14 All GPIOs listed above are for PME wakeup as a GPIO (or alternate function). Note that GP32 and GP33 cannot be used for wakeup under VTR power (VCC=0) since these are the fan control pins which come up as outputs and low following a VCC POR and Hard Reset. GP53 cannot be used for wakeup under VTR power since this is the IRTX pin which comes up as output and low following a VTR POR, a VCC POR and Hard Reset. Also, GP32 and GP33 revert to their non-inverting GPIO output function when VCC is removed from the part. GP43 reverts to the basic GPIO function when VCC is removed from the part, but its programmed input/output, invert/non-invert and output buffer type is retained. The other GPIOs function as follows: GP36, GP37 and GP40: Buffers are powered by VCC, but in the absence of VCC they are backdrive protected. These pins do not have input buffers into the wakeup logic that are powered by VTR. These pins are not used for wakeup. GP35, GP42, GP53, GP60 and GP61: • Buffers powered by VTR. GP35 and GP53 have IRTX as the alternate function and their output buffers are powered by VTR so that the pins are always forced low when not used. GP42 is the nIO_PME pin which is active under VTR. GP60 and GP61 have LED as the alternate function and the logic is able to control the pin under VTR. The IRTX pins (IRTX2/GP35 and GP53/TXD2 (IRTX)) are powered by VTR so that they are driven low when VCC = 0V with VTR = 3.3V. These pins will remain low following a VCC POR until serial port 2 is enabled by setting the activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block. The following list summarizes the blocks, registers and pins that are powered by VTR. • PME interface block • PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers) • “Wake on Specific Key” logic • LED control logic • Fan Tachometers • Pins for PME Wakeup: GP42/nIO_PME (output, buffer powered by VTR) nRI1 (input) GP50/nRI2 (input) GP52/RXD2 (input) KDAT (input) MDAT GPIOs (GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, GP61) – all input-only except GP53, GP60, GP61. See below. • Other Pins IRTX2/GP35 (output, buffer powered by VTR) GP53/TXD2(IRTX) (output, buffer powered by VTR) GP60/LED1 (output, buffer powered by VTR) GP61/LED2 (output, buffer powered by VTR) VREF Pin The LPC47M10x has a reference voltage pin input on pin 44 of the part. This reference voltage can be connected to either a 5V supply or a 3.3V supply. It is used for the game port. See the “GAME PORT LOGIC” section. Maximum Current Values See the “Operational Description” section for the maximum current values. The maximum VTR current, ITR, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or 3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by all pins that are driven by VTR. The pins that are powered by VTR are as follows: GP42 / nIO_PME, IRTX2 / GP35, GP53/TXD2(IRTX) GP60 / LED1, GP61 / LED2. These pins, if configured as push-pull outputs, will source a minimum of 6mA at 2.4V when driving. Page 15 The maximum VCC current, ICC, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or 3.3V). The maximum VREF current, IREF, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or 3.3V). Power Management Events (PME/SCI) The LPC47M10x offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nIO_PME output signal on pin 17. See the “PME Support” section. FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game port and configuration register block can be moved via the configuration registers. Some addresses are used to access more than one register. HOST PROCESSOR INTERFACE (LPC) The host processor communicates with the LPC47M10x through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide. Table 1 - Super I/O Block Addresses ADDRESS BLOCK NAME LOGICAL DEVICE Base+(0-5) and +(7) Floppy Disk 0 Base+(0-7) Serial Port Com 1 4 Base1+(0-7) Serial Port Com 2 5 Base2+(0-7) Parallel Port 3 Base+(0-3) SPP Base+(0-7) EPP Base+(0-3), +(400-402) ECP Base+(0-7), +(400-402) ECP+EPP+SPP 60, 64 KYBD 7 Base + 0 Game Port 9 Base + (0-5F) Runtime Registers A Base + (0-7) MPU-401 B Base + (0-1) Configuration Note: Refer to the configuration register descriptions for setting the base address. Page 16 LPC INTERFACE The following sub-sections specify the implementation of the LPC bus. LPC Interface Signal Definition The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal characteristics. SIGNAL NAME LAD[3:0] nLFRAME nPCI_RESET nLDRQ nIO_PME nLPCPD SER_IRQ PCI_CLK TYPE I/O Input Input Output OD Input I/O Input DESCRIPTION LPC address/data bus. Multiplexed command, address and data bus. Frame signal. Indicates start of new cycle and termination of broken cycle PCI Reset. Used as LPC Interface Reset. Same functionality as RST_DRV but active low 3.3V. Encoded DMA/Bus Master request for the LPC interface. Power Mgt Event signal. Allows the LPC47M10x to request wakeup. Powerdown Signal. Indicates that the LPC47M10x should prepare for power to be shut on the LPC interface. Serial IRQ. PCI Clock. Note: The nCLKRUN signal is not implemented in this part. LPC Cycles The following cycle types are supported by the LPC protocol. CYCLE TYPE I/O Write I/O Read DMA Write DMA Read Peripherals must ignore cycles that they do not support. TRANSFER SIZE 1 Byte 1 Byte 1 Byte 1 Byte Field Definitions The data transfers are based on specific fields that are used in various combinations, depending on the cycle type. These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the LPC bus between the host and the LPC47M10x. See the Low Pin Count (LPC) Interface Specification Reference, Section 4.2 for definition of these fields. nLFRAME Usage nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal is to be used by the LPC47M10x to know when to monitor the bus for a cycle. This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a cycle, and that the LPC47M10x monitors the bus to determine whether the cycle is intended for it. The use of nLFRAME allows the LPC47M10x to enter a lower power state internally. There is no need for the LPC47M10x to monitor the bus when it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks. When the LPC47M10x samples nLFRAME active, it immediately stops driving the LAD[3:0] signal lines on the next clock and monitor the bus for new cycle information. The nLFRAME signal functions as described in the Low Pin Count (LPC) Interface Specification, Revision 1.0. Page 17 I/O Read and Write Cycles The LPC47M10x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP cycles will depend on the speed of the external device, and may have much longer Sync times. Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it up into 8-bit transfers. See the Low Pin Count (LPC) Interface Specification Reference, Section 5.2, for the sequence of cycles for the I/O Read and Write cycles. DMA Read and Write Cycles DMA read cycles involve the transfer of data from the host (main memory) to the LPC47M10x. DMA write cycles involve the transfer of data from the LPC47M10x to the host (main memory). Data will be coming from or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47M10x are 1, 2 or 4 bytes. See the Low Pin Count (LPC) Interface Specification Reference, Section 6.4, for the field definitions and the sequence of the DMA Read and Write cycles. DMA Protocol DMA on the LPC bus is handled through the use of the nLDRQ lines from the LPC47M10x and special encodings on LAD[3:0] from the host. The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Interface Specification, Revision 1.0. Page 18 POWER MANAGEMENT CLOCKRUN Protocol The nCLKRUN pin is not implemented in the LPC47M10x. See the Low Pin Count (LPC) Interface Specification Section. LPCPD Protocol See the Low Pin Count (LPC) Interface Specification Section. SYNC Protocol See the Low Pin Count (LPC) Interface Specification Section for a table of valid SYNC values. Typical Usage The SYNC pattern is used to add wait states. For read cycles, the LPC47M10x immediately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47M10x needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The LPC47M10x will choose to assert 0101 or 0110, but not switch between the two patterns. The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The LPC47M10x uses a SYNC of 0101 for all wait states in a DMA transfer. The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47M10x uses a SYNC of 0110 for all wait states in an I/O transfer. The SYNC value is driven within 3 clocks. SYNC Timeout The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it will abort the cycle. The LPC47M10x does not assume any particular timeout. When the host is driving SYNC, it may have to insert a very large number of wait states, depending on PCI latencies and retries. SYNC Patterns and Maximum Number of SYNCS If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8. If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47M10x has protection mechanisms to complete the cycle. This is used for EPP data transfers and should utilize the same timeout protection that is in EPP. SYNC Error Indication The LPC47M10x reports errors via the LAD[3:0] = 1010 SYNC encoding. If the host was reading data from the LPC47M10x, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47M10x. If the host was writing data to the LPC47M10x, the data had already been transferred. In the case of multiple byte cycles, such as memory and DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not be transferred. Page 19 I/O and DMA START Fields I/O and DMA cycles use a START field of 0000. Reset Policy The following rules govern the reset policy: 1) When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus. 2) When nPCI_RESET goes active (low): a) the host drives the nLFRAME signal high, tristates the LAD[3:0] signals, and ignores the nLDRQ signal. b) the LPC47M10x must ignore nLFRAME, tristate the LAD[3:0] pins and drive the nLDRQ signal inactive (high). ELECTRICAL SPECIFICATIONS The LPC interface uses 3.3V signaling. No output from the LPC47M10x drives higher than 3.3V nominal. The electrical characteristics of each signal is described below. LAD[3:0] The AC and DC specifications for these signals are the same as defined for AD[31:0] in section 4.2.2 of the “PCI Local Bus Specification, Rev 2.1”. That section contains the specifications for the 3.3V signaling environment. The LAD[3:0] signals go high during the TAR phase. The last device driving the LAD[3:0] is responsible to drive the signals high during the first clock of the TAR phase. During the second clock, neither the host nor the LPC47M10x will drive LAD[3:0] (LAD[3:0] is floated). Weak pull-up resistors of 10k-100k ohms will be included on LAD[3:0] to keep the signals high. These pull-ups are external to the LPC47M10x. nLDRQ The AC and DC specifications for these signals are the same as for non-shared signals as defined in section 4.2.2 of the “PCI Local Bus Specification, Rev 2.1”. That section contains the specifications for the 3.3V signaling environment. nLDRQ is a standard output from the LPC47M10x and a standard input to the host. nLPCPD The host drives this signal as a standard 3.3V output. nLFRAME The host drives this signal as a standard 3.3V output. nPCI_RESET The host drives this signal as a standard 3.3V output. Page 20 LPC TRANSFER SEQUENCE EXAMPLES Wait State Requirements I/O Transfers The LPC47M10x inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY has been deasserted (i.e., EPP or IrCC transfers) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us). DMA Transfers The LPC47M10x inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of 0101 is used for all DMA transfers. See the example timing for the LPC cycles in the “Timing Diagrams” section. FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core. FDC INTERNAL REGISTERS The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. Table 2 - Status, Data and Control Registers (Shown with base addresses of 3F0 and 370) SECONDARY ADDRESS R/W REGISTER 370 R Status Register A (SRA) 371 R Status Register B (SRB) 372 R/W Digital Output Register (DOR) 373 R/W Tape Drive Register (TSR) 374 R Main Status Register (MSR) 374 W Data Rate Select Register (DSR) 375 R/W Data (FIFO) 376 Reserved 377 R Digital Input Register (DIR) 377 W Configuration Control Register (CCR) PRIMARY ADDRESS 3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7 STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0. PS/2 Mode Page 21 RESET COND. 7 INT PENDING 0 6 nDRV2 1 5 STEP 0 4 3 2 nTRK0 HDSEL nINDX N/A 0 N/A 1 nWP N/A 0 DIR 0 BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 This function is not supported. This bit is always read as “1”. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. PS/2 Model 30 Mode 7 INT PENDING 0 6 DRQ 0 5 STEP F/F 0 4 TRK0 N/A 3 nHDSEL 1 2 INDX N/A 1 WP N/A 0 nDIR 1 RESET COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. Page 22 BIT 6 DMA REQUEST Active high status of the DMA request pending. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt. STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1. PS/2 Mode 7 1 RESET COND. 1 6 1 1 5 4 3 2 DRIVE WDATA RDATA WGATE SEL0 TOGGLE TOGGLE 0 0 0 0 1 MOT EN1 0 0 MOT EN0 0 BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 7 RESERVED Always read as a logic "1". Page 23 PS/2 Model 30 Mode 7 nDRV2 RESET COND. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1 BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported. DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 2 1 0 DMAEN nRESE DRIVE DRIVE T SEL1 SEL0 0 0 0 0 RESET COND. BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. Page 24 BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and interrupt functions. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic "0". BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. DRIVE 0 1 DOR VALUE 1CH 2DH BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the LPC47M10x. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the LPC47M10x. TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 3 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. Table 3 - Tape Select Bits TAPE SEL1 TAPE SEL0 DRIVE (TDR.1) (TDR.0) SELECTED 0 0 None 0 1 1 1 0 2 1 1 3 Table 4 - Internal 2 Drive Decode - Normal DRIVE SELECT OUTPUTS DIGITAL OUTPUT REGISTER (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 X X X 1 0 0 1 0 X X 1 X 0 1 0 1 X 1 X X 1 0 1 1 1 X X X 1 1 1 1 0 0 0 0 X X 1 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 Page 25 Table 5 - Internal 2 Drive Decode - Drives 0 and 1 Swapped 7 6 S/W POWER RESET DOWN 0 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PREDRATE DRATE COMP0 SEL1 SEL0 0 1 0 RESET COND. DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 X X X 1 0 0 X X 1 X 0 1 X 1 X X 1 0 1 X X X 1 1 0 0 0 0 X X Normal Floppy Mode DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 nDS0 0 1 1 0 1 1 1 1 1 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are ‘0’. REG 3F3 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 tape sel1 DB0 tape sel0 Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 REG 3F3 Reserved Reserved DB5 DB4 Drive Type ID DB3 DB2 Floppy Boot Drive DB1 tape sel1 DB0 tape sel0 Table 6 - Drive Type ID DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID Bit 1 Bit 0 Bit 5 Bit 4 0 0 L0-CRF2 - B1 L0-CRF2 - B0 0 1 L0-CRF2 - B3 L0-CRF2 - B2 1 0 L0-CRF2 - B5 L0-CRF2 - B4 1 1 L0-CRF2 - B7 L0-CRF2 - B6 Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. Page 26 BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command. BIT 5 UNDEFINED Should be written as a logic "0". BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x1F in the runtime register block. Separator circuits will be turned off. The controller will come out of manual low power. Table 7 - Precompensation Delays PRECOMPENSATION DELAY (nsec) 0 5 TYP MAX 25 T4-5 50 50 50 25 UNITS µsec µsec µsec µsec µsec µsec Page 181 Data Idle (No Data) Start Bit t1 Idle (No Data) Stop Bit Data Data MIDI_Tx FIGURE 34 – MIDI DATA BYTE NAME DESCRIPTION t1 MIDI Data Bit Time Note: The MIDI bit clock is 31.25kHz +/- 1% MIN 31.7 TYP 32 MAX 32.3 UNITS µsec t1 FANx t2 FIGURE 35 – FAN OUTPUT TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 PWM Period (Note 1) 0.021 25.5 msec t2 PWM High Time (Note 2) 0.00033 25.1 msec Note 1: The period is 1/fout,where fout is programmed through the FANx and Fan Control registers. The tolerance on fout is +/- 2%. Note 2: When Bit 0 of the FANx registers is 0, then the duty cycle is programmed through Bits[6:1] of these registers. If Bits[6:1] = “000000” then the FANx pin is low. The duty cycle is programmable through Bits[6:1] to be between 1.56% and 98.44%. When Bit 0 is 1, the FANx pin is high. Page 182 t1 t2 FAN_TACHx t3 FIGURE 36 – FAN TACHOMETER INPUT TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 Pulse Time (1/2 Revolution Time=30/RPM) 4tTACH1 µsec t2 Pulse High Time 3tTACH1 µsec t3 Pulse Low Time tTACH µsec Note 1: tTACH is the clock used for the tachometer counter. It is 30.52 * DVSR, where the divisor (DVSR) is programmed in the Fan Control register. t1 t2 LEDx FIGURE 37 – LED OUTPUT TIMING NAME DESCRIPTION MIN TYP MAX UNITS t1 Period 1 2 sec t2 Blink ON Time 0 0.51 sec Note 1: The blink rate is programmed through Bits[1:0] in LEDx register. When Bits[1:0]=00, LED is OFF. Bits[1:0]=01 indicates LED blink at 1Hz rate with a 50% duty cycle (0.5 sec ON, 0.5 sec OFF). Bits[1:0]=10 indicates LED blink at ½ Hz rate with a 25% duty cycle (0.5 sec ON, 1.5 sec OFF). When Bits[1:0]=11, LED is ON. Page 183 PACKAGE OUTLINE D D1 E E1 e W A H 0 .1 0 -C D IM A A1 A2 D D1 E E1 H L L1 e 0 W T D (1) T E (1) T D (2) T E (2) A2 T D /T E 0 A1 MAX M IN 3 .1 5 2 .8 0 0 .4 5 0 .1 2 .8 7 2 .5 7 2 4 .1 5 2 3 .4 2 0 .1 1 9 .9 1 8 .1 5 1 7 .4 1 4 .1 1 3 .9 0 .2 0 .1 0 .9 5 0 .6 5 2 .6 1 .8 0 .6 5 B S C 0° 12° .2 .4 2 1 .8 2 2 .2 1 5 .8 1 6 .2 2 2 .2 1 2 2 .7 6 1 6 .2 7 1 6 .8 2 M IN MAX .1 1 0 .1 2 4 .0 0 4 .0 1 8 .1 0 1 .1 1 3 .9 2 1 .9 5 1 .7 8 3 .7 9 1 .6 8 5 .7 1 5 .5 4 7 .5 5 5 .0 0 4 .0 0 8 .0 2 6 .0 3 7 .0 7 1 .1 0 2 .0 2 5 6 B S C 0° 12° .0 0 8 .0 1 6 .8 5 8 .8 7 4 .6 2 2 .6 3 8 .8 7 4 .8 9 6 .6 6 2 .6 4 1 L L1 N o te s : 1 ) C o p la n a r ity is 0 .1 0 0 m m ( .0 0 4 ") m ax im u m . 2 ) T o le r a n c e o n th e p o sitio n o f th e le a d s is 0 .2 0 0 m m ( .0 0 8 ") m a xim u m . 3 ) P a ck a g e b o d y d im e n s io n s D 1 a n d E 1 d o n o t in c lu d e th e m o ld p r o tr u s io n . M a xim u m m o ld p r o tr u s io n is 0 .2 5 m m (.0 1 0 ") . 4 ) D im e n sio n s T D a n d T E a r e im p o r ta n t fo r tes tin g b y r o b o tic h a n d le r . O n ly a b o v e c o m b in a tio n s o f ( 1 ) o r ( 2 ) a r e a cc e p ta b le . 5 ) C o n tr o llin g d im e n s io n : m illim e te r. D im e n s io n s in in c h e s fo r r e fe r e n c e o n ly a n d n o t n e c es s a rily a c c u r a te . FIGURE 38 - 100 PIN QFP and 100 PIN QFP (LEAD-FREE) PACKAGE OUTLINE Page 184 APPENDIX - TEST MODE Board Test Mode Board test mode can be entered as follows: On the rising (deasserting) edge of nPCI_RESET, drive nLFRAME low and drive LAD[0] low. Exit board test mode as follows: On the rising (deasserting) edge of nPCI_RESET, drive either nLFRAME or LAD[0] high. See the “XNOR-Chain Test Mode” section below for a description of this board test mode. XNOR-CHAIN TEST MODE XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard during assembly and test operations. See Figure 39 below. The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is activated, the LPC47M10x pin functions are disconnected from the device pins, which all become input pins except for one output pin at the end of XNOR-Chain. The tests that are performed when the XNOR-Chain test structure is activated require the board-level test hardware to control the device pins and observe the results at the XNOR-Chain output pin. The XNOR-Chain output pin is pin 52, GP31/FAN_TACH1. The nPCI_RESET pin and the power and ground pins are not included in the XNOR-Chain. See the following subsections for more details. I/O#1 I/O#2 I/O#3 I/O#n XNor Out FIGURE 39 - XNOR-CHAIN TEST STRUCTURE Page 185 Introduction The LPC47M10x provides board test capability through the XNOR chain. When the chip is in the XNOR chain test mode, setting the state of any of the input pins to the opposite of its current state will cause the output of the chain to toggle. All pins on the chip are inputs to the XNOR chain, with the exception of the following: 1. VCC (pins 53, 65 & 93), VTR (pin 18), and VREF (pin 44). 2. VSS (pins 7, 31, 60, & 76) and AVSS (pin 40). 3. FAN_TACH1 (pin 52). This is the chain output. 4. nPCI_RESET (pin 26). To put the chip in the XNOR chain test mode, tie LAD0 (pin 20) and nLFRAME (pin 24) low. Then toggle nPCI_RESET (pin 26) from a low to a high state. Once the chip is put into XNOR chain test mode, LAD0 (pin 20) and nLFRAME (pin 24) become part of the chain. To exit the XNOR chain test mode tie LAD0 (pin 20) or nLFRAME (pin 24) high. Then toggle nPCI_RESET (pin 26) from a low to a high state. A VCC POR will also cause the XNOR chain test mode to be exited. To verify the test mode has been exited, observe the output at FAN_TACH1 (pin 52). Toggling any of the input pins should not cause its state to change. Setup Warning: Ensure power supply is off during setup. 1. Connect VSS (pins 7, 31, 60, & 76) and AVSS (pin 40) to ground. 2. Connect VCC (pins 53, 65 & 93), VTR (pin 18), and VREF (pin 44) to VCC (3.3V). 3. Connect an oscilloscope or voltmeter to FAN_TACH1 (pin 52). 4. All other pins should be tied to ground. Testing 1. Turn power on. 2. With LAD0 (pin 20) and nLFRAME (pin 24) low, bring nPCI_RESET (pin 26) high. The chip is now in XNOR chain test mode. At this point, all inputs to the XNOR chain are low. The output, on FAN_TACH1 (pin 52), should also be low. Refer to INITIAL CONFIG on Truth Table 1. 3. Bring pin 100 high. The output on FAN_TACH1 (pin 52) should go high. Refer to STEP ONE on Truth Table 1. 4. In descending pin order, bring each input high. The output should switch states each time an input is toggled. Continue until all inputs are high. The output on FAN_TACH1 should now be low. Refer to END CONFIG on Truth Table 1. 5. The current state of the chip is now represented by INITIAL CONFIG in Truth Table 2. 6. Each input should now be brought low, starting at pin one and continuing in ascending order. Continue until all inputs are low. The output on FAN_TACH1 should now be low. Refer to Truth Table 2. 7. To exit test mode, tie LAD0 (pin 20) OR nLFRAME (pin 24) high, and toggle nPCI_RESET from a low to a high state. Page 186 INITIAL CONFIG STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 … STEP N END CONFIG TRUTH TABLE 1 - Toggling Inputs In Descending Order PIN PIN PIN PIN PIN PIN 100 99 98 97 96 ... PIN 1 L L L L L L L H H H H H … H H L H H H H … H H L L H H H … H H L L L H H … H H L L L L H … H H L L L L L … H H L L L L L … L H OUTPUT PIN 52 L H L H L H … H L TRUTH TABLE 2 - Toggling Inputs In Ascending Order INITIAL CONFIG STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP N END CONFIG PIN 1 H L L L L L … L L PIN 2 H H L L L L … L L PIN 3 H H H L L L … L L PIN 4 H H H H L L … L L PIN 5 H H H H H L … L L PIN ... H H H H H H … L L PIN 100 H H H H H H … H L OUTPUT PIN 52 L H L H L H … L L Page 187 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. 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IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LPC47M10x Revision 1.0 (02-16-07) Page 188