LPC47M172_07

LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic Datasheet Product Features 3.3V Operation (5V tolerant) LPC Interface − Multiplexed Command, Address and Data Bus − Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems Enhanced Digital Data Separator − 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates − Programmable Precompensation Modes Keyboard Controller − − − − − − − − − − 8042 Software Compatible 8 Bit Microcomputer 2k Bytes of Program ROM 256 Bytes of Data RAM Four Open Drain Outputs Dedicated for Keyboard/Mouse Interface Asynchronous Access to Two Data Registers and One Status Register Supports Interrupt and Polling Access 8 Bit Counter Timer Port 92 Support Fast Gate A20 and KRESET Outputs ACPI 1.0b/2.0 Compliant Programmable Wake-up Event Interface PC99a/PC2001 Compliant General Purpose Input/Output Pins (13) Fan Tachometer Inputs (2) Green and Yellow Power LEDs ISA Plug-and-Play Compatible Register Set Motherboard GLUE Logic − − − − − − − − − − − 5V Reference Generation 5V Standby Reference Generation IDE Reset/Buffered PCI Reset Outputs Power OK Signal Generation Power Sequencing Power Supply Turn On Circuitry Resume Reset Signal Generation Hard Drive Front Panel LED Voltage Translation for DDC to VGA Monitor SMBus Isolation Circuitry CNR Dynamic Down Control Serial Ports − Two Full Function Serial Ports − High Speed 16C550A Compatible UART with Send/Receive 16-Byte FIFOs − Supports 230k and 460k Baud − Programmable Baud Rate Generator − Modem Control Circuitry − 480 Address and 15 IRQ Options Infrared Port − − − − − − Multiprotocol Infrared Interface 32-Byte Data FIFO IrDA 1.0 Compliant SHARP ASK IR HP-SIR 480 Address, Up to 15 IRQ and Three DMA Options , 2.88MB Super I/O Floppy Disk Controller − Licensed CMOS 765B Floppy Disk Controller − Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core − Supports One Floppy Drive − Configurable Open Drain/Push-Pull Output Drivers − Supports Vertical Recording Format Multi-Mode Parallel Port with ChiProtect − Standard Mode IBM PC/XT PC/AT, and PS/2 Compatible Bi-directional Parallel Port − Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) − IEEE 1284 Compliant Enhanced Capabilities Port (ECP) − ChiProtect Circuitry for Protection − 960 Address, Up to 15 IRQ and Three DMA Options 16-Byte Data FIFO − 100% IBM Compatibility − Detects All Overrun and Underrun Conditions Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption − DMA Enable Logic − Data Rate and Drive Control Registers 480 Address, Up to Eight IRQ and Three DMA Options Interrupt Generating Registers − Registers Generate IRQ1 – IRQ15 on Serial IRQ Interface. XOR-Chain Board Test 128 Pin MQFP Lead-free RoHS Compliant Package, 3.2 mm Footprint SMSC LPC47M172 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet ORDERING INFORMATION Order Number: LPC47M172-NW for 128 Pin, MQFP lead-free RoHS compliant package (3.2mm footprint) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. 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SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 2 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table Of Contents Chapter 1 Chapter 2 Chapter 3 3.1 3.2 3.3 3.4 General Description.............................................................................................................. 11 Pin Layout ............................................................................................................................ 12 Description of Pin Functions ................................................................................................ 14 Buffer Name Descriptions ..........................................................................................................................22 Pins With Internal Resistors .......................................................................................................................23 Pins That Require External Resistors.........................................................................................................23 Default State of Pins...................................................................................................................................24 Chapter 4 Chapter 5 Block Diagram ...................................................................................................................... 28 Power and Clock Functionality............................................................................................. 29 5.1 3 Volt Operation / 5 Volt Tolerance ............................................................................................................29 5.2 VCC Power ................................................................................................................................................29 5.3 VTR Power.................................................................................................................................................29 5.3.1 Trickle Power Functionality .................................................................................................................30 5.4 V5P0_STBY Power ....................................................................................................................................30 5.5 32.768 kHz Trickle Clock Input...................................................................................................................30 5.5.1 Indication of 32KHZ Clock...................................................................................................................30 5.6 14.318 MHz Clock Input .............................................................................................................................31 5.7 Internal PWRGOOD ...................................................................................................................................31 5.8 Maximum Current Values...........................................................................................................................31 5.9 Power Management Events (PME/SCI) .....................................................................................................31 Chapter 6 Functional Description.......................................................................................................... 32 6.1 Super I/O Registers....................................................................................................................................32 6.2 Host Processor Interface (LPC) .................................................................................................................33 6.3 LPC Interface .............................................................................................................................................33 6.3.1 LPC Interface Signal Definition ...........................................................................................................33 6.3.2 LPC Cycles .........................................................................................................................................33 6.3.3 Field Definitions...................................................................................................................................33 6.3.4 NLFRAME Usage................................................................................................................................34 6.3.5 I/O Read and Write Cycles..................................................................................................................34 6.3.6 DMA Read and Write Cycles ..............................................................................................................34 6.3.7 DMA Protocol ......................................................................................................................................34 6.3.8 Power Management ............................................................................................................................35 6.3.9 SYNC Protocol ....................................................................................................................................35 6.3.10 I/O and DMA START Fields.............................................................................................................36 6.3.11 LPC Transfers .................................................................................................................................36 6.4 Floppy Disk Controller ................................................................................................................................37 6.4.1 FDC Configuration Registers ..............................................................................................................37 6.4.2 FDC Internal Registers........................................................................................................................37 6.4.3 Status Register A (SRA) .....................................................................................................................38 6.4.4 Status Register B (SRB) .....................................................................................................................39 6.4.5 Digital Output Register (DOR).............................................................................................................41 6.4.6 Tape Drive Register (TDR) .................................................................................................................42 6.4.7 Data Rate Select Register (DSR)........................................................................................................43 6.4.8 Main Status Register...........................................................................................................................45 6.4.9 Data Register (FIFO)...........................................................................................................................46 6.4.10 Digital Input Register (DIR)..............................................................................................................47 6.4.11 Configuration Control Register (CCR) .............................................................................................48 6.4.12 Status Register Encoding ................................................................................................................49 6.5 Modes of Operation....................................................................................................................................51 6.5.1 PC/AT Mode .......................................................................................................................................51 6.5.2 PS/2 Mode ..........................................................................................................................................51 6.5.3 Model 30 Mode ...................................................................................................................................51 6.6 DMA Transfers ...........................................................................................................................................51 6.7 Controller Phases.......................................................................................................................................52 6.7.1 Command Phase ................................................................................................................................52 6.7.2 Execution Phase .................................................................................................................................52 6.8 Data Transfer Termination .........................................................................................................................53 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 3 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.9 Result Phase..............................................................................................................................................53 6.10 Command Set/Descriptions ....................................................................................................................53 6.10.1 Instruction Set..................................................................................................................................56 6.11 Data Transfer Commands ......................................................................................................................62 6.11.1 Read Data .......................................................................................................................................62 6.12 Read Deleted Data .................................................................................................................................63 6.13 Read A Track..........................................................................................................................................64 6.14 Write Data...............................................................................................................................................65 6.15 Write Deleted Data .................................................................................................................................65 6.16 Verify ......................................................................................................................................................65 6.17 Format A Track .......................................................................................................................................66 6.18 Control Commands.................................................................................................................................68 6.18.1 Read ID ...........................................................................................................................................68 6.18.2 Recalibrate ......................................................................................................................................68 6.18.3 Seek ................................................................................................................................................68 6.19 Sense Interrupt Status ............................................................................................................................69 6.20 Sense Drive Status .................................................................................................................................70 6.21 Specify....................................................................................................................................................70 6.22 Configure ................................................................................................................................................70 6.22.1 Configure Default Values.................................................................................................................70 6.23 Version ...................................................................................................................................................71 6.24 Relative Seek .........................................................................................................................................71 6.25 Perpendicular Mode................................................................................................................................72 6.26 Lock ........................................................................................................................................................73 6.27 Enhanced DUMPREG ............................................................................................................................74 6.27.1 Compatibility ....................................................................................................................................74 6.28 Serial Port (UART)..................................................................................................................................74 6.28.1 Register Description ........................................................................................................................74 6.28.2 Receive Buffer Register (RB) ..........................................................................................................75 6.28.3 Transmit Buffer Register (TB)..........................................................................................................75 6.28.4 Interrupt Enable Register (IER) .......................................................................................................75 6.28.5 FIFO Control Register (FCR)...........................................................................................................76 6.28.6 Interrupt Identification Register (IIR)................................................................................................76 6.28.7 Line Control Register (LCR) ............................................................................................................78 6.28.8 Modem Control Register (MCR) ......................................................................................................79 6.28.9 Line Status Register (LSR) ..............................................................................................................80 6.28.10 Modem Status Register (MSR)........................................................................................................81 6.28.11 Scratchpad Register (SCR) .............................................................................................................82 6.29 Programmable Baud Rate Generator (And Divisor Latches DLH, DLL) .................................................82 6.29.1 Effect Of The Reset on Register File ...............................................................................................83 6.29.2 FIFO Interrupt Mode Operation .......................................................................................................83 6.29.3 FIFO Polled Mode Operation...........................................................................................................84 Chapter 7 Notes On Serial Port Operation ........................................................................................... 88 7.1 FIFO Mode Operation: ...............................................................................................................................88 7.1.1 General ...............................................................................................................................................88 7.1.2 TX and RX FIFO Operation.................................................................................................................88 7.2 Infrared Interface ........................................................................................................................................89 7.3 Parallel Port................................................................................................................................................89 7.4 IBM XT/AT Compatible, Bi-Directional and EPP Modes.............................................................................91 7.4.1 Data Port .............................................................................................................................................91 7.4.2 Status Port ..........................................................................................................................................91 7.4.3 Control Port .........................................................................................................................................92 7.4.4 EPP Address Port ...............................................................................................................................93 7.4.5 EPP Data Port 0..................................................................................................................................93 7.4.6 EPP Data Port 1..................................................................................................................................93 7.4.7 EPP Data Port 2..................................................................................................................................93 7.4.8 EPP Data Port 3..................................................................................................................................94 7.5 EPP 1.9 Operation .....................................................................................................................................94 7.5.1 Software Constraints...........................................................................................................................94 7.6 EPP 1.9 Write.............................................................................................................................................94 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 4 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.7 EPP 1.9 Read ............................................................................................................................................95 7.8 EPP 1.7 Operation .....................................................................................................................................95 7.8.1 Software Constraints...........................................................................................................................95 7.9 EPP 1.7 Write.............................................................................................................................................96 7.10 EPP 1.7 Read .........................................................................................................................................96 7.10.1 Extended Capabilities Parallel Port .................................................................................................97 7.10.2 Vocabulary.......................................................................................................................................97 7.11 ECP Implementation Standard ...............................................................................................................98 7.11.1 Description.......................................................................................................................................98 7.12 Register Definitions.................................................................................................................................99 7.12.1 Data and ecpAFifo Port .................................................................................................................100 7.12.2 Device Status Register (dsr)..........................................................................................................101 7.12.3 Device Control Register (dcr) ........................................................................................................101 7.12.4 CFIFO (Parallel Port Data FIFO) ...................................................................................................102 7.12.5 ECPDFIFO (ECP Data FIFO) ........................................................................................................102 7.12.6 tFifo (Test FIFO Mode) ..................................................................................................................102 7.12.7 cnfgA (Configuration Register A) ...................................................................................................103 7.12.8 cnfgB (Configuration Register B) ...................................................................................................103 7.12.9 ecr (Extended Control Register) ....................................................................................................103 7.13 Operation..............................................................................................................................................106 7.13.1 Mode Switching/Software Control..................................................................................................106 7.14 ECP Operation .....................................................................................................................................106 7.15 Termination from ECP Mode ................................................................................................................107 7.16 Command/Data.....................................................................................................................................107 7.17 Data Compression ................................................................................................................................107 7.18 Pin Definition ........................................................................................................................................107 7.19 LPC Connections..................................................................................................................................108 7.20 Interrupts ..............................................................................................................................................108 7.21 FIFO Operation.....................................................................................................................................108 7.21.1 DMA Transfers ..............................................................................................................................109 7.21.2 DMA Mode - Transfers from the FIFO to the Host.........................................................................109 7.21.3 Programmed I/O Mode or Non-DMA Mode ...................................................................................109 7.21.4 Programmed I/O - Transfers from the FIFO to the Host ................................................................109 7.21.5 Programmed I/O - Transfers from the Host to the FIFO ................................................................110 7.22 Power Management..............................................................................................................................110 7.23 Serial IRQ .............................................................................................................................................110 7.23.1 Timing Diagrams For SER_IRQ Cycle ..........................................................................................110 7.23.2 SER_IRQ Cycle Control ................................................................................................................111 7.23.3 SER_IRQ Data Frame...................................................................................................................112 7.23.4 Stop Cycle Control.........................................................................................................................112 7.23.5 Latency ..........................................................................................................................................113 7.23.6 EOI/ISR Read Latency ..................................................................................................................113 7.23.7 AC/DC Specification Issue ............................................................................................................113 7.23.8 Reset and Initialization ..................................................................................................................113 7.24 Interrupt Generating Registers .............................................................................................................113 7.25 8042 Keyboard Controller Description ..................................................................................................114 7.25.1 Keyboard Interface ........................................................................................................................114 7.25.2 Keyboard Data Write .....................................................................................................................115 7.25.3 Keyboard Data Read .....................................................................................................................115 7.25.4 Keyboard Command Write ............................................................................................................115 7.25.5 Keyboard Status Read ..................................................................................................................115 7.25.6 CPU-to-Host Communication ........................................................................................................115 7.25.7 Host-to-CPU Communication ........................................................................................................115 7.25.8 KIRQ..............................................................................................................................................115 7.25.9 MIRQ .............................................................................................................................................116 7.25.10 External Keyboard and Mouse Interface .......................................................................................116 7.25.11 Keyboard Power Management ......................................................................................................116 7.25.12 Soft Power Down Mode.................................................................................................................116 7.25.13 Hard Power Down Mode ...............................................................................................................116 7.25.14 Interrupts .......................................................................................................................................117 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 5 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.25.15 Memory Configurations .................................................................................................................117 7.25.16 Register Definitions .......................................................................................................................117 7.25.17 External Clock Signal ....................................................................................................................118 7.25.18 Default Reset Conditions ...............................................................................................................118 7.25.19 GateA20 and Keyboard Reset.......................................................................................................118 7.26 Port 92 Fast Gatea20 and Keyboard Reset..........................................................................................118 7.26.1 Port 92 Register.............................................................................................................................118 7.26.2 Keyboard and Mouse PME Generation .........................................................................................122 7.27 General Purpose I/O.............................................................................................................................123 7.27.1 GPIO Pins .....................................................................................................................................124 7.27.2 Description.....................................................................................................................................124 7.27.3 GPIO Control .................................................................................................................................125 7.27.4 GPIO Operation.............................................................................................................................126 7.27.5 GPIO PME Functionality................................................................................................................127 7.27.6 Either Edge Triggered Interrupts ...................................................................................................127 7.28 PME Support ........................................................................................................................................127 7.28.1 ‘Wake on Specific Key’ Option.......................................................................................................128 7.29 Fan Monitoring......................................................................................................................................129 7.29.1 Fan Tachometer Inputs .................................................................................................................130 7.29.2 Detection of a Stalled Fan .............................................................................................................130 7.30 Hard Drive and Power LED Logic .........................................................................................................131 7.30.1 Hard Drive Front Panel LED (Red) ................................................................................................131 7.30.2 Yellow and Green Power LED Pins ...............................................................................................132 7.31 Power Generation (5V) .........................................................................................................................133 7.31.1 Reference Pins ..............................................................................................................................133 7.31.2 5V Main Reference Generation .....................................................................................................134 7.31.3 5V Standby Reference Generation................................................................................................134 7.31.4 Reference Timings ........................................................................................................................135 7.32 IDE Reset Output Pin ...........................................................................................................................135 7.33 PCI Reset Output Pins..........................................................................................................................135 7.34 Voltage Translation Circuit....................................................................................................................136 7.35 SMBus Isolation Circuitry......................................................................................................................138 7.36 PS_ON Logic ........................................................................................................................................140 7.37 PWRGD_3V Logic ................................................................................................................................140 7.38 SCK_BJT_GATE Output ......................................................................................................................142 7.39 Backfeed Cut and Latched Backfeed Cut Circuitry ...............................................................................143 7.40 Resume Reset Logic ............................................................................................................................148 7.41 CNR Logic ............................................................................................................................................148 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Power Control Runtime Registers...................................................................................... 150 GPIO Runtime Registers.................................................................................................... 157 Runtime Register Block Runtime Registers ....................................................................... 161 Configuration ...................................................................................................................... 172 11.1 System Elements..................................................................................................................................172 11.1.1 Primary Configuration Address Decoder .......................................................................................172 11.1.2 Entering the Configuration State....................................................................................................172 11.1.3 Exiting the Configuration State ......................................................................................................172 11.1.4 Configuration Sequence ................................................................................................................173 11.1.5 Enter Configuration Mode..............................................................................................................173 11.1.6 Configuration Mode .......................................................................................................................173 11.1.7 Exit Configuration Mode ................................................................................................................173 11.1.8 Programming Example ..................................................................................................................174 11.2 Chip Level (Global) Control/Configuration Registers[0x00-0x2F] .........................................................179 11.3 Logical Device Configuration/Control Registers [0x30-0xFF] ...............................................................182 11.4 Logical Device I/O Address ..................................................................................................................186 11.5 Logical Device Configuration Registers ................................................................................................189 Chapter 12 12.1 12.2 12.3 12.4 Electrical Characteristics .................................................................................................... 195 Maximum Guaranteed Ratings .............................................................................................................195 Operational DC Characteristics ............................................................................................................195 Standby Power Requirements ..............................................................................................................200 Capacitance Values for Pins.................................................................................................................201 Page 6 SMSC LPC47M172 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 13 Timing Diagrams ................................................................................................................202 13.1 ECP Parallel Port Timing ......................................................................................................................211 13.1.1 Parallel Port FIFO (Mode 101).......................................................................................................211 13.1.2 ECP Parallel Port Timing ...............................................................................................................211 13.1.3 Forward-Idle ..................................................................................................................................211 13.1.4 Forward Data Transfer Phase .......................................................................................................211 13.1.5 Reverse-Idle Phase .......................................................................................................................211 13.1.6 Reverse Data Transfer Phase .......................................................................................................211 13.1.7 Output Drivers ...............................................................................................................................212 Chapter 14 Chapter 15 Chapter 16 Package Outline ................................................................................................................. 223 Board Test Mode................................................................................................................224 Reference Documents........................................................................................................ 226 List Of Figures Figure 2.1 - LPC47M172 Pin Layout ............................................................................................................................12 Figure 4.1 - LPC47M172 Block Diagram......................................................................................................................28 Figure 7.1 - NKBDRST Circuit....................................................................................................................................120 Figure 7.2 - Keyboard Latch.......................................................................................................................................121 Figure 7.3 - Mouse Latch ...........................................................................................................................................121 Figure 7.4 - GPIO Function Illustration.......................................................................................................................126 Figure 7.5 - Fan Tachometer Input and Clock Source ...............................................................................................130 Figure 7.6 - NHD_LED Circuit ....................................................................................................................................132 Figure 7.7 - YLW_LED/GRN_LED Circuit ..................................................................................................................133 Figure 7.8 - REF5V Circuit .........................................................................................................................................134 Figure 7.9 - REF5V_STBY.........................................................................................................................................135 Figure 7.10 - VGA DDC Voltage Translation Circuit...................................................................................................138 Figure 7.11 - SMBUS Isolation Circuit........................................................................................................................139 Figure 7.12 - PWRGD_3V Circuit, Discrete Implementation ......................................................................................141 Figure 7.13 - PWRGD_3V Circuit in LPC47M172 ......................................................................................................141 Figure 7.14 - NFPRST Timing....................................................................................................................................142 Figure 7.15 - SCK_BJT_Gate Circuit .........................................................................................................................143 Figure 7.16 - Backfeed Cut and Latched Backfeed Cut Circuit ..................................................................................144 Figure 7.17 - Latched Backfeed Cut Power Up Sequence.........................................................................................145 Figure 7.18 - Latched Backfeed Cut Sequence 1 ......................................................................................................145 Figure 7.19 - Latched Backfeed Cut Sequence 2 ......................................................................................................146 Figure 7.20 - Latched Backfeed Cut Flowchart ..........................................................................................................147 Figure 7.21 - CNR Circuit ...........................................................................................................................................149 Figure 13.1 - Power-Up Timing ..................................................................................................................................203 Figure 13.2 - Input Clock Timing ................................................................................................................................204 Figure 13.3 - PCI Clock Timing ..................................................................................................................................204 Figure 13.4 - Reset Timing.........................................................................................................................................204 Figure 13.5 - Output Timing Measurement Conditions, LPC Signals .........................................................................205 Figure 13.6 - Input Timing Measurement Conditions, LPC Signals............................................................................205 Figure 13.7 - I/O Write................................................................................................................................................205 Figure 13.8 - I/O Read ...............................................................................................................................................206 Figure 13.9 - DMA Request Assertion through NLDRQ .............................................................................................206 Figure 13.10 - DMA Write (First Byte) ........................................................................................................................206 Figure 13.11 - DMA Read (First Byte)........................................................................................................................206 Figure 13.12 - Floppy Disk Drive Timing (At Mode Only) ...........................................................................................207 Figure 13.13 - EPP 1.9 Data or Address Write Cycle.................................................................................................208 Figure 13.14 - EPP 1.9 Data or Address Read Cycle ................................................................................................209 Figure 13.15 - EPP 1.7 Data or Address Write Cycle.................................................................................................210 Figure 13.16 - EPP 1.7 Data or Address Read Cycle ................................................................................................210 Figure 13.17 - Parallel Port FIFO Timing ...................................................................................................................212 Figure 13.18 - ECP Parallel Port Forward Timing ......................................................................................................213 Figure 13.19 - ECP Parallel Port Reverse Timing ......................................................................................................214 Figure 13.20 - Setup and Hold Time ..........................................................................................................................215 Figure 13.21 - Serial Port Data...................................................................................................................................215 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 7 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Figure 13.22 - Keyboard/Mouse Receive/Send Data Timing .....................................................................................216 Figure 13.23 - Fan Tachometer Input Timing .............................................................................................................217 Figure 13.24 - Power Led Output Timing ...................................................................................................................217 Figure 13.25 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Up Before VCC5V/ V_5P0_STBY ...............218 Figure 13.26 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Up Before VCC/VTR ...............218 Figure 13.27 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Down Before VCC5V/ V_5P0_STBY...........219 Figure 13.28 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Down Before VCC/VTR...........219 Figure 13.29 - Rise, Fall and Propagation Timings ....................................................................................................220 Figure 13.30 - Reseme Reset Sequence ...................................................................................................................222 Figure 14.1 - 128 Pin MQFP Package Outline, 14x20x2.7 Body, 3.2mm Footprint....................................................223 Figure 15.1 - Example XOR Chain Circuitry...............................................................................................................224 List Of Tables Table 3.1 - LPC47M172 Pin Description ......................................................................................................................14 Table 3.2 - Pins with Internal Resistors........................................................................................................................23 Table 3.3 - Pins that Require External Resistors..........................................................................................................23 Table 3.4 - Default State of Pins ..................................................................................................................................25 Table 6.1 - Super I/O Block Logical Device Number and Addresses ...........................................................................32 Table 6.2 - Status, Data and Control Registers............................................................................................................37 Table 6.3 - Internal 2 Drive Decode - Normal...............................................................................................................41 Table 6.4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped ...................................................................................42 Table 6.5 - Tape Select Bits .........................................................................................................................................42 Table 6.6 - Drive Type ID .............................................................................................................................................43 Table 6.7 - Precompensation Delays ...........................................................................................................................44 Table 6.8 - Data Rates .................................................................................................................................................44 Table 6.9 - DRVDEN Mapping .....................................................................................................................................45 Table 6.10 - Default Precompensation Delays .............................................................................................................45 Table 6.11 - FIFO Service Delay..................................................................................................................................46 Table 6.12 - Status Register 0 .....................................................................................................................................49 Table 6.13 - Status Register 1 .....................................................................................................................................49 Table 6.14 - Status Register 2 .....................................................................................................................................50 Table 6.15 - Status Register 3 .....................................................................................................................................50 Table 6.16 - Description of Command Symbols ...........................................................................................................54 Table 6.17 - Instruction Set ..........................................................................................................................................56 Table 6.18 - Sector Sizes .............................................................................................................................................62 Table 6.19 - Effects of MT and N Bits ..........................................................................................................................63 Table 6.20 - Skip Bit vs Read Data Command.............................................................................................................63 Table 6.21 - Skip Bit vs. Read Deleted Data Command ..............................................................................................64 Table 6.22 - Result Phase Table..................................................................................................................................64 Table 6.23 - Verify Command Result Phase Table ......................................................................................................66 Table 6.24 - Typical Values for Formatting ..................................................................................................................67 Table 6.25 - Interrupt Identification...............................................................................................................................69 Table 6.26 - Drive Control Delays (ms) ........................................................................................................................70 Table 6.27 - Effects of WGATE and GAP Bits .............................................................................................................73 Table 6.28 - Addressing the Serial Port .......................................................................................................................74 Table 6.29 - Interrupt Control Table .............................................................................................................................77 Table 6.30 - Baud Rates ..............................................................................................................................................84 Table 6.31 - Reset Function Table ...............................................................................................................................85 Table 32 - Register Summary for an Individual UART Channel ...................................................................................86 Table 7.1 - Parallel Port Connector ..............................................................................................................................91 Table 7.2 - EPP Pin Descriptions .................................................................................................................................96 Table 7.3 - ECP Pin Descriptions.................................................................................................................................99 Table 7.4 - ECP Register Definitions..........................................................................................................................100 Table 7.5 - Mode Descriptions ...................................................................................................................................100 Table 7.6 - Extended Control Register .......................................................................................................................105 Table 7.7 - Programming for Configuration Register B (Bits 5:3) ...............................................................................105 Table 7.8 - Programming for Configuration Register B (Bits 2:0) ...............................................................................105 Table 7.9 - Channel/Data Commands supported in ECP mode .................................................................................107 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 8 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 7.10 - I/O Address Map ....................................................................................................................................114 Table 7.11 - Host Interface Flags ...............................................................................................................................115 Table 7.12 - Status Register ......................................................................................................................................117 Table 7.13 - Keyboard and Mouse Pin/Register Reset Values ..................................................................................118 Table 7.14 - Keyboard Port 92 Register.....................................................................................................................119 Table 7.15 - nA20M Truth Table ................................................................................................................................120 Table 7.16 - GPIO Summary......................................................................................................................................124 Table 7.17 - General Purpose I/O Port Assignments .................................................................................................125 Table 7.18 - GPIO Configuration Summary ...............................................................................................................125 Table 7.19 - GPIO Read/Write Behavior ....................................................................................................................126 Table 7.20 - Hard Drive Front Panel Pins ..................................................................................................................131 Table 7.21 - nHD_LED Truth Table............................................................................................................................131 Table 7.22 - LED Pins ................................................................................................................................................132 Table 7.23 - LED Truth Table.....................................................................................................................................132 Table 7.24 - Reference Generation Pins....................................................................................................................133 Table 7.25 - REF5V ...................................................................................................................................................134 Table 7.26 - REF5V_STBY ........................................................................................................................................134 Table 7.27 - nIDE_RSTDRV Pin ................................................................................................................................135 Table 7.28 - nIDE_RSTDRV Truth Table ...................................................................................................................135 Table 7.29 - nPCIRST_OUT Pins ..............................................................................................................................136 Table 7.30 - nPCIRST_OUT and nPCIRST_OUT2 Truth Table ................................................................................136 Table 7.31 - Voltage Translation DDC Pins ...............................................................................................................136 Table 7.32 - VGA DDCSDA Voltage Translation Logic ..............................................................................................137 Table 7.33 - VGA DDCSCL Voltage Translation Logic ..............................................................................................137 Table 7.34 - SMBus Isolation Pins .............................................................................................................................138 Table 7.35 - SMB_CLK Isolation Logic ......................................................................................................................139 Table 7.36 - SMB_DAT Isolation Logic ......................................................................................................................139 Table 7.37 - nPS_ON, nCPU_PRESENT and nSLP_S3 Pins ...................................................................................140 Table 7.38 - nPS_ON Truth Table..............................................................................................................................140 Table 7.39 - PWRGD_3V, nFPRST and PWRGD_PS Pins .......................................................................................140 Table 7.40 - PWRGD_3V Truth Table........................................................................................................................141 Table 7.41 - SCK_BJT_GATE Pin .............................................................................................................................142 Table 7.42 - SCK_BJT_GATE Truth Table ................................................................................................................142 Table 7.43 - nBACKFEED_CUT and LATCHED_BF_CUT Pins ................................................................................143 Table 7.44 - nBACKFEED_CUT Truth Table .............................................................................................................143 Table 7.45 - LATCHED_BF_CUT Truth Table ...........................................................................................................144 Table 7.46 - Latched Backfeed Cut Power Up Sequence Timing ..............................................................................145 Table 7.47 - Latched Backfeed Cut Sequence 1 and 2 Timing ..................................................................................146 Table 7.48 - nRSMRST Pin........................................................................................................................................148 Table 7.49 - CNR Pins ...............................................................................................................................................148 Table 7.50 - CNR Logic Truth Table ..........................................................................................................................149 Table 8.1 - Power Control Runtime Registers Summary, LD_NUM Bit = 0................................................................150 Table 8.2 - Power Control Runtime Registers Description, LD_NUM Bit = 0 .............................................................151 Table 9.1 - GPIO Runtime Registers Summary, LD_NUM = 0...................................................................................157 Table 9.2 - GPIO Runtime Registers Description, LD_NUM = 0 ................................................................................158 Table 10.1 - Runtime Register Block Runtime Registers Summary ...........................................................................161 Table 10.2 - Runtime Register Block Runtime Registers Description ........................................................................162 Table 11.1 - LPC47M172 Configuration Registers Summary, LD_NUM bit = 0 .........................................................175 Table 11.2 - LPC47M172 Configuration Register Summary, LD_NUM=1..................................................................177 Table 11.3 - Chip Level Registers ..............................................................................................................................179 Table 11.4 - Logical Device Registers........................................................................................................................182 Table 11.5 - Primary Interrupt Select Configuration Register Description ..................................................................184 Table 11.6 - DMA Channel Select Configuration Register Description ......................................................................184 Table 11.7 - Logical Device I/O Address, LD_NUM Bit = 0 ........................................................................................186 Table 11.8 - Logical Device I/O Address, LD_NUM Bit = 1 .......................................................................................187 Table 11.9 - Floppy Disk Controller Logical Device Configuration Registers .............................................................189 Table 11.10 - Serial Port 2 Logical Device Configuration Registers...........................................................................190 Table 11.11 - Parallel Port Logical Device Configuration Registers ...........................................................................191 Table 11.12 - Serial Port 1 Logical Device Configuration Registers...........................................................................192 Table 11.13 - Keyboard Logical Device Configuration Registers ...............................................................................193 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 9 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 11.14 - Power Control/Runtime Register Block Logical Device Configuration Registers .................................193 Table 12.1 - Operational DC Characteristics..............................................................................................................195 Table 12.2 - S3-S5 Standby Current ..........................................................................................................................200 Table 13.1 - nIDE_RSTDRV Timing...........................................................................................................................220 Table 13.2 - nPCIRST_OUT and nPCIRST_OUT2 Timing ........................................................................................220 Table 13.3 - PS_ON Timing .......................................................................................................................................220 Table 13.4 - SCK_BJT_GATE Timing........................................................................................................................221 Table 13.5 - PWRGD_3V Timing ...............................................................................................................................221 Table 13.6 - CNR CODEC Down Enable Timing .......................................................................................................221 Table 13.7 - Resume Reset Timing............................................................................................................................222 Table 14.1 - 128 Pin MQFP Package Parameters .....................................................................................................223 Table 15.1 - XOR Test Pattern Example....................................................................................................................225 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 10 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 1 General Description The LPC47M172 is a 3.3V (5V tolerant) PC99a/PC2001 compliant Advanced I/O controller for Desktop PCs. The device, which implements the Low Pin Count (LPC) interface, includes I/O functionality as well as Motherboard GLUE logic into a 128-pin package. This is space saving solution on the motherboard resulting in lower cost. The LPC47M172 also provides 13 general purpose pins, which offer flexibility to the system designer, and two Fan Tachometer Inputs. The LPC47M172’s LPC interface supports LPC I/O and DMA cycles. The LPC47M172 includes complete legacy I/O: a keyboard interface with AMITM BIOS; SMSC's true CMOS 765B floppy disk controller with advanced digital data separator; two 16C550A compatible UARTs; one Multi-Mode parallel port including ChiProtect circuitry plus EPP and ECP. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures; in addition, it provides data overflow and underflow protection. The SMSC’s patented advanced digital data separator allows for ease of testing and use. The parallel port is compatible with IBM PC/AT architecture, as well as IEEE 1284 EPP and ECP. The LPC47M172 incorporates sophisticated power control circuitry (PCC) which includes support for keyboard and mouse wake up events as well as PME support. The PCC supports multiple low power-down modes. The LPC47M172 is ACPI 1.0b/2.0 compatible. The Motherboard GLUE logic includes various power management logic; including generation of nRSMRST, Power OK signal generation, 5V main and standby reference generation. There are also three LEDs to indicate power status and hard drive activity. The translation circuit converts 3.3V signals to 5V signals. Also included is SMBus main power well to resume power well isolation circuitry. The LPC47M172 supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47M172 may be reprogrammed through the internal configuration registers. There are up to 480 (960 for Parallel Port) I/O address location options, a Serialized IRQ interface, and three DMA channels. On chip, Interrupt Generating Registers enable external software to generate IRQ1 through IRQ15 on the Serial IRQ Interface. The LPC47M172’s Enhanced Digital Data Separator does not require any external filter components and is therefore easy to use and offers lower system costs and reduced board area. The LPC47M172 is register compatible with SMSC’s proprietary 82077AA core. This device utilizes two selectable (see Chapter 2) register sets; (1) standard SMSC and (2) tailored for Intel reference designs. These register sets are detailed in Chapter 6 (Section 6.1). SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 11 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 2 Pin Layout IRTX2 IRRX2 nDCD2 nDTR2 nCTS2 VCC nRTS2 nDSR2 TXD2 RXD2 nRI2 NC/VTR (Note) DDCSDA_5V/GP20 DDCSDA_3V/GP22 DDCSCL_5V/GP21 DDCSCL_3V/GP23 GP17/FAN_TACH2 GP16/FAN_TACH1 VSS GP15 GP14 VTR GP13 GP12 GP11 GP10 MCLK MDAT KCLK KDAT GA20M VCC nKBDRST VSS nDSKCHG nHDSEL nRDATA nWRTPRT nTRK0 nWGATE nWDATA nSTEP nDIR nDS0 nMTR0 nINDEX DRVDEN1 DRVDEN0 nDCD nDSR RXD nRTS TXD nCTS VSS nDTR (XOR) VCC nRI SLCT PE BUSY nACK PD7 PD6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 LPC47M172 128 PIN QFP nCDC_DWN_RST nCDC_DWN_ENAB/GP24 nAUD_LINK_RST nIO_PME TEST_EN F_CAP VSS YLW_LED GRN_LED VTR nRSMRST CLOCKI32 SMB_DAT_R SMB_DAT_M SMB_CLK_R SMB_CLK_M nSLP_S5 nSLP_S3 PWRGD_3V nCPU_PRESENT PWRGD_PS nPS_ON SCK_BJT_GATE LATCHED_BF_CUT VSS nBACKFEED_CUT VTR nFPRST nPCIRST_OUT2 nPCIRST_OUT REF5V_STBY V_5P0_STBY REF5V nSCSI nSECONDARY_HD nPRIMARY_HD nHD_LED CLOCKI SMSC/Non-SMSC Register Sets (Rev. 01-11-07) PD5 PD4 PD3 PD2 PD1 PD0 nERROR VSS nSLCTIN nINITP VCC nALF nSTROBE nLPCPD SER_IRQ nLDRQ PCI_CLK nLFRAME LAD3 VSS LAD2 VCC LAD1 LAD0 nPCI_RESET nIDE_RSTDRV 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Figure 2.1 - LPC47M172 Pin Layout Page 12 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Note: Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the LPC47M172. See Table 6.1 - Super I/O Block Logical Device Number and Addresses. The pin functions as follows: The pin has an internal pull-down resistor that selects the non-standard SMSC (Intel Compatible) mode. To select this mode, the pin should be left unconnected. This configuration clears the LD_NUM bit to ‘0’ and the associated functionality corresponds to the existing functionality in the part when the LD_NUM bit=0. Connecting this pin to VTR will select the standard SMSC mode of the logical device numbering. This configuration sets the LD_NUM bit to ‘1’ and the associated functionality corresponds to the existing functionality in the part when the LD_NUM bit=1. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 13 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 3 Description of Pin Functions Table 3.1 - LPC47M172 Pin Description PIN# NAME (NOTE 1) DESCRIPTION BUFFER NAME (NOTE 2) PWR WELL (NOTE 3) NOTES POWER AND GROUND PINS (20) See Note 11 6,31, 49,60, 123 76,93, 107, 117 See Note VCC +3.3 Volt Main Supply Voltage (5) PWR VTR +3.3 Volt Standby Supply Voltage (4) See Note PWR 11 71 8,29, 46,58, 78,96, 110 70 72 V_5P0_STBY VSS +5 Volt Standby Supply Voltage. Ground (7) PWR PWR REF5V REF5V_STBY 97 F_CAP 65 91 52 CLOCKI CLOCKI32 nLPCPD 53 SER_IRQ 54 nLDRQ 55 56 57,59, 61,62 PCI_CLK nLFRAME LAD[3:0] AO 5V Reference Output. Requires external pull-up to VCC5V. AO Highest System Standby Voltage. Requires external pull-up to V_5P0_STBY. Internal Regulator Filter Capacitor. This pin is a no connect. A filter capacitor can be placed on this pin if it is required by system board layout. CLOCKS (2) 14.318Mhz Clock Input IS 32.768kHz Clock Input IS PROCESSOR/HOST LPC INTERFACE (11) PCI_I Active low input Power Down signal indicates that the LPC47M172 should prepare for power to be shut-off on the LPC interface. Serial IRQ pin used with the PCI_CLK pin PCI_IO to transfer LPC47M172 interrupts to the host. PCI_O Active low output used for encoded DMA/Bus Master request for the LPC interface. 33.33 MHz PCI Clock input. PCI_ICLK PCI_I Active low input indicates start of new cycle and termination of broken cycle. PCI_IO Active high LPC I/O used for multiplexed command, address and data bus. VCC VTR VCC VTR VCC 4 5 VCC VCC VCC VCC VCC SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 14 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PIN# 63 NAME (NOTE 1) nPCI_RESET DESCRIPTION Active low input used as LPC Interface Reset. 3.3V and 5V buffered copy of PCI Reset signal is available on nPCIRST_OUT and nIDE_RSTDRV. These pins are listed under GLUE PINS. Power Management Event Output. This active low Power Management Event signal allows to request wakeup. This pin can be configured as Push-Pull Output. FDD INTERFACE (14) This input senses that the drive door is open or that the diskette has possibly been changed since the last drive selection. This input is inverted and read via bit 7 of I/O address 3F7H. The nDSKCHG bit also depends upon the state of the Force Disk Change bits in the Force Disk Change register (see Chapter 11 Configuration). Head Select Output. This high current output selects the floppy disk side for reading or writing. A logic “1” on this pin means side 0 will be accessed, while a logic “0” means side 1 will be accessed. Can be configured as an Open-Drain Output. Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data. This active low Schmitt Trigger input senses from the disk drive that a disk is write protected. Any write command is ignored. The nWRPRT bit also depends upon the state of the Force Write Protect bit in the FDD Option register (see the Configuration Registers section). This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the outermost track. Write Gate Output. This active low high current driver allows current to flow through the write head. It becomes active just prior to writing to the diskette. Can be configured as an Open-Drain Output. Write Disk Data Output. This active low high current driver provides the encoded data to the disk drive. Each falling edge causes a flux transition on the media. Can be configured as an Open-Drain Output. BUFFER NAME (NOTE 2) PCI_I PWR WELL (NOTE 3) VCC NOTES 99 nIO_PME OD8 VTR 9 nDSKCHG IS VCC 10 nHDSEL O12 VCC 11 nRDATA IS VCC 12 nWRTPRT IS VCC 13 nTRK0 IS VCC 14 nWGATE O12 VCC 15 nWDATA O12 VCC SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 15 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PIN# 16 NAME (NOTE 1) nSTEP DESCRIPTION 17 nDIR 18 19 20 nDS0 nMTR0 nINDEX 21 DRVDEN1 22 DRVDEN0 23 nDCD1 24 nDSR1 25 RXD1 Step Pulse Output. This active low high current driver issues a low pulse for each track-to-track movement of the head. Can be configured as an Open-Drain Output. O12 Step Direction Output. This high current low active output determines the direction of the head movement. A logic “1” on this pin means outward motion, while a logic “0” means inward motion. Can be configured as an Open-Drain Output. O12 Drive Select 0 Output. Can be configured as an Open-Drain Output. Motor On 0 Output. Can be configured as O12 an Open-Drain Output. IS This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. O12 Drive Density Select 1 Output. Indicates the drive and media selected. Can be configured as Open-Drain Output. O12 Drive Density Select 0 Output. Indicates the drive and media selected. Can be configured as Open-Drain Output. SERIAL PORT 1 INTERFACE (8) I Active low Data Carrier Detect input for the serial port. Handshake signal that notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD. I Active low Data Set Ready input for the serial port. Handshake signal that notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR. Receiver serial data input. IS Page 16 BUFFER NAME (NOTE 2) O12 PWR WELL (NOTE 3) VCC NOTES VCC VCC VCC VCC VCC VCC VCC VCC VCC SMSC LPC47M172 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PIN# 26 NAME (NOTE 1) nRTS1 DESCRIPTION 27 28 TXD1 nCTS1 30 nDTR1 (XOR) 32 nRI1 118 119 120 nRI2 RXD2 TXD2 Active low Request to Send output for the Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of the Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). nRTS is forced inactive during loop mode operation. Transmit serial data output. O12 I Active low Clear to Send input for the serial port. Handshake signal that notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS. O8 Active low Data Terminal Ready output for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). nDTR is forced inactive during loop mode operation. XOR Chain Output. I Active low Ring Indicator input for the serial port. Handshake signal that notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR). A nRI signal state change from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nRI changes state. Note: Bit 6 of MSR is the complement of nRI. SERIAL PORT 2 INTERFACE (8) IPD Active low Ring Indicator input for serial port 2. See description for nRI1. Receiver serial data input. ISPD_400 Transmit serial data output. O12 BUFFER NAME (NOTE 2) O8 PWR WELL (NOTE 3) VCC NOTES VCC VCC VCC VTR 6 VTR VCC VCC 6, 10 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 17 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PIN# 121 122 124 125 NAME (NOTE 1) nDSR2 nRTS2 nCTS2 nDTR2 DESCRIPTION 126 nDCD2 127 128 33 IRRX2 IRTX2 SLCT 34 PE 35 BUSY 36 nACK 37 38 39 40 41 42 43 44 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Active low Data Set Ready input for serial port 2. See description for nDSR1. O8 Active low Request to Send output for Serial Port 2. See description for nRTS1. IPD Active low Clear to Send input for serial port 2. See description for nCTS1. O8 Active low Data Terminal Ready output for serial port 2. See description for nDTR1. IPD Active low Data Carrier Detect input for serial port 2. See description for nDCD1. INFRARED INTERFACE (2) Infrared receive input. ISPD_400 Infrared transmit output. O12 PARALLEL PORT INTERFACE (17) I This high active input from the printer indicates that it has power on. Bit 4 of the Printer Status Register reads the SLCT input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. I Another status input from the printer, a high indicating that the printer is out of paper. Bit 5 of the Printer Status Register reads the PE input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. I This is a status input from the printer, a high indicating that the printer is not ready to receive new data. Bit 7 of the Printer Status Register is the complement of the BUSY input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. I A low active input from the printer indicating that it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the nACK input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Port Data 7 I/O IOP14 Port Data 6 I/O IOP14 Port Data 5 I/O IOP14 Port Data 4 I/O IOP14 Port Data 3 I/O IOP14 Port Data 2 I/O IOP14 Port Data 1 I/O IOP14 Port Data 0 I/O IOP14 BUFFER NAME (NOTE 2) IPD PWR WELL (NOTE 3) VCC VCC VCC VCC NOTES 10 10 VCC 10 VCC VCC VCC 10 9 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 18 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PIN# 45 NAME (NOTE 1) nERROR DESCRIPTION BUFFER NAME (NOTE 2) 47 nSLCTIN 48 nINITP 50 nALF 51 nSTROBE 1 2 3 4 5 7 64 66 67 68 69 MCLK MDAT KCLK KDAT GA20M nKBDRST nIDE_RSTDRV nHD_LED nPRIMARY_ HD nSECONDARY _HD nSCSI I A low on this input from the printer indicates that there is an error condition at the printer. Bit 3 of the Printer Status register reads the nERR input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. OP14 This active low output selects the printer. This is the complement of bit 3 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be Configured as an Open-Drain Output. OP14 This output is bit 2 of the printer control register. This is used to initiate the printer when low. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be configured as an Open-Drain Output. OP14 This output goes low to cause the printer to automatically feed one line after each line is printed. The nALF output is the complement of bit 1 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be configured as an Open-Drain Output. OP14 An active low pulse on this output is used to strobe the printer data into the printer. The nSTROBE output is the complement of bit 0 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Can be configured as an Open-Drain Output. KEYBOARD/MOUSE INTERFACE (6) Mouse Clock I/O IOD24 Mouse Data I/O IOD24 Keyboard Clock I/O IOD24 Keyboard Data I/O IOD24 Gate A20 Open-Drain Output OD8 Keyboard Reset Open-Drain Output OD8 GLUE PINS (29) IDE Reset Output OD8 OD12 Hard Drive Front Panel LED Open-Drain Output IDE Primary Drive Active Input ISPU_400 IDE Secondary Drive Active Input SCSI Drive Active Input ISPU_400 ISPU_400 PWR WELL (NOTE 3) VCC NOTES VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 6 6 7 7 3 3 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 19 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PIN# 73 74 75 77 79 80 81 82 83 84 85 86 87 88 89 90 92 100 101 NAME (NOTE 1) nPCIRST_OUT nPCIRST_OUT 2 nFPRST nBACKFEED_ CUT LATCHED_BF_ CUT SCK_BJT_ GATE nPS_ON PWRGD_PS nCPU_PRESENT DESCRIPTION Buffered PCI Reset Output Second Buffered PCI Reset Output Reset Input from Front Panel Open-Drain Output used for STR Circuitry Latched Backfeed Cut Output for STR Circuitry Open-Drain Gate Output for the SCK_BJT in Suspend-to-RAM Power Supply Turn-ON Open Drain Output Power Good Input from Power Supply CPU Present Input from Processor Power Good Output S3 Power State Input from South Bridge Input from South Bridge for Transitioning to the S5 Power State SMBus Clock Main SMBus Clock Resume SMBus Data Main SMBus Data Resume Resume Reset Output AC97 Link Reset Input AC97 Codec Down Enable Input. General Purpose I/O. GPIO can be configured as an open-drain output. AC97 Codec Down Reset Output. 3.3V DDC Clock General Purpose I/O. GPIO can be configured as an open-drain output. 5V DDC Clock General Purpose I/O. GPIO can be configured as an open-drain output. 3.3V DDC Data General Purpose I/O. GPIO can be configured as an open-drain output. 5V DDC Data General Purpose I/O. GPIO can be configured as an open-drain output. POWER LEDS (2) Green Power LED Open-Drain Output Yellow Power LED Open-Drain Output GENERAL PURPOSE I/O (8) General Purpose I/O. GPIO can be configured as an open-drain output. BUFFER NAME (NOTE 2) OP14 OP14 ISPU_400 OD8 OP14 OD8 OD8 ISPU_400 ISPU_400 O8 IS_400 IS_400 IO_SW IO_SW IO_SW IO_SW O8 I IO12 PWR WELL (NOTE 3) VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR 6 3 3 NOTES 3 PWRGD_3V nSLP_S3 nSLP_S5 SMB_CLK_M SMB_CLK_R SMB_DAT_M SMB_DAT_R nRSMRST nAUD_LINK_ RST nCDC_DWN_ ENAB/GP24 nCDC_DWN_ RST DDCSCL_3V/ GP23 DDCSCL_5V/ GP21 DDCSDA_3V/ GP22 DDCSDA_5V/ GP20 102 113 O12 IO_SW/IS OD8 IO_SW/IS OD8 IO_SW/IS OD8 IO_SW/IS OD8 VTR VTR 3, 6, 8 114 VTR 3, 6, 8 115 VTR 3, 6, 8 116 VTR 3, 6, 8 94 95 103105 GRN_LED YLW_LED GP10-GP12 OD24 OD24 ISO8 VTR VTR VTR 6 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 20 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PIN# 106, 108, 109 111 NAME (NOTE 1) GP13-GP15 DESCRIPTION General Purpose I/O. GPIO can be configured as an open-drain output. General Purpose I/O. GPIO can be configured as an open-drain output. Fan Tachometer 1 Input General Purpose I/O. GPIO can be configured as an open-drain output. Fan Tachometer 2 Input TEST (1) Test Enable Input for XOR-Chain test – the external pull-up or internal pull-down sets the strap value. The XOR output is the nDTR1 pin. NO CONNECT (1) See Note11 No Connect BUFFER NAME (NOTE 2) IO8 PWR WELL (NOTE 3) VTR NOTES 6 GP16/ FAN_TACH1 GP17/ FAN_TACH2 IO8 VTR 6 112 IO8 VTR 6 98 TEST_EN IPD VTR 117 Note 1: NC IPD - 11 The “n” as the first letter of a signal name or the “#” as the suffix of a signal name indicates an “Active Low” signal. The primary and secondary functions on the pins are separated by “/”. The buffer names are described in the “Buffer Name Descriptions” section. Open-drain pins should be pulled-up externally to supply shown in the power well column. The nIDE_RSTDRV, nHD_LED, DDCSDA_5V and DDCSCL_5V open-drain pins require external pull-ups to VCC5V. The nBACKFEED_CUT, SCK_BJT_GATE and nPS_ON open-drain pins require external pullups to V_5P0_STBY. Inputs with internal pull-ups are pulled internally to the supply shown in the power well column. All other pins are driven under the power well shown. See the “Pins With Internal Resistors”, “Pins That Require External Resistors” and “Default State of Pins” sections. The 32.768 kHz input clock must not be driven high when VTR = 0V. CLOCKI32 is clock source to various logic in the part, including LED, “wake on specific key” and nFPRST debounce circuitry. The 32 KHz input clock must always be connected. There is a bit in the configuration register at 0xF0 in Logical Device A that indicates whether or not the 32KHz clock is connected. This bit determines the clock source for the logic. This bit must always be set to ‘0’ (‘0’=32 KHz clock connected; reset default=‘0’). The nLPCPD pin may be tied high. The LPC interface will function properly if the nPCI_RESET signal follows the protocol defined for the nLRESET signal in the “Low Pin Count Interface Specification”. However, if nLPCPD is tied high, the keyboard wakeup isolation logic will be affected. These pins (except DDC and FAN_TACH functions) are also inputs to VTR powered logic internal to the part. If DDC and FAN_TACH functions are selected on GPIOs, the pins will tri-state when VCC power is removed. External pullups must be placed on the nKBDRST and GA20M pins. If the nKBDRST and GA20M functions are to be used, the system must ensure that these pins are high. See the “That Require External Resistors” section. When DDC functions are selected on GP20-GP23, the pins become IO_SW type and require external pullups to the appropriate voltages. See the “That Require External Resistors” section. When the GPIO functions are selected, the pins are IS0D8. The IRTX2 pin is driven low upon power-up of VCC. This pin will remain low following a power-up (VCC POR) until it is selected via the IR MUX bits and serial port 2 is enabled by setting the activate bit, at which Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 21 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet time the pin will reflect the state of the transmit output of the Serial Port 2 block. This is a VCC powered pin. Note 10: These pins are internally pulled down to VSS only until Serial Port 2 is enabled. Once Serial Port 2 is enabled, the pull-downs are removed until VTR POR. Note 11: Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the LPC47M172. See Table 6.1 - Super I/O Block Logical Device Number and Addresses. The pin has an internal pull-down resistor that selects the non-SMSC (Intel Compatible) mode. To select this mode, the pin should be left unconnected. Connecting this pin to VTR will select the SMSC mode of the logical device numbering. 3.1 Note: PWR I IPU IPD IS IS_400 ISPU_400 ISPD_400 O8 OD8 O12 OD12 OP14 OD24 AO IO8 ISO8 ISOD8 IO12 IOP14 IOD24 IO_SW PCI_IO PCI_O PCI_I PCI_ICLK Note 1: Note 2: Buffer Name Descriptions Refer to the “Electrical Characteristics” section. Power and Ground Input TTL Compatible. Input with 30uA Integrated Pull-Up Input with 30uA Integrated Pull-Down Input with 250mV Schmitt Trigger. Input with 400mV Schmitt Trigger. Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Up. Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Down. Output, 8mA sink, 4mA source. Output (Open Drain), 8mA sink. Output, 12mA sink, 6mA source. Output (Open Drain), 12mA sink. Output, 14mA sink, 14mA source. Output (Open Drain), 24mA sink. Output – Analog with 5V Level Input/Output, 8mA sink, 4mA source. Input with 250mV Schmitt Trigger /Output, 8mA sink, 4mA source. Input with 250mV Schmitt Trigger, Low Leakage/Output (Open-Drain), 8mA sink. Input with Schmitt Trigger/Output, 12mA sink, 6mA source. Input/Output, 14mA sink, 14mA source. Input/Output (Open Drain), 24mA sink. Input/Output, special type. Pins of this type are connected in pairs through a switch. The switch provides a 25 ohm (max) resistance to ground when closed. Input/Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) Output. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) Input. These pins meet the PCI 3.3V AC and DC Characteristics. (Note 1) Clock Input. These pins meet the PCI 3.3V AC and DC Characteristics and timing. (Note 2) See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2. See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 22 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 3.2 Pins With Internal Resistors The following pins have internal resistors: Table 3.2 - Pins with Internal Resistors SIGNAL NAME nCPU_PRESENT nFPRST nPRIMARY_HD PWRGD_PS nSCSI nSECONDARY_HD TEST_EN RESISTOR VALUE 30uA 30uA 30uA 30uA 30uA 30uA 30uA NOTES Pull-up to VTR Pull-up to VTR Pull-up to VCC Pull-up to VTR Pull-up to VCC Pull-up to VCC Pull-down to VSS 3.3 Pins That Require External Resistors The following pins require external resistors: Table 3.3 - Pins that Require External Resistors SIGNAL NAME SER_IRQ nLDRQ LAD[3:0] MCLK MDAT KCLK KDAT GA20M KBDRST nIO_PME nHDSEL nWGATE nWDATA nSTEP nDIR nDS0 nMTR0 DRVDEN1 DRVDEN0 nDSKCHG nRDATA nWRTPRT nTRK0 nINDEX REF5V REF5V_STBY RESISTOR VALUE 10 kohm 100 kohm 100 kohm 2.7 kohm NOTES Pull-up to VCC Pull-up to VCC Pull-up to VCC Pull-up to VREG_PS2. The VREG_PS2 is the voltage regulator for the PS/2 ports. 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 10 kohm 1 kohm 1 kohm 1 kohm 1 kohm 10 kohm 1 kohm 1 kohm Pull-up to VCC Pull-up to VCC Pull-up to VTR Pull-up required if used as Open-Drain Output. Pull-up to VCC. Pull-up to VCC Pull-up to VCC Pull-up to VCC Pull-up to VCC Pull-up to VCC Pull-up to VCC5V Pull-up to V_5P0_STBY SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 23 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SIGNAL NAME nIDE_RSTDRV nPS_ON nBACKFEED_CUT SCK_BJT_GATE nCDC_DWN_ENAB YLW_LED nHD_LED DDCSDA_3V DDCSCL_3V DDCSDA_5V DDCSCL_5V SMB_CLK_M SMB_CLK_R SMB_DAT_M SMB_DAT_R GRN_LED GPIOs RESISTOR VALUE 1 kohm 1 kohm 1 kohm 1 kohm 10 kohm 220 ohm 330 ohm 4.7 kohm 4.7 kohm 2.2 kohm 2.2 kohm 2.7 kohm 2.7 kohm 2.7 kohm 2.7 kohm 220 ohm design-dependant NOTES Pull-up to VCC5V Pull-up to V_5P0_STBY Pull-up to V_5P0_STBY Pull-up to V_5P0_STBY Pull-down to VSS Pull-up to VTR Pull-up to VCC Pull-up to VCC Pull-up to VCC Pull-up to VCC5V Pull-up to VCC5V Pull-up to VCC Pull-up to VTR Pull-up to VCC Pull-up to VTR Pull-up to VTR Pull-up to appropriate voltage (not to exceed 5V) 3.4 Default State of Pins The following table shows the default state of pins. Notes: Off The pin is not powered by suspend supply and is valid under main power only. Hi-Z The pin is powered, but tri-stated either because the pin is open-drain or VCC function is selected on VTR powered pin. The pin requires external pull-up when tri-stated. Active The pin is powered and active high. Running The input clock is powered and running. Input The pin is powered and driven by external circuitry to high or low level. Out The pin is powered and driven to high or low level by the part. The input or output configuration state of the pin is retained and is not affected by PCI Reset or VCC POR. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 24 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 3.4 - Default State of Pins SIGNAL NAME REF5V_STBY REF5V CLOCKI CLOCKI32 nIO_PME PCI_CLK nLPCPD nPCI_RESET SER_IRQ nLDRQ nLFRAME LAD[0:3] nDSKCHG nHDSEL nRDATA nWRTPRT nTRK0 nWGATE nWDATA nSTEP nDIR nDS0 nMTR0 nINDEX DRVDEN0 DRVDEN1 nDCD1 nDSR1 RXD1 nRTS1 TXD1 nCTS1 nDTR1 (XOR) nRI1 nDCD2 PWR WELL VTR VCC VCC VTR VTR VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VTR VCC PCI RESET Active Running Running Input Input Input Input Input Input Input Input Out – low Input Input Input Hi-Z Hi-Z Out – low Out – low Hi-Z Hi-Z Input Out – high Out – high Input Input Input Out – high Out – low Input Out – high Input Active Running Running Input Input Input Input Input Input Input Input Out – low Input Input Input Hi-Z Hi-Z Out – low Out – low Hi-Z Hi-Z Input Out – high Out – high Input Input Input Out – high Out – low Input Out – high Input VCC POR VTR POR Active Off Off Running Hi-Z Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Input Off This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. NOTES This pin requires external pullup to V_5P0_STBY This pin requires external pullup to VCC5V nDSR2 VCC Input Input Off RXD2 nRTS2 TXD2 VCC VCC VCC Input Out – high Out – low Input Out – high Out – low Off Off Off SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 25 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SIGNAL NAME nCTS2 nDTR2 nRI2 PWR WELL VCC VCC VTR PCI RESET Input Out – high - VCC POR Input Out – high - VTR POR Off Off Input NOTES This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. This pin is internally pulled down to VSS until Serial Port 2 is enabled. IRRX2 IRTX2 SLCT PE BUSY nACK PD[7:0] ERROR nSLCTIN nINITP nALF nSTROBE MCLK MDAT KCLK KDAT GA20M nKBDRST nAUD_LINK_RST nCDC_DWN_ENAB/ GP24 nCDC_DWN_RST nFPRST nBACKFEED_CUT LATCHED_BF_CUT SCK_BJT_GATE nSCSI GRN_LED YLW_LED nHD_LED nSECONDARY_HD nPRIMARY_HD nIDE_RSTDRV PWRGD_PS nPS_ON nCPU_PRESENT VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VTR VTR VTR VTR VTR VTR VTR VCC VTR VTR VCC VCC VCC VCC VTR VTR VTR Input Out – low Input Input Input Input Input Input Out – High Out – High Out – High Out – High Hi-Z Hi-Z Hi-Z Hi-Z Input Hi-Z Input Input Out – low - Input Out – low Input Input Input Input Input Input Out – High Out – High Out – High Out – High Hi-Z Hi-Z Hi-Z Hi-Z Input Hi-Z Input Input Out – low Page 26 Off Off Off Off Off Off Off Off Off Off Off Off Off Input Off Input Off Off Input Input Out – low Input Hi-Z Out – low Hi-Z Off Out – low Out – low Off Off Off Off Input Hi-Z Input This pin is pulled up internally This pin requires external pullup to V_5P0_STBY. This pin requires external pullup to V_5P0_STBY. This pin is pulled up internally This pin is pulled up internally This pin is pulled up internally Requires external pull-up to VCC5V Requires external pull-up to V_5P0_STBY This pin is pulled up internally SMSC LPC47M172 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SIGNAL NAME nSLP_S3 nSLP_S5 nRSMRST PWRGD_3V nPCIRST_OUT nPCIRST_OUT2 GP10-GP15 GP16 FAN_TACH1 GP17 FAN_TACH2 SMB_CLK_M SMB_CLK_R SMB_DAT_M SMB_DAT_R DDCSDA_5V PWR WELL VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR VTR PCI RESET Out – low Out – low Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z VCC POR Out – low Out – low Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - VTR POR Input Input Out – low Out – low Out – low Out – low Input Input Hi-Z Input Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z NOTES The GPIO and FAN_TACH functions are multiplexed on the same pin with GPIO as the default function. GP20 DDCSCL_5V VTR GP21 DDCSDA_3V VTR GP22 DDCSCL_3V VTR GP23 Hi-Z Hi-Z - The DDC and GPIO functions are multiplexed on the same pin with DDC as the default function. DDC function requires external pull-up to VCC5V. The DDC and GPIO functions are multiplexed on the same pin with DDC as the default function. DDC function requires external pull-up to VCC. Test Mode pin. This pin has internally pull-down to VSS. External pull-up required to enable the test mode. TEST_EN VTR - - Input SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 27 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 4 Block Diagram FAN_TACH1* FAN_TACH2* CLOCKI32 GRN_LED YLW_LED TEST_EN CLOCKI SER_IRQ PCI_CLK LAD[3:0] nLFRAME nLDRQ nPCI_RESET nLPCPD nIO_PME GP10-GP15, GP16*, GP17* (GP20-GP23)* GP24* F_CAP V_5P0_STBY nRSMRST REF5V REF5V_STBY nAUD_LINK_RST nCDC_DWN_ENAB* nCDC_DWN_RST nPCI_RST_OUT nPCI_RST_OUT2 nIDE_RSTDRV nPRIMARY_HD nSECONDARY_HD nSCSI nHD_LED nFPRST nBACKFEED_CUT LATCHED_BF_CUT SCK_BJT_GATE nPS_ON PWRGD_PS nSLP_S5 SERIAL IRQ / Interrupt Generating Registers CLOCK GEN Power LED FAN Monitoring XOR-Chain XOR* PD[7:0] Multi-Mode Parallel Port with ChiProtectTM BUSY, SLCT, PE, nERROR, nACK nSTROBE, nINITP, nSLCTIN, nALF RXD TXD nCTS nRTS nDSR nDTR* nDCD nRI RXD2 TXD2 nCTS2 nRTS2 nDSR2 nDTR2 nDCD2 nRI2 IRRX2 IRTX2 KDAT, MDAT LPC Bus Interface Internal Bus (Data, Address, and Control lines) PME / Power Control GPIOs LPC47M172 (128 QFP) VCC (3.3V) VTR (3.3V) High-Speed 16550A UART PORT Resume Reset Generation 5V Reference Generation V_5P0_STBY High-Speed 16550A UART PORT 2 W/ Infrared Configuration Registers nPCI_RESET Keyboard/Mouse 8042 Controller CNR Logic Buffered PCI Reset KCLK, MCLK GA20M nKBDRST Hard Drive Front Panel LED SMSC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE WDATA WCLOCK DIGITAL DATA SEPARATOR WITH WRITE PRECOMPENSATION Power Sequencing SMBus Isolation VGA Voltage Translation RCLOCK RDATA SMB_DAT_M SMB_CLK_R SMB_DAT_R DDCSDA_5V* DDCSDA_3V* DDCSCL_5V* nCPU_PRESENT DDCSCL_3V* SMB_CLK_M nDIR, nSTEP, nDS0, nMTR0 DRVDEN0, DRVDEN1 nWGATE, nHDSEL nTRK0, nDSKCHG, nINDEX, nWRTPRT nSLP_S3 PWRGD_3V nSLP_S5 nWDATA nRDATA Note 1: This diagram shows the various functions available on the chip (not pin layout). The block diagram should not be used for pin count. Note 2: Functions with asterisks (*) are located on multifunctional pins. Figure 4.1 - LPC47M172 Block Diagram SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 28 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 5 Power and Clock Functionality The LPC47M172 has three power planes: VCC, VTR and V5P0_STBY. 5.1 3 Volt Operation / 5 Volt Tolerance The LPC47M172 is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the operating input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected (they do not impose a load on any external VCC powered circuitry). The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. The nRSMRST pin is also 3.3V only. The following lists the pins that are 3.3V only (not 5V tolerant): LAD[3:0] nLFRAME nLDRQ nLPCPD nRSMRST The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins: nPCI_RESET PCI_CLK SER_IRQ nIO_PME 5.2 VCC Power The LPC47M172 is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). Description” Section and the “Maximum Current Values” subsection. See the “Operational 5.3 VTR Power The LPC47M172 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME interface and other suspend state logic when VCC is removed. The VTR supply is 3.3 Volts (nominal). See the Operational Description Section. The maximum VTR current that is required depends on the functions that are used in the part. See Trickle Power Functionality subsection and Maximum Current Values subsection. If the LPC47M172 is not intended to provide wake-up and/or suspend power capabilities on standby current, VTR can be connected to VCC. The VTR pin generates a VTR Power-on-Reset signal to initialize these components. Note: If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full minimum potential at least 10 μs before VCC begins a power-on cycle. When VTR and VCC are fully powered, the potential difference between the two supplies must not exceed 500mV. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 29 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 5.3.1 Trickle Power Functionality When the LPC47M172 is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The following lists the wakeup events: UART1 and UART 2 Ring Indicator Keyboard data Mouse data “Wake on Specific Key” Logic GPIOs for wakeup. See below. The following requirements apply to all I/O pins that are specified to be 5 volt tolerant. I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR. I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present. The GPIOs that are used for PME wakeup as input are GP10-GP17 and GP20-GP23 Buffers are powered by VTR. These pins have input buffers into the wakeup logic that are powered by VTR. GP24 does not have input buffer into the wakeup logic. The output buffer of GP24 is by VTR but does this pin does not have an input buffer into wakeup logic powered by VTR. For blocks, registers and pins that are powered by VTR see Table 3.1 and Figure 4.1. 5.4 V5P0_STBY Power The V5P0_STBY pin is used in nRSMRST generation circuit. The V5P0_STBY, however, does not power the nRSMRST pad. 5.5 32.768 kHz Trickle Clock Input The LPC47M172 utilizes a 32.768 kHz trickle input to supply a clock signal for the nFPRST debounce circuitry, LED blink and wake on specific key function. 5.5.1 Indication of 32KHZ Clock There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M172. This bit is located at bit 0 of the CLOCKI32 configuration register at 0xF0 in Logical Device A (see Table 11.14). This register is powered by VTR and reset on a VTR POR. Bit[0] (CLK32_PRSN) is defined as follows: 0=32kHz clock is connected to the CLKI32 pin (default) 1=32kHz clock is not connected to the CLKI32 pin (pin is grounded). SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 30 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Bit 0 controls the source of the 32kHz (nominal) clock for the nFPRST debounce circuitry, the LED blink logic and the “wake on specific key” logic. When the external 32kHz clock is connected, that will be the source for the nFPRST debounce circuitry, LED and “wake on specific key” logic. When the external 32kHz clock is not connected, an internal 32kHz clock source will be derived from the 14MHz clock for the “wake on specific key” logic. The nFPRST debounce circuitry and LED require the 32kHz clock be always connected. The “wake on specific key” function will not work under VTR power (VCC removed) if the external 32kHz clock is not connected. It will work under VCC power even if the external 32 kHz clock is not connected. 5.6 14.318 MHz Clock Input The LPC47M172 utilizes a 14.318 MHz clock input (CLOCKI). This clock is used to generate specific clocks needed for various logic (including SIO functions, Fan Tachometer, etc.) in the LPC47M172. The CLOCKI is powered by VCC and is not available in VTR power only (VCC=0). 5.7 Internal PWRGOOD An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as VCC cycles on and off. When the internal PWRGOOD signal is “1” (active), VCC > 2.3V (nominal), and the LPC47M172 host interface is active. When the internal PWRGOOD signal is “0” (inactive), VCC 1 microsecond). However, the LPC47M172 uses a SYNC of 0110 for all wait states in an I/O transfer. The SYNC value is driven within 3 clocks. SYNC Timeout The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it will abort the cycle. The LPC47M172 does not assume any particular timeout. When the host is driving SYNC, it may have to insert a very large number of wait states, depending on PCI latencies and retries. SYNC Patterns and Maximum Number of SYNCS If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8. If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47M172 has protection mechanisms to complete the cycle. This is used for EPP data transfers and should utilize the same timeout protection that is in EPP. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 35 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet SYNC Error Indication The LPC47M172 reports errors via the LAD[3:0] = 1010 SYNC encoding. If the host was reading data from the LPC47M172, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47M172. If the host was writing data to the LPC47M172, the data had already been transferred. In the case of multiple byte cycles, such as memory and DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not be transferred. 6.3.10 I/O and DMA START Fields I/O and DMA cycles use a START field of 0000. Reset Policy The following rules govern the reset policy: When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that is used for the PCI bus. When nPCI_RESET goes active (low): the host drives the nLFRAME signal high, tristates the LAD[3:0] signals, and ignores the nLDRQ signal. the LPC47M172 ignores nLFRAME, tristate the LAD[3:0] pins and drive the nLDRQ signal inactive (high). 6.3.11 LPC Transfers Wait State Requirements I/O Transfers The LPC47M172 inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used for all I/O transfers. The exception to this is for transfers where IOCHRDY would normally be deasserted in an ISA transfer (i.e., EPP or IrCC transfers) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330 which corresponds to a timeout of 10us). DMA Transfers The LPC47M172 inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of 0101 is used for all DMA transfers. See the example timing for the LPC cycles in the “Timing Diagrams” section. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 36 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.4 Floppy Disk Controller The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC is compatible to the 82077AA using SMSC’s proprietary floppy disk controller core. 6.4.1 FDC Configuration Registers The FDC configuration registers are summarized Table 11.2 in the “Configuration” section. The FDC logical device configuration registers (0xF0, 0xF1, 0xF2 and 0xF4) are defined in Table 11.9. 6.4.2 FDC Internal Registers The Floppy Disk Controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. Table 6.2 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. Table 6.2 - Status, Data and Control Registers (Shown with base addresses of 3F0 and 370) PRIMARY ADDRESS 3F0 3F1 3F2 3F3 3F4 3F4 3F5 3F6 3F7 3F7 SECONDARY ADDRESS 370 371 372 373 374 374 375 376 377 377 R/W R R R/W R/W R W R/W R W REGISTER Status Register A (SRA) Status Register B (SRB) Digital Output Register (DOR) Tape Drive Register (TDR) Main Status Register (MSR) Data Rate Select Register (DSR) Data (FIFO) Reserved Digital Input Register (DIR) Configuration Control Register (CCR) SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 37 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.4.3 Status Register A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 modes. The SRA can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 – D7 are held in a high impedance state for a read of address 3F0. PS/2 Mode 7 INT PENDIN G 0 6 nDRV2 5 STEP 4 nTRK0 3 HDSEL 2 nINDX 1 nWP 0 DIR RESET COND. 1 0 N/A 0 N/A N/A 0 BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic “1” indicates inward direction; a logic “0” indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic “0” indicates that the disk is write protected. BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic “1” selects side 1 and a logic “0” selects side 0. BIT 4 nTRACK 0 Active low status of the TRK0 disk interface input. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 6 nDRV2 This function is not supported. This bit is always read as “1”. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. PS/2 Model 30 Mode 7 INT PENDING RESET COND. BIT 0 DIRECTION Active low status indicating the direction of head movement. A logic “0” indicates inward direction; a logic “1” indicates outward direction. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 38 SMSC LPC47M172 6 DRQ 0 0 5 STEP F/F 0 4 3 2 TRK0 nHDSEL INDEX N/A 1 N/A 1 WP N/A 0 nDIR 1 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic “1” indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 HEAD SELECT Active low status of the HDSEL disk interface input. A logic “0” selects side 1 and a logic “1” selects side 0. BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. BIT 6 DMA REQUEST Active high status of the DMA request pending. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt. 6.4.4 Status Register B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 – D7 are held in a high impedance state for a read of address 3F1. PS/2 Mode 7 1 RESET COND. BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 2 WRITE GATE Active high status of the WGATE disk interface output. 1 6 1 1 5 DRIVE SEL0 0 4 3 2 WDATA RDATA WGATE TOGGLE TOGGLE 0 0 0 1 MOT EN1 0 0 MOT EN0 0 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 39 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 6 RESERVED Always read as a logic “1”. BIT 7 RESERVED Always read as a logic “1” PS/2 Model 30 Mode 7 nDRV2 RESET COND. BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. BIT 7 nDRV2 Active low status of the DRV2 disk interface input. Note: This function is not supported. N/A 6 nDS1 1 5 nDS0 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 1 0 nDS2 1 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 40 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.4.5 Digital Output Register (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 DMAEN 0 2 nRESET 0 1 DRIVE SEL1 0 0 DRIVE SEL0 0 RESET COND. BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic “1” is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic “1” will enable the DMA and interrupt functions. This bit being a logic “0” will disable the DMA and interrupt functions. This bit is a logic “0” after a reset and in these modes. PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this bit will be cleared to a logic “0”. BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic “1” in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic “1” in this bit will cause the output pin to go active. DRIVE 0 1 DOR VALUE 1CH 2DH Table 6.3 - Internal 2 Drive Decode - Normal DIGITAL OUTPUT REGISTER Bit 5 X 1 0 Bit 4 1 X 0 Bit1 0 0 X Bit 0 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 1 0 1 nDS0 0 1 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 41 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 6.4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped DIGITAL OUTPUT REGISTER Bit 5 X 1 0 Bit 4 1 X 0 Bit1 0 0 X Bit 0 0 1 X DRIVE SELECT OUTPUTS (ACTIVE LOW) nDS1 0 1 1 nDS0 1 0 1 MOTOR ON OUTPUTS (ACTIVE LOW) nMTR1 nMTR0 nBIT 4 nBIT 5 nBIT 4 nBIT 5 nBIT 4 nBIT 5 BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not supported in the LPC47M172. BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not supported in the LPC47M172. 6.4.6 Tape Drive Register (TDR) Address 3F3 READ/WRITE The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. Table 6.5 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. Table 6.5 - Tape Select Bits TAPE SEL1 (TDR.1) 0 0 1 1 TAPE SEL0 (TDR.0) 0 1 0 1 DRIVE SELECTED None 1 2 3 Normal Floppy Mode Normal mode.Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 – 7 are ‘0’. DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 tape sel1 DB0 tape sel0 REG 3F3 Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 REG 3F3 Reserved Reserved DB5 DB4 Drive Type ID DB3 DB2 Floppy Boot Drive DB1 tape sel1 DB0 tape sel0 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 42 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 6.6 - Drive Type ID DIGITAL OUTPUT REGISTER Bit 1 Bit 0 0 0 0 1 1 0 1 1 Note: REGISTER 3F3 – DRIVE TYPE ID Bit 5 Bit 4 L0-CRF2 – B1 L0-CRF2 – B0 L0-CRF2 – B3 L0-CRF2 – B2 L0-CRF2 – B5 L0-CRF2 – B4 L0-CRF2 – B7 L0-CRF2 – B6 L0-CRF2-Bx = FDC Logical Device, Configuration Register F2, Bit x. 6.4.7 Data Rate Select Register (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30. 7 6 S/W POWER RESET DOWN 0 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PREDRATE DRATE COMP0 SEL1 SEL0 0 1 0 RESET COND. This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 6.7 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. This starting track number can be changed by the configure command. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 43 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 6.7 - Precompensation Delays PRECOMP 432 111 001 010 011 100 101 110 000 BIT 5 UNDEFINED Should be written as a logic “0”. BIT 6 LOW POWER A logic “1” written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or access to the Data Register or Main Status Register. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Separator circuits will be turned off. The controller will come out of manual low power. Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located at the offset 0x19 in the Power Control/Runtime Register block. Table 6.8 - Data Rates DRIVE RATE DRT1 0 0 0 0 0 0 0 0 1 1 1 1 DRT0 0 0 0 0 1 1 1 1 0 0 0 0 DATA RATE SEL1 1 0 0 1 1 0 0 1 1 0 0 1 SEL0 1 0 1 0 1 0 1 0 1 0 1 0 DATA RATE MFM 1Meg 500 300 250 1Meg 500 500 250 1Meg 500 2Meg 250 FM --250 150 125 --250 250 125 --250 --125 1 1 0 0 1 1 0 0 1 1 0 0 DENSEL DRATE(1) 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 PRECOMPENSATION DELAY (NSEC) 1.5V, VCC5V>VCC + 0.15; High Output Level VOH VREF3IN -0.15 VREF3IN +0.15 V VCC>1.5V, VCC>VCC5V + 0.15; IOH = -3.3mA For REF5V_STBY Low Output Level VOL 0.4 V V_5P0_STBY>1.5V, V_5P0_STBY>VTR + 0.15; VTR>1.5V, VTR>V_5P0_STBY + 0.15; IOH = -3.3mA High Output Level O8 Output Buffer VOH VTR-0.15 VTR+ 0.15 V Low Output Level High Output Level OD8 Output Buffer Low Output Level High Output Level VOL VOH 2.4 0.4 V V IOL = 8mA IOH = -4mA VOL VOH Page 196 0.4 Vcc+10% V V IOL = 8mA Open-Drain SMSC LPC47M172 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PARAMETER O12 Output Buffer SYMBOL MIN TYP MAX UNITS COMMENTS Low Output Level High Output Level OD12 Output Buffer Low Output Level High Output Level OP14 Output Buffer Low Output Level High Output Level OD24 Output Buffer Low Output Level High Output Level IO8 Input/Output Buffer Low Input Level High Input Level Low Output Level High Output Level ISO8 Input/Output Buffer Low Input Level High Input Level Schmitt Trigger Hystersis Low Output Level High Output Level VOL VOH 2.4 0.4 V V IOL = 12mA IOH = -6mA VOL VOH 0.4 Vcc+10% V V IOL = 12mA Open-Drain VOL VOH 2.4 0.4 V V IOL = 14mA IOH = -14mA VOL VOH 0.4 Vcc+10% V V IOL = 24mA Open-Drain VIL VIH VOL VOH 2.4 2.0 0.8 5.5 0.4 V V V V TTL Levels TTL Levels IOL = 8mA IOH = -4mA VIL VIH VHYS VOL VOH 2.4 2.2 250 0.8 5.5 V V mV Schmitt Trigger Schmitt Trigger 0.4 V IOL = 8mA IOH = -4mA SMSC LPC47M172 Page 197 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PARAMETER ISOD8 Input/Output Buffer SYMBOL MIN TYP MAX UNITS COMMENTS Low Input Level High Input Level Schmitt Trigger Hystersis Low Output Level High Output Level IPDO8 Input Buffer VIL VIH VHYS VOL VOH 2.2 250 0.8 5.5 V V mV Schmitt Trigger Schmitt Trigger 0.4 Vcc+10% V V IOL = 8mA Open-Drain, Vcc = 5V Max Low Input Level High Input Level Pull-Down Low Output Level High Output Level IO12 Input/Output Buffer Low Input Level High Input Level Low Output Level High Output Level IOP14 Input/Output Buffer Low Input Level High Input Level Low Output Level High Output Level IO_SW Input/Output Special Type VIL VIH PD VOL VOH 2.0 30 0.8 5.5 V V uA TTL Levels TTL Levels 0.4 Vcc+10% V V IOL = 8mA IOH = -4mA VIL VIH VOL VOH 2.4 2.0 0.8 5.5 0.4 V V V V TTL Levels TTL Levels IOL = 12mA IOH = -6mA VIL VIH VOL 2.0 0.8 5.5 0.4 V V V TTL Levels TTL Levels IOL = 14mA VOH IOH = -14mA 2.4 V Pins of this type are connected in pairs through a switch. The switch provides a 25 ohm (max) resistance to ground when closed. See SMBus Isolation Circuitry and Voltage Translation Circuit sections for a description. Note: Vcc=5V max. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 198 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PARAMETER IOD24 Input/Output Buffer SYMBOL MIN TYP MAX UNITS COMMENTS Low Input Level High Input Level Low Output Level High Output Level PCI Type Buffers (PCI_ICLK, PCI_I, PCI_O, PCI_IO) Leakage Current (ALL except IS, IS_400, ISPU_400, ISOD8, AO, O8_3V and PCI Buffers) Input High Current Input Low Current Leakage Current (IS, IS_400, ISPU_400 and ISOD8 Buffers) VIL VIH VOL VOH 3.3V PCI 2.1 Compatible. 2.0 0.8 5.5 0.4 Vcc+10% V V V V TTL Levels TTL Levels IOL = 24mA Open-Drain ILEAKIH ILEAKIL 10 -10 uA uA VIN = Vcc VIN = 0V Input High Leakage Current Input Low Leakage Current Leakage Current (AO Buffer) ILEAKIH ILEAKIL 1 -1 uA uA VIN = Vcc VIN = 0V Input High Leakage Current Input Low Leakage Current Leakage Current (PCI Buffers and nRSMRST) Input High Leakage Current Input Low Leakage Current Backdrive Protect/ChiProtect (All except PCI Buffers and nRSMRST) Input High Leakage Current Input Low Leakage Current ILEAKIH ILEAKIL 20 -20 uA uA VIN = Vcc VIN = 0V VCC = 0V and VCC = 3.3V VIN = 3.6V Max VIN = 0V ILEAKIH ILEAKIL 10 -10 µA µA ILEAKIH ILEAKIL 10 -10 µA µA VCC = 0V VIN = 5.5V Max VIN = 0V SMSC LPC47M172 Page 199 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PARAMETER 5V Tolerant Pins (All except PCI Buffers and nRSMRST) SYMBOL MIN TYP MAX UNITS COMMENTS Input High Leakage Current Input Low Leakage Current 3.3V Main Supply Voltage 3.3V Main Supply Current ILEAKIH ILEAKIL VCC ICC3 10 -10 3.6 15 µA µA V mA VCC = 0V VIN = 5.5V Max VIN = 0V VCC must not be greater than 0.5V above VTR All outputs open, all inputs transitioning to/from 0V from/to 3.3V All outputs open, all inputs transitioning to/from 0V from/to 3.3V 3.0 3.3 10 3.3V Standby Supply Current 5V Standby Supply Voltage 5V Standby Supply Current Note: ITR3 0.2 2 mA V_5P0_S TBY ITR5 4.75 1 5.25 3 V mA All leakage currents are measured with pins in high impedance. 12.3 Standby Power Requirements This includes only signals that are outputs and source standby current (no OD outputs). Internal pull-ups are ignored due to their small contribution. External pull-ups are not in this analysis because they do not cause LPC47M172 to draw a discernable amount of additional power. Application Note: The following pins are powered by VTR. If configured as output pins, the VTR current will increase if these pins are sourcing current into a load. The board designer must make allowances for this additional current based upon this board design and the loads these pins are driving. Table 12.2 - S3-S5 Standby Current SYMBOL REF5V_STBY nCDC_DWN_ENAB/GP24 nCDC_DWN_RST nPCIRST_OUT nPCIRST_OUT2 nIO_PME LATCHED_BF_CUT PWRGD_3V nRSMRST GP10-GP17, GP20-GP23 Total TYPE AO IO12 O12 OP14 OP14 O8/OD8 OP14 O8 O8 IO8 STBY MAX. CURRENT (MA) 3.3 6 6 14 14 4 0 4 4 48 103.3 NAME AND FUNCTION Standby Reference Output CODEC Down Enable/GPIO CODEC Down Reset 3.3V Buffered copy of nPCI_RESET Second 3.3V Buffered copy of nPCI_RESET Power Management Events Signal only on for a short period of time Power Good Signal Reset for the ICH Resume Well 12 GPIOs SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 200 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 12.4 Capacitance Values for Pins MAX 20 10 20 UNIT pF pF pF TEST CONDITION All pins except pin under test tied to AC ground CAPACITANCE TA = 25oC; fc = 1MHz; VCC = 3.3V ±10% LIMITS PARAMETER SYMBOL MIN TYP Clock Input Capacitance CIN Input Capacitance CIN Output Capacitance COUT Note: The input capacitance of a port is measured at the connector pins. SMSC LPC47M172 Page 201 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 13 Timing Diagrams For the Timing Diagrams shown, the following capacitive loads are used on outputs. NAME SER_IRQ LAD [3:0] nLDRQ nDIR nSTEP nDS0 PD[0:7] nSTROBE nALF KDAT KCLK MDAT MCLK TXD YLW_LED GRN_LED nIDE_RSTDRV nPCIRST_OUT nPCIRST_OUT2 PS_ON SCK_BJT_GATE PWRGD_3V nCDC_DWN_ENAB/ GP24 nCDC_DWN_RST CAPACITANCE TOTAL (pF) 50 50 50 240 240 240 240 240 240 240 240 240 240 50 50 50 40 40 40 50 50 50 50 50 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 202 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet t1 V cc t2 t3 A ll H o s t A ccesses Figure 13.1 - Power-Up Timing NAME DESCRIPTION MIN TYP MAX UNITS t1 t2 t3 Note 1: Vcc Slew from 2.7V to 0V Vcc Slew from 0V to 2.7V All Host Accesses After Powerup (Note 1) 300 100 125 500 us us us Internal write-protection period after Vcc passes 2.7 volts on power-up SMSC LPC47M172 Page 203 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet t1 CLOCKI t2 t2 Figure 13.2 - Input Clock Timing NAME t1 t2 t1 DESCRIPTION Clock Cycle Time for 14.318MHZ Clock High Time/Low Time for 14.318MHz Clock Cycle Time for 32KHZ MIN TYP 69.84 35 31.25 MAX UNITS ns ns μs μs ns 20 t2 Clock High Time/Low Time for 32KHz Clock Rise Time/Fall Time (not shown) 15.63 5 t1 t4 t3 t2 P C I_ C L K t5 Figure 13.3 - PCI Clock Timing NAME t1 t2 t3 t4 t5 DESCRIPTION MIN 30 12 12 TYP MAX 33.3 UNITS nsec nsec nsec nsec nsec Period High Time Low Time Rise Time Fall Time 3 3 nPCI_RESET t1 Figure 13.4 - Reset Timing NAME t1 DESCRIPTION MIN 1 TYP MAX UNITS ms nPCI_RESET width SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 204 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet CLK t1 Output Delay t2 t3 Tri-State Output Figure 13.5 - Output Timing Measurement Conditions, LPC Signals NAME DESCRIPTION t1 CLK to Signal Valid Delay – Bused Signals t2 Float to Active Delay t3 Active to Float Delay MIN 2 2 TYP MAX 11 11 28 UNITS ns ns ns t1 CLK Input Inputs Valid t2 Figure 13.6 - Input Timing Measurement Conditions, LPC Signals NAME DESCRIPTION t1 Input Set Up Time to CLK – Bused Signals t2 Input Hold Time from CLK MIN 7 0 TYP MAX UNITS ns ns PCI_CLK nLFRAME LAD[3:0] L1 L2 Address Data TAR Sync=0110 L3 TAR Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 Figure 13.7 - I/O Write SMSC LPC47M172 Page 205 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PCI_CLK nLFRAME LAD[3:0] L1 L2 Address TAR Sync=0110 L3 Data TAR Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 Figure 13.8 - I/O Read PCI_CLK nLDRQ Start MSB LSB ACT Figure 13.9 - DMA Request Assertion through NLDRQ PCI_CLK LFRAME# LAD[3:0] Start C+D CHL Size TAR Sync=0101 L1 Data TAR Note: L1=Sync of 0000 Figure 13.10 - DMA Write (First Byte) PCI_CLK nLFRAME LAD[3:0] Note: Start C+D CHL Size Data TAR Sync=0101 L1 TAR L1=Sync of 0000 Figure 13.11 - DMA Read (First Byte) SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 206 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet nDIR t3 t4 nSTEP t9 nDS0 t5 t1 t2 nINDEX t6 nRDATA t7 nWDATA t8 Figure 13.12 - Floppy Disk Drive Timing (At Mode Only) NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 Notes: DESCRIPTION nDIR Set Up to STEP Low nSTEP Active Time Low nDIR Hold Time after nSTEP nSTEP Cycle Time nDS0 Hold Time from nSTEP Low (Note) nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low nDS0 Setup Time nDIR Low (Note) MIN TYP 4 24 96 132 20 2 40 .5 MAX UNITS X* X* X* X* X* X* ns Y* ns 0 *X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16 x Data Rate (at 500 kb/s MCLK = 8 MHz) WCLK = 2 x Data Rate (at 500 kb/s WCLK = 1 MHz) The DS0 setup and hold time must be met by software. SMSC LPC47M172 Page 207 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet t1 nWRITE t2 t3 PD t4 t5 t6 nDATASTB nADDRSTB t8 nWAIT Figure 13.13 - EPP 1.9 Data or Address Write Cycle NAME t1 t2 t3 t4 t5 t6 t7 DESCRIPTION nWAIT Asserted to nWRITE Asserted (Note 1) nWAIT Asserted to nWRITE Change (Note 1) nWAIT Asserted to PDATA Invalid (Note 1) PDATA Valid to Command Asserted nWRITE to Command Asserted nWAIT Asserted to Command Asserted (Note 1) nWAIT Deasserted to Command Deasserted (Note 1) Command Asserted to nWAIT Deasserted Command Deasserted to nWAIT Asserted MIN 60 60 0 10 5 60 60 TYP MAX 185 185 UNITS ns ns ns ns ns ns ns t7 t9 35 210 190 10 t8 t9 Note 1: 0 0 us ns nWAIT must be filtered to compensate for ringing on the parallel bus cable. nWAIT is considered to have settled after it does not transition for a minimum of 50 nsec. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 208 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet t1 nWRITE t3 PD t7 t8 t9 nDATASTB nADDRSTB t11 nWAIT Figure 13.14 - EPP 1.9 Data or Address Read Cycle NAME t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 DESCRIPTION nWAIT Asserted to nWRITE Deasserted nWAIT Asserted to nWRITE Modified (Notes 1,2) nWAIT Asserted to PDATA Hi-Z (Note 1) Command Asserted to PDATA Valid Command Deasserted to PDATA Hi-Z nWAIT Asserted to PDATA Driven (Note 1) PDATA Hi-Z to Command Asserted nWRITE Deasserted to Command nWAIT Asserted to Command Asserted nWAIT Deasserted to Command Deasserted (Note 1) PDATA Valid to nWAIT Deasserted PDATA Hi-Z to nWAIT Asserted MIN 0 60 60 0 0 60 0 1 0 60 TYP MAX 185 190 180 t2 t4 t5 t6 t10 t12 190 30 195 180 UNITS ns ns ns ns ns ns ns ns ns ns t11 t12 Note 1: Note 2: 0 0 ns µs nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. When not executing a write cycle, EPP nWRITE is inactive high. SMSC LPC47M172 Page 209 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet t1 nWRITE t2 PD t3 t4 nDATASTB nADDRSTB t5 nWAIT Figure 13.15 - EPP 1.7 Data or Address Write Cycle NAME t1 t2 t3 t4 t5 DESCRIPTION Command Deasserted to nWRITE Change Command Deasserted to PDATA Invalid PDATA Valid to Command Asserted nWRITE to Command Command Deasserted to nWAIT Deasserted MIN 0 50 10 5 0 TYP MAX 40 UNITS ns ns ns ns ns 35 35 nWRITE t1 PD nDATASTB nADDRSTB t3 nWAIT Figure 13.16 - EPP 1.7 Data or Address Read Cycle NAME DESCRIPTION t1 Command Asserted to PDATA Valid t2 Command Deasserted to PDATA Hi-Z t3 Command Deasserted to nWAIT Deasserted MIN 0 0 0 TYP MAX UNITS ns ns ns t2 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 210 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 13.1 ECP Parallel Port Timing 13.1.1 Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer to Figure 13.17. 13.1.2 ECP Parallel Port Timing The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter cable is used then the bandwidth will increase. 13.1.3 Forward-Idle When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. 13.1.4 Forward Data Transfer Phase The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk. The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest. The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the peripheral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the peripheral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data. The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in Figure 13.18. The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk (nStrobe). 13.1.5 Reverse-Idle Phase The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low. 13.1.6 Reverse Data Transfer Phase The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk. The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has been accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low when it has data to send. The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to accept a byte it sets HostAck (nALF) high to acknowledge the SMSC LPC47M172 Page 211 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet handshake. The peripheral then sets PeriphClk (nACK) high. After the host has accepted the data it sets HostAck (nALF) low, completing the transfer. This sequence is shown in Figure 13.19. 13.1.7 Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used in ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode (the control signals, by tradition, are specified as open-drain), the drivers are dynamically changed from open-drain to push-pull. The timing for the dynamic driver change is specified in then IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs. t6 t3 PD t1 t2 t5 nSTROBE t4 BUSY Figure 13.17 - Parallel Port FIFO Timing NAME t1 t2 t3 t4 t5 t6 Note 1: DESCRIPTION PDATA Valid to nSTROBE Active nSTROBE Active Pulse Width PDATA Hold from nSTROBE Inactive (Note 1) nSTROBE Active to BUSY Active BUSY Inactive to nSTROBE Active BUSY Inactive to PDATA Invalid (Note 1) MIN 600 600 450 TYP MAX UNITS ns ns ns ns ns ns 500 680 80 The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending. If no other data transfer is pending, the data is held indefinitely. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 212 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet t3 nALF t4 PD t2 t1 t7 nSTROBE BUSY t6 t5 t6 t8 Figure 13.18 - ECP Parallel Port Forward Timing NAME DESCRIPTION t1 nALF Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nALF Changed (Notes 1,2) t4 BUSY Deasserted to PDATA Changed (Notes 1,2) t5 nSTROBE Asserted to Busy Asserted t6 nSTROBE Deasserted to Busy Deasserted t7 BUSY Deasserted to nSTROBE Asserted (Notes 1,2) t8 BUSY Asserted to nSTROBE Deasserted (Note 2) Note 1: Note 2: MIN 0 0 80 TYP MAX 60 60 180 UNITS ns ns ns 80 0 0 80 80 180 200 180 ns ns ns ns ns Maximum value only applies if there is data in the FIFO waiting to be written out. BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. SMSC LPC47M172 Page 213 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet t2 PD t1 t5 nACK t4 nALF Figure 13.19 - ECP Parallel Port Reverse Timing NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nALF Deasserted to PDATA Changed t3 nACK Asserted to nALF Deasserted (Notes 1,2) t4 nACK Deasserted to nALF Asserted (Note 2) t5 nALF Asserted to nACK Asserted t6 nALF Deasserted to nACK Deasserted Note 1: MIN 0 0 80 TYP MAX UNITS ns ns ns t6 t3 t4 200 200 80 0 0 ns ns ns Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP can stall by keeping nALF low. nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. Note 2: SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 214 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet PCI_CLK t1 SER_IRQ Figure 13.20 - Setup and Hold Time NAME t1 t2 DESCRIPTION SER_IRQ Setup Time to PCI_CLK Rising SER_IRQ Hold Time to PCI_CLK Rising MIN 7 0 TYP MAX UNITS nsec nsec t2 Data Start TXD Data (5-8 Bits) t1 Parity Stop (1-2 Bits) Figure 13.21 - Serial Port Data NAME t1 Note 1: DESCRIPTION Serial Port Data Bit Time MIN TYP tBR1 MAX UNITS nsec tBR is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have percentage errors indicated in the “Baud Rate” table in the “Serial Port” section. SMSC LPC47M172 Page 215 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet KCLK/ MCLK t1 CLK CLK 1 2 t3 t4 t2 t6 CLK 9 CLK 10 CLK 11 t5 KDAT/ Start Bit MDAT Bit 0 Bit 7 Parity Bit Stop Bit Figure 13.22 - Keyboard/Mouse Receive/Send Data Timing NAME t1 DESCRIPTION Time from DATA transition to falling edge of CLOCK (Receive) Time from rising edge of CLOCK to DATA transition (Receive) Duration of CLOCK inactive (Receive/Send) Duration of CLOCK active (Receive/Send) Time to keyboard inhibit after clock 11 to ensure the keyboard does not start another transmission (Receive) Time from inactive to active CLOCK transition, used to time when the auxiliary device samples DATA (Send) MIN 5 TYP MAX 25 UNITS µsec t2 t3 t4 t5 t6 5 30 30 >0 5 T4-5 50 50 50 25 µsec µsec µsec µsec µsec SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 216 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet t1 t2 FAN_TACHx Figure 13.23 - Fan Tachometer Input Timing NAME t1 t2 t3 DESCRIPTION Pulse Time (1/2 Revolution Time=30/RPM) Pulse High Time Pulse Low Time MIN TYP 11.11 5.55 5.55 MAX UNITS µsec µsec µsec t3 t2 LED t1 Figure 13.24 - Power Led Output Timing NAME t1 t2 DESCRIPTION MIN TYP 1.49 0.59 MAX UNITS sec sec Period Blink ON Time SMSC LPC47M172 Page 217 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet 3.3V VCC/VTR 5V 3.3V VCC5V/V_5P0_STBY 5V 3.3V 2.95V (min) REF5V/REF5V_STBY Figure 13.25 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Up Before VCC5V/ V_5P0_STBY Note: The value 2.95V minimum in Figure 13.25 is (3.3 Supply Voltage – 350 mV). 3.3V VCC/VTR 5V VCC5V/V_5P0_STBY 5V REF5V/REF5V_STBY Figure 13.26 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Up Before VCC/VTR SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 218 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet VCC/VTR 3.3V VCC5V/V_5P0_STBY 5V REF5V/REF5V_STBY 5V Figure 13.27 - REF5V/REF5V_STBY Output When VCC/VTR Ramps Down Before VCC5V/ V_5P0_STBY VCC/VTR 3.3V VCC5V/V_5P0_STBY 5V 3.3V REF5V/REF5V_STBY 5V 3.3V 2.95V (min) Figure 13.28 - REF5V/REF5V_STBY Output When VCC5V/ V_5P0_STBY Ramps Down Before VCC/VTR Note: The value 2.95V minimum in Figure 13.28 is (3.3 Supply Voltage – 350 mV). SMSC LPC47M172 Page 219 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet A Tpropr Tpropf B Tr Tf Figure 13.29 - Rise, Fall and Propagation Timings Table 13.1 - nIDE_RSTDRV Timing NAME Tf DESCRIPTION (Refer to Figure 13.29) nIDE_RSTDRV (B) high to low fall time. Measured form 90% to 10% nIDE_RSTDRV (B) high to low propagation time. Measured from nPCI_RESET (A) to nIDE_RSTDRV (B). Output Capacitance Load Capacitance MIN TYP MAX 15 UNITS ns Tpropf CO CL 20 25 40 ns pF pF Table 13.2 - nPCIRST_OUT and nPCIRST_OUT2 Timing NAME Tr DESCRIPTION (Refer to Figure 13.29) nPCIRST_OUT/nPCIRST_OUT2 (B) low to high rise time. Measured form 10% to 90% nPCIRST_OUT/nPCIRST_OUT2 (B) low to high propagation time. Measured from nPCI_RESET (A) to nPCIRST_OUT/nPCIRST_OUT2 (B). Output Capacitance Load Capacitance Table 13.3 - PS_ON Timing NAME Tz Tf DESCRIPTION (Refer to Figure 13.29) nPS_ON (B) low to Hi-Z rise time. nPS_ON (B) high to low fall time. Measured form 90% to 10% nPS_ON (B) low to Hi-Z propagation time. Measured from nSLP_S3 (A) to nPS_ON (B). nPS_ON (B) high to low propagation time. Measured from nSLP_S3 (A) to nPS_ON (B). Output Capacitance Load Capacitance MIN TYP MAX 50 50 UNITS ns ns MIN TYP MAX 53 UNITS ns Tpropr 30 ns CO CL 25 40 pF pF Tpropz Tpropf CO CL 1 1 25 50 us us pF pF SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 220 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 13.4 - SCK_BJT_GATE Timing NAME Tf DESCRIPTION (Refer to Figure 13.29) SCK_BJT_GATE (B) low to high fall time. Measured form 90% to 10% SCK_BJT_GATE (B) high to low propagation time. Measured from PWRGD_3V (A) to SCK_BJT_GATE (B). Output Capacitance Load Capacitance Table 13.5 - PWRGD_3V Timing NAME Tr Tf DESCRIPTION (Refer to Figure 13.29) PWRGD_3V (B) low to high rise time. PWRGD_3V (B) low to high fall time. Measured form 90% to 10% PWRGD_3V (B) low to high propagation time. Measured from nFPRST (A) to PWRGD_3V (B). PWRGD_3V (B) high to low propagation time. Measured from nFPRST (A) to PWRGD_3V (B). Output Capacitance Load Capacitance MIN TYP MAX 50 50 UNITS ns ns MIN TYP MAX 50 UNITS ns Tpropf 1 us CO CL 25 50 pF pF Tpropr Tpropf CO CL 1 1 25 50 us us pF pF Table 13.6 - CNR CODEC Down Enable Timing NAME Tr DESCRIPTION (Refer to Figure 13.29) nCDC_DWN_RST (B) rise time. Measured from 10% to 90%. nCDC_DWN_RST (B) fall time. Measured from 90% to 10%. nCDC_DWN_RST (B) low to high propagation delay. Measured from nAUD_LNK_RST (A) or nCDC_DWN_ENAB (A) to nCDC_DWN_RST (B). nCDC_DWN_RST (B) high to low propagation delay. Measured from nAUD_LNK_RST (A) or nCDC_DWN_ENAB (A) to nCDC_DWN_RST (B). MIN TYP MAX UNITS us 6 6 15.3 Tf Tpropr us ns Tpropf 15.3 ns SMSC LPC47M172 Page 221 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet VTR (3.3V) t3 V_5P0_STBY Max Vtrip Min t4 t1 nRSMRST t2 Figure 13.30 - Reseme Reset Sequence Table 13.7 - Resume Reset Timing NAME t1 DESCRIPTION Treset delay. V_5P0_STBY active to nRSMRST inactive MIN 10 TYP 32 MAX 100 UNITS msec Notes 1 t2 t3 t4 VTRIP Note 1: Treset_fall. V_5P0_STBY inactive to nRSMRST active (Glitch width allowance) Treset_rise V_5P0_STBY active to VTR active V_5P0_STBY inactive to VTR inactive V_5P0_STBY low trip voltage 100 100 0 0 4.2 nsec nsec msec msec V 4.5 2 2 3 The nRSMRST will be inactive high max 100 msec after V_5P0_STBY is active assuming the VTR (3.3V) is active. If the VTR (3.3V) is not active within 100 msec, the delay from V_5P0_STBY will be greater than 100 msec and the nRSMRST will go inactive when VTR (3.3V) goes active. The V_5P0_STBY supply must power up before or simultaneous with VTR, and must power down simultaneous with or after VTR (from ICH2 data sheet) The trip point can vary between these limits on a per part basis, but on a given part it should remain relatively stable. Note 2: Note 3: SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 222 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 14 Package Outline Figure 14.1 - 128 Pin MQFP Package Outline, 14x20x2.7 Body, 3.2mm Footprint MIN ~ 0.05 2.55 23.00 19.90 17.00 13.90 0.09 0.73 ~ Table 14.1 - 128 Pin MQFP Package Parameters NOMINAL MAX REMARKS ~ 3.4 Overall Package Height ~ 0.5 Standoff ~ 3.05 Body Thickness 23.20 23.40 X Span 20.00 20.10 X body Size 17.20 17.40 Y Span 14.00 14.10 Y body Size ~ 0.20 Lead Frame Thickness 0.88 1.03 Lead Foot Length 1.60 ~ Lead Length 0.50 Basic Lead Pitch ~ 7o Lead Foot Angle ~ 0.30 Lead Width ~ ~ Lead Shoulder Radius ~ 0.30 Lead Foot Radius ~ 0.08 Coplanarity A A1 A2 D D1 E E1 H L L1 e θ W R1 R2 ccc Notes: 1. 2. 3. 4. 5. 0o 0.10 0.08 0.08 ~ Controlling Unit: millimeter. Tolerance on the position of the leads is ± 0.04 mm maximum. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC LPC47M172 Page 223 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 15 Board Test Mode Board level testing is implemented with an XOR Chain. The XOR chain testing allows motherboard manufacturers to check component connectivity (e.g., opens and shorts to VCC or GND). The TEST_EN pin is used as a strap pin to enter test mode. This pin has an internal 30 µA pull-down resistor to VSS. An external 10 kohm pull-up to V_3P3_STBY is used to put the device in test mode. Both VCC and VTR supplies are required for the device to operate properly in test mode. The part enters board test (XOR-chain) mode when the TEST_EN pin is brought high. The part remains in test mode while TEST_EN is high. Bringing TEST_EN low will exit test mode. When the XOR chain is entered, all output and bi-directional buffers within that chain are tri-stated, except for the XOR chain output. Every signal in the XOR chain (except for the XOR chain’s output) functions as an input. Figure 15.1 is a schematic example of XOR chain circuitry. VCC3 Input Pin 1 Input Pin 2 Input Pin 3 Input Pin 4 Input Pin 5 XOR Chain Output Figure 15.1 - Example XOR Chain Circuitry The XOR chain output is on pin 30, nDTR1/XOR. The input pin ordering is as follows: the first input pin in the XOR chain is pin 1 of the chip (MCLK), and the order continues around the chip in increasing pin number order to end at pin 128, skipping those pins that are excluded from the chain. The following pins are excluded from the XOR chain. nRSMRST pin (1) REF5V pin (1) REF5V_STBY pin (1) VCC pins (5) VTR pins (4) V_5P0_STBY pin (1) VSS pins (7) F_CAP pin (1) nDTR1/XOR pin (1) TEST_EN pin (1) The total number of pins excluded from the XOR chain is 23; therefore there are an odd number of pins in the XOR chain. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 224 SMSC LPC47M172 DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet XOR Chain Testability Algorithm Example An example algorithm for using the XOR chain for board test is shown below. Table 15.1 - XOR Test Pattern Example TEST VECTOR INPUT PIN 1 0 1 1 1 1 1 INPUT PIN 2 0 0 1 1 1 1 INPUT PIN 3 0 0 0 1 1 1 INPUT PIN 4 0 0 0 0 1 1 INPUT PIN 5 0 0 0 0 0 1 XOR OUTPUT 1 2 3 4 5 6 1 0 1 0 1 0 In this example, Vector 1 applies all "0s" to the chain inputs. The outputs being non-inverting, will consistently produce a "1" at the XOR output on a good board. One short to VCC (or open floating to VCC) will result in a "0" at the chain output, signaling a defect. Likewise, applying Vector 6 (all "1s") to the chain inputs (given that there is an odd number of input signals in the chain) will consistently produce a "0" at the XOR chain output on a good board. One short to VSS (or open floating to VSS) will result in a "1" at the chain output, signaling a defect. It is important to note that the number of inputs pulled to "1" will affect the chain output value. If the number of chain inputs pulled to "1" is even, then a "1" will be seen at the output. If the number of chain inputs pulled to "1" is odd, a "0" will be seen at the output. Continuing with the example in Table 15.1, as the input pins are driven to "1" across the chain in sequence, the XOR Output will toggle between "0" and "1." Any break in the toggling sequence (e.g., "1011") will identify the location of the short or open. SMSC LPC47M172 Page 225 SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DATASHEET Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 16 Reference Documents 1. 2. 3. 4. 5. 6. 7. 8. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997. Low Pin Count (LPC) Interface Specification, Revision 1.0, September 29, 1997, Intel Document. Metalious ACPI/Manageability Specification, v1.0, Aril 30, 1999 Advanced Configuration and Power Interface Specification, v 1.0 SMSC Application Note, AN 8-8: Using the Enhanced Keyboard and Mouse Wakeup Feature in SMSC Super I/O Parts. SMSC Application Note, AN 9-3: Application Considerations When Using the Powerdown Feature of SMSC Floppy Disk Controllers. SMSC/Non-SMSC Register Sets (Rev. 01-11-07) Page 226 SMSC LPC47M172 DATASHEET