LPC47N207

LPC47N207 LPC Super I/O IrDA Hot Docking Chip with UART PRODUCT FEATURES 3.3 Volt Operation (5V tolerant) Programmable Wakeup Event Interface (IO_PME# Pin) SMI Support (IO_SMI# Pin) GPIOs (16) — Programmable internal pull-up resistors Data Brief Infrared Communications Controller — IrDA v1.2 (4Mbps), HPSIR, ASKIR, Consumer IR Support — 2 IR Ports — 96 Base I/O Address, 15 IRQ Options and 3 DMA Options Two IRQ Input Pins XNOR Chain PC99a and ACPI 1.0 Compliant 64 PIN STQFP Lead-free RoHS Compliant Package Intelligent Auto Power Management One Full Function Serial Port — High Speed 16C550A Compatible UARTs with Send/Receive 16-Byte FIFOs — Supports 230k and 460k Baud — Programmable Baud Rate Generator — Modem Control Circuitry LPC Bus Host Interface — — — — — Multiplexed Command, Address and Data Bus 8-Bit I/O Transfers 8-Bit DMA Transfers 16-Bit Address Qualification Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems — PCI nCLKRUN Support — Power Management Event (IO_PME#) Interface Pin LPC PortSwitchTM Interface — Secondary Switchable LPC Interface (3.3V only) — Buffered 14 MHz output — Switched PCI Clock output SMSC LPC47N207 PRODUCT PREVIEW Revision 0.31 (09-21-06) LPC Super I/O IrDA Hot Docking Chip with UART ORDER NUMBER: LPC47N207-JV FOR 64 PIN, STQFP LEAD-FREE ROHS COMPLIANT PACKAGE 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © 2006 SMSC or its subsidiaries. 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All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. 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Revision 0.31 (09-21-06) PRODUCT PREVIEW 2 SMSC LPC47N207 LPC Super I/O IrDA Hot Docking Chip with UART General Description The SMSC LPC47N207 is a 3.3V PC 99 and ACPI 1.0 compliant Super I/O Controller. The LPC47N207 implements the LPC interface with the L PC PortSwitch ™ I nterface. T he L PC PortSwitch™ Interface is a hot-switchable external Docking LPC interface. The LPC47N207 also features a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI nCLKRUN support, relocatable configuration ports and three DMA channel options. The part also includes 16 GPIO pins. The LPC47N207 incorporates one 8-pin 16C550A compatible UART. In addition, the LPC47N207 provides a second UART to support a Serial Infrared Interface that complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR formats (used by Sharp and other PDAs), as well as Consumer IR. The LPC47N207 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. The LPC47N207 also features Software Configurable Logic (SCL) for ease of use. SCL allows programmable system configuration of key functions such as the UARTs. The LPC47N207 supports the ISA Plug-and-Play Standard register set (Version 1.0a) and provides the recommended functionality to support Windows ‘9x, 2K, ME, XP and PC99. The I/O Address, DMA Channel and Hardware IRQ of each device in the LPC47N207 may be reprogrammed through the internal configuration registers. There are 192 I/O address location options, a Serialized IRQ interface, and three DMA channels. Block Diagram nIO_SMI* SIO_14M nIO_PME SIO_14M LAD[3:0] LFRAME# LDRQ0# LDRQ1# PCI_RESET# LPCPD# nCLKRUN PCI_CLK SER_IRQ nIO_PME LPC_CLK_33 CLOCK GEN SMI PME WDT HOST LPC BUS INTERFACE CONTROL, ADDRESS, DATA GENERAL PURPOSE I/O DOCKING LPC SWITCHES BUFFERS AND CONTROL GP30-GP37 GP10-GP11 GP15-GP17 GP12*, GP13*, GP14*, CONFIGURATION REGISTERS ACPI BLOCK IRQIN1*, IRQIN2*, DSIO_14M DLAD[3:0] DLFRAME# DLDRQ1# nDCLKRUN DLPC_CLK_33 DSER_IRQ DOCK LPC BUS INTERFACE (UART1) 16C550 COMPATIBLE SERIAL PORT 1 16C550 COMPATIBLE 2 PIN INFRARED INTERFACE SERIAL PORT TXD1, nRTS1, nDTR1 nCTS1, RXD1, nDSR1, nDCD1, nRI1 IRTX2, IRMODE* VTR Vcc Vss IRRX2, IRRX3*, Figure 1 Block Diagram SMSC LPC47N207 3 Revision 0.31 (09-21-06) PRODUCT PREVIEW LPC Super I/O IrDA Hot Docking Chip with UART Package Outline Figure 2 64-pin STQFP Package Outline Table 1 64-pin STQFP Package Parameters A A1 A2 D D1 E E1 H L L1 e ∂ W ccc MIN ~ 0.05 1.35 8.80 6.80 8.80 6.80 0.09 0.45 ~ 0o 0.13 ~ NOMINAL ~ ~ 1.40 9.00 7.00 9.00 7.00 ~ 0.60 1.00 REF. 0.40 Basic ~ 0.18 ~ MAX 1.60 0.15 1.45 9.20 7.20 9.20 7.20 0.20 0.75 ~ 7o 0.23 0.08 REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Coplanarity Notes: 1. Controlling Unit: millimeter. 2. Tolerance on the true position of the leads is ± 0.035 mm maximum. 3. Package body dimensions D1 and E1 do not include the mold protrusion. 4. Maximum mold protrusion is 0.25 mm per side. D1 and E1 dimensions determined at datum plane H. 5. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 6. Details of pin 1 identifier are optional but must be located within the zone indicated. Revision 0.31 (09-21-06) PRODUCT PREVIEW 4 SMSC LPC47N207