LPC47N227

LPC47N227 100 Pin Super I/O with LPC Interface for Notebook Applications FEATURES 3.3 Volt Operation (5V Tolerant) PC99 and ACPI 1.0b Compliant Programmable Wakeup Event Interface (nIO_PME Pin) SMI Support (nIO_SMI Pin) GPIOs (29) Two IRQ Input Pins XNOR Chain Intelligent Auto Power Management 2.88MB Super I/O Floppy Disk Controller Licensed CMOS 765B Floppy Disk Controller Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core Supports One Floppy Drive Directly Configurable Open Drain/Push-Pull Output Drivers Supports Vertical Recording Format 16-Byte Data FIFO 100% IBM Compatibility Detects All Overrun and Underrun Conditions Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption DMA Enable Logic Data Rate and Drive Control Registers Swap Drives A and B Non-Burst Mode DMA Option 48 Base I/O Address, 15 IRQ and 3 DMA Options Forceable Write Protect and Disk Change Controls Floppy Disk Available on Parallel Port Pins (ACPI Compliant) Enhanced Digital Data Separator 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates Programmable Precompensation Modes Serial Ports Two Full Function Serial Ports High Speed NS16C550 Compatible UARTs with Send/Receive 16-Byte FIFOs Supports 230k and 460k Baud Programmable Baud Rate Generator Modem Control Circuitry Infrared Communications Controller IrDA v1.2 (4Mbps), HPSIR, ASKIR, Consumer IR Support 2 IR Ports 96 Base I/O Address, 15 IRQ Options and 3 DMA Options Multi-Mode Parallel Port with ChiProtect Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port Enhanced Parallel Port (EPP) Compatible EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) IEEE 1284 Compliant Enhanced Capabilities Port (ECP) ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On 192 Base I/O Address, 15 IRQ and 3 DMA Options LPC Bus Host Interface Multiplexed Command, Address and Data Bus 8-Bit I/O Transfers 8-Bit DMA Transfers 16-Bit Address Qualification Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems PCI nCLKRUN Support Power Management Event (nIO_PME) Interface Pin 100 Pin TQN, lead-free RoHS compliant package and 100 Pin STQN, lead-free RoHS compliant package - GENERAL DESCRIPTION The SMSC LPC47N227 is a 3.3V PC 99 and ACPI 1.0b compliant Super I/O Controller. The LPC47N227 implements the LPC interface, a pin reduced ISA interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. The part also includes 29 GPIO pins. The LPC47N227 incorporates SMSC’s true CMOS 765B floppy disk controller, advanced digital data separator, 16byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support and one floppy direct drive support. The LPC47N227 does not require any external filter components, is easy to use and offers lower system cost and reduced board area. The LPC47N227 is software and register compatible with SMSC’s proprietary 82077AA core. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and provides data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC’s patented data SMSC DB – LPC47N227 Page 1 Rev. 03-29-07 PRODUCT PREVIEW 100 Pin Super I/O with LPC Interface for Notebook Applications separator technology allowing for ease of testing and use. The LPC47N227 supports both 1Mbps and 2Mbps data rates and vertical recording operation at 1Mbps Data Rate. The LPC47N227 also features a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI nCLKRUN support, relocatable configuration ports and three DMA channel options. Both on-chip UARTs are compatible with the NS16C550. One UART includes additional support for a Serial Infrared Interface that complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR formats (used by Sharp and other PDAs), as well as Consumer IR. The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and ECP. The parallel port ChiProtect circuitry prevents damage caused by an attached powered printer when the LPC47N227 is not powered. The LPC47N227 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. The LPC47N227 also features Software Configurable Logic (SCL) for ease of use. SCL allows programmable system configuration of key functions such as the FDC, parallel port, and UARTs. The LPC47N227 supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the recommended functionaity to support Windows ‘95/’98 and PC99. The I/O Address, DMA Channel and Hardware IRQ of each device in the LPC47N227 may be reprogrammed through the internal configuration registers. There are 192 I/O address location options, a Serialized IRQ interface, and three DMA channels. ORDERING INFORMATION Order Numbers: LPC47N227-MT for 100 Pin TQN, Lead-free RoHS Compliant Package LPC47N227-MV for 100 Pin STQN, Lead-free RoHS Compliant Package 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Rev. 03-29-07 Page 2 SMSC DB – LPC47N227 PRODUCT PREVIEW 100 Pin Super I/O with LPC Interface for Notebook Applications BLOCK DIAGRAM nIO_SMI* nIO_PME SMI PME WDT MULTI-MODE PARALLEL PORT/FDC MUX PD[0:7], BUSY, SLCT, PE, nERROR, nACK nSLCTIN, nALF nINIT, nSTROBE GP10, GP11, GP12*, GP13*, GP14*, GP1[5:7], GP2[0:2], GP23*, GP24, GP3[0:7], GP4[0:7] IRQIN1*, IRQIN2*, FDC_PP* CONTROL, ADDRESS, DATA GENERAL PURPOSE I/O SER_IRQ PCI_CLK LAD0 LAD1 LAD2 LAD3 nLFRAME nLDRQ nPCI_RESET nLPCPD nCLKRUN SERIAL IRQ CONFIGURATION REGISTERS ACPI BLOCK TXD1, nRTS1, nDTR1 LPC BUS INTERFACE WDATA SMSC DIGITAL PROPRIETARY WCLOCK DATA 82077 SEPERATOR COMPATIBLE PREVERTICAL COMPENSATION FLOPPY DISK CONTROLLER RCLOCK CORE RDATA 16C550 COMPATIBLE SERIAL PORT 1 nCTS1, RXD1, nDSR1, nDCD1, nRI1 IRTX2, IRMODE*, TXD2, nRTS2, nDTR2 IRRX2, IRRX3*, RXD2, nCTS2, nDSR2, nDCD2, nRI2 CLOCK GEN 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED INTERFACE V TR Vcc Vss CLOCKI nMTR0, nDS0, nDIR, nTRK0, nSTEP, DRVDEN0*, nDSKCHG, nWGATE, HDSEL, nINDEX, DRVDEN1*, nWDATA nWRTPRT, nRDATA nWDATA nRDATA * Denotes Multifunction Pins SMSC DB – LPC47N227 Page 3 Rev. 03-29-07 PRODUCT PREVIEW 100 Pin Super I/O with LPC Interface for Notebook Applications PACKAGE OUTLINES FIGURE 1 – 100 PIN TQN LEAD-FREE PACKAGE OUTLINE MIN ~ 0.05 1.35 15.80 7.90 13.90 15.80 7.90 13.90 ~ 0.45 ~ 0o ~ ~ ~ ~ ~ NOMINAL ~ ~ 1.40 16.00 8.00 14.00 16.00 8.00 14.00 ~ 0.60 1.00 0.50 Basic ~ 0.25 0.20 0.20 ~ ~ MAX 1.60 ~ 1.45 16.20 8.10 14.10 16.20 8.10 14.10 0.20 0.75 ~ 8o ~ ~ ~ 0.0762 0.08 REMARK Overall Package Height Standoff Body Thickness X Span 1 /2 X Span Measure from Centerline X body Size Y Span 1 /2 Y Span Measure from Centerline Y body Size Lead Frame Thickness Lead Foot Length from Centerline Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity (Assemblers) Coplanarity (Test House) A A1 A2 D D/2 D1 E E/2 E1 H L L1 e θ W R1 R2 ccc ccc Notes: 1 Controlling Unit: millimeter 2 Tolerance on the position of the leads is ± 0.04 mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane is 0.781.08 mm. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. 6 Shoulder widths must conform to JEDEC MS-026 dimension 'S' of a minimum of 0.20mm. Rev. 03-29-07 Page 4 SMSC DB – LPC47N227 PRODUCT PREVIEW 100 Pin Super I/O with LPC Interface for Notebook Applications (ddd) FIGURE 2 – 100 PIN STQN LEAD-FREE PACKAGE OUTLINE MIN ~ 0.05 1.35 13.80 6.90 11.80 13.80 6.90 11.80 0.09 0.45 ~ 0o 0.13 0.08 0.08 ~ ~ ~ NOMINAL ~ ~ 1.40 14.00 7.00 12.00 14.00 7.00 12.00 ~ 0.60 1.00 0.40 Basic 3.5o 0.16 ~ ~ ~ ~ ~ MAX 1.60 0.15 1.45 14.20 7.10 12.20 14.20 7.10 12.20 0.20 0.75 ~ 7o 0.23 ~ 0.20 .0762 0.08 0.035 REMARK Overall Package Height Standoff Body Thickness X Span 1 /2 X Span Measure from Centerline X body Size Y Span 1 /2 Y Span Measure from Centerline Y body Size Lead Frame Thickness Lead Foot Length from Centerline Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity (Assemblers) Coplanarity (Test House) True Position Spread (Bent Leads) A A1 A2 D D/2 D1 E E/2 E1 H L L1 e θ W R1 R2 ccc ccc ddd Notes: 1 Controlling Unit: millimeter 2 Minimum space between protrusion and an adjacent lead is .007 mm. 3 Details of pin 1 identifier are optional but must be located within the zone indicated. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5 Shoulder widths must conform to JEDEC MS-026 dimension 'S' of a minimum of 0.20mm. SMSC DB – LPC47N227 Page 5 Rev. 03-29-07 PRODUCT PREVIEW