USB2502
2-Port USB 2.0 Hub Controller
PRODUCT FEATURES
Integrated USB 2.0 Compatible 2-Port Hub
— High-Speed (480Mbits/s), Full-Speed (12Mbits/s) and Low-Speed (1.5Mbits/s) compatible — Full power management with ganged power control — Detects Bus-Power/Self-Power source and changes mode automatically
Datasheet On-Board 24MHz Crystal Driver Circuit or 24 MHz external clock driver Internal PLL for 480MHz USB 2.0 Sampling Internal 1.8V Linear Voltage Regulator Integrated USB termination and Pull-up/Pull-down resistors Internal Short Circuit protection of USB differential signal pins Basic single-color LED support 1.8 Volt Low Power Core Operation 3.3 Volt I/O with 5V Input Tolerance 36 Pin QFN or 48 Pin TQFP lead-free RoHS compliant package
Complete USB Specification 2.0 Compatibility
— Includes USB 2.0 Transceivers
VID/PID/DID, and Port Configuration for Hub via:
— Single Serial I2C EEPROM — SMBus Slave Port
Default VID/PID/DID, allows functionality when configuration EEPROM is absent Hardware Strapping options allow for configuration without an external EEPROM or SMBus Host
SMSC USB2502
DATASHEET
Revision 2.1 (12-06-06)
2-Port USB 2.0 Hub Controller Datasheet
ORDER NUMBERS: USB2502-AEZG FOR 36 PIN LEAD-FREE ROHS COMPLIANT QFN PACKAGE; USB2502-HT FOR 48 PIN LEAD-FREE ROHS COMPLIANT TQFP PACKAGE
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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2-Port USB 2.0 Hub Controller Datasheet
Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 OEM Selectable Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2 Pin Table 2-Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 3 Pin Configuration 2-Port Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 4 2-Port Hub Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 5 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 5.2 2-Port Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Hub Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 VBus Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 In-Circuit EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 EEPROM DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Bus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Invalid Protocol Response Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 General Call Address Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Slave Device Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 Stretching the SCLK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.6 SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.7 Bus Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.8 SMBus Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.9 Internal SMBus Memory Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Configuration Option: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Strapping Options: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 External Hardware RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 USB Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 18 19 19 19 19 24 24 25 25 26 26 26 26 26 26 32 32 32 33 36
5.3
5.4 5.5 5.6
Chapter 6 XNOR Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chapter 7 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.1 7.2 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 8 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1 Oscillator/Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 SMBus Interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2 I2C EEPROM: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3 USB 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 42 42
Chapter 9 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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List of Tables
Table 2.1 Table 2.2 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 4.5 Table 5.1 Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Table 5.7 Table 7.1 Table 9.1 2-Port Pin Table for 36-QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-Port Pin Table for 48-TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2-Port Hub Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SMBus or EEPROM Interface Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power, Ground, and No Connect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 User-Defined Descriptor Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SMBus Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SMBus Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SMBus Slave Interface Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Reset_N Timing for Default/Strap Option Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset_N Timing for EEPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset_N Timing for SMBus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 48 Pin TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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List of Figures
Figure 3.1 Figure 3.2 Figure 4.1 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 9.1 Figure 9.2 2-Port 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2-Port 48-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2-Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LED Strapping Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset_N Timing for Default/Strap Option Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset_N Timing for EEPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset_N Timing for SMBus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 48 Pin TQFP Package Outline (7x7x1.4 mm body, 2mm Footprint) . . . . . . . . . . . . . . . . . . . 44
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Chapter 1 General Description
The SMSC 2-Port Hub is fully compliant with the USB 2.0 Specification and will attach to a USB host as a Full-Speed Hub or as a Full-/High-Speed Hub. The 2-Port Hub supports Low-Speed, Full-Speed, and High-Speed (if operating as a High-Speed Hub) downstream devices on all of the enabled downstream ports. The Hub works with an external USB power distribution switch device to control VBUS switching to downstream ports, and to limit current and sense over-current conditions. All required resistors on the USB ports are integrated into the Hub. This includes all series termination resistors on D+ and D– pins and all required pull-down and pull-up resistors on D+ and D– pins. The over-current sense inputs for the downstream facing ports have internal pull-up resistors. Throughout this document the upstream facing port of the hub will be referred to as the upstream port, and the downstream facing ports will be called the downstream ports.
1.1
OEM Selectable Features
A default configuration is available in the USB2502 following a reset. This configuration may be sufficient for some applications. Strapping option pins make it possible to modify a limited sub-set of the configuration options. The USB2502 may also be configured by an external EEPROM or a microcontroller. When using the microcontroller interface, the Hub appears as an SMBus slave device. If the Hub is pin-strapped for external EEPROM configuration but no external EEPROM is present, then a value of ‘0’ will be written to all configuration data bit fields (the hub will attach to the host with all ‘0’ values). The 2-Port Hub supports several OEM selectable features: Operation as a Self-Powered USB Hub or as a Bus-Powered USB Hub. Operation as a Dynamic-Powered Hub (Hub operates as a Bus-Powered device if a local power source is not available and switches to Self-Powered operation when a local power source is available). Optional OEM configuration via I2C EEPROM or via the industry standard SMBus interface from an external SMBus Host. Compound device support (port is permanently hardwired to a downstream USB peripheral device). Hardware strapping options enable configuration of the following features. Non-Removable Ports Port Power Polarity (active high or active low logic)
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Chapter 2 Pin Table 2-Port
Table 2.1 2-Port Pin Table for 36-QFN UPSTREAM USB 2.0 INTERFACE (3 PINS) USBDP0 USBDN0 VBUS_DET
2-PORT USB 2.0 INTERFACE (10 PINS) USBDP1 GR1/ NON_REM0 PRTPWR USBDN1 GR2/ NON_REM1 OCS_N SERIAL PORT INTERFACE (3 PINS) SDA/SMBDATA SCL/SMBCLK/ CFG_SEL0 MISC (7 PINS) XTAL1/CLKIN ATEST/ REG_EN XTAL2 CLKIN_EN RESET_N TEST SELF_PWR CFG_SEL1 USBDP2 PRTPWR_POL USBDN2 RBIAS
POWER, GROUND (13 PINS)
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Table 2.2 2-Port Pin Table for 48-TQFP UPSTREAM USB 2.0 INTERFACE (3 PINS) USBDP0 USBDN0 VBUS_DET
2-PORT USB 2.0 INTERFACE (10 PINS) USBDP1 GR1/ NON_REM0 PRTPWR USBDN1 GR2/ NON_REM1 OCS_N SERIAL PORT INTERFACE (3 PINS) SDA/SMBDATA SCL/SMBCLK CFG_SEL0 MISC (7 PINS) XTAL1/CLKIN ATEST/ REG_EN XTAL2 CLKIN_EN RESET_N TEST SELF_PWR CFG_SEL1 USBDP2 PRTPWR_POL USBDN2 RBIAS
POWER, GROUND AND NO CONNECT (25 PINS)
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Chapter 3 Pin Configuration 2-Port Hub
SCL/SMBCLK/CFG_SEL0 20
21
23
22
25
26
24
27
VDD33CR VSS XTAL2 XTAL1/CLKIN VDDA18PLL VDDA33PLL ATEST/REG_EN RBIAS VSS
28 29 30 31 32 33 34 35 36
1 4 3 5 7 2 6 8 9
19
SDA/SMBDATA
VBUS_DET
VDD18
RESET_N
VSS
CLKIN_EN
TEST
CFG_SEL1
18 17 16
VDD18 VSS SELF_PWR OCS_N PRTPWR PRTPWR_POL GR2/NON_REM1 GR1/NON_REM0 VSS
SMSC USB2502 (Top View QFN-36)
Thermal Slug (must be connected to VSS)
15 14 13 12 11 10
VDDA33
VSS
USBDN0
USBDN1
VDDA33
Indicates pins on the bottom of the device.
Figure 3.1 2-Port 36-Pin QFN
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USBDN2
USBDP0
USBDP1
USBDP2
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Figure 3.2 2-Port 48-Pin TQFP
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Chapter 4 2-Port Hub Block Diagram
VBUS
Upstream USB Data 3.3V
24 MHz Crystal
To EEPROM or SMBus Master 1.8V SD SCK
PLL Bus-Power Upstream PHY 1.8V Reg
Serial Interface
Repeater
SIE
Controller
Transaction Translator
Port Controller
Routing Logic
Downstream PHY #1
OC Sense Switch Driver LED Driver Strapping Options
Downstream PHY #2
Downstream USB Data
OC Sense
Switch/LED Driver/optís
Downstream USB Data
Figure 4.1 2-Port Block Diagram Table 4.1 2-Port Hub Pin Descriptions NAME SYMBOL TYPE UPSTREAM USB 2.0 INTERFACE FUNCTION
USB Bus Data Detect Upstream VBUS Power
USBDN0 USBDP0 VBUS_DET
IO-U I/O8
These pins connect to the upstream USB bus data signals. Detects state of Upstream VBUS power. The SMSC Hub monitors VBUS_DET to determine when to assert the internal D+ pull-up resistor (signalling a connect event). When designing a detachable hub, this pin must be connected to the VBUS power pin of the USB port that is upstream of the hub. (Use of a weak pull-down resistor is recommended.) For self-powered applications with a permanently attached host, this pin must be pulled-up to either 3.3V or 5.0V (typically VDD33).
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Table 4.1 2-Port Hub Pin Descriptions (continued) NAME SYMBOL TYPE 2-PORT USB 2.0 HUB INTERFACE FUNCTION
High-Speed USB Data USB Power Enable
USBDN[2:1] USBDP[2:1] PRTPWR
IO-U O8
These pins connect to the downstream USB peripheral devices attached to the Hub’s ports. Enables power to USB peripheral devices (downstream). The active signal level of the PRTPWR pin is determined by the Power Polarity Strapping function of the PRTPWR_POL pin.
Port [2:1] Green LED & Port NonRemovable strapping option.
GR[2:1]/ NON_REM[1:0]
I/O8
Green indicator LED for ports 2 and 1. Will be active low when LED support is enabled via EEPROM or SMBus. If the hub is configured by the internal default configuration, these pins will be sampled at the rising edge of RESET_N (see the applicable RESET_N timing table in Section 5.6.1) to determine if ports [2:1] contain permanently attached (non-removable) devices. Also, the active state of the LED’s will be determined as follows: NON_REM[1:0] = ‘00’, All ports are removable, GR2 is active high, GR1 is active high. NON_REM1:0] = ‘01’, Port 1 is non-removable, GR2 is active high, GR1 is active low. NON_REM[1:0] = ‘10’, Ports 1 & 2 are non-removable, GR2 is active low, GR1 is active high. NON_REM[1:0] = ‘11’, Ports 1 & 2 are non-removable, GR2 is active low, GR1 is active low.
Port Power Polarity strapping.
PRTPWR_POL
I/O8
Port Power Polarity strapping determination for the active signal polarity of the PRTPWR pin. While RESET_N is asserted, the logic state of this pin will (though the use of internal combinatorial logic) determine the active state of the PRTPWR pin in order to ensure that downstream port power is not inadvertently enabled to inactive ports during a hardware reset. On the rising edge of RESET_N (see the applicable RESET_N timing table in Section 5.6.1), the logic value will be latched internally, and will retain the active signal polarity for the PRTPWR pin. ‘1’ = PRTPWR pin has an active ‘high’ polarity ‘0’ = PRTPWR pin has an active ‘low’ polarity
Over Current Sense USB Transceiver Bias
OCS_N
IPU
Input from external current monitor indicating an overcurrent condition. {Note: Contains internal pull-up to 3.3V supply} A 12.0kΩ (+/− 1%) resistor is attached from ground to this pin to set the transceiver’s internal bias settings.
RBIAS
I-R
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Table 4.1 2-Port Hub Pin Descriptions (continued) NAME SYMBOL TYPE SERIAL PORT INTERFACE FUNCTION
Serial Data/SMB Data Serial Clock/SMB Clock & Config Select 0 Configuration Programming Select
SDA/SMBDATA SCL/SMBCLK/ CFG_SEL0
IOSD12 IOSD12
(Serial Data)/(SMB Data) signal. (Serial Clock)/(SMB Clock) signal. This multifunction pin is read on the rising edge of RESET_N (see the applicable RESET_N timing table in Section 5.6.1) and will determine the hub configuration method as described in Table 4.2. This pin is read on the rising edge of RESET_N (see the applicable RESET_N timing table in Section 5.6.1) and will determine the hub configuration method as described in Table 4.2.
CFG_SEL1
I
Table 4.2 SMBus or EEPROM Interface Behavior
CFG_SEL1 0 0 1 1
CFG_SEL0 0 1 0 1
SMBus or EEPROM interface behavior. Reserved Configured as an SMBus slave for external download of userdefined descriptors. SMBus slave address is 0101100 Internal Default Configuration via strapping options. 2-wire (I2C) EEPROMS are supported,
Table 4.3 Miscellaneous Pins NAME SYMBOL TYPE FUNCTION
Crystal Input/External Clock Input Crystal Output
XTAL1/ CLKIN XTAL2
ICLKx
24MHz crystal or external clock input. This pin connects to either one terminal of the crystal or to an external 24MHz clock when a crystal is not used. 24MHz Crystal This is the other terminal of the crystal, or left unconnected when an external clock source is used to drive XTAL1/CLKIN. It must not be used to drive any external circuitry other than the crystal circuit. Clock In Enable: Low = XTAL1 and XTAL2 pins configured for use with external crystal High = XTAL1 pin configured as CLKIN, and must be driven by an external CMOS clock. This active low signal is used by the system to reset the chip. The minimum active low pulse is 1us. Detects availability of local self-power source. Low = Self/local power source is NOT available (i.e., Hub gets all power from Upstream USB VBus). High = Self/local power source is available. Used for testing the chip. User must treat as a noconnect or connect to ground.
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OCLKx
Clock Input Enable
CLKIN_EN
I
RESET Input Self-Power / Bus-Power Detect TEST Pin
RESET_N SELF_PWR
IS I
TEST
IPD
SMSC USB2502
DATASHEET
2-Port USB 2.0 Hub Controller Datasheet
Table 4.3 Miscellaneous Pins (continued) NAME SYMBOL TYPE FUNCTION
Analog Test & Internal 1.8V voltage regulator enable
ATEST/ REG_EN
AIO
This signal is used for testing the analog section of the chip, and to enable or disable the internal 1.8v regulator. This pin must be connected to VDDA33 to enable the internal 1.8V regulator, or to VSS to disable the internal regulator. When the internal regulator is enabled, the 1.8V power pins must be left unconnected, except for the required bypass capacitors.When the PHY is in test mode, the internal regulator is disabled and the ATEST pin functions as a test pin.
Table 4.4 Power, Ground, and No Connect NAME SYMBOL TYPE FUNCTION
VDDCORE3P3
VDD33CR
+3.3V I/O Power. If the internal core 1.8V regulator is enabled, then this pin acts as the regulator input
VDD1P8
VDD18
+1.8V core power. If the internal regulator is enabled, then VDD18 pin 27 must have a 4.7μF (or greater) ±20% (ESR