USB97C201

USB97C201 Rev 1.6 USB 2.0 ATA/ ATAPI Controller FEATURES 2.5 Volt, Low Power Core Operation 3.3 Volt I/O with 5V input tolerance Complete USB Specification 2.0 Compatibility Includes USB 2.0 Transceiver A Bi-directional Control, a Bi-directional Interrupt, and a Bi-directional Bulk Endpoint are provided. Complete System Solution for interfacing ATA or ATAPI devices to USB 2.0 bus Supports USB Mass Storage Compliant Bootable BIOS Support for ATAPI Devices: CD-ROM CD-R CD-RW DVD DVD/R/W 8051 8 bit microprocessor Provides low speed control functions 30 Mhz execution speed at 4 cycles per instruction average 768 Bytes of internal SRAM for general purpose scratchpad or program execution while re-flashing external ROM Double Buffered Bulk Endpoint Bi-directional 512 Byte Buffer for Bulk Endpoint 64 Byte RX Control Endpoint Buffer 64 Byte TX Control Endpoint Buffer 64 Byte TX Interrupt Endpoint Buffer 64 Byte RX Interrupt Endpoint Buffer External Program Memory Interface 64K Byte Code Space - Flash, SRAM, or EPROM Memory On Board 12Mhz Crystal Driver Circuit Internal PLL for 480Mhz USB2.0 Sampling, 30Mhz MCU clock, and 60Mhz ATA clock Supports firmware upgrade via USB bus if “boot block” Flash program memory is used 8 GPIOs for special function use : LED indicators, button inputs, etc. Inputs capable of generating interrupts with either edge sensitivity One GPIO has automatic ½ sec toggle capability for flashing an LED indicator. 100 Pin TQFP Package (14.0 x 14.0 mm footprint) 25% smaller body size than other 100 pin TQFP Packages 100 Pin QFP Package ORDERING INFORMATION Order Number(s): USB97C201-MN for 100 pin TQFP package USB97C201-MC for 100 pin QFP package SMSC USB97C201 Page 1 Rev. 11-05-03 DATASHEET © STANDARD MICROSYSTEMS CORPORATION (SMSC) 2003 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Standard Microsystems and SMSC are registered trademarks of Standard Microsystems Corporation. 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SMSC USB97C201 Page 2 Rev. 11-05-03 DATASHEET TABLE OF CONTENTS 1.0 2.0 3.0 GENERAL DESCRIPTION ..............................................................................................................................6 PIN TABLE ......................................................................................................................................................7 PIN CONFIGURATION....................................................................................................................................8 3.1 4.0 5.0 QFP/TQFP 100 Pin.......................................................................................................................... 8 BLOCK DIAGRAM ..........................................................................................................................................9 PIN DESCRIPTIONS .....................................................................................................................................10 5.1 6.0 BUFFER TYPE DESCRIPTIONS .................................................................................................. 13 FUNCTIONAL BLOCK DESCRIPTIONS ......................................................................................................14 6.1 MCU ............................................................................................................................................... 14 6.1.1 MCU Memory Map: Code Space............................................................................................... 14 6.1.2 MCU Memory Map: XData Space ............................................................................................. 15 6.1.3 MCU Block Register Summary.................................................................................................. 16 6.1.4 MCU Register Descriptions ....................................................................................................... 19 6.2 SIE Block....................................................................................................................................... 42 6.2.1 Autonomous USB Protocol........................................................................................................ 43 6.2.2 USB Events ............................................................................................................................... 43 6.2.3 Standard Device Requests........................................................................................................ 44 6.2.4 SIE Configurations..................................................................................................................... 44 6.3 IDE Controller Description .......................................................................................................... 45 6.3.1 IDE Configurations..................................................................................................................... 45 6.3.2 PIO IDE Operations ................................................................................................................... 45 6.3.3 PIO IDE Data Prefetching and Posting...................................................................................... 46 6.3.4 DMA Transfers........................................................................................................................... 46 6.3.5 Ultra ATA/66 Synchronous DMA Operation .............................................................................. 46 6.3.6 Ultra ATA/66 Operation ............................................................................................................. 47 6.4 SRAM Buffers ............................................................................................................................... 48 6.5 8051 Options................................................................................................................................. 48 6.6 Address Multiplexing................................................................................................................... 48 6.7 SRAM Time Multiplexer Operation ............................................................................................. 49 6.7.1 Phase 0 (Ø0) ............................................................................................................................. 49 6.7.2 Phase 1 (Ø1) ............................................................................................................................. 49 6.7.3 Phase 2 (Ø2) ............................................................................................................................. 49 6.7.4 Phase 3 (Ø3) ............................................................................................................................. 50 6.8 EP2 SRAM Buffer Operation ....................................................................................................... 50 6.9 EP2 Automatic Buffer Operations .............................................................................................. 50 6.9.1 Receive Auto-Toggle ................................................................................................................. 50 6.9.2 Transmit Buffer Operation ......................................................................................................... 52 6.9.3 Automatic Transfer Operation ................................................................................................... 52 7.0 8.0 DC PARAMETERS........................................................................................................................................54 AC SPECIFICATIONS...................................................................................................................................56 8.1 8.2 9.0 10.0 ATA/ATAPI .................................................................................................................................... 56 USB2.0 Timing.............................................................................................................................. 56 PACKAGING .................................................................................................................................................57 USB97C201 REVISIONS ..............................................................................................................................59 SMSC USB97C201 Page 3 Rev. 11-05-03 DATASHEET TABLES Table 1 - USB97C201 Buffer Type Descriptions ..........................................................................................................13 Table 2 - MCU Code Memory Map ..............................................................................................................................14 Table 3 - MCU XData Memory Map .............................................................................................................................15 Table 4 - MCU Block Register Summary......................................................................................................................16 Table 5 - 8051 Core SFR Register Summary...............................................................................................................18 Table 6 - Interrupt 0 Source Register ...........................................................................................................................19 Table 7 - Interrupt 0 Mask ............................................................................................................................................20 Table 8 - Interrupt 1 Source Register ...........................................................................................................................20 Table 9 - Interrupt 1 Mask ............................................................................................................................................21 Table 10 - Device Revision Register ............................................................................................................................21 Table 11 - Device Identification Register......................................................................................................................21 Table 12 - GPIO Direction Register..............................................................................................................................22 Table 13 - GPIO Output Register .................................................................................................................................24 Table 14 - GPIO Input Register....................................................................................................................................24 Table 15 – GPIO Interrupt Status Register (INT4) .......................................................................................................24 Table 16 – GPIO Interrupt Mask Register ....................................................................................................................25 Table 17 - Utility Configuration Register.......................................................................................................................26 Table 18 – SRAM Data Port Register ..........................................................................................................................26 Table 19 – SRAM Address Register 1 .........................................................................................................................27 Table 20 – SRAM Address Register 2 .........................................................................................................................27 Table 21 - MCU Clock Source Select...........................................................................................................................27 Table 22 - Wakeup Source 1 Register (INT2) ..............................................................................................................28 Table 23 - Wakeup Mask 1 Register ............................................................................................................................28 Table 24 –USB Address Register ................................................................................................................................29 Table 25 – SIE Configuration Register .........................................................................................................................29 Table 26 - USB Bus Status Register ............................................................................................................................30 Table 27 – USB Bus Status Mask Register..................................................................................................................30 Table 28 – SIE Status Register ....................................................................................................................................31 Table 29 – SIE Status Mask Register ..........................................................................................................................31 Table 30 – USB Configuration Number Register..........................................................................................................32 Table 31 – Endpoint 0 Receive Control Register .........................................................................................................32 Table 32 – Endpoint 0 Transmit Control Register ........................................................................................................32 Table 33 – Endpoint 1 Receive Control Register .........................................................................................................32 Table 34 – Endpoint 1 Transmit Control Register ........................................................................................................33 Table 35 – Endpoint 2 Control Register .......................................................................................................................33 Table 36 – Endpoint 0 Receive Byte Count Register ...................................................................................................34 Table 37 – Endpoint 0 Transmit Byte Count Register ..................................................................................................35 Table 38 – Endpoint 1 Receive Byte Count Register ...................................................................................................35 Table 39 – Endpoint 1 Transmit Byte Count Register ..................................................................................................35 Table 40 – RAM Buffer Write Byte Count Register A1 .................................................................................................35 Table 41 – RAM BUFFER WRITE Byte Count Register A2 Register...........................................................................35 Table 42 – RAM Buffer Write Byte Count Register B1 .................................................................................................36 Table 43 – RAM Buffer Write Byte Count Register B2 Register...................................................................................36 Table 44 – RAM Buffer Read Byte Count Register A1 .................................................................................................36 Table 45 – RAM Buffer Read Byte Count Register A2 Register...................................................................................36 Table 46 – RAM Buffer Read Byte Count Register B1 .................................................................................................36 Table 47 – RAM Buffer Read Byte Count Register B2 Register...................................................................................36 Table 48 – NAK Register (INT5) ..................................................................................................................................36 Table 49 – NAK Mask Register ....................................................................................................................................37 Table 50 – USB Error Register.....................................................................................................................................37 Table 51 – MSB ATA Data Register.............................................................................................................................38 Table 52 – LSB ATA Data Register..............................................................................................................................38 Table 53 – ATA Transfer Count Register 0 ..................................................................................................................38 Table 54 – ATA Transfer Count Register 1 ..................................................................................................................38 Table 55 – ATA Transfer Count Register 2 ..................................................................................................................38 Table 56 – ATA Transfer Count Register 3 ..................................................................................................................39 Table 57 –ATA Control Register ..................................................................................................................................39 Table 58 –ATA Ultra DMA Timing Register..................................................................................................................40 Table 59 – IDE Timing Register ...................................................................................................................................40 Table 60 –ATA Slew Rate Control A Register..............................................................................................................42 Table 61 –ATA Slew Rate Control B Register..............................................................................................................42 Table 62 – IDE Transaction Timing..............................................................................................................................46 Table 63 – ULTRA ATA/66 Control Signal Assignments..............................................................................................47 Table 64 –Buffer SRAM Mapping.................................................................................................................................48 SMSC USB97C201 Page 4 Rev. 11-05-03 DATASHEET Table 65 – RAMWR_TOGGLE State Control ..............................................................................................................51 FIGURES Figure 1 - MCU to EXTERNAL CODE SPACE MAP....................................................................................................14 Figure 2 - GPIO MUXING BLOCK DIAGRAM..............................................................................................................23 Figure 3 - RECEIVE BUFFER OPERATION................................................................................................................51 Figure 4 - TRANSMIT BUFFER OPERATION .............................................................................................................52 Figure 5 - AUTOMATIC DATA TRANSFER OPERATION..........................................................................................53 Figure 6 - 100 PIN TQFP PACKAGE ...........................................................................................................................57 Figure 7 – 100 PIN QFP PACKAGE ............................................................................................................................58 SMSC USB97C201 Page 5 Rev. 11-05-03 DATASHEET 1.0 GENERAL DESCRIPTION The USB97C201 is a USB2.0 Mass Storage Class Peripheral Controller intended for use with standard ATA hard drives and standard ATAPI-5 devices. The device consists of a USB 2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded scratchpad and 768 of program SRAM, and an ATA-66 compatible interface. Provisions for external Flash Memory up to 64K bytes for program storage is provided. Internal 768 Bytes of program SRAM are also provided.. This internal SRAM is used for program storage to implement program upgrade via USB download to “boot block” Flash program memory, if desired. Eight GPIO pins are provided for controlling external power control elements and sensing specialized drive functions. Provisions are made to allow dynamic attach and re-attach to the USB bus to allow hot swap of drives to be implemented. SMSC USB97C201 Page 6 Rev. 11-05-03 DATASHEET 2.0 PIN TABLE DISK DRIVE INTERFACE (27 Pins) IDE_D0 IDE_D1 IDE_D2 IDE_D4 IDE_D5 IDE_D6 IDE_D8 IDE_D9 IDE_D10 IDE_D12 IDE_D13 IDE_D14 IDE_nIOR IDE_nIOW IDE_IRQ IDE_DRQ IDE_nCS0 IDE_nCS1 IDE_SA1 IDE_SA2 IORDY USB INTERFACE (7 Pins) USBD+ USBDLOOPFLTR RTERM FS+ FSMEMORY/IO INTERFACE (28 Pins) MD0 MD1 MD2 MD4 MD5 MD6 MA0 MA1 MA2 MA4 MA5 MA6 MA8 MA9 MA10 MA12 MA13 MA14 nMRD nIOR nMWR MISC (15 Pins) GPIO0 GPIO1 GPIO2 GPIO4/nWE GPIO5 GPIO6 XTAL1/CLKIN XTAL2 nRESET TST_OUT/DBGOUT nTESTEN CLKOUT POWER, GROUNDS, and NO CONNECTS (23 Pins) IDE_D3 IDE_D7 IDE_D11 IDE_D15 IDE_DACK IDE_SA0 RBIAS MD3 MD7 MA3 MA7 MA11 MA15 nIOW GPIO3 GPIO7 nTEST/nDBGSTR SMSC USB97C201 Page 7 Rev. 11-05-03 DATASHEET 3.0 PIN CONFIGURATION 3.1 QFP/TQFP 100 Pin 75 RBIAS VDDA FS+ USB+ USBFSRTERM VSSA XTAL1/CLKIN XTAL2 VSSP LOOPFLTR VDDP N.C. N.C. MD7 MD6 MD5 MD4 GND MD3 MD2 MD1 MD0 nRESET GPIO0 GPIO1 GPIO2 GPIO3 GND GPIO4 GPIO5 GPIO6 GPIO7 nTEST0 nTEST1 nTEST2 VDDIO IDE_D8 IDE_D7 IDE_D9 VDD IDE_D6 IDE_D10 GND IDE_D5 IDE_D11 IDE_D4 VDDIO IDE_D12 51 IDE_D3 IDE_D13 IDE_D2 GND IDE_D14 IDE_D1 IDE_D15 IDE_D0 VDDIO IDE_DRQ IDE_nIOW IDE_nIOR IORDY GND IDE_DACK IDE_IRQ IDE_SA1 IDE_SA0 VDD IDE_SA2 IDE_nCS0 IDE_nCS1 VDDIO nMWR nMRD 25 USB97C201 1 SMSC USB97C201 nIOR nIOW VDDIO CLKOUT MA15 MA14 GND MA13 MA12 VDD MA11 MA10 MA9 MA8 VDDIO MA7 MA6 MA5 MA4 N.C. MA3 MA2 MA1 MA0 GND Page 8 Rev. 11-05-03 DATASHEET 4.0 BLOCK DIAGRAM Auto address generators 512 Bytes EP2 TX/RX Buffer B 512 Bytes EP2 TX/RX Buffer A 64 Bytes EP1RX 64 Bytes EP1TX 64 Bytes EP0RX EP0RX_BC Address 64 Bytes EP0TX Data Buss Address EP0TX_BC Address 1.25KB SRAM Address MUX EP1TX_BC EP1RX_BC Address Address 32 Bit 60MHz RAMWR_A/B Address Latch phase 0 Latch phase 1 Latch phase 2 Future phase 3 Granted SRAM access during Phase 2 RAMRD_A/B Address Address Register Data @ 32 bit 15MHz ATA-66 Interface ATA/ATAPI Drive Granted SRAM access during Phase 0 SIE ( Serial Interface Engine ) 32 bit 15MHz Data Buss SIE Control Regs USB 2.0 PHY ( Transceiver ) XDATA & SFR 8 bit Data busses Configuration and Control GPIO 8 pins Clock Generation 7 pins Interrupt Controller Osc 768 Byte Program/Scratchpad SRAM MEM/IO Bus OPTIONAL External PHY CLOCKOUT XTAL 29pins Program Memory/ IO Bus FAST 8051 CPU CORE Granted SRAM access during Phase 1 12 MHz SMSC USB97C201 Page 9 Rev. 11-05-03 DATASHEET 5.0 PIN DESCRIPTIONS IDE DMA Request IDE IO Read Strobe IDE Register Address 1 IDE Register Address 0 IDE Register Address 2 IDE Data IDE_DRQ DISK DRIVE INTERFACE IS This pin is the active high DMA request from the ATA/ATAPI interface. O20 This pin is the active low read signal for the interface. This pin is the register select address bit 1 signal for the ATA/ATAPI interface. This pin is the register select address bit 0 signal for the ATA/ATAPI interface. This pin is the register select address bit 2 signal for the ATA/ATAPI interface. This pin is the bi-directional data bus bit 15 signal for the ATA/ATAPI interface. This pin is active low write signal for the ATA/ATAPI interface. This pin is the active low DMA acknowledge signal for the ATA/ATAPI interface. This pin is the active high interrupt request signal for the ATA/ATAPI interface. This pin is the bi-directional data bus bit 13 signal for the ATA/ATAPI interface. This pin is the bi-directional data bus bit 14 signal for the ATA/ATAPI interface. . This pin is the active low chip select 0 signal for the ATA/ATAPI interface. This pin is the active low select 1 signal for the ATA/ATAPI interface. These pins are bits 0-12 of the ATA/ATAPI bidirectional data bus. This pin is the active high IORDY signal from the IDE drive. IDE_nIOR IDE_SA1 O20 IDE_SA0 O20 IDE_SA2 O20 IDE_D15 IO20 IDE IO Write Strobe IDE_nIOW O20 IDE DMA IDE_nDACK Acknowledge IDE Interrupt Request IDE Data IDE_IRQ O20 IS IDE_D13 IO20 IDE Data IDE_D14 IO20 IDE Chip Select 0 IDE Chip Select 1 0 IDE Data IO Ready IDE_nCS0 O20 IDE_nCS1 O20 IDE_D[0:12] IORDY IO20 I SMSC USB97C201 Page 10 Rev. 11-05-03 DATASHEET USB Bus Data USB Transceiver Filter USB Transceiver Bias Termination Resistor Full Speed USB Data USBUSB+ LOOPFLTR USB INTERFACE IO-U These pins connect to the USB bus data signals. This pin provides the ability to supplement the internal filtering of the transceiver with an external network, if required. A 9.09 Kohm precision resistor is attached from ground to this pin to set the transceiver’s internal bias currents. A precision 1.5Kohm precision resistor is attached to this pin from a 3.3V supply. These pins connect to the USB- and USB+ pins through 31.6 ohm series resistors. RBIAS RTERM FSFS+ IO-U Memory Data MD[7:0] Bus Memory Address Bus Memory Write Strobe Memory Read Strobe IO Read Strobe IO Write Strobe MA[15:0] nMWR nMRD nIOR nIOW MEMORY/IO INTERFACE IO12 These signals are used to transfer data between the internal CPU and the external program memory. O12 These signals address memory locations within the external memory. O12 Program Memory Write; active low O12 O12 O12 Program Memory Read; active low XDATA space Read; active low XDATA space Write; active low SMSC USB97C201 Page 11 Rev. 11-05-03 DATASHEET MISC 12Mhz Crystal or external clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 12Mhz clock when a crystal is not used. Crystal Output XTAL2 OCLKx 12Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit. Clock Output CLKOUT O8 This pin produces a 30Mhz clock signal independent of the processor clock divider. It is held inactive and low whenever the internal processor clock is stopped or is being obtained from the ring oscillator. General GPIO[0:7] IO20 These general purpose pins may be used Purpose I/O either as inputs, edge sensitive interrupt inputs, or outputs. In addition, GPIO0 has the capability of auto-toggling at a 1Hz rate when used as an output. RESET input nRESET IS This active low signal is used by the system to reset the chip. The active low pulse should be at least 100ns wide. Test input nTest[0:2} IP These signals are used for testing the chip. User should normally leave them unconnected. For board testing, all pads except these test inputs are included in an XNOR chain, such that by tying nTEST2 low, nIOR will reflect the toggling of a signal on each pin. Circuit board continuity of the pin solder connections after assembly can be checked in this manner POWER, GROUNDS, and NO CONNECTS VDD +2.5V Core power VDDIO +3.3V I/O power VDDP +2.5 Analog power VSSP Analog Ground Reference VDDA +3.3V Analog power VSSA Analog Ground Reference GND Ground Reference NC No Connect. These pins should not be connected externally. XTAL1/ Crystal Input/External CLKIN Clock Input ICLKx SMSC USB97C201 Page 12 Rev. 11-05-03 DATASHEET 5.1 BUFFER TYPE DESCRIPTIONS Table 1 - USB97C201 Buffer Type Descriptions BUFFER I IS IO8 O8 O12 IO20 OD12 O20 ICLKx OCLKx I/O-U DESCRIPTION Input Input with Schmitt trigger Input/Output with 8 mA drive Output with 8mA drive Output with 12mA drive Input/output with 20mA drive Open drain….12mA sink Output with 20mA drive XTAL clock input XTAL clock output Defined in USB specification SMSC USB97C201 Page 13 Rev. 11-05-03 DATASHEET 6.0 FUNCTIONAL BLOCK DESCRIPTIONS 6.1 MCU The 64K memory map is as follows from the 8051's viewpoint: 6.1.1 MCU MEMORY MAP: CODE SPACE The 8051 has a single flat 64K Code space. External memory requires 80ns access times from Address to Data and less than 80ns output enable access times, assuming the use of the nMEMR signal as OE on the memory. 8051 ADDRESS 0x0700-0xFFFF Table 2 - MCU Code Memory Map CODE SPACE Fixed Memory ACCESS External Program Memory 0x0400-0x06FF 0x0000-0x03FF 768 Bytes of Fixed 16k FLASH Page OR 768 Bytes of Internal SRAM for program execution (see bit 7 of the UTIL_CFG register for more information) Fixed Memory External Program Memory OR Internal Program SRAM External Program Memory 8051 MCU External Code Address Space 0xFFFF 0x0700 Internal 768 Byte SRAM or External Memory 0x0400 0x0000 FIGURE 1 - MCU TO EXTERNAL CODE SPACE MAP SMSC USB97C201 Page 14 64K Rev. 11-05-03 DATASHEET 6.1.2 MCU MEMORY MAP: XDATA SPACE Table 3 - MCU XData Memory Map DATA SPACE External Memory or I/O Devices 8051 ADDRESS 0x3F30-0xFFFF 0x3F00-0x3F2F 0x33F7-0X3EFF Internal Test Registers (reserved access) External Memory or I/O Devices 033F6 External ATA Interface I/O 0x31F8-0x33F5 External Memory or I/O Devices 0x31F0-0x31F7 External ATA Interface I/O 0x30F4-0x31EF External Memory or I/O Devices 0X30F0-0X30F3 0X0700-0X30EF Internal Test Registers (reserved access) External Memory or I/O Devices 0x0400-0x06FF 0x0000-0x03FF 768 Byte SRAM (see Note 1) ACCESS External (IOR or IOW active) DO NOT ACCESS External (IOR or IOW active) External (IOR or IOW active) External (IOR or IOW active) External (IOR or IOW active) External (IOR or IOW active) DO NOT ACCESS External (IOR or IOW active) Internal External (IOR or IOW active)(see Note 1) Note 1: This XDATA space is accessed using MOVX instructions. A region of 8051 Special Function Registers (SFR) is also accessible at 0x0100 to 0x01FF addresses using the MOV instructions. In addition to the normal 8051 SFRs, there are also numerous Runtime Registers in this SFR space. These Runtime Registers are external to the 8051, but internal to the USB97C201. SMSC USB97C201 Page 15 Rev. 11-05-03 DATASHEET 6.1.3 MCU BLOCK REGISTER SUMMARY Table 4 - MCU Block Register Summary (These registers are external to the 8051 design core) ADDRESS 80 93 90 94 95 96 97 9A 9B C0 9C 9D 9F A1 A2 A5 A0 A6 NAME ISR_0 IMR_0 ISR_1 IMR_1 DEV_REV DEV_ID GPIO_DIR GPIO_OUT GPIO_IN GPIO_IRQ GPIO_MSK UTIL_CONFIG SRAM_DATA SRAM_ADD1 SRAM_ADD2 R/W DESCRIPTION RUNTIME REGISTERS R/W INT0 Source Register R/W INT0 Mask Register R/W INT1 Source Register R/W INT1 Mask Register R Device Revision Register R Device ID Register UTILITY REGISTERS R/W GPIO Direction Register R/W GPIO Data Output Register R GPIO Data Input Register R/W GPIO Interrupt Status Register (INT4) R/W GPIO Interrupt Mask Register (INT4) R/W Miscellaneous Configuration Register PAGE 19 20 20 21 21 21 22 24 24 24 25 26 26 27 27 27 28 28 SRAM Data Port Register R/W R/W SRAM Address 1 Register R/W SRAM Address 2 Register POWER MANAGEMENT REGISTERS CLOCK_SEL R/W 8051 Clock Select Register WU_SRC_1 R/W Wakeup Source 1 Register (INT2) WU_MSK_1 R/W Wakeup Mask 1 Register (INT2) SMSC USB97C201 Page 16 Rev. 11-05-03 DATASHEET A9 AA AB AC B0 AD AE AF B1 B2 B3 B4 B5 B6 B7 C7 CE CF D1 D2 D3 D4 D5 D6 D7 D9 DA DB DC DD DE DF E1 E2 E3 E4 E5 E6 SIE & BUFFER CONTROL REGISTERS USB_ADD R/W USB Address Register SIE_CONF R/W SIE Configuration Register USB_STAT R/W USB Bus Status Register USB_MSK R/W USB Bus Status Mask Register SIE_STAT R SIE Status Register USB_CONF R/W USB Configuration Number Register SIE_MSK R/W SIE Status Mask Register EP0RX_CTL R/W Endpoint 0 Receive Control Register EP0TX_CTL R/W Endpoint 0 Transmit Control Register EP1RX_CTL R/W Endpoint 1 Receive Control Register EP1TX_CTL R/W Endpoint 1 Transmit Control Register EP2_CTL R/W Endpoint 2 Control Register EP0RX_BC R/W Endpoint 0 Receive Byte Count Register EP0TX_BC R/W Endpoint 0 Transmit Byte Count Register EP1RX_BC R/W Endpoint 1 Receive Byte Count Register EP1TX_BC R/W Endpoint 1 Transmit Byte Count Register RAMWRBC_A1 R/W RAM Buffer Write Byte Count Register A1 RAMWRBC_A2 R/W RAM Buffer Write Byte Count Register A2 RAMWRBC_B1 R/W RAM Buffer Write Byte Count Register B1 RAMWRBC_B2 R/W RAM Buffer Write Byte Count Register B2 RAMRDBC_A1 R/W RAM Buffer Read Byte Count Register A1 RAMRDBC_A2 R/W RAM Buffer Read Byte Count Register A2 RAMRDBC_B1 R/W RAM Buffer Read Byte Count Register B1 RAMRDBC_B2 R/W RAM Buffer Read Byte Count Register B2 NAK R/W NAK Status Register NAK_MSK R/W NAK Mask Register USB_ERR R USB Error Register MSB_ATA LSB_ATA ATA_CTL ATA_DMA IDE_TIM ATA_CNT0 ATA_CNT1 ATA_CNT2 ATA_CNT3 ATA_SRCA ATA_SRCB ATA CONFIGURATION REGISTERS R/W MSB ATA Data Register R/W LSB ATA Data Register R/W ATA Control Register R/W ATA Ultra DMA Timing Register R/W IDE Timing Register R/W ATA Transfer Count Register 0 R/W ATA Transfer Count Register 1 R/W ATA Transfer Count Register 2 R/W ATA Transfer Count Register 3 R/W ATA Slew Rate Control A Register R/W ATA Slew Rate Control B Register 29 29 30 30 31 32 31 32 32 32 33 33 34 35 35 35 35 35 36 36 36 36 36 36 36 37 39 38 38 39 40 40 38 38 38 39 42 42 SMSC USB97C201 Page 17 Rev. 11-05-03 DATASHEET Table 5 - 8051 Core SFR Register Summary These registers are part of the 8051 design core itself. REGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ADDRESS SP 81h DPL0 82h DPH0 83h DPL1 84h DPH1 85h DPS 0 0 0 0 0 0 0 SEL 86h PCON SMOD0 – 1 1 GF1 GF0 STOP IDLE 87h TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 88h TMOD GATE C/T M1 M0 GATE C/T M1 M0 89h TL0 8Ah TL1 8Bh TH0 8Ch TH1 8Dh CKCON T2M T1M T0M MD2 MD1 MD0 8Eh SPC_ 0 0 0 0 0 0 0 WR 8Fh S FNC EXIF IE5 IE4 IE3 IE2 1 0 0 0 91h MPAGE 92h SCON0 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 98h SBUF0 99h IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 A8h IP 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 B8h TL2 CCh TH2 CDh PSW CY AC F0 RS1 RS0 OV F1 P D0h EICON SMOD1 1 EPFI PFI WDTI 0 0 0 D8h ACC E0h EIE 1 1 1 EWDI EX5 EX4 EX3 EX2 E8h B F0h EIP 1 1 1 PWDI PX5 PX4 PX3 PX2 F8h Notes: Bit WRS of the SPC_FNC register controls the operation of MOVX writes the program or XDATA bus of the 8051. Setting it to 0 ( the reset state), will direct writes to the XDATA bus, either to internal or external destinations, while setting it to 1 will allow writes to the program memory bus to occur, either internally( if the 768 SRAM is the target) or externally. Bits MD2:0 of the CKCON SFR register (8Eh) control the cycle timing for external accesses using the nIOR and nIOW signals. This allows slow peripheral devices to be attached. The values and corresponding strobe widths are shown below: MD2 MD1 MD0 NIOR/NIOW STOBE NIOR/NIOW STROBE (AT (CLKS) 30MHZ) 0 0 0 2 66ns 0 0 1 4 133ns 0 1 0 8 267ns 0 1 1 12 400ns 1 0 0 16 533ns 1 0 1 20 667ns 1 1 0 24 800ns 1 1 1 28 933ns Note: the strobe width will vary with the actual clock divider used for the processor. For example if, 16 Mhz is used, an MD[2:0] value of 111 will result in a 28 clock strobe or 1866ns. SMSC USB97C201 Page 18 Rev. 11-05-03 DATASHEET 6.1.4 6.1.4.1 MCU REGISTER DESCRIPTIONS MCU Runtime Registers Table 6 - Interrupt 0 Source Register ISR_0 (0x80 - RESET=0x0C) INTERRUPT 0 SOURCE REGISTER BIT NAME R/W DESCRIPTION 7 USB_STAT R 1= USB Bus System Event has occurred. Check USB_STAT register for the specific event(s). This must be cleared by clearing the USB_STAT register. 6 SETUP R/W 1= A SETUP packet was received on Endpoint 0. The EP0RX bit of ISR_1 will not be set. If another SETUP packet is received on Endpoint 0 while this bit is high, the bit will go low and then immediately high again, to signal the duplicate SETUP. If all other bits in this register are clear and the INT0 of the 8051is configured for edge triggering, then another interrupt will be generated within the 8051. The firmware must clear this bit by writing a "1" to it to allow the Enpoint 0 buffer to receive subsequent data packets during the SETUP transaction. Receipt of these packets will set EP0RX in ISR_1. 5 Reserved R This bit always reads a “0”. 4 ATA_IRQ R/W External interrupt input from the ATA-66 Interface. 1 = An ATA interrupt has occurred. 3 RAMRD_B R/W 1 = The current transfer from the SRAM B Buffer has been completed. See Sections 6.7 and 6.9 for more detail. This bit is also cleared by writing a “1” to the RAMRD_TOGGLE bit of the EP2_CTL register. 2 RAMRD_A R/W 1 = The current transfer from the SRAM A Buffer has been completed. See Sections 6.7 and 6.9 for more detail. . This bit is also cleared by writing a “0” to the RAMRD_TOGGLE bit of the EP2_CTL register. 1 RAMWR_B R/W 1 = The current transfer to the SRAM B Buffer has been completed. This bit may be cleared by the internal hardware state machine while operating in “Auto Transfer” mode. See Sections 6.7 and 6.9 for more detail. 0 RAMWR_A R/W 1 = The current transfer to the SRAM A Buffer has been completed. This bit may be cleared by the internal hardware state machine while operating in “Auto Transfer” mode. See Sections 6.7 and 6.9 for more detail. The bits in this register (except bit 7) are set to their POR values by writing a ‘1’ to the corresponding bit. If not masked by the corresponding bit in the IMR0 mask register, a “1” on any of these bits will generate a “1” on the 8051 core’s external INT0 input. SMSC USB97C201 Page 19 Rev. 11-05-03 DATASHEET Table 7 - Interrupt 0 Mask IMR_0 (0x93- RESET=0xFF) INTERRUPT 0 MASK REGISTER BIT NAME R/W DESCRIPTION 7 USB_STAT R/W USB Bus System Event interrupt mask 0 = Enable Interrupt 1 = Mask Interrupt 6 SETUP R/W SETUP interrupt mask 0 = Enable Interrupt 1 = Mask Interrupt 5 Reserved R/W Reserved. 4 ATA_IRQ R/W External ATA-66 interrupt input mask 0 = Enable Interrupt 1 = Mask Interrupt 3 RAMRD_B R/W SRAM Buffer B Output Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt 2 RAMRD_A R/W SRAM Buffer A Output Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt 1 RAMWR_B R/W SRAM Buffer B Input Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt 0 RAMWR_A R/W SRAM Buffer A Input Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt Note1: The mask bits do not prevent the status in the ISR_0 register from being set, only from generating an interrupt. Table 8 - Interrupt 1 Source Register ISR_1 (0x90- RESET=0x00) INTERRUPT 1 SOURCE REGISTER BIT NAME R/W DESCRIPTION 7 ZLP_EP0 R/W 1= A ZLP has been received on EP0RX. 6 Reserved R This bit always reads a “0”. 5 ATA_PIO R This bit reflects that state of the PIO_COMPLETE bit (bit 6) of the ATA_CTL register. It cannot be written directly. 4 EP1RX R/W 1 = A Packet was successfully received on Endpoint 1 and stored in the Buffer SRAM. OUT tokens will be NAK’d until this bit is cleared. 3 EP1TX R/W 1 = A Packet was successfully transmitted on Endpoint 1 from the Buffer SRAM. IN tokens will be NAK’d until this bit is cleared. 2 EP0RX R/W 1 = A non-SETUP, non ZLP Packet (see ISR_0 SETUP bit) was successfully received on Endpoint 0 and stored in the Buffer SRAM. OUT tokens will be NAK’d until this bit is cleared. 1 EP0TX R/W 1 = A Packet was successfully transmitted on Endpoint 0 from the Buffer SRAM. IN tokens will be NAK’d until this bit is cleared. 0 SUSPEND R/W Suspend – If 3ms of IDLE state are detected by the hardware, then this bit will be set. Note 1: The bits (except for bit 5)in this register are cleared by writing a ‘1’ to the corresponding bit. If not masked by the corresponding bit in the IMR1 mask register, a “1” on any of these bits will generate a “1” on the 8051 core’s external INT1 input. SMSC USB97C201 Page 20 Rev. 11-05-03 DATASHEET Table 9 - Interrupt 1 Mask IMR_1 (0x94- RESET=0xFF) BIT NAME R/W 7 ZLP_EP0 R/W INTERRUPT 1 MASK REGISTER DESCRIPTION Zero Length Packet Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt Reserved. This bit should never be written to a “0”. ATA PIO Complete Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt Endpoint 1 Received Packet Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt Endpoint 1 Transmitted Packet Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt Endpoint 0 Received Packet Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt Endpoint 0 Transmitted Packet Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt SUSPEND Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt 6 5 Resereved ATA_PIO R/W R/W 4 EP1RX R/W 3 EP1TX R/W 2 EP0RX R/W 1 EP0TX R/W 0 SUSPEND R/W Note 1: The mask bits do not prevent the status in the ISR_1 register from being set, only from generating an interrupt. Table 10 - Device Revision Register DEV_REV (0x95- RESET=0xXX) DEVICE REVISION REGISTER BIT R/W DESCRIPTION [7:0] XXh R This register defines additional revision information used internally by SMSC. The value is silicon revision dependent. Table 11 - Device Identification Register DEV_ID (0x96- RESET=0x12) DEVICE IDENTIFICATION REGISTER BIT R/W DESCRIPTION [7:0] 12h R This register defines additional revision information used internally by SMSC SMSC USB97C201 Page 21 Rev. 11-05-03 DATASHEET 6.1.4.2 Utility Registers Table 12 - GPIO Direction Register GPIO_DIR GPIO DIRECTION REGISTER (0x97- RESET=0x00) BIT NAME R/W DESCRIPTION 7 GPIO7 R/W GPIO7 Direction 0 = In 1 = Out 6 GPIO6 R/W GPIO6 Direction 0 = In 1 = Out 5 GPIO5 R/W GPIO5 Direction 0 = In 1 = Out 4 GPIO4/nWE R/W GPIO4 Direction 0 = In 1 = Out 3 GPIO3/T1 R/W GPIO3 Direction 0 = In 1 = Out 2 GPIO2/T0 R/W GPIO2 Direction 0 = In 1 = Out 1 GPIO1/TXD R/W GPIO1 Direction 0 = In 1 = Out 0 GPIO0/RXD R/W GPIO0 Direction 0 = In 1 = Out SMSC USB97C201 Page 22 Rev. 11-05-03 DATASHEET GPIO out data GPIO Direction Bit GPIO in data GPIO[7:5] Edge Detector GPIO2 data out GPIO2 DIR 8051 "T0 timer P3.4" 0 S1 GPIO2 GPIO2 data in TBD Mux Enable Edge Detector GPIO3 data out GPIO3 DIR 8051 "T1 timer P3.5" 0 S1 GPIO3 GPIO3 data in TBD Mux Enable Edge Detector Enable GPIO0 data out 1 Hz gate GPIO0 DIR GPIO0 data in RXD "Uart P3.0" Mux Enable 0 S1 GPIO0 "0" Edge Detector GPIO1 data out TXD "Uart P3.1" Mux Enable 0 1S GPIO1 DIR GPIO1 data in Edge Detector GPIO1 GPIO4 data out IDE_nIOW Mux Enable 0 1S GPIO4 DIR GPIO4 data in GPIO4/ nWE FIGURE 2 - GPIO MUXING BLOCK DIAGRAM SMSC USB97C201 Page 23 Rev. 11-05-03 DATASHEET Table 13 - GPIO Output Register GPIO_OUT GPIO DATA OUTPUT REGISTER (0x9A- RESET=0x00) BIT NAME R/W DESCRIPTION 7 GPIO7 R/W GPIO7 Output Buffer Data 6 GPIO6 R/W GPIO6 Output Buffer Data 5 GPIO5 R/W GPIO5 Output Buffer Data 4 GPIO4/nWE R/W GPIO4 Output Buffer Data 3 GPIO3/T1 R/W GPIO3 Output Buffer Data 2 GPIO2/T0 R/W GPIO2 Output Buffer Data 1 GPIO1/TXD R/W GPIO1 Output Buffer Data 0 GPIO0/RXD R/W GPIO0 Output Buffer Data Table 14 - GPIO Input Register GPIO_IN (0x9B- RESET=0x00) GPIO INPUT REGISTER BIT NAME R/W DESCRIPTION 7 GPIO7 R GPIO7 Input Buffer Data 6 GPIO6 R GPIO6 Input Buffer Data 5 GPIO5 R GPIO5 Input Buffer Data 4 GPIO4/nWE R GPIO4 Input Buffer Data 3 GPIO3/T1 R GPIO3 Input Buffer Data 2 GPIO2/T0 R GPIO2 Input Buffer Data 1 GPIO1/TXD R GPIO1 Input Buffer Data 0 GPIO0/RXD R GPIO0 Input Buffer Data Table 15 – GPIO Interrupt Status Register (INT4) GPIO_IRQ (0XC0- RESET=0x00) GPIO INTERRUPT STATUS REGISTER BIT NAME R/W DESCRIPTION 7 GPIO7_IRQ R/W 1 = A level change has occurred on GPIO7. 6 GPIO6_IRQ R/W 1 = A level change has occurred on GPIO6. 5 GPIO5_IRQ R/W 1 = A level change has occurred on GPIO5. 4 GPIO4_IRQ R/W 1 = A level change has occurred on GPIO4. 3 GPIO3_IRQ R/W 1 = A level change has occurred on GPIO3. 2 GPIO2_IRQ R/W 1 = A level change has occurred on GPIO2. 1 GPIO1_IRQ R/W 1 = A level change has occurred on GPIO1. 0 GPIO0_IRQ R/W 1 = A level change has occurred on GPIO0. Note 1: Writing a “1” (one) to a bit clears the bit and enables the detection of the next level transition. If not masked by the corresponding bit in the GPIO_MSK register, “1” in any bit in this register will force a “1” on the 8051 core’s external INT4 interrupt input. SMSC USB97C201 Page 24 Rev. 11-05-03 DATASHEET Table 16 – GPIO Interrupt Mask Register GPIO_MSK (0x9C- RESET=0xFF) GPIO INTERRUPT MASK REGISTER BIT NAME R/W DESCRIPTION 7 GPIO7_MSK R/W 1 = Prevents a high in the corresponding in the GPIO_IRQ register from generating interrupt on the INT4 input to the 8051. 6 GPIO6_MSK R/W 1 = Prevents a high in the corresponding in the GPIO_IRQ register from generating interrupt on the INT4 input to the 8051.. 5 GPIO5_MSK R/W 1 = Prevents a high in the corresponding in the GPIO_IRQ register from generating interrupt on the INT4 input to the 8051... 4 GPIO4_MSK R/W 1 = Prevents a high in the corresponding in the GPIO_IRQ register from generating interrupt on the INT4 input to the 8051... 3 GPIO3_MSK R/W 1 = Prevents a high in the corresponding in the GPIO_IRQ register from generating interrupt on the INT4 input to the 8051... 2 GPIO2_MSK R/W 1 = Prevents a high in the corresponding in the GPIO_IRQ register from generating interrupt on the INT4 input to the 8051... 1 GPIO1_MSK R/W 1 = Prevents a high in the corresponding in the GPIO_IRQ register from generating interrupt on the INT4 input to the 8051... 0 GPIO0_MSK R/W 1 = Prevents a high in the corresponding in the GPIO_IRQ register from generating interrupt on the INT4 input to the 8051... bit an bit an bit an bit an bit an bit an bit an bit an SMSC USB97C201 Page 25 Rev. 11-05-03 DATASHEET BIT 7 6 5 4 3 2 1 0 Table 17 - Utility Configuration Register UTIL_CONFIG (9D RESET=0x00) UTILITY CONFIGURATION REGISTER NAME R/W DESCRIPTION SRAMSW R/W 1 = The 768 byte SRAM is located at 0x04000x06FF in the Code Space, instead of external Memory. 0 = The 768 byte SRAM is located at 0x04000x06FF in the XDATA space. Reserved R/W Reserved. This bit should never be written to a “1”. GPIO0_TOG R/W 1 = GPIO0 Output Auto Toggle enabled. 0 = Disabled, normal operation occurs. GPIO4/nWE R/W GPIO4/SOF Output Select Mux 0 = GPIO4 1 = The IDE_nIOW signal is output. GPIO3/T1 R/W P3.5 Timer 1 input trigger source 0 = GPIO3 1 = TBD GPIO2/T0 R/W P3.4 Timer 0 input trigger source 0 = GPIO2 1 = TBD GPIO1/TXD R/W GPIO1/TXD Output Select Mux 0 = GPIO1 1 = P3.1 GPIO0/RXD R/W P3.0 RXD/GPIO0 Input Select Mux 0 = RXD