USB97C202

USB97C202 USB 2.0 ATA/ ATAPI Controller Datasheet Product Features 2.5 Volt, Low Power Core Operation 3.3 Volt I/O with 5V input tolerance Complete USB Specification 2.0 Compatibility − − Includes USB 2.0 Transceiver A Bi-directional Control and a Bi-directional Bulk Endpoint are provided. Double Buffered Bulk Endpoint − − − − Bi-directional 512 Byte Buffer for Bulk Endpoint 64 Byte RX Control Endpoint Buffer 64 Byte TX Control Endpoint Buffer 48K Byte Internal ROM or optional 64K Byte External Code Space using Flash, SRAM, or EPROM Memory Internal or External Program Memory Interface Complete System Solution for interfacing ATA or ATAPI devices to USB 2.0 bus − − − − Supports USB Mass Storage Compliant Bootable BIOS Supports ATA6 Drive capacities up to 2048GB True UDMA Mode 4 transfer rates Support for ATAPI Devices: - CD-ROM - CD-R - CD-RW - DVD - DVD/R/W Provides low speed control functions 30 Mhz execution speed at 4 cycles per instruction average 768 Bytes of internal SRAM for general purpose scratchpad or program execution while re-flashing external ROM On Board 12Mhz Crystal Driver Circuit Internal PLL for 480Mhz USB 2.0 Sampling, 30Mhz MCU clock, and 60Mhz ATA clock Supports firmware upgrade via USB bus if “boot block” Flash program memory is used for optional external program memory 7 GPIOs for special function use: LED indicators, button inputs, etc. − − − Inputs capable of generating interrupts with either edge sensitivity USB High Speed LED Serial EEPROM interface for VID/PID/Serial Number Customization (Required for internal ROM operation) 8051 8 bit microprocessor − − − Can share drive in MP3 player and 1394/USB applications by isolating the IDE Interface with other controllers. 100-Pin STQFP (12x12x1.4 body, 2mm footprint) lead-free RoHS compliant package. ORDERING INFORMATION Order Number: USB97C202-MV-05 for 100 pin, STQFP lead-free RoHS compliant package SMSC USB97C202 Page 1 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. 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SMSC USB97C202 Page 2 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet Table of Contents CHAPTER 1 CHAPTER 2 CHAPTER 3 CHAPTER 4 CHAPTER 5 GENERAL DESCRIPTION................................................................................................................4 PIN TABLE........................................................................................................................................5 PIN CONFIGURATION .....................................................................................................................6 BLOCK DIAGRAM............................................................................................................................8 PIN DESCRIPTIONS.........................................................................................................................9 5.1 Buffer Type Descriptions................................................................................................................ 13 TYPICAL APPLICATION ................................................................................................................14 DC PARAMETERS .........................................................................................................................15 CHAPTER 6 CHAPTER 7 7.1 Maximum Guaranteed Ratings ...................................................................................................... 15 7.1.1 Capacitance TA = 25°C; FC = 1MHz; VDD = 2.5V ...................................................................... 17 CHAPTER 8 AC SPECIFICATIONS ....................................................................................................................18 8.1 8.2 ATA/ATAPI..................................................................................................................................... 18 USB 2.0 Timing .............................................................................................................................. 18 PACKAGE OUTLINE ......................................................................................................................19 CHAPTER 9 List of Figures Figure 3.1 - 100-PIN STQFP..........................................................................................................................................6 Figure 9.1 - 100-Pin STQFP Package Outline, 12x12x1.4 Body, 2MM Footprint (Rev A)............................................19 List of Tables Table 5.1 - USB97C202 Pin Descriptions ......................................................................................................................9 Table 5.2 - USB97C202 Buffer Type Descriptions .......................................................................................................13 Table 7.1 - DC Electrical Characteristics .......................................................................................................................15 Table 9.1 - 100-Pin STQFP Package Parameters (Rev A) ..........................................................................................19 SMSC USB97C202 Page 3 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet Chapter 1 General Description The USB97C202 is a USB 2.0 Mass Storage Class Peripheral Controller intended for use with standard ATA-5 and -6 hard drives and standard ATAPI-5 devices. The device consists of a USB 2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded scratchpad and 768 of program SRAM, internal 48 KB program ROM, and an ATA-66 compatible interface. Provisions for optional external Flash Memory up to 64K bytes for program storage is provided. A serial EEPROM which can be modified via USB from the host provides unique VID/PID/Serial numbers, as well as optional configuration information. Internal 768 Bytes of scratchpad SRAM are also provided. This internal SRAM can also be used for program storage to implement program upgrade via USB download to external “boot block” Flash program memory, if desired. Seven GPIO pins are provided for controlling external power control elements and sensing specialized drive functions. Provisions are made to allow dynamic attach and re-attach to the USB bus to allow hot swap of drives to be implemented. ATA-6 HDD or ATAPI-5 Optical drive USB 2.0 BUS USB97C202 ATA-66 HS Indicator Serial EEPROM (VID/PID/options) SMSC USB97C202 Page 4 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet Chapter 2 Pin Table DISK DRIVE INTERFACE (27 Pins) IDE_D1 IDE_D2 IDE_D5 IDE_D6 IDE_D9 IDE_D10 IDE_D13 IDE_D14 IDE_nIOW IDE_IRQ IDE_nCS0 IDE_nCS1 IDE_SA2 IORDY USB INTERFACE (7 Pins) USBDLOOPFLTR FS+ FSMEMORY/IO INTERFACE (28 Pins) MD1 MD2 MD5 MD6 MA1 MA2 MA5 MA6 MA9 MA10 MA13 MA14 nIOR nMWR MISC (15 Pins) GPIO1/HS GPIO2/EE_CS GPIO5/ATA RESET GPIO6/A16 XTAL2 nRESET nTEST2 CLKOUT POWER, GROUNDS, and NO CONNECTS (23 Pins) IDE_D0 IDE_D4 IDE_D8 IDE_D12 IDE_nIOR IDE_DRQ IDE_SA1 USBD+ RTERM MD0 MD4 MA0 MA4 MA8 MA12 nMRD ROMEN GPIO4/EE_DIO XTAL1/CLKIN nTEST2 IDE_D3 IDE_D7 IDE_D11 IDE_D15 IDE_DACK IDE_SA0 RBIAS MD3 MD7 MA3 MA7 MA11 MA15 nIOW GPIO3/VBUS GPIO7/EE_CLK nTEST0 SMSC USB97C202 Page 5 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet Chapter 3 Pin Configuration 75 RBIAS VDDA FS+ USB+ USBFSRTERM VSSA XTAL1/CLKIN XTAL2 VSSP LOOPFLTR VDDP N.C. N.C. MD7 MD6 MD5 MD4 GND MD3 MD2 MD1 MD0 nRESET ROMEN GPIO1 GPIO2 GPIO3 GND GPIO4 GPIO5 GPIO6 GPIO7 nTEST0 nTEST1 nTEST2 VDDIO IDE_D8 IDE_D7 IDE_D9 VDD IDE_D6 IDE_D10 GND IDE_D5 IDE_D11 IDE_D4 VDDIO IDE_D12 51 IDE_D3 IDE_D13 IDE_D2 GND IDE_D14 IDE_D1 IDE_D15 IDE_D0 VDDIO IDE_DRQ IDE_nIOW IDE_nIOR IORDY GND IDE_DACK IDE_IRQ IDE_SA1 IDE_SA0 VDD IDE_SA2 IDE_nCS0 IDE_nCS1 VDDIO nMWR nMRD 25 USB97C202 1 SMSC USB97C202 nIOR nIOW VDDIO CLKOUT MA15 MA14 GND MA13 MA12 VDD MA11 MA10 MA9 MA8 VDDIO MA7 MA6 MA5 MA4 N.C. MA3 MA2 MA1 MA0 GND Figure 3.1 - 100-PIN STQFP Page 6 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet Chapter 4 Block Diagram 512 Bytes EP2 TX/RX Buffer B 512 Bytes EP2 TX/RX Buffer A 64 Bytes EP1RX 64 Bytes EP1TX 64 Bytes EP0RX EP0RX_BC Address 64 Bytes EP0TX Auto address generators 1.25KB SRAM Address EP0TX_BC Address Data Buss EP1TX_BC EP1RX_BC Address Address Address MUX 32 Bit 60MHz RAMWR_A/B Address Latch phase 0 Latch phase 1 Latch phase 2 Future phase 3 Clocked byPhase 2 Clock RAMRD_A/B Address Address Register Data @ 32 bit 15MHz XDATA 8 bits ( Address and Data busses ) ATA-66 Interface ATA/ATAPI Drive Clocked byPhase 0 Clock SIE ( Serial Interface Engine ) 32 bit 15MHz Data Buss SIE Control Regs USB 2.0 PHY ( Transciever ) Configuration and Control GPIO 7 pins Clock Generation 7 pins Interrupt Controller Osc 768 Byte Program/Scratchpad SRAM 48KB ROM ROMEN MEM/IO Bus OPTIONAL External PHY CLOCKOUT XTAL 29pins Program Memory/ IO Bus FAST 8051 CPU CORE Debug Serial 2 wire ( Data/Strobe) 12 MHz 2 pins Clocked byPhase 1 Clock SMSC USB97C202 Page 8 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet Chapter 5 Pin Descriptions Table 5.1 - USB97C202 Pin Descriptions DISK DRIVE INTERFACE IS This pin is the active high DMA request from the ATA/ATAPI interface. O20 This pin is the active low read signal for the interface. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. IDE DMA Request IDE IO Read Strobe IDE_DRQ IDE_nIOR IDE Register Address 1 IDE_SA1 O20 This pin is the register select address bit 1 signal for the ATA/ATAPI interface. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. IDE Register Address 0 IDE_SA0 O20 This pin is the register select address bit 0 signal for the ATA/ATAPI interface. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. IDE Register Address 2 IDE_SA2 O20 This pin is the register select address bit 2 signal for the ATA/ATAPI interface. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. IDE Data IDE_D15 IO20 This pin is the bi-directional data bus bit 15 signal for the ATA/ATAPI interface. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. IDE IO Write Strobe IDE_nIOW O20 This pin is active low write signal for the ATA/ATAPI interface. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. IDE DMA IDE_nDACK Acknowledge O20 This pin is the active low DMA acknowledge signal for the ATA/ATAPI interface. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. IDE Interrupt Request IDE Data IDE_IRQ IDE_D13 IS IO20 This pin is the active high interrupt request signal for the ATA/ATAPI interface. This pin is the bi-directional data bus bit 13 signal for the ATA/ATAPI interface. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. IDE Data IDE_D14 IO20 This pin is the bi-directional data bus bit 14 signal for the ATA/ATAPI interface. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. SMSC USB97C202 Page 9 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet IDE Chip Select 0 IDE_nCS0 DISK DRIVE INTERFACE O20 This pin is the active low chip select 0 signal for the ATA/ATAPI interface. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. IDE Chip Select 1 0 IDE_nCS1 O20 This pin is the active low select 1 signal for the ATA/ATAPI interface. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. IDE Data IDE_D[0:12] IO20 These pins are bits 0-12 of the ATA/ATAPI bidirectional data bus. In part number USB97C202-MN-03 or later ROM codes, this pin is high impedance when VBUS is removed. IO Ready IORDY I This pin is the active high IORDY signal from the IDE drive. USB Bus Data USB Transceiver Filter USB Transceiver Bias Termination Resistor Full Speed USB Data USBUSB+ LOOPFLTR USB INTERFACE IO-U These pins connect to the USB bus data signals. This pin provides the ability to supplement the internal filtering of the transceiver with an external network, if required. A 9.09 Kohm precision resistor is attached from ground to this pin to set the transceiver’s internal bias currents. A precision 1.5Kohm precision resistor is attached to this pin from a 3.3V supply. These pins connect to the USB- and USB+ pins through 31.6 ohm series resistors. RBIAS RTERM FSFS+ IO-U Memory Data MD[7:0] Bus Memory Address Bus Memory Write Strobe Memory Read Strobe IO Read Strobe IO Write Strobe MA[15:0] nMWR nMRD nIOR nIOW MEMORY/IO INTERFACE IO12PU When ROMEN=0, these signals are used to transfer data between the internal CPU and the external program memory. When ROMEN=1, a weak internal pull up is activated to prevent these pins from floating. O12 These signals address memory locations within the external memory. O12 Program Memory Write; active low O12 O12 O12 Program Memory Read; active low XDATA space Read; active low XDATA space Write; active low SMSC USB97C202 Page 10 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet XTAL1/ Crystal Input/External CLKIN Clock Input Crystal Output XTAL2 ICLKx OCLKx Clock Output CLKOUT O8 Internal ROM ROMEN Enable IP General Purpose I/O GPIO[1:7] IO20 RESET input nRESET IS Test input nTEST[0:2] IP MISC 12Mhz Crystal or external clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 12Mhz clock when a crystal is not used. 12Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit. This pin produces a 30Mhz clock signal independent of the processor clock divider. It is held inactive and low whenever the internal processor clock is stopped or is being obtained from the ring oscillator. When left unconnected or tied high, the USB97C202 uses the internal ROM for program execution. When tied low, an external program memory should be connected to the memory/data bus. The state of this pin latched internally on the rising edge of nRESET. These general purpose pins may be used either as inputs, edge sensitive interrupt inputs, or outputs. When using internal ROM mode, these pins have the following assignments: GPIO1: USB HS Indicator; active high. In part number USB97C202-MN-03 or later ROM codes, this pin also goes high during USB data transfers. GPIO2: Serial EEPROM (93LC66 type) Chip Select GPIO3: USB VBUS Detect Input GPIO4: Serial EEPROM Data In/OutGPIO5: ATA Drive Reset GPIO6: A16 control line for external program Flash memory when using firmware upgrade capability (external ROM operation only) GPIO7: Serial EEPROM Clock output This active low signal is used by the system to reset the chip. The active low pulse should be at least 100ns wide. These signals are used for testing the chip. User should normally leave them unconnected. For board continuity testing, all pads (except RBIAS, FSDP, USBDP, USBDM, FSDM, RTERM, XTAL1, XTAL2, LOOPFLTR and nTEST[0:2]) are included in an XNOR chain which is enabled by pulling nTEST2 low. nIOR is the output of the chain (the chain begins at pin 2) and will reflect the toggling of a signal on each pin. Circuit board continuity of the pin solder connections after assembly can be checked in this manner SMSC USB97C202 Page 11 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet VDD VDDIO VDDP VSSP VDDA VSSA GND NC POWER, GROUNDS, and NO CONNECTS +2.5V Core power +3.3V I/O power +2.5 Analog power Analog Ground Reference +3.3V Analog power Analog Ground Reference Ground Reference No Connect. These pins should not be connected externally. SMSC USB97C202 Page 12 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet 5.1 Buffer Type Descriptions Table 5.2 - USB97C202 Buffer Type Descriptions BUFFER I IS IP IO8 O8 O12 IO12PU IO12 IO20 O20 O20PU ICLKx OCLKx I/O-U DESCRIPTION Input Input with Schmitt trigger Input with weak pull-up Input/Output with 8 mA drive Output with 8mA drive Output with 12mA drive Input/Output with 12 ma drive and controlled weak pull up Input/Output with 12 ma drive Input/output with 20mA drive Output with 20mA drive Output with 20mA drive and weak pullup XTAL clock input XTAL clock output Defined in USB specification SMSC USB97C202 Page 13 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet Chapter 6 IDE_D7 IDE_D8 IDE_D6 IDE_D9 Typical Application IDE_D[0:15] R1 nRESET 1/8W 1% R2 5.62K 1/8W 1% IDE_DRQ IDE_nIOW IDE_nIOR IORDY IDE_DACK IDE_IRQ IDE_SA1 IDE_SA0 IDE_nCS0 1 1 IDE_D7 IDE_D6 IDE_D5 IDE_D4 IDE_D3 IDE_D2 IDE_D1 IDE_D0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 100 Primary IDE P1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 IDE supports : Mode 1, Mode 2, Mode 3, Mode 4 Ultra DMA 33/66 IDE_D5 IDE_D10 IDE_D4 IDE_D11 IDE_D3 IDE_D12 IDE_D2 IDE_D13 2 IDE_SA2 IDE_nCS1 1 1 C1 0.047uF 25V 10% 2 2 R6 2.21K 1/8W 1% DVDD 1 R8 4.75K 1/8W 1% 1 1 2 R9 332 1/8W 1% IDE_D1 IDE_D14 IDE_D0 IDE_D15 R7 1.0K 1/8W 1% 2 DVDD 1 R7 1.0K 1/8W 1% 2 DVDD 2 LED1 T1 GREEN GPIO3 2 1M R14 R 13 10K VDD VCCEXT DVDD FS1 R11 31.6 2 R12 31.6 2 USB1 2 3 4 P2 VCC DD+ GND FS+ C2 .1uF C3 .1uF C4 .1uF C5 .1uF C6 .1uF C7 .1uF C8 .1uF C9 .1uF C10 .1uF 1 USB+ USB TYPE B 3.3V Regulator VCCEXT R15 9.09K 1/10W 1% 1 3 + 2 C11 10uF 1 VR1 VIN VOUT 2 + VDDIO C12 10uF IDE_nIOW IDE_nCS0 IDE_nCS1 IDE_SA0 IDE_SA2 IDE_nIOR IDE_DACK IDE_SA1 IDE_D13 IDE_IRQ IDE_D14 IDE_DRQ IDE_D15 4 4 4 1 4 6 3 5 4 9 3 4 3 6 3 9 3 1 3 3 3 7 2 9 3 0 4 0 4 7 7 8 7 7 8 7 7 6 8 0 8 1 7 9 VDD VDDIO IDE_D12 IDE_D11 IDE_D10 IDE_D9 IDE_D8 IDE_D7 IDE_D6 IDE_D5 IDE_D4 IDE_D3 IDE_D2 IDE_D1 IDE_D0 IORDY GPIO2 GPIO3 3 51 54 56 57 60 52 62 61 58 55 53 83 50 48 45 43 42 38 75 74 73 72 70 90 VDDIO IDE_D12 IDE_D11 GND IDE_D10 IDE_D9 VDDIO IDE_D8 IDE_D7 IDE_D6 IDE_D5 IDE_D4 VSSA IDE_D3 IDE_D2 IDE_D1 IDE_D0 VDDIO IORDY ROMEN GPIO1 GPIO2 GPIO3 GPIO4 N.C. 6 9 VDDA FS + FS UB S+ UB SR16 1.5K 1/10W 5% M1 A5 M1 A4 GD N VDDIO,VDDA VDDIO 2.5V Regulator VCCEXT 3 8 2 VR2 VIN VOUT 2 + VDD C19 10uF C13 .1uF C14 .1uF C15 .1uF C16 .1uF C17 .1uF ID _ IO En W ID _ R ED Q ID _ Q E IR ID _ A K ED C L OFT OPLR ID _ IO En R ID _ A ES 1 ID _ A ES 2 ID _ A ES 0 ID _ 1 ED5 ID _ 1 ED4 ID _ 1 ED3 ID _ C 1 En S ID _ C 0 En S REM TR FS + R IA BS VD DA UB S+ GD N GD N M1 A5 M1 A4 UB S- FS - USB97C202 X A 1 L IN T L /C K CK U LOT n EE RST nET TS0 nET TS1 nET TS2 VD D IO G IO P6 G IO P7 nW MR G IO P5 X A2 TL GD N nR MD nW IO VS SP nR IO GD N VD D IO VD D M7 D M6 D M5 D N. .C N. .C U3 8 7 6 5 1 nRESET 2 3 4 R18 1K Q1 VDD MA13 MA12 GND MA11 MA10 MA9 MA8 MA7 VDDIO MA6 MA5 MA4 MA3 GND MA2 MA1 MA0 VDD MD0 MD1 MD2 MD3 MD4 VDDP 59 8 9 7 11 12 13 14 16 15 17 18 19 21 95 22 23 24 32 99 98 97 96 94 88 U1 MA13 MA12 MA11 MA10 MA9 MA8 MA7 + C18 10uF 1 MA[0:15] MA6 MA5 MA4 MA3 MA2 MA1 MA0 13 14 15 17 18 19 20 21 GD N 5 6 D0 D1 D2 D3 D4 D5 D6 D7 2 30 NC NC 10 0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE WE VPP 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 22 24 31 1 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 6 3 6 8 6 7 7 1 6 6 6 5 8 4 8 5 8 6 1 0 6 4 2 7 2 5 2 6 2 8 2 0 9 1 9 2 9 3 8 9 VCC N.C. N.C. VSS CS CLK DI DO VDDIO 32 16 4 1 2 VCC GND U2 VDDIO 93LC66A Serial EEPROM Y1 R17 R3 120 C21 22pf D1 LED Size C Date: 39VF512-70 or e quiv OTP/EPROM 10K OPTIONAL for test purposes only, if used tie ROMEN low;otherwise do not populate 12.00Mhz C22 22pf C20 1µf Title USB97C202 T ypical Application Document Number Friday , June 07, 2002 Sheet 1 of 1 Rev A SMSC USB97C202 Page 14 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet Chapter 7 7.1 DC Parameters Maximum Guaranteed Ratings Operating Temperature Range........................................................................................................................... 0oC to +70oC Storage Temperature Range ............................................................................................................................-55o to +150oC Lead Temperature Range (soldering, 10 seconds) ..................................................................................................... +325oC Positive Voltage on any pin, with respect to Ground ........................................................................................................ 5.5V Negative Voltage on any pin, with respect to Ground......................................................................................................-0.3V Maximum VDDA, VDDIO ......................................................................................................................................................+4.0V Maximum VDD, VDDP .........................................................................................................................................................+3.0V *Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used. Table 7.1 - DC Electrical Characteristics (TA = 0°C - 70°C, VDDIO, VDDA = +3.3 V ± 10%, VDD, VDDP = +2.5 V ± 10%,) PARAMETER I Type Input Buffer Low Input Level High Input Level ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage VILI VIHI 2.0 0.8 V V TTL Levels SYMBOL MIN TYP MAX UNITS COMMENTS VILCK VIHCK 2.2 0.4 V V IIL IIH -10 -10 +10 +10 uA uA VIN = 0 VIN = VDDIO SMSC USB97C202 Page 15 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet PARAMETER O8 Type Buffer Low Output Level SYMBOL MIN TYP MAX UNITS COMMENTS VOL 0.4 V IOL = 8 mA @ VDDIO = 3.3V High Output Level VOH 2.4 V IOH = -4mA @ VDDIO = 3.3V Output Leakage IOL -10 +10 uA VIN = 0 to VDDIO (Note 7.1) I/O8 Type Buffer Low Output Level VOL 0.4 V IOL = 8 mA @ VDDIO = 3.3V High Output Level VOH 2.4 V IOH = -4 mA @ VDDIO = 3.3V Output Leakage IOL -10 +10 µA VIN = 0 to VDDIO (Note 7.1, Note 7.3) I/O12 Type Buffer Low Output Level VOL 0.4 V IOL = 12 mA @ VDDIO = 3.3V High Output Level VOH 2.4 V IOH = -6mA @ VDDIO = 3.3V Output Leakage I/O20 Type Buffer Low Output Level IOL -10 +10 µA VIN = 0 to VDDIO (Note 7.1, Note 7.3) VOL 0.4 V IOL = 20 mA @ VDDIO = 3.3V High Output Level VOH 2.4 V IOH = -5 mA @ VDDIO = 3.3V Output Leakage IOL -10 +10 µA VIN = 0 to VDDIO (Note 7.1, Note 7.3) SMSC USB97C202 Page 16 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet PARAMETER IO-U Note 7.2 Supply Current Unconfigured Supply Current Active SYMBOL MIN TYP MAX UNITS COMMENTS ICCINIT ICC 65 85 85 120 mA mA mA mA VDDIO, VDDA VDD, VDDP VDDIO, VDDA VDD, VDDP Note 7.1 Note 7.2 Note 7.3 Output leakage is measured with the current pins in high impedance. See appendix A for USB DC electrical characteristics. Output leakage is valid only on pins without internal weak pull ups or pull downs. 7.1.1 Capacitance TA = 25°C; FC = 1MHz; VDD = 2.5V SYMBOL CIN CIN COUT LIMITS MIN TYP MAX 20 10 20 UNIT TEST CONDITION pF All pins except USB pins (and pins under test tied pF to AC ground) pF PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SMSC USB97C202 Page 17 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet Chapter 8 8.1 AC Specifications ATA/ATAPI The USB97C202 conforms to all timing diagrams and specifications for ATAPI-5 as set forth in the T13/1321D Revision 3 NCITS specification. Please refer to this specification for more information. 8.2 USB 2.0 Timing The USB97C202 conforms to all timing diagrams and specifications for USB peripheral silicon building blocks as set forth in the USB-IF USB 2.0 specification. Please refer to this specification for more information. SMSC USB97C202 Page 18 Revision 1.6 (01-09-07) DATASHEET USB 2.0 ATA/ATAPI Controller Datasheet Chapter 9 Package Outline Figure 9.1 - 100-Pin STQFP Package Outline, 12x12x1.4 Body, 2MM Footprint (Rev A) Table 9.1 - 100-Pin STQFP Package Parameters (Rev A) NOMINAL MAX REMARKS ~ 1.60 Overall Package Height ~ 0.15 Standoff ~ 1.45 Body Thickness ~ 14.20 X Span ~ 12.20 X body Size ~ 14.20 Y Span ~ 12.20 Y body Size ~ 0.20 Lead Frame Thickness 0.60 0.75 Lead Foot Length 1.00 ~ Lead Length 0.40 Basic Lead Pitch ~ 7o Lead Foot Angle 0.16 0.23 Lead Width ~ ~ Lead Shoulder Radius ~ 0.20 Lead Foot Radius ~ 0.08 Coplanarity A A1 A2 D D1 E E1 H L L1 e o 0 θ 0.13 W 0.08 R1 0.08 R2 ~ ccc Notes: 1. Controlling Unit: millimeter. 2. Tolerance on the true position of the leads is ± 0.035 mm maximum. 3. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated. MIN ~ 0.05 1.35 13.80 11.80 13.80 11.80 0.09 0.45 ~ SMSC USB97C202 Page 19 Revision 1.6 (01-09-07) DATASHEET