USB97C211

USB97C211 ADVANCE INFORMATION Rev 1.3 USB 2.0 Flash Media Controller FEATURES Complete USB Specification 2.0 Compatibility - Includes USB 2.0 Transceiver - A Bi-directional Control and a Bi-directional Bulk Endpoint are provided. Complete System Solution for interfacing CompactFlash (CF) and SmartMedia (SM) devices to USB 2.0 bus* - Supports USB Bulk Only Mass Storage Compliant Bootable BIOS - Support for the following devices: - CF: 300K – 15MB/sec - SM: 2M –15MB/sec - Support for simultaneous operation of both the above devices. - Enhanced CF support to allow true sequential read operations to improve throughput 16 GPIOs for special function use: LED indicators, button inputs, power control to memory devices, etc. - Inputs capable of generating interrupts with either edge sensitivity - One GPIO has automatic 1 sec toggle capability for flashing an LED indicator. 8051 8 bit microprocessor - Provides low speed control functions - 30 Mhz execution speed at 4 cycles per instruction average - 12K Bytes of internal SRAM for general purpose scratchpad - 768 Bytes of internal SRAM for general purpose scratchpad or program execution while reflashing external ROM Double Buffered Bulk Endpoint - Bi-directional 512 Byte Buffer for Bulk Endpoint - 64 Byte RX Control Endpoint Buffer - 64 Byte TX Control Endpoint Buffer External Program Memory Interface - 64K Byte Code Space - Flash, SRAM, or EPROM Memory On Board 12Mhz Crystal Driver Circuit Internal PLL for 480Mhz USB2.0 Sampling, 30Mhz MCU clock Supports firmware upgrade via USB bus if “boot block” Flash program memory is used 2.5 Volt, Low Power Core Operation 3.3 Volt I/O with 5V input tolerance 128 Pin TQFP (1.0 mm height package) or QFP Package ORDERING INFORMATION Order Number(s): USB97C211-NE for TQFP Package USB97C211-NC for QFP Package SMSC USB97C211 Page 1 Revision 1.3 (11-05-03) DATASHEET © STANDARD MICROSYSTEMS CORPORATION (SMSC) 2003 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Standard Microsystems and SMSC are registered trademarks of Standard Microsystems Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC USB97C211 Page 2 Revision 1.3 (11-05-03) DATASHEET 1 GENERAL DESCRIPTION The USB97C211 is a USB2.0 Bulk Only Mass Storage Class Peripheral Controller intended for supporting CompactFlash (CF), in True IDE Mode only, and SmartMedia (SM) flash memory devices. It provides a single chip solution for the most popular flash memory cards in the market.* The device consists of a USB 2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded scratchpad, and program SRAM, and CF/SM controllers.* Provisions for external Flash Memory up to 64K bytes for program storage is provided. 12K bytes of scratchpad SRAM and 768Bytes of program SRAM are also provided. Sixteen GPIO pins are for the 128-pin device. Provisions are made to allow hot swap of flash media to be implemented. The USB97C211 supports the insertion of cards (CF, SM) simultaneously. SMSC provides the following object code software free of charge with purchase of the USB97C211**: Multiple LUN Mass Storage Class compliant firmware to support all media types in a single code image, with option for firmware download via USB if a sector erasable program memory is used. Windows application for programming VID/PID/OEM strings, and unique serial number into serial EEPROM via USB. Serial EEPROM may be eliminated entirely if appropriate firmware and specific Flash device is used for program code. Firmware with field upgrade capability via USB (requires specific 128KB Flash for firmware storage). Source code licenses are also available for USB97C211 customers.** SMSC may make complete internal specifications available for those customers requiring programming information, subject to SMSC’s applicable Proprietary Information Agreement (nondisclosure agreement). Contact your SMSC sales representative for more information. Note: * In order to develop, make, use, or sell readers and/or other products using or incorporating any of the SMSC devices made the subject of this document or to use related SMSC software programs, technical information and licenses under patent and other intellectual property rights from or through various persons or entities, including without limitation media standard companies, forums, and associations, and other patent holders may be required. These media standard companies, forums, and associations include without limitation the following: Sony Corporation (Memory Stick), SD3 LLC (Secure Digital/MultiMediaCard), the SSFDC Forum (SmartMedia), and the Compact Flash Association (Compact Flash). SMSC does not make such licenses or technical information available; does not promise or represent that any such licenses or technical information will actually be obtainable from or through the various persons or entities (including the media standard companies, forums, and associations), or with respect to the terms under which they may be made available; and is not responsible for the accuracy or sufficiency of, or otherwise with respect to, any such technical information. SMSC's obligations (if any) under the Terms of Sale Agreement, or any other agreement with any customer, or otherwise, with respect to infringement, including without limitation any obligations to defend or settle claims, to reimburse for costs, or to pay damages, shall not apply to any of the devices made the subject of this document or any software programs related to any of such devices, or to any combinations involving any of them, with respect to infringement or claimed infringement of any existing or future patents related to solid state disk or other flash memory technology or applications (“Solid State Disk Patents”). By making any purchase of any of the devices made the subject of this document, the customer represents, warrants, and agrees that it has obtained all necessary licenses under then-existing Solid State Disk Patents for the manufacture, use and sale of solid state disk and other flash memory products and that the customer will timely obtain at no cost or expense to SMSC all necessary licenses under Solid State Disk Patents; that the manufacture and testing by or for SMSC of the units of any of the devices made the subject of this document which may be sold to the customer, and any sale by SMSC of such units to the customer, are valid exercises of the customer’s rights and licenses under such Solid State Disk Patents; that SMSC shall have no obligation for royalties or otherwise under any Solid State Disk Patents by reason of any such manufacture, use, or sale of such units; and that SMSC shall have no obligation for any costs or expenses related to the customer’s obtaining or having obtained rights or licenses under any Solid State Disk Patents. SMSC USB97C211 Page 3 Revision 1.3 (11-05-03) DATASHEET SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR OTHER VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES AGAINST INFRINGEMENT AND THE LIKE. No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark, copyright, mask work right, trade secret, or other intellectual property right. **To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect. Forms of these Software License Agreements may be obtained by contacting SMSC. SMSC USB97C211 Page 4 Revision 1.3 (11-05-03) DATASHEET TABLE OF CONTENTS 1 2 GENERAL DESCRIPTION.................................................................................................................................3 PIN TABLE.........................................................................................................................................................6 2.1 By Interface................................................................................................................................... 6 2.2 Pin Numbers ................................................................................................................................. 7 2.2.1 128 Pin VTQFP.......................................................................................................................... 7 2.2.2 128 Pin QFP .............................................................................................................................. 8 3 PIN CONFIGURATION ......................................................................................................................................9 3.1 3.2 4 5 128 Pin VTQFP.............................................................................................................................. 9 128 Pin QFP ................................................................................................................................ 10 BLOCK DIAGRAM ...........................................................................................................................................11 PIN DESCRIPTIONS........................................................................................................................................12 5.1 5.2 6 Pin Descriptions......................................................................................................................... 12 Buffer Type Descriptions .......................................................................................................... 16 DC PARAMETERS ..........................................................................................................................................17 6.1 7 Maximum Guaranteed Ratings ................................................................................................. 17 PACKAGE OUTLINES.....................................................................................................................................20 7.1 7.2 8 9 10 128 Pin VTQFP Package Outline, 14X14X1.0 Body, 2 MM Footprint .................................... 20 128 Pin QFP Package Outline, 14X20X2.7 Body, 3.9 MM Footprint ...................................... 21 TYPICAL APPLICATION .................................................................................................................................22 REFERENCES .................................................................................................................................................23 USB97C211 REVISIONS .................................................................................................................................24 SMSC USB97C211 Page 5 Revision 1.3 (11-05-03) DATASHEET 2 2.1 PIN TABLE By Interface CompactFlash Interface (28 Pins) CF_D1 CF_D2 CF_D5 CF_D6 CF_D9 CF_D10 CF_D13 CF_D14 CF_nIOW CF_IRQ CF_nCS0 CF_nCS1 CF_SA2 CF_nCD1 SmartMedia Interface (17 Pins) SM_D1 SM_D2 SM_D5 SM_D6 SM_CLE SM_nRE SM_nB/R SM_nCE USB Interface (7 Pins) USBLOOPFLTR FS+ FSMemory/IO Interface (29 Pins) MA1 MA2 MA5 MA6 MA9 MA10 MA13 MA14 MD1 MD2 MD5 MD6 nMWR nMCE nIOR Misc (21 Pins) GPIO1/TXD GPIO2/T0 GPIO5 GPIO6 XTAL2 nRESET GPIO9 GPIO10 GPIO13 GPIO14 nTEST1 Power, Grounds (15 Pins) No Connects (11 Pins) Total 128 CF_D0 CF_D4 CF_D8 CF_D12 CF_nIOR CF_IORDY CF_SA1 SM_D0 SM_D4 SM_ALE SM_nWP SM_nWPS USB+ RTERM MA0 MA4 MA8 MA12 MD0 MD4 nMRD nIOW GPIO0/RXD GPIO4 XTAL1/CLKIN GPIO8 GPIO12 nTEST0 CF_D3 CF_D7 CF_D11 CF_D15 CF_nRESET CF_SA0 CF_nCD2 SM_D3 SM_D7 SM_nWE SM_nCD RBIAS MA3 MA7 MA11 MA15 MD3 MD7 GPIO3/nWE GPIO7 GPIO11 GPIO15 SMSC USB97C211 Page 6 Revision 1.3 (11-05-03) DATASHEET 2.2 2.2.1 Pin Numbers 128 PIN VTQFP NAME MA1 MA2 MA3 VDDIO MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 VDDCORE MA13 MA14 MA15 MD0 MD1 MD2 MD3 MD4 VSSIO MD5 MD6 MD7 nMRD nMWR nMCE nIOW nIOR N.C. MA 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PIN # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME TEST3 TEST4 TEST5 N.C. N.C. PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 N.C. N.C. N.C. VDDIO N.C. TEST2 CF_D0 CF_D1 CF_D2 CF_D3 CF_D4 CF_D5 CF_D6 VSSIO VSSCORE CF_D7 CF_D8 CF_D9 CF_D10 CF_D11 CF_D12 CF_D13 CF_D14 CF_D15 CF_nCD1 CF_nCD2 CF_IRQ MA 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 - PIN # NAME 65 CF_IORDY 66 CF_nIOR 67 CF_nIOW 68 CF_nRESET 69 CF_nCS0 70 CF_nCS1 71 CF_SA0 72 CF_SA1 73 CF_SA2 74 VDDIO 75 SM_D0 76 SM_D1 77 SM_D2 78 SM_D3 79 VSSIO 80 SM_D4 81 VDDCORE 82 SM_D5 83 SM_D6 84 SM_D7 85 SM_ALE 86 SM_CLE 87 SM_nRE 88 SM_nWE 89 SM_nWP 90 SM_nCE 91 SM_nWPS 92 SM_nB/R 93 SM_nCD 94 nRESET 95 nTEST0 96 nTEST1 MA PIN # NAME MA 97 RBIAS 8 98 VDDA 8 99 FS+ 8 100 USB+ 8 101 USB8 102 FS8 103 RTERM 8 104 VSSA 8 105 XTAL1 106 XTAL2 8 107 VSSP 8 108 LOOPFLTR 8 109 VDDP 8 110 GPIO0 8 111 GPIO1 8 8 112 GPIO2 8 8 113 GPIO3 8 8 114 VSSCORE 115 GPIO4 8 8 116 GPIO5 8 8 117 GPIO6 8 8 118 GPIO7 8 8 119 GPIO8 8 8 120 GPIO9 8 8 121 GPIO10 8 8 122 GPIO11 8 123 GPIO12 8 124 VSSIO 125 GPIO13 8 126 GPIO14 8 127 GPIO15 8 128 MA0 8 SMSC USB97C211 Page 7 Revision 1.3 (11-05-03) DATASHEET 2.2.2 PIN # 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 128 PIN QFP NAME MA1 MA2 MA3 VDDIO MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 VDDCORE MA13 MA14 MA15 MD0 MD1 MD2 MD3 MD4 VSSIO MD5 MD6 MD7 nMRD nMWR nMCE nIOW nIOR N.C. MA 8 8 8 PIN # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 NAME TEST3 TEST4 TEST5 N.C. N.C. N.C. N.C. N.C. VDDIO N.C. MA 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 - TEST2 CF_D0 CF_D1 CF_D2 CF_D3 CF_D4 CF_D5 CF_D6 VSSIO VSSCORE CF_D7 CF_D8 CF_D9 CF_D10 CF_D11 CF_D12 CF_D13 CF_D14 CF_D15 CF_nCD1 CF_nCD2 CF_IRQ 8 8 8 8 8 8 8 8 8 - PIN # NAME MA PIN # NAME MA 68 CF_IORDY 100 RBIAS 69 CF_nIOR 8 101 VDDA 70 CF_nIOW 8 102 FS+ 71 CF_nRESE 8 103 USB+ T 72 CF_nCS0 8 104 USB73 CF_nCS1 8 105 FS74 CF_SA0 8 106 RTERM 75 CF_SA1 8 107 VSSA 76 CF_SA2 8 108 XTAL1 77 VDDIO 109 XTAL2 78 SM_D0 8 110 VSSP 79 SM_D1 8 111 LOOPFLT R 80 SM_D2 8 112 VDDP 81 SM_D3 8 113 GPIO0 8 82 VSSIO 114 GPIO1 8 83 SM_D4 8 115 GPIO2 8 84 VDDCORE 116 GPIO3 8 85 SM_D5 8 117 VSSCORE 86 SM_D6 8 118 GPIO4 8 87 SM_D7 8 119 GPIO5 8 88 SM_ALE 8 120 GPIO6 8 89 SM_CLE 8 121 GPIO7 8 90 SM_nRE 8 122 GPIO8 8 91 SM_nWE 8 123 GPIO9 8 92 SM_nWP 8 124 GPIO10 8 93 SM_nCE 8 125 GPIO11 8 94 SM_nWPS 126 GPIO12 8 95 SM_nB/R 127 VSSIO 96 SM_nCD 128 GPIO13 8 97 nRESET 1 GPIO14 8 98 nTEST0 2 GPIO15 8 99 nTEST1 3 MA0 8 SMSC USB97C211 Page 8 Revision 1.3 (11-05-03) DATASHEET 3 3.1 PIN CONFIGURATION 128 Pin VTQFP 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 MA0 GPIO15 GPIO14 GPIO13 VSSIO GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 VSSCORE GPIO3 GPIO2 GPIO1 GPIO0 VDDP LOOPFLTR VSSP XTAL2 XTAL1 VSSA RTERM FSUSBDUSBD+ FS+ VDDA RBIAS MA1 MA2 MA3 VDDIO MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 VDDCORE MA13 MA14 MA15 MD0 MD1 MD2 MD3 MD4 VSSIO MD5 MD6 MD7 nMRD nMWR nMCE nIOW nIOR N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 USB97C211 nTEST1 nTEST0 nRESET SM_nCD SM_nB/R SM_nWPS SM_nCE SM_nWP SM_nWE SM_nRE SM_CLE SM_ALE SM_D7 SM_D6 SM_D5 VDDCORE SM_D4 VSSIO SM_D3 SM_D2 SM_D1 SM_D0 VDDIO CF_SA2 CF_SA1 CF_SA0 CF_nCS1 CF_nCS0 CF_nRESET CF_nIOW CF_nIOR CF_IORDY SMSC USB97C211 TEST3 TEST4 TEST5 N.C. N.C. N.C. N.C. N.C. VDDIO N.C. TEST2 CF_D0 CF_D1 CF_D2 CF_D3 CF_D4 CF_D5 CF_D6 VSSIO VSSCORE CF_D7 CF_D8 CF_D9 CF_D10 CF_D11 CF_D12 CF_D13 CF_D14 CF_D15 CF_nCD1 CF_nCD2 CF_IRQ Page 9 Revision 1.3 (11-05-03) DATASHEET 3.2 SMSC USB97C211 USB+ USBFSRTERM VSSA XTAL1 XTAL2 VSSP LOOPFLTR VDDP GPIO0 GPIO1 GPIO2 GPIO3 VSSCORE GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 VSSIO GPIO13 128 102 1 128 Pin QFP Page 10 DATASHEET USB97C211 GPIO14 GPIO15 MA0 MA1 MA2 MA3 VDDIO MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 VDDCORE MA13 MA14 MA15 MD0 MD1 MD2 MD3 MD4 VSSIO MD5 MD6 MD7 nMRD nMWR nMCE nIOW nIOR N.C. TEST3 TEST4 TEST5 38 FS+ VDDA RBIAS nTEST1 nTEST0 nRESET SM_nCD SM_nB/R SM_nWPS SM_nCE SM_nWP SM_nWE SM_nRE SM_CLE SM_ALE SM_D7 SM_D6 SM_D5 VDDCORE SM_D4 VSSIO SM_D3 SM_D2 SM_D1 SM_D0 VDDIO CF_SA2 CF_SA1 CF_SA0 CF_nCS1 CF_nCS0 CF_nRESET CF_nIOW CF_nIOR CF_IORDY CF_IRQ CF_nCD2 CF_nCD1 65 Revision 1.3 (11-05-03) CF_D15 CF_D14 CF_D13 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8 CF_D7 VSSCORE VSSIO CF_D6 CF_D5 CF_D4 CF_D3 CF_D2 CF_D1 CF_D0 TEST2 N.C. VDDIO N.C. N.C. N.C. N.C. N.C. 4 BLOCK DIAGRAM Auto address generators 512 Bytes EP2 TX/RX Buffer B 512 Bytes EP2 TX/RX Buffer A 64 Bytes EP1RX 64 Bytes EP1TX 64 Bytes EP0RX EP0RX_BC Address 64 Bytes EP0TX Address EP0TX_BC Address 1.25KB SRAM Flash Media Controllers (FMC) CF Controller Control/ Status Memory Cards Flash Media DMA Unit Data Buss Address MUX EP1TX_BC Address 32 Bit 60MHz DATA EP1RX_BC RAMWR_A/B Address Address CF FMC Data MUX Latch phase 0, 2 SIE Latch phase 3 8051 Latch phase 1 FMC DATA ECC Control/ Status SM Controller Control/ Status RAMRD_A/B Address Address Register Data @ 32 bit 15Mhz SM/SSFDC Clocked byPhase 0, 2 Clock SIE ( Serial Interface Engine ) 32 bit 15MHz Data Buss XDATA & SFR Address and Data busses SIE Control Regs USB 2.0 PHY ( Transciever ) Work Scratchpad SRAM (768 Byte) Configuration and Control GPIO 8 pins Clock Generation 7 pins Interrupt Controller Osc 12K Byte Program/Scratchpad SRAM MEM/IO Bus XTAL 29pins Program Memory/ IO Bus FAST 8051 CPU CORE CLOCKOUT 12 MHz Clocked by Phase 3 Clock SMSC USB97C211 Page 11 Revision 1.3 (11-05-03) DATASHEET 5 PIN DESCRIPTIONS This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “n” symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “n” is not present before the signal name, the signal is asserted when at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of “active low” and “active high” signal. The term assert, or assertion indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive. 5.1 Pin Descriptions NAME BUFFER DESCRIPTION TYPE CompactFlash (In True IDE mode) Interface CF_nCS1 O8 This pin is the active low chip select 1 signal for the CF ATA device SYMBOL CF_nCS0 CF_SA2 CF_SA1 CF_SA0 CF_IRQ O8 O8 O8 O8 IPD This pin is the active low chip select 0 signal for the task file registers of CF ATA device in the True IDE mode. This pin is the register select address bit 2 for the CF ATA device. Address signal 1 for the task file registers, when the CFC is enabled in True IDE mode Address signal 0 for the task file registers, when the CFC is enabled in True IDE mode. This is the active high interrupt request signal from the CF device. This pin has an internal weak pull-down resistor. The bi-directional data signals CF_D15-CF_D8 in True IDE mode data transfer, when the CFC is enabled. In the True IDE Mode, all of task file register operation occur on the CF_D[7:0], while the data transfer is on CF_D[15:0]. These pins have an internal weak pull-down resistor. The bi-directional data signals CF_D7-CF_D0 in the True IDE mode data transfer. In the True IDE Mode, all of task file register operation occur on the CF_D[7:0], while the data transfer is on CF_D[15:0]. These pins have an internal weak pull-down resistor. This pin is active high input signal with an internal weak pull-up resistor. This card detection pin is connected to the ground on the CF device, when the CF device is inserted. This pin has an internal weak pull-up resistor. This card detection pin is connected to ground on the CF device, when the CF device is inserted. This pin has an internal weak pull-up resistor. CF Chip Select 1 CF Chip Select 0 CF Register Address 2 CF Register Address 1 CF Register Address 0 CF Interrupt CF Data 15-8 CF_D[15:8] IO8 CF Data7-0 CF_D[7:0] IO8 IO Ready CF Card Detection2 CF_IORDY CF_nCD2 IPU IPU CF Card Detection1 CF_nCD1 IPU SMSC USB97C211 Page 12 Revision 1.3 (11-05-03) DATASHEET NAME CF Hardware Reset CF IO Read CF IO Write Strobe SM Write Protect SM Address Strobe SM Command Strobe SM Data7-0 SYMBOL CF_nRESET CF_nIOR CF_nIOW BUFFER DESCRIPTION TYPE O8 This pin is an active low hardware reset signal to CF device. O8 O8 This pin is an active low read strobe signal for CF device, when the CFC is enabled. This pin is an active low write strobe signal for CF device, when the CFC is enabled. SM_nWP SM_ALE SM_CLE SM_D[7:0] SmartMedia Interface O8 This pin is an active low write protect signal for the SM device, when the SMC is enabled. O8 O8 IO8 This pin is an active high Address Latch Enable signal for the SM device, when the SMC is enabled This pin is an active high Command Latch Enable signal for the SM device, when the SMC is enabled. These pins are the bi-directional data signal SM_D7SM_D0, when the SMC is enabled. The bi-directional input signal should have an internal weak pull-up resister on the input. This pin is an active low read strobe signal for SM device, when SMC is enabled. This pin is an active low write strobe signal for SM device, when SMC is enabled. A write-protect seal is detected, when this pin is low. This pin has an internal weak pull-up resistor. This pin is connected to the BSY/RDY pin of the SM device. This pin has an internal weak pull-up resistor. This pin is the active low chip enable signal to the SM device. This pin has an internal weak pull-up resistor. This is the card detection signal from SM device to indicate if the device is inserted. This pin has internal weak pull-up resistor. SM Read Enable SM Write Enable SM Write Protect Switch SM Busy or Data Reday SM_nRE SM_nWE SM_nWPS O8 O8 IPU SM_nB/R IPU SM Chip Enable SM_nCE O8 SM Card Detection SM_nCD IPU SMSC USB97C211 Page 13 Revision 1.3 (11-05-03) DATASHEET NAME USB Bus Data USB Transceiver Filter SYMBOL USBUSB+ LOOPFLTR BUFFER DESCRIPTION TYPE USB Interface IO-U These pins connect to the USB bus data signals. This pin provides the ability to supplement the internal filtering of the transceiver with an external network, if required. This pin is normally not connected. A precision 10.0K resistor is attached from ground to this pin to set the transceiver’s internal bias currents. A precision 1.5K resistor is attached to this pin from a 3.3V supply. These pins connect to the USB- and USB+ pins through 39.2 ohm series resistors. USB Transceiver Bias Termination Resistor Full Speed USB Data RBIAS RTERM FSFS+ MD[7:0] MA[15:0] IO-U Memory Data Bus Memory Address Bus Memory Write Strobe Memory Read Strobe nMWR nMRD Memory Chip Enable nMCE I/O Read Strobe I/O Write Strobe Crystal Input/External Clock Input nIOR nIOW. XTAL1/ CLKIN Crystal Output XTAL2 General Purpose I/O GPIO0 /RXD Memory/IO Interface IO8 These signals are used to transfer data between the internal CPU and the external program memory. O8 These signals address memory locations within the external memory. Memory access time should be 80 ns or less. O8 Program Memory Write; active low O8 Program Memory Read; active low. Memory output enable time (assuming this signal is used for this memory function) must be 80 ns or less. O8 Program Memory Chip Enable; active low. This signal shall be deasserted, when the USB97C211 is in power down mode (USB SUSPEND). O8 This is an active low I/O Read strobe signal of MD bus. O8 This is an active low I/O Write strobe signal of MD bus. Misc ICLKx 12Mhz Crystal or external clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 12Mhz clock when a crystal is not used. OCLKx 12Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit. I/O8 This pin may be used either as input, edge sensitive interrupt input, or output. In addition to the above, this port has the capability of auto-toggling at a 1 Hz rate when used as an output. As an input, the GPIO0 can also be used as input to the RXD of a UART in the device for firmware debug purposes. Note: This pin defaults as an input and should be terminated to a supply via a high value resistor to avoid a floating input condition. SMSC USB97C211 Page 14 Revision 1.3 (11-05-03) DATASHEET NAME General Purpose I/O SYMBOL GPIO1 /TXD BUFFER DESCRIPTION TYPE I/O8 This pin may be used either as input, edge sensitive interrupt input, or output. In addition, as an output, the GPIO1 can also be used as an output TXD of a UART in the device for firmware debug purposes. Note: This pin defaults as an input and should be terminated to a supply via a high value resistor to avoid a floating input condition. General Purpose I/O GPIO2 /T0 I/O8 This pin may be used either as input, edge sensitive interrupt input, or output. In addition, the pin can be used as the internal 8051 “T0 timer P3.4” output. Note: This pin defaults as an input and should be terminated to a supply via a high value resistor to avoid a floating input condition. This pin may be used either as input, edge sensitive interrupt input, or output. In addition, the output can be nWE, for use with PCMCIA form factor flash cards with “true IDE” capability. Note: This pin defaults as an input and should be terminated to a supply via a high value resistor to avoid a floating input condition. General Purpose I/O GPIO3 /nWE I/O8 General Purpose I/O General Purpose I/O RESET input TEST Input TEST Input GPIO[7:4] GPIO[15:8] nRESET nTEST[0:1] TEST[2:5] I/O8 I/O8 IS I I This pin may be used either as input, edge sensitive interrupt output, or output. These pins may be used either as input, or output. This active low signal is used by the system to reset the chip. The active low pulse must be at least 100ns wide. These signals are used for testing the chip. User should normally leave them unconnected. These pins are used for testing the chips. They should be tied to ground thru high value resistors for normal operation. SMSC USB97C211 Page 15 Revision 1.3 (11-05-03) DATASHEET VDD VDDIO VDDP VSSP VDDA VSSA GND N.C. POWER, GROUNDS, and NO CONNECTS +2.5V Core power +3.3V I/O power +2.5 Analog power Analog Ground Reference +3.3V Analog power Analog Ground Reference Ground Reference No connection should be made externally 5.2 Buffer Type Descriptions Table 1 - USB97C211 Buffer Type Descriptions BUFFER DESCRIPTION I Input IPU Input with internal weak pull-up resistor. IPD Input with internal weak pull-down resistor. IS Input with Schmitt trigger I/O4 Input/Output with 4mA drive I/OD4 Input/Open drain output … 4mA sink I/O8 Input/Output with 8mA drive I/OD8 Input/Open drain output … 8mA sink O4 Output with 4mA drive O8 Output with 8mA drive I/O12 Output with 12mA drive O12 Output with 12mA drive OD12 Open drain….12mA sink ICLKx XTAL clock input OCLKx XTAL clock output I/O-U Defined in USB specification SMSC USB97C211 Page 16 Revision 1.3 (11-05-03) DATASHEET 6 6.1 DC PARAMETERS Maximum Guaranteed Ratings Operating Temperature Range........................................................................................................................... 0oC to +70oC Storage Temperature Range ............................................................................................................................-55o to +150oC Lead Temperature Range (soldering, 10 seconds) ..................................................................................................... +325oC Positive Voltage on any pin, with respect to Ground ........................................................................................................ 5.5V Negative Voltage on any pin, with respect to Ground......................................................................................................-0.3V Maximum VDD, VDDP ........................................................................................................................................................+3.0V Maximum VDDIO, VDDA ......................................................................................................................................................+4.0V *Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS (TA = 0°C - 70°C, VDDIO,VDA = +3.3 V ± 10%, VDD, VDDP = +2.5 V ± 10%,) PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS I Type Input Buffer Low Input Level High Input Level ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage O8 Type Buffer Low Output Level VILI VIHI 2.0 0.8 V V TTL Levels VILCK VIHCK 2.2 0.4 V V IIL IIH -10 -10 +10 +10 uA uA VIN = 0 VIN = VDDIO VOL 0.4 V IOL = 8 mA @ VDDIO = 3.3V High Output Level VOH 2.4 V IOH = -4mA @ VDDIO = 3.3V Output Leakage IOL -10 +10 uA VIN = 0 to VDDIO (Note 1) SMSC USB97C211 Page 17 Revision 1.3 (11-05-03) DATASHEET PARAMETER I/O8 Type Buffer Low Output Level SYMBOL MIN TYP MAX UNITS COMMENTS VOL 0.4 V IOL = 8 mA @ VDDIO = 3.3V HIGH OUTPUT LEVEL VOH 2.4 V IOH = -4 mA @ VDDIO = 3.3V Output Leakage I/O12 Type Buffer Low Output Level IOL -10 +10 µA VIN = 0 to VDDIO (Note 1) VOL 0.4 V IOL = 12 mA @ VDDIO = 3.3V High Output Level VOH 2.4 V IOH = -6mA @ VDDIO = 3.3V Output Leakage I/O24 Type Buffer Low Output Level IOL -10 +10 µA VIN = 0 to VDDIO (Note 1) VOL 0.4 V IOL = 24 mA @ VDDIO = 3.3V High Output Level VOH 2.4 V IOH = -12 mA @ VDDIO = 3.3V Output Leakage IO-U (Note 2) Supply Current Unconfigured Supply Current Active Supply Current Standby IOL -10 +10 µA VIN = 0 to VDDIO (Note 1) ICCINIT ICC ICSBY 80 60 80 60 4 2 mA 100 70 170 130 mA µA VDD, VDDP = 2.5V VDDA, VDDIO = 3.3V VDD, VDDP = 2.5V VDDA, VDDIO = 3.3V VDD, VDDP = 2.5V VDDA, VDDIO = 3.3V Note 1: Output leakage is measured with the current pins in high impedance. Note 2: See Appendix A for USB DC electrical characteristics. Note 3: Unconfigured and Operating Supply currents are measured in HS mode. Note 4: Standby currents are measured in optimum board configuration and vary depending on system configuration. SMSC USB97C211 Page 18 Revision 1.3 (11-05-03) DATASHEET CAPACITANCE TA = 25°C; fc = 1MHz; VDD = 2.5V PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SYMBOL CIN CIN COUT MIN LIMITS TYP MAX 20 10 20 UNIT TEST CONDITION pF All pins except USB pins (and pins under test tied pF to AC ground) pF SMSC USB97C211 Page 19 Revision 1.3 (11-05-03) DATASHEET 7 7.1 PACKAGE OUTLINES 128 Pin VTQFP Package Outline, 14X14X1.0 Body, 2 MM Footprint A A1 A2 D D1 E E1 H L L1 e θ W R1 R2 ccc Notes: MIN ~ 0.05 0.95 15.80 13.80 15.80 13.80 0.09 0.45 ~ 0 0.13 0.08 0.08 ~ o NOMINAL ~ ~ ~ ~ ~ ~ ~ ~ 0.60 1.00 0.40 Basic ~ 0.18 ~ ~ ~ MAX 1.20 0.15 1.05 16.20 14.20 16.20 14.20 0.20 0.75 ~ 7o 0.23 ~ 0.20 0.08 REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity 1 2 Controlling Unit: millimeter. Tolerance on the true position of the leads is ± 0.035 mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC USB97C211 Page 20 Revision 1.3 (11-05-03) DATASHEET 7.2 128 Pin QFP Package Outline, 14X20X2.7 Body, 3.9 MM Footprint A A1 A2 D D1 E E1 H L L1 e θ W R1 R2 ccc Notes: 1 2 MIN ~ 0.05 2.55 23.70 19.90 17.70 13.90 0.09 0.73 ~ 0 0.10 0.13 0.13 ~ o NOMINAL ~ ~ ~ ~ ~ ~ ~ ~ 0.88 1.95 0.50 Basic ~ ~ ~ ~ ~ MAX 3.4 0.5 3.05 24.10 20.10 18.10 14.10 0.20 1.03 ~ 7o 0.30 ~ 0.30 0.08 REMARKS Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity Controlling Unit: millimeter. Tolerance on the position of the leads is ± 0.04 mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC USB97C211 Page 21 Revision 1.3 (11-05-03) DATASHEET 8 TYPICAL APPLICATION COMPACT FLASH MEDIA SOCKET J1 VCCEXT 3 + C1 10uF 2.5V Regulator VR1 VIN VOUT 2 VDD + C2 10uF + C3 10uF 3.3V Regulator VCCEXT 3 VR2 VIN VOUT 2 + VDDIO C4 10uF GND A10 A09 A08 A07 A06 A05 A04 A03 CSEL# ATASEL# VS1# GND GND VS2# DASP# IOCS16# PDIAG# INPACK# CD2# CD1# A02 A01 A00 CS1# CS0# IORDY RESET# INTRQ IOWR# IORD# D15 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 Compact_Flash_1 VCC VCC REG# WE# 1 38 13 44 36 40 45 24 46 43 25 26 18 19 20 32 7 42 41 37 35 34 31 30 29 28 27 49 48 47 6 5 4 3 2 23 22 21 VDDSM VCC VCC 12 22 17 24 6 7 8 9 13 14 15 16 3 2 20 4 5 19 21 11 23 1 10 18 R6 10 K R7 10 K VDDCF VDDIO,VDDA VDD LVD Card Det. SW1 D0 D1 D2 D3 D4 D5 D6 D7 ALE CLE RE# WE# WP# R/B# CE# CD# Card Det. SW0 GND GND GND 8 10 11 12 14 15 16 17 39 9 33 1 50 C5 .1uF C6 .1uF C7 .1uF C8 .1uF C9 .1uF C10 .1uF C11 .1uF 1 GND R9 R10 VDD VDDCF VDDSM GPIO13 Q1 GPIO14 Q2 69 70 71 72 73 62 63 75 76 79 77 78 80 82 81 83 84 85 86 87 88 89 92 90 93 91 36 40 39 41 CF_nCS0 CF_nCS1 CF_SA0 CF_SA1 CF_SA2 CF_nCD1 CF_nCD2 SM_D0 SM_D1 VSS SM_D2 SM_D3 SM_D4 SM_D5 VDDCORE SM_D6 SM_D7 SM_ALE SM_CLE SM_nRE SM_nWE SM_nWP SM_nB/R SM_nCE SM_nCD SM_nWPS NC NC NC VDDIO VDDIO CF_IORDY CF_nRESET CF_IRQ CF_nIOW CF_nIOR CF_D15 CF_D14 CF_D13 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8 VSS CF_D7 CF_D6 CF_D5 CF_D4 CF_D3 CF_D2 CF_D1 CF_D0 VDDP USB+ FS+ LOOPFLTR RBIAS VSSA RTERM FSUSBVDDA VSSP 74 65 68 64 67 66 61 60 59 58 57 56 55 54 52 53 50 49 48 47 46 45 44 109 100 99 108 97 104 103 102 101 98 107 NC NC TEST2 NC NC TEST4 TEST3 TEST5 XTAL2 nTEST0 nTEST1 XTAL1/CLKIN VSS GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 VSS GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 nRESET nIOR nIOW 38 37 43 42 32 34 33 35 106 95 96 105 114 110 111 112 113 115 116 117 118 124 119 120 121 122 123 125 126 127 94 31 30 GPIO13 GPIO14 GPIO9 GPIO10 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 MA16 GPIO7 R14 R15 R16 R13 SERIAL EEPROM SMSC USB97C211 SMART MEDIA CARD SOCKET J2 8 7 6 5 C12 .1uF C13 .1uF C14 .1uF R1 10.0K 1/10W 1% 1 GPIO3 R2 10K 1M R3 2 USB+ FS+ P1 FSUSBFSF S+ 1 1 R4 39.2 2 2 USBUSB+ 1 2 3 4 VCC DD+ GND R5 39.2 R8 1.5K1/10W 5% VDDIO USB TYPE B Smart_Media VDD 100K VDDIO 100K VDDA U1 USB97C211 (128 pin VTQFP) R11 CF Insertion/ Activity Indicator 100 R12 SM Insertion/ Activity Indicator D1 LED 100 VDDIO MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 VSS MA6 MA5 MA4 MA3 VDDCORE MA2 MA1 MA0 MD0 MD1 MD2 MD3 MD4 VDDIO MD5 MD6 MD7 nMWR nMRD nMCE VSS 17 16 15 13 12 11 10 9 8 23 7 6 5 3 14 2 1 128 18 19 20 21 22 4 24 25 26 28 27 29 51 MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 VDD MA[0:15] 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 1 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MA16 D0 D1 D2 D3 D4 D5 D6 D7 VDDIO VDDIO 30 32 NC VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CE OE WE VPP 16 GND VDDIO D2 LED U2 39VF010 or equiv OTP/EPROM VDDIO R17 10K Note 1: If firmware download is not required,a 64KB Flash (39VF512) can be used. GPIO6 should be not connected. 4x100K VDDIO High Speed INIDICATOR Flash Card Power Control VDDIO 93LC66A Serial EEPROM 1 VCC CS N.C. N.C. U3 CLK DI 2 3 GPIO5 GPIO2 GPIO7 GPIO4 R18 1K HS Indicator Q3 Q4 MOSFET P VDDCF Q5 MOSFET P Y1 GPIO9 C16 22pf GPIO10 Title C15 12.00Mhz C17 22pf 1µf D3 LED 4 VSS DO Note: May be eliminated with appropriate firmware and component utilization for U2 R19 100 VDDSM USB97C211 Typical Application Size Custom Document Number Friday , August 02, 2002 Sheet 1 of 1 Rev D Date: Page 22 Revision 1.3 (11-05-03) DATASHEET 9 1. 2. 3. 4. 5. 6. 7. 8. REFERENCES SmartMedia Electrical Specification Version 1.30 SmartMedia Physical Format Specifications Version 1.30 SmartMedia Logical Format Specifications Version 1.20 SMIL (SmartMedia Interface Library) Software Edition Version 1.00, Toshiba Corporation, 01, July, 2000 SMIL (SmartMedia Interface Library) Hardware Edition Version 1.00, Toshiba Corporation, 01, July, 2000 CompactFlash Specification Rev 1.4 CF+ & CF Specification Rev. ATA-5 Draft 0.2 Universal Serial Bus Specification Rev 2.0 SMSC USB97C211 Page 23 Revision 1.3 (11-05-03) DATASHEET 10 USB97C211 REVISIONS PAGE 17 3 SECTION 6 - DC PARAMETERS 1 - GENERAL DESCRIPTION COMMENT DC ELECTRICAL CHARACTERISTICS – Updated High Input Leakage units. Two bullets under SMSC provides the following object code software free of charge with purchase of the USB97C211** Updated diagram DATE 11-05-03 08-02-02 22 8 - Typical Application 08-02-02 SMSC USB97C211 Page 24 Revision 1.3 (11-05-03) DATASHEET