SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
SN8F27E60 Series
USER’S MANUAL
Version 2.1
SN8F27E65
SN8F27E64
SN8F27E62
SN8F27E65L
SN8F27E64L
SN8F27E63L
SN8F27E62L
SONiX 8-Bit Micro-Controller
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD
Page 1
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
AMENDENT HISTORY
Version
VER 0.1
VER 0.2
Date
Oct. 2009
Dec. 2009
VER 0.3
Dec. 2009
VER 0.4
Jan. 2010
VER 0.5
Feb. 2010
VER 1.0
Jul. 2010
VER 1.1
Jun. 2011
VER 1.2
VER 1.3
VER 1.4
VER 1.5
VER 1.6
VER 1.7
VER 1.8
VER 1.9
VER 2.0
VER 2.1
Jul. 2011
Jun. 2012
May 2013
Mar. 2014
Oct. 2014
Nov. 2014
Jun. 2015
July. 2015
Jan. 2016
May 2017
Description
First issue.
1. Update electrical characteristic.
2. Modify development tool section.
1. Update electrical characteristic.
2. Modify UART section.
1. Update electrical characteristic.
2. Add PB-Free part number.
3. Add QFN package type.
1. Fix SN8F27E65LF pin 31/32 VDD name.
2. Modify Wafer Form part number as “S8F27E65W”.
1. Update electrical characteristic.
2. Modify MSP section.
3. Modify QFN 4x4 package dimension.
1. Update ROM programming pin.
2. Modify QFN 4x4 package dimension.
3. Add AVREFH pin name in SN8F27E64 and SN8F27E62.
4. Modify SN8F27E65 starter-kit section.
5. Update electrical characteristic maximum rating.
1. Add SDIP package type.
1. Add the schematic of SN8F27E65 starter-kit.
1. Modify ADC section.
1. Add SN8F27E63LJ part number.
1. Modify ISP section.
1. Modify QFN 5x5 package dimension.
1. Add Junction temperature specification in electrical characteristic section.
1. Modify Junction temperature specification in electrical characteristic section.
1. Add asynchronous signal description in interrupt section.
1. Modify SN8F27E63L operating voltage in features selection table.
SONiX TECHNOLOGY CO., LTD
Page 2
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
Table of Content
AMENDENT HISTORY ................................................................................................................................ 2
11 PRODUCT OVERVIEW .............................................................................................................................. 8
1.1 FEATURES .............................................................................................................................................. 8
1.2 SYSTEM BLOCK DIAGRAM .............................................................................................................. 10
1.3 PIN ASSIGNMENT ............................................................................................................................... 11
1.4 PIN DESCRIPTIONS ............................................................................................................................. 13
1.5 PIN CIRCUIT DIAGRAMS ................................................................................................................... 14
22 CENTRAL PROCESSOR UNIT (CPU) ................................................................................................... 16
2.1 PROGRAM MEMORY (FLASH ROM) ................................................................................................ 16
2.1.1 RESET VECTOR (0000H) ............................................................................................................. 17
2.1.2 INTERRUPT VECTOR (0008H~0014H) ....................................................................................... 18
2.1.3 LOOK-UP TABLE DESCRIPTION ............................................................................................... 20
2.1.4 JUMP TABLE DESCRIPTION ...................................................................................................... 22
2.1.5 CHECKSUM CALCULATION...................................................................................................... 24
2.2 DATA MEMORY (RAM) ...................................................................................................................... 25
2.2.1 SYSTEM REGISTER ..................................................................................................................... 26
2.2.1.1 SYSTEM REGISTER TABLE ................................................................................................ 26
2.2.1.2 SYSTEM REGISTER DESCRIPTION ................................................................................... 26
2.2.1.3 BIT DEFINITION of SYSTEM REGISTER ........................................................................... 27
2.2.2 ACCUMULATOR .......................................................................................................................... 29
2.2.3 PROGRAM FLAG .......................................................................................................................... 30
2.2.4 PROGRAM COUNTER.................................................................................................................. 31
2.2.5 H, L REGISTERS............................................................................................................................ 34
2.2.6 X REGISTERS ................................................................................................................................ 35
2.2.7 Y, Z REGISTERS............................................................................................................................ 35
2.2.8 R REGISTER .................................................................................................................................. 36
2.2.9 W REGISTERS ............................................................................................................................... 37
2.3 ADDRESSING MODE........................................................................................................................... 38
2.3.1 IMMEDIATE ADDRESSING MODE ........................................................................................... 38
2.3.2 DIRECTLY ADDRESSING MODE .............................................................................................. 38
2.3.3 INDIRECTLY ADDRESSING MODE .......................................................................................... 38
2.4 STACK OPERATION ............................................................................................................................ 39
2.4.1 OVERVIEW .................................................................................................................................... 39
2.4.2 STACK POINTER .......................................................................................................................... 39
2.4.3 STACK BUFFER ............................................................................................................................ 40
2.4.4 STACK OVERFLOW INDICATOR .............................................................................................. 40
2.4.5 STACK OPERATION EXAMPLE................................................................................................. 41
2.5 CODE OPTION TABLE ........................................................................................................................ 42
2.5.1 Fcpu Code Option ............................................................................................................................ 43
2.5.2 Reset_Pin code option ..................................................................................................................... 43
2.5.3 Security code option ........................................................................................................................ 43
2.5.4 Noise Filter code option .................................................................................................................. 43
33 RESET .......................................................................................................................................................... 44
3.1 OVERVIEW ........................................................................................................................................... 44
3.2 POWER ON RESET ............................................................................................................................... 45
3.3 WATCHDOG RESET ............................................................................................................................ 45
3.4 BROWN OUT RESET ........................................................................................................................... 45
3.4.1 THE SYSTEM OPERATING VOLTAGE ..................................................................................... 46
SONiX TECHNOLOGY CO., LTD
Page 3
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
3.4.2 LOW VOLTAGE DETECTOR (LVD) .......................................................................................... 46
3.4.3 BROWN OUT RESET IMPROVEMENT...................................................................................... 48
3.5 EXTERNAL RESET .............................................................................................................................. 49
3.6 EXTERNAL RESET CIRCUIT ............................................................................................................. 49
3.6.1 Simply RC Reset Circuit ................................................................................................................. 49
3.6.2 Diode & RC Reset Circuit ............................................................................................................... 50
3.6.3 Zener Diode Reset Circuit ............................................................................................................... 50
3.6.4 Voltage Bias Reset Circuit .............................................................................................................. 51
3.6.5 External Reset IC ............................................................................................................................. 51
44 SYSTEM CLOCK ....................................................................................................................................... 52
4.1 OVERVIEW ........................................................................................................................................... 52
4.2 FCPU (INSTRUCTION CYCLE) ............................................................................................................ 52
4.3 NOISE FILTER ...................................................................................................................................... 52
4.4 SYSTEM HIGH-SPEED CLOCK .......................................................................................................... 52
4.4.1 HIGH_CLK CODE OPTION .......................................................................................................... 53
4.4.2 INTERNAL HIGH-SPEED OSCILLATOR RC TYPE (IHRC) .................................................... 53
4.4.3 EXTERNAL HIGH-SPEED OSCILLATOR .................................................................................. 53
4.4.4 EXTERNAL OSCILLATOR APPLICATION CIRCUIT .............................................................. 53
4.5 SYSTEM LOW-SPEED CLOCK ........................................................................................................... 54
4.6 OSCM REGISTER ................................................................................................................................. 54
4.7 SYSTEM CLOCK MEASUREMENT ................................................................................................... 55
4.8 SYSTEM CLOCK TIMING ................................................................................................................... 55
55 SYSTEM OPERATION MODE ................................................................................................................ 58
5.1 OVERVIEW ........................................................................................................................................... 58
5.2 NORMAL MODE................................................................................................................................... 59
5.3 SLOW MODE......................................................................................................................................... 60
5.4 POWER DOWN MDOE......................................................................................................................... 60
5.5 GREEN MODE....................................................................................................................................... 61
5.6 OPERATING MODE CONTROL MACRO .......................................................................................... 62
5.7 WAKEUP ............................................................................................................................................... 63
5.7.1 OVERVIEW .................................................................................................................................... 63
5.7.2 WAKEUP TIME ............................................................................................................................. 63
5.7.3 P1W WAKEUP CONTROL REGISTER ....................................................................................... 64
66 INTERRUPT ................................................................................................................................................ 65
6.1 OVERVIEW ........................................................................................................................................... 65
6.2 INTERRUPT OPERATION ........................................................................................................................... 66
6.3 INTEN INTERRUPT ENABLE REGISTER ......................................................................................... 67
6.4 INTRQ INTERRUPT REQUEST REGISTER ....................................................................................... 68
6.5 GIE GLOBAL INTERRUPT OPERATION .......................................................................................... 69
6.6 EXTERNAL INTERRUPT OPERATION (INT0~INT1) ...................................................................... 70
6.7 T0 INTERRUPT OPERATION .............................................................................................................. 71
6.8 TC0 INTERRUPT OPERATION ........................................................................................................... 72
6.9 TC1 INTERRUPT OPERATION ........................................................................................................... 73
6.10 TC2 INTERRUPT OPERATION ......................................................................................................... 74
6.11 T1 INTERRUPT OPERATION ............................................................................................................ 75
6.12 ADC INTERRUPT OPERATION ........................................................................................................ 76
6.13 SIO INTERRUPT OPERATION .......................................................................................................... 77
6.14 UART INTERRUPT OPERATION ..................................................................................................... 78
6.15 MULTI-INTERRUPT OPERATION ................................................................................................... 79
77 I/O PORT ..................................................................................................................................................... 80
7.1 OVERVIEW ........................................................................................................................................... 80
7.2 I/O PORT MODE ................................................................................................................................... 81
SONiX TECHNOLOGY CO., LTD
Page 4
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
7.3 I/O PULL UP REGISTER ...................................................................................................................... 82
7.4 I/O PORT DATA REGISTER ................................................................................................................ 83
7.5 PORT 4, PORT 5 ADC SHARE PIN ........................................................................................................ 84
7.6 OPEN-DRAIN REGISTER .................................................................................................................... 86
88 TIMERS ....................................................................................................................................................... 87
8.1 WATCHDOG TIMER ............................................................................................................................ 87
8.2 T0 8-BIT BASIC TIMER .............................................................................................................................. 89
8.2.1 OVERVIEW .................................................................................................................................... 89
8.2.2 T0 Timer Operation ......................................................................................................................... 90
8.2.3 T0M MODE REGISTER ................................................................................................................ 91
8.2.4 T0C COUNTING REGISTER ........................................................................................................ 91
8.2.5 T0 TIMER OPERATION EXPLAME ............................................................................................ 92
8.3 TC0 8-BIT TIMER/COUNTER ............................................................................................................. 93
8.3.1 OVERVIEW .................................................................................................................................... 93
8.3.2 TC0 TIMER OPERATION ............................................................................................................. 94
8.3.3 TC0M MODE REGISTER .............................................................................................................. 95
8.3.4 TC0C COUNTING REGISTER ..................................................................................................... 95
8.3.5 TC0R AUTO-RELOAD REGISTER .............................................................................................. 96
8.3.6 TC0D PWM DUTY REGISTER .................................................................................................... 96
8.3.7 TC0 EVENT COUNTER ................................................................................................................ 97
8.3.8 PULSE WIDTH MODULATION (PWM) ..................................................................................... 97
8.3.9 TC0 TIMER OPERATION EXPLAME ......................................................................................... 98
8.4 TC1 8-BIT TIMER/COUNTER ........................................................................................................... 100
8.4.1 OVERVIEW .................................................................................................................................. 100
8.4.2 TC1 TIMER OPERATION ........................................................................................................... 101
8.4.3 TC1M MODE REGISTER ............................................................................................................ 102
8.4.4 TC1C COUNTING REGISTER ................................................................................................... 102
8.4.5 TC1R AUTO-RELOAD REGISTER ............................................................................................ 103
8.4.6 TC1D PWM DUTY REGISTER .................................................................................................. 103
8.4.7 TC1 EVENT COUNTER .............................................................................................................. 104
8.4.8 PULSE WIDTH MODULATION (PWM) ................................................................................... 104
8.4.9 TC1 TIMER OPERATION EXPLAME ....................................................................................... 105
8.5 TC2 8-BIT TIMER/COUNTER ........................................................................................................... 107
8.5.1 OVERVIEW .................................................................................................................................. 107
8.5.2 TC2 TIMER OPERATION ........................................................................................................... 108
8.5.3 TC2M MODE REGISTER ............................................................................................................ 109
8.5.4 TC2C COUNTING REGISTER ................................................................................................... 109
8.5.5 TC2R AUTO-RELOAD REGISTER ............................................................................................ 110
8.5.6 TC2D PWM DUTY REGISTER .................................................................................................. 110
8.5.7 TC2 EVENT COUNTER .............................................................................................................. 111
8.5.8 PULSE WIDTH MODULATION (PWM) ................................................................................... 111
8.5.9 TC2 TIMER OPERATION EXPLAME ....................................................................................... 112
8.6 T1 16-BIT TIMER WITH CAPTURE TIMER FUNCTION .............................................................................. 114
8.6.1 OVERVIEW .................................................................................................................................. 114
8.6.2 T1 TIMER OPERATION .............................................................................................................. 114
8.6.3 T1M MODE REGISTER .............................................................................................................. 115
8.6.4 T1CH, T1CL 16-bit COUNTING REGISTERS ........................................................................... 116
8.6.5 T1 CPATURE TIMER .................................................................................................................. 117
8.6.5.1 Capture Timer ......................................................................................................................... 117
8.6.5.2 High Pulse Width Measurement ............................................................................................. 118
8.6.5.3 Low Pulse Width Measurement ............................................................................................. 118
8.6.5.4 Input Cycle Measurement ....................................................................................................... 119
SONiX TECHNOLOGY CO., LTD
Page 5
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
8.6.6 CAPTURE TIMER CONTROL REGISTERS ............................................................................. 119
8.6.7 T1 TIMER OPERATION EXPLAME .......................................................................................... 120
99 12 CHANNEL ANALOG TO DIGITAL CONVERTER (ADC) .......................................................... 123
9.1 OVERVIEW ......................................................................................................................................... 123
9.2 ADC MODE REGISTER ..................................................................................................................... 124
9.3 ADC DATA BUFFER REGISTERS .................................................................................................... 125
9.4 ADC OPERATION DESCRIPTION AND NOTIC ............................................................................. 126
9.4.1 ADC SIGNAL FORMAT ............................................................................................................. 126
9.4.2 ADC CONVERTING TIME ......................................................................................................... 126
9.4.3 ADC PIN CONFIGURATION ..................................................................................................... 127
9.4.4 ADC OPERATION EXAMLPE ................................................................................................... 128
9.5 ADC APPLICATION CIRCUIT ................................................................................................................ 130
1100 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) ..................................... 131
10.1 OVERVIEW ....................................................................................................................................... 131
10.2 UART OPERATION .......................................................................................................................... 132
10.3 UART BAUD RATE .......................................................................................................................... 133
10.4 UART TRANSFER FORMAT................................................................................................................... 134
10.5 BREAK POCKET............................................................................................................................... 134
10.6 ABNORMAL POCKET ..................................................................................................................... 135
10.7 UART RECEIVER CONTROL REGISTER...................................................................................... 135
10.8 UART TRANSMITTER CONTROL REGISTER ............................................................................. 136
10.9 UART DATA BUFFER ...................................................................................................................... 136
10.10 UART OPERATION EXAMLPE .................................................................................................... 137
1111 SERIAL INPUT/OUTPUT TRANSCEIVER (SIO) ............................................................................ 140
11.1 OVERVIEW ....................................................................................................................................... 140
11.2 SIO OPERATION............................................................................................................................... 140
11.3 SIOM MODE REGISTER .................................................................................................................. 143
11.4 SIOB DATA BUFFER ....................................................................................................................... 144
11.5 SIOR REGISTER DESCRIPTION ..................................................................................................... 145
1122 MAIN SERIAL PORT (MSP) ................................................................................................................ 146
12.1 OVERVIEW ....................................................................................................................................... 146
12.2 MSP STATUS REGISTER ................................................................................................................. 146
12.3 MSP MODE REGISTER 1 ................................................................................................................. 147
12.4 MSP MODE REGISTER 2 ................................................................................................................. 148
12.5 MSP MSPBUF REGISTER ................................................................................................................ 149
12.6 MSP MSPADR REGISTER ............................................................................................................... 149
12.7 SLAVE MODE OPERATION.................................................................................................................... 149
12.7.1 Addressing ................................................................................................................................... 149
12.7.2 Slave Receiving ........................................................................................................................... 150
12.7.3 Slave Transmission ...................................................................................................................... 150
12.7.4 General Call Address ................................................................................................................... 151
12.7.5 Slave Wake up ............................................................................................................................. 152
12.8 MASTER MODE ..................................................................................................................................... 154
12.8.1 Mater Mode Support .................................................................................................................... 154
12.8.2 MSP Rate Generator .................................................................................................................... 154
12.8.3 MSP Mater START Condition .................................................................................................... 155
12.8.3.1 WCOL Status Flag................................................................................................................ 155
12.8.4 MSP Master mode Repeat START Condition ............................................................................ 155
12.8.4.1 WCOL Status Flag................................................................................................................ 155
12.8.5 Acknowledge Sequence Timing .................................................................................................. 156
12.8.5.1 WCOL Status Flag................................................................................................................ 156
12.8.6 STOP Condition Timing.............................................................................................................. 156
SONiX TECHNOLOGY CO., LTD
Page 6
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
12.8.6.1 WCOL Status Flag................................................................................................................ 156
12.8.7 Clock Arbitration ......................................................................................................................... 157
12.8.8 Master Mode Transmission ......................................................................................................... 157
12.8.8.1 BF Status Flag ...................................................................................................................... 157
12.8.8.2 WCOL Flag .......................................................................................................................... 157
12.8.8.3 ACKSTAT Status Flag ......................................................................................................... 157
12.8.9 Master Mode Receiving............................................................................................................... 158
12.8.9.1 BF Status Flag ...................................................................................................................... 158
12.8.9.2 MSPOV Flag ........................................................................................................................ 158
12.8.9.3 WCOL Flag .......................................................................................................................... 158
1133 IN SYSTEM PROGRAM FLASH ROM .............................................................................................. 159
13.1 OVERVIEW ....................................................................................................................................... 159
13.2 ISP FLASH ROM ERASE OPERATION .......................................................................................... 160
13.3 ISP FLASH ROM PROGRAM OPERATION ................................................................................... 161
13.4 ISP PROGRAM/ERASE CONTROL REGISTER ............................................................................. 164
13.5 ISP ROM ADDRESS REGISTER ...................................................................................................... 164
13.6 ISP RAM ADDRESS REGISTER ...................................................................................................... 164
13.7 ISP ROM PROGRAMMING LENGTH REGISTER ......................................................................... 165
1144 INSTRUCTION TABLE ........................................................................................................................ 166
1155 ELECTRICAL CHARACTERISTIC ................................................................................................... 168
15.1 ABSOLUTE MAXIMUM RATING .................................................................................................. 168
15.2 ELECTRICAL CHARACTERISTIC ................................................................................................. 168
15.3 CHARACTERISTIC GRAPHS.......................................................................................................... 170
1166 DEVELOPMENT TOOL ....................................................................................................................... 171
16.1 SMART DEVELOPMENT ADAPTER ........................................................................................................ 172
16.2 SN8F27E65 STARTER-KIT ................................................................................................................... 173
16.3 EMULATOR/DEBUGGER INSTALLATION ........................................................................................... 174
16.4 PROGRAMMER INSTALLATION ......................................................................................................... 175
1177 ROM PROGRAMMING PIN ................................................................................................................ 176
17.1 MP-III WRITER TRANSITION BOARD SOCKET PIN ASSIGNMENT ....................................... 176
17.2 MP-III WRITER PROGRAMMING PIN MAPPING: ....................................................................... 177
1188 MARKING DEFINITION ...................................................................................................................... 180
18.1 INTRODUCTION .............................................................................................................................. 180
18.2 MARKING INDETIFICATION SYSTEM ........................................................................................ 180
18.3 MARKING EXAMPLE ...................................................................................................................... 181
18.4 DATECODE SYSTEM ...................................................................................................................... 182
1199 PACKAGE INFORMATION ................................................................................................................ 183
19.1 P-DIP 32 PIN ...................................................................................................................................... 183
19.2 LQFP 32 PIN....................................................................................................................................... 184
19.3 QFN 5X5 32 PIN ................................................................................................................................. 185
19.4 S-DIP 32 PIN ...................................................................................................................................... 186
19.5 SK-DIP 28 PIN ................................................................................................................................... 187
19.6 SOP 28 PIN ......................................................................................................................................... 188
19.7 SSOP 28 PIN ....................................................................................................................................... 189
19.8 QFN 4X4 28 PIN ................................................................................................................................. 190
19.9 QFN 4X4 24 PIN ................................................................................................................................. 191
19.10 P-DIP 20 PIN .................................................................................................................................... 192
19.11 SOP 20 PIN ....................................................................................................................................... 193
SONiX TECHNOLOGY CO., LTD
Page 7
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
1 PRODUCT OVERVIEW
SN8F27E60 series 8-bit micro-controller is a new series production applied advanced semiconductor technology to
implement flash ROM architecture. Under flash ROM platform, SN8F27E60 builds in in-system-programming (ISP)
function extending to EEPROM emulation and Embedded ICE function. It offers high performance 12-ch 10-bit ADC,
3-set individual programmable PWMs, 3-type serial interfaces and flexible operating modes. Powerful functionality,
high reliability and low power consumption can apply to AC power application and battery level application easily.
1.1 FEATURES
Four 8-bit timer. (T0, TC0, TC1, TC2).
T0: Basic timer.
TC0: Timer/counter/PWM0.
TC1: Timer/counter/PWM1.
TC2: Timer/counter/PWM2
3 channel duty/cycle programmable PWM to
Generate PWM, Buzzer and IR carrier signals.
(PWM0~2).
One 16-bit timer (T1) with capture timer function.
12-channel 10-bit SAR ADC.
Serial Interface: SIO, UART, MSP
Build in Embedded ICE function.
I/O pin configuration
Four system clocks
Bi-directional: P0, P1, P4, P5.
External high clock: RC type up to 10MHz
Wakeup: P0, P1 level change.
External high clock: Crystal type up to 16MHz
Pull-up resisters: P0, P1, P4, P5.
Internal high clock: RC type 16MHz
External interrupt: P0.0, P0.1
Internal low clock: RC type 16KHz
ADC input pin: AIN0~AIN11.
Four operating modes
Normal mode: Both high and low clock active
Fcpu (Instruction cycle)
Slow mode: Low clock only
Fcpu = Fhosc/1, Fhosc/2, Fhosc/4, Fhosc/8, Fhosc/16,
Sleep mode: Both high and low clock stop
Fhosc/32, Fhosc/64, Fhosc/128
Green mode: Periodical wakeup by timer
On chip watchdog timer and clock source
Package (Chip form support)
1.8V/2.4V/3.3V 3-level LVD with trim.
PDIP 32 pin
LQFP 32 pin
Powerful instructions
QFN 32 pin
Instruction’s length is one word.
SDIP 32 pin
Most of instructions are one cycle only.
SKDIP 28 pin
All ROM area JMP instruction.
SOP 28 pin
All ROM area lookup table function (MOVC).
SSOP 28 pin
QFN 28 pin
QFN 24 pin
DIP 20 pin
SOP 20 pin
Memory configuration
Flash ROM size: 6K x 16 bits. Including EEROM
emulation. (In system programming)
RAM size: 512 x 8 bits.
8 levels stack buffer.
13 interrupt sources
11 internal interrupts: T0, TC0, TC1, TC2, T1, ADC,
SIO, MSP, UTX(UART TX), URX(UART RX), WAKE
2 external interrupts: INT0, INT1
Multi-interrupt vector structure.
Each of interrupt sources has a unique interrupt vector.
SONiX TECHNOLOGY CO., LTD
Page 8
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
SN8F27E60 series micro-controller includes two types for different power types.
For AC power type (alternating current power source) and DC high voltage power (≦5.5V), the power pin has VDD and
VDDL. VDD pin is connect to DC power source from DC-DC inverter or regulator and connects a 0.1uF capacitor to
VSS pin (ground). VDDL is internal power terminal, not connect with power source, and only connects a 0.1uF
capacitor to VSS pin (ground). This pin assignment has high power noise immunity, but the static current is larger. The
application field is household, motor control…
(1.8V~5.5V)
VDD
VDDL
+
Regulator
VDD
0.1uF
L
AC Power
Source
Rectification
0.1uF
-
VSS
+
VDDL
0.1uF
0.1uF
N
DC Power
Source
(1.8V~5.5V)
VSS
SN8F27E60
Series MCU
-
SN8F27E60
Series MCU
For DC power type (battery power source), the power pin is VDD. VDD pin is connect to DC power source from battery
and connects a 0.1uF capacitor to VSS pin (ground). This pin assignment has low power noise immunity, but the static
current is very low. The application field is portable application…
(1.8V~3.3V)
VDD
Regulator
+
+
VDD
DC Power
Source
(>3.3V)
0.1uF
0.1uF
-
VSS
-
VSS
SN8F27E60L
Series MCU
DC Power
Source
(1.8V~3.3V)
SN8F27E60L
Series MCU
Features Selection Table
SN8F27E60 Series
CHIP
ROM
RAM
I/O
PWM
ADC
SIO
UART
MSP
Ext.INT
ISP/
Embedded
ICE
Operating
Voltage
Stack
Timer
27
3-ch
12-ch
V
V
V
2
V
1.8V~5.5V
Package
DIP32
LQFP32
QFN32
SDIP32
SKDIP28
SOP28
SSOP28
QFN28
DIP20
SOP20
SN8F27E65
6K*16
512
8
8-bit*4
16-bit*1
SN8F27E64
6K*16
512
8
8-bit*4
16-bit*1
25
3-ch
11-ch
V
V
V
2
V
1.8V~5.5V
SN8F27E62
6K*16
512
8
8-bit*4
16-bit*1
17
3-ch
9-ch
-
V
-
1
V
1.8V~5.5V
Stack
Timer
I/O
PWM
ADC
SIO
UART
MSP
Ext.INT
ISP/
Embedded
ICE
Operating
Voltage
27
3-ch
12-ch
V
V
V
2
V
1.8V~3.3V
25
3-ch
11-ch
V
V
V
2
V
1.8V~3.3V
21
3-ch
8-ch
V
V
V
2
V
1.8V~3.3V
QFN24
17
3-ch
9-ch
-
V
-
1
V
1.8V~3.3V
DIP20
SOP20
SN8F27E60L Series
CHIP
ROM
RAM
SN8F27E65L
6K*16
512
8
8-bit*4
16-bit*1
SN8F27E64L
6K*16
512
8
8-bit*4
16-bit*1
SN8F27E63L
6K*16
512
8
SN8F27E62L
6K*16
512
8
8-bit*4
16-bit*1
8-bit*4
16-bit*1
SONiX TECHNOLOGY CO., LTD
Page 9
Package
DIP32
LQFP32
QFN32
SDIP32
SKDIP28
SOP28
SSOP28
QFN28
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
1.2 SYSTEM BLOCK DIAGRAM
INTERNAL HIGH
RC 16MHz
PC
3-Level LVD
(Low Voltage Detector)
FLASH
IR
ROM
EXTERNAL
HIGH OSC.
INTERNAL
LOW RC
WATCHDOG TIMER
Embedded ICE
System
FLAGS
TIMING GENERATOR
12-ch 10-bit ADC
EIDA, EICK
AIN0~AIN11
MSP
SCL,SDA
UART
UTX,URX
ALU
RAM
SCK,SDI,SDO,
SCS
SIO
ACC
SYSTEM REGISTERS
INTERRUPT
CONTROL
TIMER & COUNTER
P0
SONiX TECHNOLOGY CO., LTD
P1
P4
Page 10
PWM0
PWM0
PWM1
PWM1
PWM2
PWM2
P5
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
1.3 PIN ASSIGNMENT
VDDL
VDDL
VDD
AVREFH
P4.0/AIN0
P4.1/AIN1
P4.2/AIN2
P4.3/AIN3
P4.4/AIN4
P4.5/AIN5
P4.6/AIN6
P4.7/AIN7
P5.0/AIN8
P5.1/AIN9/PWM0
P5.2/AIN10/PWM1
P5.3/AIN11/PWM2
P4.0/AIN0
P4.1/AIN1
P4.2/AIN2
P4.3/AIN3
P4.4/AIN4
P4.5/AIN5
P4.6/AIN6
P4.7/AIN7
VDD
VDD
VDD
AVREFH
P4.0/AIN0
P4.1/AIN1
P4.2/AIN2
P4.3/AIN3
P4.4/AIN4
P4.5/AIN5
P4.6/AIN6
P4.7/AIN7
P5.0/AIN8
P5.1/AIN9/PWM0
P5.2/AIN10/PWM1
P5.3/AIN11/PWM2
VDD
VDD
AVREFH
24
23
22
21
20
19
18
17
P4.0/AIN0
P4.1/AIN1
P4.2/AIN2
P4.3/AIN3
P4.4/AIN4
P4.5/AIN5
P4.6/AIN6
P4.7/AIN7
P5.0/AIN8
P5.1/AIN9/PWM0
P5.2/AIN10/PWM1
P5.3/AIN11/PWM2
SONiX TECHNOLOGY CO., LTD
P1.0/EICK
VDDL
VDD/AVREFH
P4.1/AIN1
P4.2/AIN2
P4.3/AIN3
P4.4/AIN4
P4.5/AIN5
P4.6/AIN6
P4.7/AIN7
P5.0/AIN8
P5.1/AIN9/PWM0
P5.2/AIN10/PWM1
P5.3/AIN11/PWM2
P1.0/EICK
P1.1/EIDA
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P1.2/SDA
U
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
1 O
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
P1.3/SCL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P0.3/UTX/T1
P0.2/URX/TC2
P0.1/INT1/TC1
P0.0/INT0/TC0
P1.7/SCS
P1.6/SCK
P1.5/SDI
P1.4/SDO
P5.0/AIN8
P5.1/AIN9/PWM0
P5.2/AIN10/PWM1
P5.3/AIN11/PWM2
P1.0/EICK
P1.1/EIDA
P1.2/SDA
P1.3/SCL
SN8F27E64K (AC field, SKDIP 28 Pin):
SN8F27E64S (AC field, SOP 28 Pin):
SN8F27E64X (AC field, SSOP 28 Pin):
U
SN8F27E65LF (DC field, LQFP 32 Pin):
SN8F27E65LJ (DC field, QFN 5x5 32 Pin):
RST/P0.4
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDD
AVREFH
VDD
VDDL
VDDL
VSS
XIN/P0.6
RST/P0.4
32 31 30 29 28 27 26 25
1 O
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
VSS
XIN/P0.6
XOUT/P0.5
RST/P0.4
P0.3/UTX/T1
P0.2/URX/TC2
P0.1/INT1/TC1
P0.0/INT0/TC0
P1.6/SCK
P1.5/SDI
P1.4/SDO
P1.3/SCL
P1.2/SDA
P1.1/EIDA
VSS
XIN/P0.6
XOUT/P0.5
RST/P0.4
P0.3/UTX/T1
P0.2/URX/TC2
P0.1/INT1/TC1
P0.0/INT0/TC0
P1.7/SCS
P1.6/SCK
P1.5/SDI
P1.4/SDO
P1.3/SCL
P1.2/SDA
P1.1/EIDA
P1.0/EICK
VSS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
XIN/P0.6
U
SN8F27E65F (AC field, LQFP 32 Pin):
SN8F27E65J (AC field, QFN 5x5 32 Pin):
P0.3/UTX/T1
P0.2/URX/TC2
P0.1/INT1/TC1
P0.0/INT0/TC0
P1.7/SCS
P1.6/SCK
P1.5/SDI
P1.4/SDO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SN8F27E65LP (DC field, DIP 32 Pin):
SN8F27E65LU (DC field, SDIP 32 Pin):
XOUT/P0.5
VSS
XIN/P0.6
XOUT/P0.5
RST/P0.4
P0.3/UTX/T1
P0.2/URX/TC2
P0.1/INT1/TC1
P0.0/INT0/TC0
P1.7/SCS
P1.6/SCK
P1.5/SDI
P1.4/SDO
P1.3/SCL
P1.2/SDA
P1.1/EIDA
P1.0/EICK
SN8F27E65P (AC field, DIP 32 Pin):
SN8F27E65U (AC field, SDIP 32 Pin):
XOUT/P0.5
SN8F27E64LK (DC field, SKDIP 28 Pin):
SN8F27E64LS (DC field, SOP 28 Pin):
SN8F27E64LX (DC field, SSOP 28 Pin):
VSS
XIN/P0.6
XOUT/P0.5
RST/P0.4
P0.3/UTX/T1
P0.2/URX/TC2
P0.1/INT1/TC1
P0.0/INT0/TC0
P1.6/SCK
P1.5/SDI
P1.4/SDO
P1.3/SCL
P1.2/SDA
P1.1/EIDA
Page 11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
U
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VDD/AVREFH
P4.1/AIN1
P4.2/AIN2
P4.3/AIN3
P4.4/AIN4
P4.5/AIN5
P4.6/AIN6
P4.7/AIN7
P5.0/AIN8
P5.1/AIN9/PWM0
P5.2/AIN10/PWM1
P5.3/AIN11/PWM2
P1.0/EICK
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
P0.3/UTX/T1
P0.2/URX/TC2
P0.1/INT1/TC1
P0.0/INT0/TC0
P1.6/SCK
P1.5/SDI
P1.4/SDO
P4.2/AIN2
P4.3/AIN3
P4.4/AIN4
P4.5/AIN5
P4.6/AIN6
P4.7/AIN7
P5.0/AIN8
P0.3/UTX/T1
P0.2/URX/TC2
P0.1/INT1/TC1
P0.0/INT0/TC0
P1.6/SCK
P1.5/SDI
P1.4/SDO
P4.1/AIN1
VDD/AVREFH
VDD
VSS
XIN/P0.6
RST/P0.4
21
20
19
18
17
16
15
XOUT/P0.5
SN8F27E64LJ (DC field, QFN 4x4 28 Pin):
P4.1/AIN1
VDD/AVREFH
VDDL
28 27 26 25 24 23 22
1 O
2
3
4
5
6
7
8 9 10 11 12 13 14
21
20
19
18
17
16
15
P4.2/AIN2
P4.3/AIN3
P4.4/AIN4
P4.5/AIN5
P4.6/AIN6
P4.7/AIN7
P5.0/AIN8
P5.1/AIN9/PWM0
P5.2/AIN10/PWM1
P5.3/AIN11/PWM2
P1.0/EICK
P1.1/EIDA
P1.2/SDA
P1.3/SCL
P5.1/AIN9/PWM0
P5.2/AIN10/PWM1
P5.3/AIN11/PWM2
P1.0/EICK
P1.1/EIDA
P1.2/SDA
AVREFH
VDD
VSS
RST/P0.4
P0.3/UTX/T1
P0.2/URX/TC2
SN8F27E63LJ (DC field, QFN 4x4 24 Pin):
P0.1/INT1/TC1
P0.0/INT0/TC0
P1.7/SCS
P1.6/SCK
P1.5/SDI
P1.4/SDO
24 23 22 21 20 19
1 O
18 P4.4/AIN4
2
17 P4.5/AIN5
3
16 P4.6/AIN6
4
15 P4.7/AIN7
5
14 P5.1/AIN9/PWM0
6
13 P5.0/AIN8
7 8 9 10 11 12
P5.2/AIN10/PWM1
P5.3/AIN11/PWM2
P1.0/EICK
P1.1/EIDA
P1.2/SDA
P1.3/SCL
VSS
28 27 26 25 24 23 22
1 O
2
3
4
5
6
7
8 9 10 11 12 13 14
P1.3/SCL
XIN/P0.6
XOUT/P0.5
SN8F27E64J (AC field, QFN 4x4 28 Pin):
RST/P0.4
SN8F27E62P (AC field, DIP 20 Pin):
SN8F27E62S (AC field, SOP 20 Pin):
VSS
XIN/P0.6
XOUT/P0.5
RST/P0.4
P0.3/UTX/T1
P0.2/URX/TC2
P0.0/INT0/TC0
P1.1/EIDA
P1.0/EICK
P5.3/AIN11/PWM2
1
2
3
4
5
6
7
8
9
10
U
20
19
18
17
16
15
14
13
12
11
VDDL
VDD/AVREFH
P4.3/AIN3
P4.4/AIN4
P4.5/AIN5
P4.6/AIN6
P4.7/AIN7
P5.0/AIN8
P5.1/AIN9/PWM0
P5.2/AIN10/PWM1
SONiX TECHNOLOGY CO., LTD
SN8F27E62LP (DC field, DIP 20 Pin):
SN8F27E62LS (DC field, SOP 20 Pin):
VSS
XIN/P0.6
XOUT/P0.5
RST/P0.4
P0.3/UTX/T1
P0.2/URX/TC2
P0.0/INT0/TC0
P1.1/EIDA
P1.0/EICK
P5.3/AIN11/PWM2
Page 12
1
2
3
4
5
6
7
8
9
10
U
20
19
18
17
16
15
14
13
12
11
VDD
VDD/AVREFH
P4.3/AIN3
P4.4/AIN4
P4.5/AIN5
P4.6/AIN6
P4.7/AIN7
P5.0/AIN8
P5.1/AIN9/PWM0
P5.2/AIN10/PWM1
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
1.4 PIN DESCRIPTIONS
PIN NAME
VDD, VSS
VDDL
AVREFH
RST/P0.4
XIN/P0.6
XOUT/P0.5
P0.0/INT0/
TC0
P0.1/INT1/
TC1
P0.2/URX/
TC2
P0.3/UTX/T1
P1.0/EICK
P1.1/EIDA
P1.2/SDA
P1.3/SCL
P1.4/SDO
P1.5/SDI
P1.6/SCK
P1.7/SCS
P4.0/AIN0
P4.1/AIN1
P4.2/AIN2
P4.3/AIN3
P4.4/AIN4
TYPE
DESCRIPTION
P
Power supply input pins for digital and analog circuit.
P
Low voltage power pin. Connect 0.1uF capacitor to Vss.
P
ADC high reference voltage input pin.
RST: System external reset input pin. Schmitt trigger structure, active “low”, normal stay to “high”.
I/O P0.4: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
wake-up.
XIN: Oscillator input pin while external oscillator enable (crystal and RC).
I/O P0.6: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
wake-up.
XOUT: Oscillator output pin while external crystal enable.
I/O P0.5: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
wake-up.
P0.0: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
wake-up.
I/O
INT0: External interrupt 0 input pin.
TC0: TC0 event counter input pin.
P0.1: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
wake-up.
I/O
INT1: External interrupt 1 input pin.
TC1: TC1 event counter input pin.
P0.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
wake-up. Programmable open-drain structure.
I/O
TC2: TC2 event counter input pin.
URX: UART receive input pin.
P0.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
wake-up. Programmable open-drain structure.
I/O
UTX: UART transmit output pin.
T1: T1 event counter input pin.
P1.0: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
I/O wake-up. Programmable open-drain structure.
EICK: Embedded ICE clock pin.
P1.1: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
I/O wake-up. Programmable open-drain structure.
EIDA: Embedded ICE data pin.
P1.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
I/O wake-up. Programmable open-drain structure.
SDA: MSP data pin.
P1.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
I/O wake-up. Programmable open-drain structure.
SCL: MSP clock pin.
P1.4: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
I/O wake-up. Programmable open-drain structure.
SDO: SIO data output pin.
P1.5: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
I/O wake-up. Programmable open-drain structure.
SDI: SIO data input pin.
P1.6: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
I/O wake-up. Programmable open-drain structure.
SCK: SIO clock pin.
P1.7: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Level change
I/O wake-up. Programmable open-drain structure.
SCS: SIO bus control pin.
P4.0: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
I/O
AIN0: ADC channel 0 input pin.
P4.1: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
I/O
AIN1: ADC channel 1 input pin.
P4.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
I/O
AIN2: ADC channel 2 input pin.
P4.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
I/O
AIN3: ADC channel 3 input pin.
I/O P4.4: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
SONiX TECHNOLOGY CO., LTD
Page 13
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
P4.5/AIN5
I/O
P4.6/AIN6
I/O
P4.7/AIN7
I/O
P5.0/AIN8
I/O
P5.1/AIN9/
PWM0
I/O
P5.2/AIN10/
PWM1
I/O
P5.3/AIN11/
PWM2
I/O
AIN4: ADC channel 4 input pin.
P4.5: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN5: ADC channel 5 input pin.
P4.6: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN6: ADC channel 6 input pin.
P4.7: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN7: ADC channel 7 input pin.
P5.0: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN8: ADC channel 8 input pin.
P5.1: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN9: ADC channel 9 input pin.
PWM0: PWM 0 output pin.
P5.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN10: ADC channel 10 input pin.
PWM1: PWM 1 output pin.
P5.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
AIN11: ADC channel 11 input pin.
PWM2: PWM 2 output pin.
1.5 PIN CIRCUIT DIAGRAMS
Normal bi-direction I/O pin.
Pull-Up
Resistor
PnM
PnUR
Pin
I/O Input Bus
PnM
Output
Latch
I/O Output Bus
Bi-direction I/O pin shared with specific digital input function, e.g. INT0, event counter, SIO, MSP, UART…
Pull-Up
Resistor
PnM
Specific Input
Function Control Bit
PnUR
Specific Input Bus
Pin
IO Input Bus
PnM
Output
Latch
Output Bus
*. Specific Output
Function Control Bit
*. Some specific functions switch I/O direction directly, not through PnM register.
Bi-direction I/O pin shared with specific digital output function, e.g. PWM, SIO, MSP, UART…
Pull-Up
Resistor
PnM
PnUR
Pin
IO Input Bus
PnM
Output
Latch
Output Bus
Specific Output Bus
*. Specific Output
Function Control Bit
Specific Output
Function Control Bit
*. Some specific functions switch I/O direction directly, not through PnM register.
SONiX TECHNOLOGY CO., LTD
Page 14
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
Bi-direction I/O pin shared with specific analog input function, e.g. XIN, ADC…
Pull-Up
Resistor
*. Specific Analog
Function Control Bit
PnM
PnUR
Pin
I/O Input Bus
PnM
Output
Latch
I/O Output Bus
Analog IP Input
Terminal
*. Some specific functions switch I/O direction directly, not through PnM register.
Bi-direction I/O pin shared with specific analog output function, e.g. XOUT…
Pull-Up
Resistor
*. Specific Analog
Function Control Bit
PnM
PnUR
Pin
I/O Input Bus
PnM
Output
Latch
I/O Output Bus
Analog IP Output
Terminal
*. Some specific functions switch I/O direction directly, not through PnM register.
SONiX TECHNOLOGY CO., LTD
Page 15
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2 CENTRAL PROCESSOR UNIT (CPU)
2.1 PROGRAM MEMORY (FLASH ROM)
6K words FLASH ROM
Address
ROM
Reset vector
0000H
0001H
General purpose area
.
0007H
0008H WAKE Interrupt vector
0009H
INT0 Interrupt vector
000AH
INT1 Interrupt vector
000BH
T0 Interrupt vector
000CH
TC0 Interrupt vector
000DH
TC1 Interrupt vector
000EH
TC2 Interrupt vector
000FH
T1 Interrupt vector
0010H
ADC Interrupt vector
0011H
SIO Interrupt vector
0012H
I2C Interrupt vector
0013H UART RX Interrupt vector
0014H UART TX Interrupt vector
0015H
.
General purpose area
.
.
.
17F8H
17F9H
.
Reserved
17FDH
17FEH
17FFH
Comment
Reset vector
User program
Interrupt vector
User program
End of user program
The ROM includes Reset vector, Interrupt vector, General purpose area and Reserved area. The Reset vector is
program beginning address. The Interrupt vector is the head of interrupt service routine when any interrupt occurring.
The General purpose area is main program area including main loop, sub-routines and data table.
0x0000 Reset Vector: Program counter points to 0x0000 after any reset events (power on reset, reset pin
reset, watchdog reset, LVD reset…).
0x0001~0x0007: General purpose area to process system reset operation.
0x0008~0x0014: Multi interrupt vector area. Each of interrupt events has a unique interrupt vector.
0x0015~0x177F: General purpose area for user program and ISP (EEPROM function).
0x1780~0x17F7: General purpose area for user program. Do not execute ISP.
0x17F8~0x17FF: Reserved area. Do not execute ISP.
ROM security rule is even address ROM data protected and outputs 0x0000.
SONiX TECHNOLOGY CO., LTD
Page 16
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.1.1 RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
Power On Reset (POR=1).
Watchdog Reset (WDT=1).
External Reset (RST=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from POR, WDT,
and RST flags of PFLAG register. The following example shows the way to define the reset vector in the program
memory.
Example: Defining Reset Vector
ORG
JMP
…
0
START
ORG
15H
START:
…
…
ENDP
; 0000H
; Jump to user program address.
; 0015H, The head of user program.
; User program
; End of program
Note: The head of user program should skip interrupt vector area to avoid program execution error.
SONiX TECHNOLOGY CO., LTD
Page 17
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.1.2 INTERRUPT VECTOR (0008H~0014H)
A 13-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h~0014h of program memory to execute the vectored
interrupt. This interrupt is multi-vector and each of interrupts points to unique vector. Users have to define the interrupt
vector. The following example shows the way to define the interrupt vector in the program memory.
Note: The “PUSH” and “POP” operations aren’t through instruction (PUSH, POP) and can executed save
and load ACC and working registers (0x80~0x8F) by hardware automatically.
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
0010H
0011H
0012H
0013H
0014H
ROM
WAKE Interrupt vector
INT0 Interrupt vector
INT1 Interrupt vector
T0 Interrupt vector
TC0 Interrupt vector
TC1 Interrupt vector
TC2 Interrupt vector
T1 Interrupt vector
ADC Interrupt vector
SIO Interrupt vector
MSP Interrupt vector
UART RX Interrupt vector
UART TX Interrupt vector
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
When one interrupt request occurs, and the program counter points to the correlative vector to execute interrupt
service routine. If WAKE interrupt occurs, the program counter points to ORG 8. If INT0 interrupt occurs, the program
counter points to ORG 9. In normal condition, several interrupt requests happen at the same time. So the priority of
interrupt sources is very important, or the system doesn’t know which interrupt is processed first. The interrupt priority
is follow vector sequence. ORG 8 is priority 1. ORG 9 is priority 2. In the case, the interrupt processing priority is as
following.
If WAKE, T0, TC2, T1 and SIO interrupt requests happen at the same time, the system processing interrupt sequence
is WAKE, T0, TC2, T1, and then SIO. The system processes WAKE interrupt service routine first, and then processes
T0 interrupt routine…Until finishing processing all interrupt requests.
Example:
Interrupt Request Occurrence Sequence: (2~8 interrupt requests occur during WAKE interrupt service routine
execution.)
1
2
3
4
5
6
7
8
WAKE
ADC
TC1
T0
SIO
INT0
T1
UART RX
Interrupt Processing Sequence:
1
2
WAKE
INT0
3
T0
SONiX TECHNOLOGY CO., LTD
4
TC1
5
T1
Page 18
6
ADC
7
SIO
8
UART RX
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.CODE
ORG
JMP
…
ORG
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
0
START
; 0000H
; Jump to user program address.
8
ISR_WAKE
ISR_INT0
ISR_INT1
ISR_T0
ISR_TC0
ISR_TC1
ISR_TC2
ISR_T1
ISR_ADC
ISR_SIO
ISR_MSP
ISR_UART_RX
ISR_UART_TX
; Interrupt vector, 0008H.
; Jump to interrupt service routine address.
ORG
15H
START:
…
…
…
JMP
…
; 0015H, The head of user program.
; User program.
START
ISR_WAKE:
; End of user program.
; The head of interrupt service routine.
; Save ACC and 0x80~0x8F register to buffers.
…
RETI
ISR_INT0:
; Load ACC and 0x80~0x8F register from buffers.
; End of interrupt service routine.
;
; Save ACC and 0x80~0x8F register to buffers.
…
RETI
…
…
…
…
…
ISR_UART_TX:
; Load ACC and 0x80~0x8F register from buffers.
; End of interrupt service routine.
;
; Save ACC and 0x80~0x8F register to buffers.
…
RETI
; Load ACC and 0x80~0x8F register from buffers.
; End of interrupt service routine.
ENDP
; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
2. The address 0008H~0014H is interrupt vector.
3. User’s program is a loop routine for main purpose application.
SONiX TECHNOLOGY CO., LTD
Page 19
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.1.3 LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
Example: To look up the ROM data located “TABLE1”.
@@:
TABLE1:
B0MOV
B0MOV
MOVC
Y, #TABLE1$M
Z, #TABLE1$L
INCMS
JMP
INCMS
NOP
Z
@F
Y
MOVC
…
DW
DW
DW
…
0035H
5105H
2012H
; To set lookup table1’s middle address
; To set lookup table1’s low address.
; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
; Z+1
; Z is not overflow.
; Z overflow (FFH 00), Y=Y+1
;
;
; To lookup data, R = 51H, ACC = 05H.
;
; To define a word (16 bits) data.
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must take care such situation to avoid look-up table errors. If Z register is
overflow, Y register must be added one. The following INC_YZ macro shows a simple method to process
Y and Z registers automatically.
Example: INC_YZ macro.
INC_YZ
MACRO
INCMS
JMP
INCMS
NOP
Z
@F
; Z+1
; Not overflow
Y
; Y+1
; Not overflow
@@:
ENDM
SONiX TECHNOLOGY CO., LTD
Page 20
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
Example: Modify above example by “INC_YZ” macro.
B0MOV
B0MOV
MOVC
Y, #TABLE1$M
Z, #TABLE1$L
INC_YZ
@@:
TABLE1:
MOVC
…
DW
DW
DW
…
0035H
5105H
2012H
; To set lookup table1’s middle address
; To set lookup table1’s low address.
; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
;
; To lookup data, R = 51H, ACC = 05H.
;
; To define a word (16 bits) data.
The other example of look-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
Example: Increase Y and Z register by B0ADD/ADD instruction.
B0MOV
B0MOV
Y, #TABLE1$M
Z, #TABLE1$L
; To set lookup table’s middle address.
; To set lookup table’s low address.
B0MOV
B0ADD
A, BUF
Z, A
; Z = Z + BUF.
B0BTS1
JMP
INCMS
NOP
FC
GETDATA
Y
; Check the carry flag.
; FC = 0
; FC = 1. Y+1.
GETDATA:
;
; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
MOVC
…
TABLE1:
DW
DW
DW
…
0035H
5105H
2012H
SONiX TECHNOLOGY CO., LTD
; To define a word (16 bits) data.
Page 21
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.1.4 JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
Example: Jump table.
ORG
0X0100
; The jump table is from the head of the ROM boundary
B0ADD
JMP
JMP
JMP
JMP
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
Example: If “jump table” crosses over ROM boundary will cause errors.
@JMP_A
MACRO
IF
JMP
ORG
ENDIF
ADD
ENDM
VAL
(($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
($ | 0XFF)
($ | 0XFF)
PCL, A
Note: “VAL” is the number of the jump table listing number.
SONiX TECHNOLOGY CO., LTD
Page 22
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; “BUF0” is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
If the jump table position is across a ROM boundary (0x00FF~0x0100), the “@JMP_A” macro will adjust the jump table
routine begin from next RAM boundary (0x0100).
Example: “@JMP_A” operation.
; Before compiling program.
ROM address
0X00FD
0X00FE
0X00FF
0X0100
0X0101
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; “BUF0” is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
A, BUF0
5
A0POINT
A1POINT
A2POINT
A3POINT
A4POINT
; “BUF0” is from 0 to 4.
; The number of the jump table listing is five.
; ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
; ACC = 4, jump to A4POINT
; After compiling program.
ROM address
0X0100
0X0101
0X0102
0X0103
0X0104
B0MOV
@JMP_A
JMP
JMP
JMP
JMP
JMP
SONiX TECHNOLOGY CO., LTD
Page 23
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.1.5 CHECKSUM CALCULATION
The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the
Checksum value.
Example: The demo program shows how to calculated Checksum from 00H to the end of user’s code.
MOV
B0MOV
MOV
B0MOV
CLR
CLR
A,#END_USER_CODE$L
END_ADDR1, A
; Save low end address to end_addr1
A,#END_USER_CODE$M
END_ADDR2, A
; Save middle end address to end_addr2
Y
; Set Y to 00H
Z
; Set Z to 00H
MOVC
B0BSET
ADD
MOV
ADC
JMP
FC
DATA1, A
A, R
DATA2, A
END_CHECK
; Clear C flag
; Add A to Data1
INCMS
JMP
JMP
Z
@B
Y_ADD_1
; Z=Z+1
; If Z != 00H calculate to next address
; If Z = 00H increase Y
MOV
CMPRS
JMP
MOV
CMPRS
JMP
JMP
A, END_ADDR1
A, Z
AAA
A, END_ADDR2
A, Y
AAA
CHECKSUM_END
INCMS
NOP
JMP
Y
; Increase Y
@B
; Jump to checksum calculate
@@:
; Add R to Data2
; Check if the YZ address =
the end of code
AAA:
END_CHECK:
; Check if Z = low end address
; If Not jump to checksum calculate
; If Yes, check if Y = middle end address
; If Not jump to checksum calculate
; If Yes checksum calculated is done.
Y_ADD_1:
CHECKSUM_END:
…
…
END_USER_CODE:
SONiX TECHNOLOGY CO., LTD
; Label of program end
Page 24
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.2 DATA MEMORY (RAM)
512 X 8-bit RAM
Bank
Bank 0
Bank 1
Bank 2
Address
000H
...
...
07FH
080H
...
0FFH
100H
…
…
1FFH
200H
…
…
27FH
RAM Location
Comment
RAM Bank 0
General purpose area
System Register
End of Bank 0
RAM Bank 1
General purpose area
End of Bank 1
RAM Bank 2
General purpose area
End of Bank 2
The 512-byte general purpose RAM is separated into Bank0, Bank1 and Bank2. Accessing the three banks’ RAM is
controlled by “RBANK” register. When RBANK = 0, the program controls Bank 0 RAM directly. When RBANK = 1, the
program controls Bank 1 RAM directly. When RBANK = 2, the program controls Bank 2 RAM directly. Under one bank
condition and need to access the other bank RAM, setup the RBANK register is necessary. When interrupt occurs,
RBANK register is saved, and RAM bank is still last condition. User can select RAM bank through setup RBANK
register during processing interrupt service routine. When RETI is executed to leave interrupt operation, RBANK
register is reloaded, and RAN bank returns to last condition. Sonix provides “Bank 0” type instructions (e.g. b0mov,
b0add, b0bts1, b0bset…) to control Bank 0 RAM in non-zero RAM bank condition directly.
Example: Access Bank 0 RAM in Bank 1 condition. Move Bank 0 RAM (WK00) value to Bank 1 RAM
(WK01).
; Bank 1 (RBANK = 1)
B0MOV
MOV
A, WK00
WK01,A
; Use Bank 0 type instruction to access Bank 0 RAM.
Note:
1. For multi-bank RAM program, it is not easy to control RAM Bank selection. Users have to take care
the RBANK condition very carefully, especially for interrupt service routine. The system won’t save
the RBANK and switch RAM bank to Bank 0, so these controls must be through program. It is a
good to use Bank 0 type instruction to process the situations.
2. The 190H, 191H of RAM address doesn’t support directly addressing mode to access RAM but
support indirectly addressing mode @HL/@YZ.
SONiX TECHNOLOGY CO., LTD
Page 25
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.2.1 SYSTEM REGISTER
2.2.1.1SYSTEM REGISTER TABLE
8
9
A
B
C
D
0
1
2
3
4
5
L
H
R
Z
Y
X
@HL
@YZ
-
PCL
PCH
OSCM
6
7
PFLAG RBANK
8
9
A
B
C
D
E
F
W0
W1
W2
W3
W4
W5
W6
W7
P1OC
P1W
PEDGE
WDTR INTRQ0 INTRQ1
-
INTEN0 INTEN1 P0OC
P0M
P1M
-
-
P4M
P5M
P0
P1
-
-
P4
P5
P0UR
P1UR
-
-
P4UR
P5UR
T0M
T0C
TC0M
TC0C
TC0R
TC0D
TC1M
TC1C
TC1R
TC1D
TC2M
TC2C
TC2R
TC2D
T1M
T1CL
T1CH
ADM
ADB
ADR
ADT
-
-
-
-
-
-
-
-
SIOR
SIOB
SIOC
URTX
URRX
URCR
UTXD
STK6L STK6H STK5L STK5H STK4L
STK4H
E SIOM
F STK7L STK7H
CPTM CPTCL CPTCH P4CON P5CON
PE
PECMD
ROML
PE
PE
PERAM
ROMH RAML
CNT
MSP
MSP
MSP
URXD
MSPM1 MSPM2
STKP
STAT
BUF
ADR
STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H
2.2.1.2SYSTEM REGISTER DESCRIPTION
H, L =
R=
X=
RBANK =
P1W =
PEDGE =
URTX =
URRX =
URCR =
UTXD =
T1CH, L =
ADM =
ADR =
PEDGE =
INTEN0,1 =
PnM =
PnUR =
PCH, PCL =
T0C =
TCnC =
TCnD=
CPTCL,H=
MSPBUF=
MSPADR=
PECMD=
PEROM=
@HL =
STKP =
Working, @HL addressing register.
Working register and ROM look-up data buffer.
Working and ROM address register
RAM bank select register.
Port 1 wakeup register.
P0.0, P0.1 edge direction register.
UART transmit control register.
UART receive control register.
UART baud rate control register.
UART transmit data buffer.
T1 counting registers.
ADC mode register.
ADC resolution select register.
P0.0, P0.1, P0.2 edge direction register.
Interrupt enable register.
Port n input/output mode register.
Port n pull-up resister control register.
Program counter.
T0 counting register.
TCn counting register.
TCn duty control register.
Capture timer counting registers
MSP buffer register.
MSP address register.
ISP command register.
ISP ROM address
RAM HL indirect addressing index pointer.
Stack pointer buffer.
SONiX TECHNOLOGY CO., LTD
Y, Z =
PFLAG =
W0~W7=
P0OC,P1OC =
SIOM =
SIOR =
SIOB =
SIOC =
T1M =
URXD =
P4CON,P5CON =
ADB =
ADT =
INTRQ0,1 =
WDTR =
Pn =
OSCM =
T0M =
TCnM =
TCnR =
CPTM=
MSPSTAT=
MSPM1=
MSPM2=
PERAM=
PERAMCNT=
@YZ =
STK0~STK7 =
Page 26
Working, @YZ and ROM addressing register.
Special flag register.
Working register
Open-drain control register.
SIO mode control register.
SIO clock rate control register.
SIO data buffer.
SIO control register.
T1 mode register.
UART receive data buffer.
P4, P5 configuration register.
ADC data buffer.
ADC offset calibration register.
Interrupt request register.
Watchdog timer clear register.
Port n data buffer.
Oscillator mode register.
T0 mode register.
TCn mode register.
TCn auto-reload data buffer.
Capture timer control register
MSP status register
MSP mode register1
MSP mode register2
ISP RAM mapping address
ISP RAM programming counter register.
RAM YZ indirect addressing index pointer.
Stack 0 ~ stack 7 buffer.
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.2.1.3
Address
080H
081H
082H
083H
084H
085H
086H
087H
088H
089H
08AH
08BH
08CH
08DH
08EH
08FH
090H
091H
093H
094H
095H
096H
097H
098H
09AH
09BH
09CH
09DH
09EH
09FH
0A0H
0A1H
0A4H
0A5H
0A6H
0A7H
0AAH
0ABH
0ACH
0ADH
0B0H
0B1H
0B2H
0B3H
0B4H
0B5H
0B6H
0B7H
0B8H
0B9H
0BAH
0BBH
0BCH
0BDH
0BEH
0BFH
0C0H
0C1H
0C2H
0C3H
0C4H
0C5H
0C6H
0C7H
0C8H
0C9H
0CAH
BIT DEFINITION of SYSTEM REGISTER
Bit7
LBIT7
HBIT7
RBIT7
ZBIT7
YBIT7
XBIT7
POR
Bit6
LBIT6
HBIT6
RBIT6
ZBIT6
YBIT6
XBIT6
WDT
Bit5
LBIT5
HBIT5
RBIT5
ZBIT5
YBIT5
XBIT5
RST
Bit4
LBIT4
HBIT4
RBIT4
ZBIT4
YBIT4
XBIT4
STKOV
Bit3
LBIT3
HBIT3
RBIT3
ZBIT3
YBIT3
XBIT3
Bit2
LBIT2
HBIT2
RBIT2
ZBIT2
YBIT2
XBIT2
C
W0BIT7
W1BIT7
W2BIT7
W3BIT7
W4BIT7
W5BIT7
W6BIT7
W7BIT7
@HL7
@YZ7
PC7
W0BIT6
W1BIT6
W2BIT6
W3BIT6
W4BIT6
W5BIT6
W6BIT6
W7BIT6
@HL6
@YZ6
PC6
W0BIT5
W1BIT5
W2BIT5
W3BIT5
W4BIT5
W5BIT5
W6BIT5
W7BIT5
@HL5
@YZ5
PC5
WDTR7
ADCIRQ
WDTR6
T1IRQ
WDTR5
TC2IRQ
ADCIEN
T1IEN
TC2IEN
W0BIT4
W1BIT4
W2BIT4
W3BIT4
W4BIT4
W5BIT4
W6BIT4
W7BIT4
@HL4
@YZ4
PC4
PC12
CPUM1
WDTR4
TC1IRQ
MSPIRQ
TC1IEN
MSPIEN
W0BIT3
W1BIT3
W2BIT3
W3BIT3
W4BIT3
W5BIT3
W6BIT3
W7BIT3
@HL3
@YZ3
PC3
PC11
CPUM0
WDTR3
TC0IRQ
UTXIRQ
TC0IEN
UTXIEN
W0BIT2
W1BIT2
W2BIT2
W3BIT2
W4BIT2
W5BIT2
W6BIT2
W7BIT2
@HL2
@YZ2
PC2
PC10
CLKMD
WDTR2
T0IRQ
URXIRQ
T0IEN
URXIEN
P17OC
P17W
P16OC
P16W
P15OC
P15W
P14OC
P14W
P17M
P47M
P06M
P16M
P46M
P05M
P15M
P45M
P04M
P14M
P44M
P17
P47
P06
P16
P46
P05
P15
P45
P04
P14
P44
P17UR
P47UR
P06UR
P16UR
P46UR
P05UR
P15UR
P45UR
P04UR
P14UR
P44UR
P13OC
P13W
P01G1
P03M
P13M
P43M
P53M
P03
P13
P43
P53
P03UR
P13UR
P43UR
P53UR
P12OC
P12W
P01G0
P02M
P12M
P42M
P52M
P02
P12
P42
P52
P02UR
P12UR
P42UR
P52UR
T0ENB
T0C7
TC0ENB
TC0C7
TC0R7
TC0D7
TC1ENB
TC1C7
TC1R7
TC1D7
TC2ENB
TC2C7
TC2R7
TC2D7
T1ENB
T1C7
T1C15
CPTEN
CPTC7
CPTC15
P4CON7
T0rate2
T0C6
TC0rate2
TC0C6
TC0R6
TC0D6
TC1rate2
TC1C6
TC1R6
TC1D6
TC2rate2
TC2C6
TC2R6
TC2D6
T1rate2
T1C6
T1C14
T0rate1
T0C5
TC0rate1
TC0C5
TC0R5
TC0D5
TC1rate1
TC1C5
TC1R5
TC1D5
TC2rate1
TC2C5
TC2R5
TC2D5
T1rate1
T1C5
T1C13
T0rate0
T0C4
TC0rate0
TC0C4
TC0R4
TC0D4
TC1rate0
TC1C4
TC1R4
TC1D4
TC2rate0
TC2C4
TC2R4
TC2D4
T1rate0
T1C4
T1C12
T0C2
TC0CKS0
TC0C2
TC0R2
TC0D2
TC1CKS0
TC1C2
TC1R2
TC1D2
TC2CKS0
TC2C2
TC2R2
TC2D2
CPTC6
CPTC14
P4CON6
CPTC5
CPTC13
P4CON5
CPTC4
CPTC12
P4CON4
ADENB
ADB9
ADS
ADB8
ADCKS1
EOC
ADB7
ADLEN
GCHS
ADB6
ADCKS0
T0C3
TC0CKS1
TC0C3
TC0R3
TC0D3
TC1CKS1
TC1C3
TC1R3
TC1D3
TC2CKS1
TC2C3
TC2R3
TC2D3
T1CKS
T1C3
T1C11
CPTMD
CPTC3
CPTC11
P4CON3
P5CON3
CHS3
ADB5
SONiX TECHNOLOGY CO., LTD
T1C2
T1C10
CPTStart
CPTC2
CPTC10
P4CON2
P5CON2
CHS2
ADB4
Page 27
Bit1
Bit0
LBIT1
LBIT0
HBIT1
HBIT0
RBIT1
RBIT0
ZBIT1
ZBIT0
YBIT1
YBIT0
XBIT1
XBIT0
DC
Z
RBANKS1 RBANKS0
W0BIT1
W0BIT0
W1BIT1
W1BIT0
W2BIT1
W2BIT0
W3BIT1
W3BIT0
W4BIT1
W4BIT0
W5BIT1
W5BIT0
W6BIT1
W6BIT0
W7BIT1
W7BIT0
@HL1
@HL0
@YZ1
@YZ0
PC1
PC0
PC9
PC8
STPHX
WDTR1
WDTR0
P01IRQ
P00IRQ
SIOIRQ
WAKEIRQ
P01IEN
P00IEN
SIOIEN
WAKEIEN
P03OC
P02OC
P11OC
P10OC
P11W
P10W
P00G1
P00G0
P01M
P00M
P11M
P10M
P41M
P40M
P51M
P50M
P01
P00
P11
P10
P41
P40
P51
P50
P01UR
P00UR
P11UR
P10UR
P41UR
P40UR
P51UR
P50UR
T0TB
T0C1
T0C0
PWM0OUT
TC0C1
TC0C0
TC0R1
TC0R0
TC0D1
TC0D0
PWM1OUT
TC1C1
TC1C0
TC1R1
TC1R0
TC1D1
TC1D0
PWM2OUT
TC2C1
TC2C0
TC2R1
TC2R0
TC2D1
TC2D0
T1C1
T1C9
CPTG1
CPTC1
CPTC9
P4CON1
P5CON1
CHS1
ADB3
ADB1
T1C0
T1C8
CPTG0
CPTC0
CPTC8
P4CON0
P5CON0
CHS0
ADB2
ADB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Remarks
L
H
R
Z
Y
X
PFLAG
RBANK
W0
W1
W2
W3
W4
W5
W6
W7
@HL
@YZ
PCL
PCH
OSCM
WDTR
INTRQ0
INTRQ1
INTEN0
INTEN1
P0OC
P1OC
P1W
PEDGE
P0M
P1M
P4M
P5M
P0
P1
P4
P5
P0UR
P1UR
P4UR
P5UR
T0M
T0C
TC0M
TC0C
TC0R
TC0D
TC1M
TC1C
TC1R
TC1D
TC2M
TC2C
TC2R
TC2D
T1M
T1CL
T1CH
CPTM
CPTCL
CPTCH
P4CON
P5CON
ADM
ADB
ADR
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
0CBH
0DBH
0DCH
0DDH
0DEH
0DFH
0E0H
0E1H
0E2H
0E3H
0E4H
0E5H
0E6H
0E7H
0E8H
0EAH
0EBH
0ECH
0EDH
0EEH
0EFH
0F0H
0F1H
0F2H
0F3H
0F4H
0F5H
0F6H
0F7H
0F8H
0F9H
0FAH
0FBH
0FCH
0FDH
0FEH
0FFH
ADTS1
PECMD7
PEROML7
PEROMH7
PERAML7
PERAMCN
T7
SENB
SIOR7
SIOB7
ADTS0
PECMD6
PEROML6
PEROMH6
PERAML6
PERAMCN
T6
START
SIOR6
SIOB6
ADT3
ADT2
ADT1
ADT0
PECMD3
PECMD2
PECMD1
PECMD0
PEROML3 PEROML2 PEROML1 PEROML0
PEROMH3 PEROMH2 PEROMH1 PEROMH0
PERAML3 PERAML2 PERAML1 PERAML0
PERAMCN
PERAML9 PERAML8
T3
MLSB
SCLKMD
CPOL
CPHA
SIOR3
SIOR2
SIOR1
SIOR0
SIOB3
SIOB2
SIOB1
SIOB0
SIOBZ
SCSEN
SCSP
UTXEN
UTXPEN
UTXPS
UTXBRK
URXBZ
UTXBZ
URXEN
URXPEN
URXPS
URXPC
UFMER
URS2
URS1
URS0
URCR7
URCR6
URCR5
URCR4
URCR3
URCR2
URCR1
URCR0
UTXD7
UTXD6
UTXD5
UTXD4
UTXD3
UTXD2
UTXD1
UTXD0
URXD7
URXD6
URXD5
URXD4
URXD3
URXD2
URXD1
URXD0
CKE
D_A
P
S
RED_WRT
BF
WCOL
MSPOV
MSPENB
CKP
SLRXCKP MSPWK
MSPC
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
MSPBUF7 MSPBUF6 MSPBUF5 MSPBUF4 MSPBUF3 MSPBUF2 MSPBUF1 MSPBUF0
MSPADR7 MSPADR6 MSPADR5 MSPADR4 MSPADR3 MSPADR2 MSPADR1 MSPADR0
GIE
LVD24
LVD33
STKPB2
STKPB1
STKPB0
S7PC7
S7PC6
S7PC5
S7PC4
S7PC3
S7PC2
S7PC1
S7PC0
S7PC12
S7PC11
S7PC10
S7PC9
S7PC8
S6PC7
S6PC6
S6PC5
S6PC4
S6PC3
S6PC2
S6PC1
S6PC0
S6PC12
S6PC11
S6PC10
S6PC9
S6PC8
S5PC7
S5PC6
S5PC5
S5PC4
S5PC3
S5PC2
S5PC1
S5PC0
S5PC12
S5PC11
S5PC10
S5PC9
S5PC8
S4PC7
S4PC6
S4PC5
S4PC4
S4PC3
S4PC2
S4PC1
S4PC0
S4PC12
S4PC11
S4PC10
S4PC9
S4PC8
S3PC7
S3PC6
S3PC5
S3PC4
S3PC3
S3PC2
S3PC1
S3PC0
S3PC12
S3PC11
S3PC10
S3PC9
S3PC8
S2PC7
S2PC6
S2PC5
S2PC4
S2PC3
S2PC2
S2PC1
S2PC0
S2PC12
S2PC11
S2PC10
S2PC9
S2PC8
S1PC7
S1PC6
S1PC5
S1PC4
S1PC3
S1PC2
S1PC1
S1PC0
S1PC12
S1PC11
S1PC10
S1PC9
S1PC8
S0PC7
S0PC6
S0PC5
S0PC4
S0PC3
S0PC2
S0PC1
S0PC0
S0PC12
S0PC11
S0PC10
S0PC9
S0PC8
PECMD5
PEROML5
PEROMH5
PERAML5
PERAMCN
T5
SRATE1
SIOR5
SIOB5
ADT4
PECMD4
PEROML4
PEROMH4
PERAML4
PERAMCN
T4
SRATE0
SIOR4
SIOB4
R/W
R/W
R/W
R/W
R/W
ADT
PECMD
PEROML
PEROMH
PERAML
R/W
PERAMCNT
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SIOM
SIOR
SIOB
SIOC
URTX
URRX
URCR
UTXD
URXD
MSPSTAT
MSPM1
MSPM2
MSPBUF
MSPADR
STKP
STK7L
STK7H
STK6L
STK6H
STK5L
STK5H
STK4L
STK4H
STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
Note:
1.
To avoid system error, make sure to put all the “0” and “1” as it indicates in the above table.
2.
All of register names had been declared in SN8ASM assembler.
3.
One-bit name had been declared in SN8ASM assembler with “F” prefix code.
4.
“b0bset”, “b0bclr”,”bset”,”bclr” instructions are only available to the “R/W” registers.
SONiX TECHNOLOGY CO., LTD
Page 28
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.2.2 ACCUMULATOR
The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If
the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.
ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing
mode.
Example: Read and write ACC value.
; Read ACC data and store in BUF data memory
MOV
BUF, A
; Write a immediate data into ACC
MOV
A, #0FH
; Write ACC data from BUF data memory
MOV
A, BUF
The system will store ACC and working registers (0x80-0x8F) by hardware automatically when interrupt executed.
Example: Protect ACC and working registers.
.CODE
INT_SERVICE:
; Save ACC to buffer.
; Save working registers to buffer.
…
…
.
; Load working registers form buffers.
; Load ACC form buffer.
RETI
SONiX TECHNOLOGY CO., LTD
; Exit interrupt service vector
Page 29
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.2.3 PROGRAM FLAG
The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status.
POR, WDT, and RST bits indicate system reset status including power on reset, LVD reset, reset by external pin active
and watchdog reset. C, DC, Z bits indicate the result status of ALU operation. LVD24, LVD33 bits indicate LVD
detecting power voltage status.
086H
PFLAG
Read/Write
After Reset
Bit 7
POR
R
-
Bit 6
WDT
R
-
Bit 5
RST
R
-
Bit 4
STKOV
R
-
Bit 3
-
Bit 2
C
R/W
0
Bit 1
DC
R/W
0
Bit 0
Z
R/W
0
Bit 7
POR: Power on reset and LVD brown-out reset indicator.
0 = Non-active.
1 = Reset active. LVD announces reset flag.
Bit 6
WDT: Watchdog reset indicator.
0 = Non-active.
1 = Reset active. Watchdog announces reset flag.
Bit 5
RST: External reset indicator.
0 = Non-active.
1 = Reset active. External reset announces reset flag.
Bit 4
STKOV: Stack overflow indicator.
0 = Non-overflow.
1 = Stack overflow.
Bit 2
C: Carry flag
1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic “1”, comparison
result ≥ 0.
0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic “0”, comparison
result < 0.
Bit 1
DC: Decimal carry flag
1 = Addition with carry from low nibble, subtraction without borrow from high nibble.
0 = Addition without carry from low nibble, subtraction with borrow from high nibble.
Bit 0
Z: Zero flag
1 = The result of an arithmetic/logic/branch operation is zero.
0 = The result of an arithmetic/logic/branch operation is not zero.
0EFH
STKP
Read/Write
After Reset
Bit 7
GIE
R/W
0
Bit 6
LVD24
R
-
Bit 5
LVD33
R
-
Bit 6
LVD24: LVD24 low voltage detect indicator.
0 = Vdd > LVD24 detect level.
1 = Vdd < LVD24 detect level.
Bit 5
LVD33: LVD33 low voltage detect indicator.
0 = Vdd > LVD33 detect level.
1 = Vdd < LVD33 detect level.
Bit 4
-
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
Note: Refer to instruction set table for detailed information of C, DC and Z flags.
SONiX TECHNOLOGY CO., LTD
Page 30
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.2.4 PROGRAM COUNTER
The program counter (PC) is a 13-bit binary counter separated into the high-byte 5 and the low-byte 8 bits. This
counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program
counter is automatically incremented with each instruction during program execution.
Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction
is executed, the destination address will be inserted to bit 0 ~ bit 12.
PC
After
reset
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
PC12 PC11 PC10 PC9
-
-
-
0
0
0
0
Bit 8
PC8
Bit 7
PC7
Bit 6
PC6
Bit 5
PC5
Bit 4
PC4
Bit 3
PC3
Bit 2
PC2
Bit 1
PC1
Bit 0
PC0
0
0
0
0
0
0
0
0
0
PCH
PCL
ONE ADDRESS SKIPPING
There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one
address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction.
If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction.
FC
C0STEP
; To skip, if Carry_flag = 1
; Else jump to C0STEP.
C0STEP:
B0BTS1
JMP
…
…
NOP
A, BUF0
FZ
C1STEP
; Move BUF0 value to ACC.
; To skip, if Zero flag = 0.
; Else jump to C1STEP.
C1STEP:
B0MOV
B0BTS0
JMP
…
…
NOP
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.
C0STEP:
CMPRS
JMP
…
…
NOP
A, #12H
C0STEP
SONiX TECHNOLOGY CO., LTD
; To skip, if ACC = 12H.
; Else jump to C0STEP.
Page 31
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next
instruction.
INCS instruction:
C0STEP:
INCS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if ACC is not zero.
INCMS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if BUF0 is not zero.
INCMS instruction:
C0STEP:
If the destination decreased by 1, which results underflow of 0x01 to 0x00, the PC will add 2 steps to skip next
instruction.
DECS instruction:
C0STEP:
DECS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if ACC is not zero.
DECMS
JMP
…
…
NOP
BUF0
C0STEP
; Jump to C0STEP if BUF0 is not zero.
DECMS instruction:
C0STEP:
SONiX TECHNOLOGY CO., LTD
Page 32
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
MULTI-ADDRESS JUMPING
Users can jump around the multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate
multi-address jumping function. Program Counter supports “ADD M,A”, ”ADC M,A” and “B0ADD M,A” instructions
for carry to PCH when PCL overflow automatically. For jump table or others applications, users can calculate PC value
by the three instructions and don’t care PCL overflow problem.
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
Example: If PC = 0323H
(PCH = 03H, PCL = 23H)
; PC = 0323H
MOV
B0MOV
…
A, #28H
PCL, A
; Jump to address 0328H
MOV
B0MOV
…
A, #00H
PCL, A
; Jump to address 0300H
; PC = 0328H
Example: If PC = 0323H
(PCH = 03H, PCL = 23H)
; PC = 0323H
B0ADD
JMP
JMP
JMP
JMP
…
…
PCL, A
A0POINT
A1POINT
A2POINT
A3POINT
SONiX TECHNOLOGY CO., LTD
; PCL = PCL + ACC, the PCH cannot be changed.
; If ACC = 0, jump to A0POINT
; ACC = 1, jump to A1POINT
; ACC = 2, jump to A2POINT
; ACC = 3, jump to A3POINT
Page 33
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.2.5 H, L REGISTERS
The H and L registers are the 8-bit buffers. There are two major functions of these registers.
Can be used as general working registers
Can be used as RAM data pointers with @HL register
081H
H
Read/Write
After reset
Bit 7
HBIT7
R/W
-
Bit 6
HBIT6
R/W
-
Bit 5
HBIT5
R/W
-
Bit 4
HBIT4
R/W
-
Bit 3
HBIT3
R/W
-
Bit 2
HBIT2
R/W
-
Bit 1
HBIT1
R/W
-
Bit 0
HBIT0
R/W
-
080H
L
Read/Write
After reset
Bit 7
LBIT7
R/W
-
Bit 6
LBIT6
R/W
-
Bit 5
LBIT5
R/W
-
Bit 4
LBIT4
R/W
-
Bit 3
LBIT3
R/W
-
Bit 2
LBIT2
R/W
-
Bit 1
LBIT1
R/W
-
Bit 0
LBIT0
R/W
-
Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode to
access data as following.
B0MOV
B0MOV
B0MOV
H, #00H
L, #20H
A, @HL
; To set RAM bank 0 for H register
; To set location 20H for L register
; To read a data into ACC
Example: Clear general-purpose data memory area of bank 0 using @HL register.
CLR
B0MOV
H
L, #07FH
; H = 0, bank 0
; L = 7FH, the last address of the data memory area
CLR
DECMS
JMP
@HL
L
CLR_HL_BUF
; Clear @HL to be zero
; L – 1, if L = 0, finish the routine
; Not zero
CLR
@HL
CLR_HL_BUF:
END_CLR:
; End of clear general purpose data memory area of bank 0
…
…
SONiX TECHNOLOGY CO., LTD
Page 34
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.2.6 X REGISTERS
X register is an 8-bit buffer and only general working register purpose.
Can be used as general working registers
085H
X
Read/Write
After reset
Bit 7
XBIT7
R/W
-
Bit 6
XBIT6
R/W
-
Bit 5
XBIT5
R/W
-
Bit 4
XBIT4
R/W
-
Bit 3
XBIT3
R/W
-
Bit 2
XBIT2
R/W
-
Bit 1
XBIT1
R/W
-
Bit 0
XBIT0
R/W
-
2.2.7 Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers.
Can be used as general working registers
Can be used as RAM data pointers with @YZ register
Can be used as ROM data pointer with the MOVC instruction for look-up table
084H
Y
Read/Write
After reset
Bit 7
YBIT7
R/W
-
Bit 6
YBIT6
R/W
-
Bit 5
YBIT5
R/W
-
Bit 4
YBIT4
R/W
-
Bit 3
YBIT3
R/W
-
Bit 2
YBIT2
R/W
-
Bit 1
YBIT1
R/W
-
Bit 0
YBIT0
R/W
-
083H
Z
Read/Write
After reset
Bit 7
ZBIT7
R/W
-
Bit 6
ZBIT6
R/W
-
Bit 5
ZBIT5
R/W
-
Bit 4
ZBIT4
R/W
-
Bit 3
ZBIT3
R/W
-
Bit 2
ZBIT2
R/W
-
Bit 1
ZBIT1
R/W
-
Bit 0
ZBIT0
R/W
-
Example:
Uses Y, Z register as the data pointer to access data in the RAM address 025H of bank0.
B0MOV
B0MOV
B0MOV
Example:
Y, #00H
Z, #25H
A, @YZ
; To set RAM bank 0 for Y register
; To set location 25H for Z register
; To read a data into ACC
Uses the Y, Z register as data pointer to clear the RAM data.
B0MOV
B0MOV
Y, #0
Z, #07FH
; Y = 0, bank 0
; Z = 7FH, the last address of the data memory area
CLR
@YZ
; Clear @YZ to be zero
DECMS
JMP
Z
CLR_YZ_BUF
; Z – 1, if Z= 0, finish the routine
; Not zero
CLR
@YZ
CLR_YZ_BUF:
END_CLR:
; End of clear general purpose data memory area of bank 0
…
SONiX TECHNOLOGY CO., LTD
Page 35
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.2.8 R REGISTER
R register is an 8-bit buffer. There are two major functions of the register.
Can be used as working register
For store high-byte data of look-up table
(MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the
low-byte data will be stored in ACC).
082H
R
Read/Write
After reset
Bit 7
RBIT7
R/W
-
Bit 6
RBIT6
R/W
-
Bit 5
RBIT5
R/W
-
Bit 4
RBIT4
R/W
-
Bit 3
RBIT3
R/W
-
Bit 2
RBIT2
R/W
-
Bit 1
RBIT1
R/W
-
Bit 0
RBIT0
R/W
-
Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.
SONiX TECHNOLOGY CO., LTD
Page 36
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.2.9 W REGISTERS
W register includes W0~W7 8-bit buffers. There are two major functions of the register.
Can be used as general working registers in assembly language situation.
Can be used as program buffers in C-language situation.
088H
W0
Read/Write
After reset
Bit 7
W0BIT7
R/W
-
Bit 6
W0BIT6
R/W
-
Bit 5
W0BIT5
R/W
-
Bit 4
W0BIT4
R/W
-
Bit 3
W0BIT3
R/W
-
Bit 2
W0BIT2
R/W
-
Bit 1
W0BIT1
R/W
-
Bit 0
W0BIT0
R/W
-
089H
W1
Read/Write
After reset
Bit 7
W1BIT7
R/W
-
Bit 6
W1BIT6
R/W
-
Bit 5
W1BIT5
R/W
-
Bit 4
W1BIT4
R/W
-
Bit 3
W1BIT3
R/W
-
Bit 2
W1BIT2
R/W
-
Bit 1
W1BIT1
R/W
-
Bit 0
W1BIT0
R/W
-
08AH
W2
Read/Write
After reset
Bit 7
W2BIT7
R/W
-
Bit 6
W2BIT6
R/W
-
Bit 5
W2BIT5
R/W
-
Bit 4
W2BIT4
R/W
-
Bit 3
W2BIT3
R/W
-
Bit 2
W2BIT2
R/W
-
Bit 1
W2BIT1
R/W
-
Bit 0
W2BIT0
R/W
-
08BH
W3
Read/Write
After reset
Bit 7
W3BIT7
R/W
-
Bit 6
W3BIT6
R/W
-
Bit 5
W3BIT5
R/W
-
Bit 4
W3BIT4
R/W
-
Bit 3
W3BIT3
R/W
-
Bit 2
W3BIT2
R/W
-
Bit 1
W3BIT1
R/W
-
Bit 0
W3BIT0
R/W
-
08CH
W4
Read/Write
After reset
Bit 7
W4BIT7
R/W
-
Bit 6
W4BIT6
R/W
-
Bit 5
W4BIT5
R/W
-
Bit 4
W4BIT4
R/W
-
Bit 3
W4BIT3
R/W
-
Bit 2
W4BIT2
R/W
-
Bit 1
W4BIT1
R/W
-
Bit 0
W4BIT0
R/W
-
08DH
W5
Read/Write
After reset
Bit 7
W5BIT7
R/W
-
Bit 6
W5BIT6
R/W
-
Bit 5
W5BIT5
R/W
-
Bit 4
W5BIT4
R/W
-
Bit 3
W5BIT3
R/W
-
Bit 2
W5BIT2
R/W
-
Bit 1
W5BIT1
R/W
-
Bit 0
W5BIT0
R/W
-
08EH
W6
Read/Write
After reset
Bit 7
W6BIT7
R/W
-
Bit 6
W6BIT6
R/W
-
Bit 5
W6BIT5
R/W
-
Bit 4
W6BIT4
R/W
-
Bit 3
W6BIT3
R/W
-
Bit 2
W6BIT2
R/W
-
Bit 1
W6BIT1
R/W
-
Bit 0
W6BIT0
R/W
-
08FH
W7
Read/Write
After reset
Bit 7
W7BIT7
R/W
-
Bit 6
W7BIT6
R/W
-
Bit 5
W7BIT5
R/W
-
Bit 4
W7BIT4
R/W
-
Bit 3
W7BIT3
R/W
-
Bit 2
W7BIT2
R/W
-
Bit 1
W7BIT1
R/W
-
Bit 0
W7BIT0
R/W
-
Note:
1. In assembly language situation, W0~W7 can be used as general working registers.
2. In C-language situation, W0~W7 are reserved for C-compiler, and recommend not to access W0~W7
by program strongly.
SONiX TECHNOLOGY CO., LTD
Page 37
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.3 ADDRESSING MODE
2.3.1 IMMEDIATE ADDRESSING MODE
The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM.
Example: Move the immediate data 12H to ACC.
MOV
; To set an immediate data 12H into ACC.
Example: Move the immediate data 12H to R register.
B0MOV
A, #12H
R, #12H
; To set an immediate data 12H into R register.
Note: In immediate addressing mode application, the specific RAM must be 0x80~0x8F working register.
2.3.2 DIRECTLY ADDRESSING MODE
The directly addressing mode moves the content of RAM location in or out of ACC.
Example: Move 0x12 RAM location data into ACC.
B0MOV
A, 12H
; To get a content of RAM location 0x12 of bank 0 and save in
ACC.
Example: Move ACC data into 0x12 RAM location.
B0MOV
12H, A
; To get a content of ACC and save in RAM location 12H of
bank 0.
2.3.3 INDIRECTLY ADDRESSING MODE
The indirectly addressing mode is to access the memory by the data pointer registers (H/L, Y/Z).
Example: Indirectly addressing mode with @HL register
B0MOV
B0MOV
B0MOV
H, #0
L, #12H
A, @HL
; To clear H register to access RAM bank 0.
; To set an immediate data 12H into L register.
; Use data pointer @HL reads a data from RAM location
; 012H into ACC.
Example: Indirectly addressing mode with @YZ register
B0MOV
B0MOV
B0MOV
Y, #0
Z, #12H
A, @YZ
SONiX TECHNOLOGY CO., LTD
; To clear Y register to access RAM bank 0.
; To set an immediate data 12H into Z register.
; Use data pointer @YZ reads a data from RAM location
; 012H into ACC.
Page 38
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.4 STACK OPERATION
2.4.1 OVERVIEW
The stack buffer has 8-level. These buffers are designed to push and pop up program counter’s (PC) data when
interrupt service routine and “CALL” instruction are executed. The STKP register is a pointer designed to point active
level in order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program
counter (PC) data.
RET /
RETI
STKP + 1
CALL /
INTERRUPT
PCH
PCL
STACK Level
STACK Buffer
High Byte
STACK Buffer
Low Byte
STKP = 7
STK7H
STK7L
STKP = 6
STK6H
STK6L
STKP - 1
STKP = 5
STK5H
STKP
STK5L
STKP
STKP = 4
STK4H
STK4L
STKP = 3
STK3H
STK3L
STKP = 2
STK2H
STK2L
STKP = 1
STK1H
STK1L
STKP = 0
STK0H
STK0L
2.4.2 STACK POINTER
The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 13-bit data memory
(STKnH and STKnL) set aside for temporary storage of stack addresses. The two stack operations are writing to the
top of the stack (push) and reading from the top of stack (pop). Push operation decrements the STKP and the pop
operation increments each time. That makes the STKP always point to the top address of stack buffer and write the
last program counter value (PC) into the stack buffer.
0EFH
STKP
Read/Write
After reset
Bit 7
GIE
R/W
0
Bit 6
LVD24
R
-
Bit 5
LVD33
R
-
Bit 4
-
Bit[2:0]
STKPBn: Stack pointer (n = 0 ~ 2)
Bit 7
GIE: Global interrupt control bit.
0 = Disable.
1 = Enable. Please refer to the interrupt chapter.
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointers in the
beginning of the program.
MOV
B0MOV
A, #00000111B
STKP, A
SONiX TECHNOLOGY CO., LTD
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Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.4.3 STACK BUFFER
The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt
service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer
(STKnH and STKnL) are located in the system register area bank 0.
0F0H~0FFH
STKnH
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
SnPC12
R/W
0
Bit 3
SnPC11
R/W
0
Bit 2
SnPC10
R/W
0
Bit 1
SnPC9
R/W
0
Bit 0
SnPC8
R/W
0
0F0H~0FFH
STKnL
Read/Write
After reset
Bit 7
SnPC7
R/W
0
Bit 6
SnPC6
R/W
0
Bit 5
SnPC5
R/W
0
Bit 4
SnPC4
R/W
0
Bit 3
SnPC3
R/W
0
Bit 2
SnPC2
R/W
0
Bit 1
SnPC1
R/W
0
Bit 0
SnPC0
R/W
0
STKn = STKnH , STKnL (n = 7 ~ 0)
2.4.4 STACK OVERFLOW INDICATOR
If stack pointer is normal and not overflow, the program execution is correct. If stack overflows, the program counter
would be incorrect making program execution error. STKOV bit is stack pointer overflow indicator to monitor stack
pointer status. When STKOV=0, stack pointer status is normal. If STKOV=1, stack overflow occurs, and the program
execution would be error. The program can take measures to recover program execution from stack overflow situation
through STKOV bit.
086H
PFLAG
Read/Write
After Reset
Bit 4
Bit 7
POR
R
-
Bit 6
WDT
R
-
Bit 5
RST
R
-
Bit 4
STKOV
R
-
Bit 3
-
Bit 2
C
R/W
0
Bit 1
DC
R/W
0
Bit 0
Z
R/W
0
STKOV: Stack overflow indicator.
0 = Non-overflow.
1 = Stack overflow.
Note: If STKOV bit is set as stack overflowing, only system reset event can clear STKOV bit, e.g.
watchdog timer overflow, external reset pin low status or LVD reset.
Example: Stack overflow protection through watchdog reset. Watchdog timer must be enabled.
MAIN:
…
StackChk:
B0BTS1
JMP
JMP
STKOV
MAIN
$
; STKOV=0, program keeps executing.
; STKOV=1, stack overflows, and use “jump here” operation
; making watchdog timer overflow to trigger system reset.
Example: Stack overflow protection through external reset. External reset function must be enabled, and
one GPIO pin (output mode) connects to external reset pin.
MAIN:
…
StackChk:
B0BTS1
JMP
B0BCLR
STKOV
MAIN
P1.0
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; STKOV=0, program keeps executing.
; STKOV=1, stack overflows, and set P1.0 output low status to
; force reset pin to low status to trigger system reset.
Page 40
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.4.5 STACK OPERATION EXAMPLE
The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC)
to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to
the next available stack location. The stack buffer stores the program counter about the op-code address. The
Stack-Save operation is as the following table.
Stack Level
0
1
2
3
4
5
6
7
8
>8
STKPB2
1
1
1
1
0
0
0
0
1
1
STKP Register
STKPB1
STKPB0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
Stack Buffer
High Byte Low Byte
Free
Free
STK0H
STK0L
STK1H
STK1L
STK2H
STK2L
STK3H
STK3L
STK4H
STK4L
STK5H
STK5L
STK6H
STK6L
STK7H
STK7L
-
STKOV
Description
0
0
0
0
0
0
0
0
0
1
Stack Over, error
There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI
instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs,
the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter
(PC) to the program counter registers. The Stack-Restore operation is as the following table.
Stack Level
8
7
6
5
4
3
2
1
0
STKPB2
1
0
0
0
0
1
1
1
1
STKP Register
STKPB1
STKPB0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Stack Buffer
High Byte Low Byte
STK7H
STK6H
STK5H
STK4H
STK3H
STK2H
STK1H
STK0H
Free
STK7L
STK6L
STK5L
STK4L
STK3L
STK2L
STK1L
STK0L
Free
STKOV
Description
0
0
0
0
0
0
0
0
0
-
Note: When stack overflow occurs, the system detects the condition and set STKOV flag (“Logic 1”).
STKOV flag can’t be cleared by program.
SONiX TECHNOLOGY CO., LTD
Page 41
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.5 CODE OPTION TABLE
The code option is the system hardware configurations including oscillator type, noise filter option, watchdog timer
operation, LVD option, reset pin option and Flash ROM security control. The code option items are as following table:
Code Option
Content
IHRC_16M
IHRC_RTC
High_Clk
RC
32K X’tal
12M X’tal
High_Fcpu
Low_Fcpu
Noise_Filter
WDT_CLK
4M X’tal
Fhosc/1
Fhosc/2
Fhosc/4
Fhosc/8
Fhosc/16
Fhosc/32
Fhosc/64
Fhosc/128
Flosc/1
Flosc/2
Flosc/4
Flosc/8
Enable
Disable
Flosc/4
Flosc/8
Flosc/16
Flosc/32
Always_On
Watch_Dog
Reset_Pin
Security
Enable
Disable
Reset
P04
Enable
Disable
LVD_L
LVD_M
LVD
LVD_H
LVD_MAX
SONiX TECHNOLOGY CO., LTD
Function Description
High speed internal 16MHz RC. XIN/XOUT pins are bi-direction GPIO
mode.
High speed internal 16MHz RC. XIN/XOUT pins are connected to
external 32768Hz crystal.
Low cost RC for external high clock oscillator. XIN pin is connected to RC
oscillator. XOUT pin is bi-direction GPIO mode.
Low frequency, power saving crystal (e.g. 32.768KHz) for external high
clock oscillator.
High speed crystal /resonator (e.g. 12MHz) for external high clock
oscillator.
Standard crystal /resonator (e.g. 4M) for external high clock oscillator.
Normal mode instruction cycle is 1 high speed oscillator clocks.
Normal mode instruction cycle is 2 high speed oscillator clocks.
Normal mode instruction cycle is 4 high speed oscillator clocks.
Normal mode instruction cycle is 8 high speed oscillator clocks.
Normal mode instruction cycle is 16 high speed oscillator clocks.
Normal mode instruction cycle is 32 high speed oscillator clocks.
Normal mode instruction cycle is 64 high speed oscillator clocks.
Normal mode instruction cycle is 128 high speed oscillator clocks.
Slow mode instruction cycle is 1 low speed oscillator clocks.
Slow mode instruction cycle is 2 low speed oscillator clocks.
Slow mode instruction cycle is 4 low speed oscillator clocks.
Slow mode instruction cycle is 8 low speed oscillator clocks.
Enable Noise Filter.
Disable Noise Filter.
Watchdog timer clock source Flosc/4.
Watchdog timer clock source Flosc/8.
Watchdog timer clock source Flosc/16.
Watchdog timer clock source Flosc/32.
Watchdog timer is always on enable even in power down and green
mode.
Enable watchdog timer. Watchdog timer stops in power down mode and
green mode.
Disable Watchdog function.
Enable External reset pin.
Enable P0.4.
Enable ROM code Security function.
Disable ROM code Security function.
LVD will reset chip if VDD is below 1.8V
LVD will reset chip if VDD is below 1.8V
Enable LVD24 bit of PFLAG register for 2.4V low voltage indicator.
LVD will reset chip if VDD is below 2.4V
Enable LVD33 bit of PFLAG register for 3.3V low voltage indicator.
LVD will reset chip if VDD is below 3.3V
Page 42
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
2.5.1 Fcpu Code Option
Fcpu means instruction cycle whose clock source includes high/low speed oscillator in different operating modes.
High_Fcpu and Low_Fcpu code options select instruction cycle pre-scaler to decide instruction cycle rate. In normal
mode (high speed clock), the system clock source is high speed oscillator, and Fcpu clock rate has eight options
including Fhosc/1, Fhosc/2, Fhosc/4, Fhosc/8, Fhosc/16, Fhosc/32, Fhosc/64, Fhosc/128. In slow mode (low speed
clock), the system clock source is internal low speed RC oscillator, and the Fcpu including Flosc/1, Flosc/2, Flosc/4,
Flosc/8.
2.5.2 Reset_Pin code option
The reset pin is shared with general input only pin controlled by code option.
Reset: The reset pin is external reset function. When falling edge trigger occurring, the system will be reset.
P04: Set reset pin to general bi-direction pin (P0.4). The external reset function is disabled and the pin is
bi-direction pin.
2.5.3 Security code option
Security code option is Flash ROM protection. When enable security code option, the ROM code is secured and not
dumped complete ROM contents.
2.5.4 Noise Filter code option
Noise Filter code option is a power noise filter manner to reduce noisy effect of system clock. If noise filter enable, In
high noisy environment, enable noise filter, enable watchdog timer and select a good LVD level can make whole
system work well and avoid error event occurrence.
SONiX TECHNOLOGY CO., LTD
Page 43
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
3 RESET
3.1 OVERVIEW
The system would be reset in three conditions as following.
Power on reset
Watchdog reset
Brown out reset
External reset (only supports external reset pin enable situation)
When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared.
After reset status released, the system boots up and program starts to execute from ORG 0. The POR, WDT and RST
flags indicate system reset status. The system can depend on POR, WDT and RST status and go to different paths by
program.
086H
PFLAG
Read/Write
After reset
Bit 7
Bit 6
Bit 5
Bit 7
POR
R
-
Bit 6
WDT
R
-
Bit 5
RST
R
-
Bit 4
STKOV
R
-
Bit 3
-
Bit 2
C
R/W
0
Bit 1
DC
R/W
0
Bit 0
Z
R/W
0
POR: Power on reset and LVD brown-out reset indicator.
0 = Non-active.
1 = Reset active. LVD announces reset flag.
WDT: Watchdog reset indicator.
0 = Non-active.
1 = Reset active. Watchdog announces reset flag.
RST: External reset indicator.
0 = Non-active.
1 = Reset active. External reset announces reset flag.
Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset
successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of
different oscillator is not fixed. RC type oscillator’s start-up time is very short, but the crystal type is longer. Under client
terminal application, users have to take care the power on reset time for the master terminal requirement. The reset
timing diagram is as following.
VDD
Power
LVD Detect Level
VSS
VDD
External Reset
VSS
External Reset
Low Detect
External Reset
High Detect
Watchdog
Overflow
Watchdog Normal Run
Watchdog Reset
Watchdog Stop
System Normal Run
System Status
System Stop
Power On
Delay Time
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External
Reset Delay
Time
Page 44
Watchdog
Reset Delay
Time
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
3.2 POWER ON RESET
The power on reset depend no LVD operation for most power-up situations. The power supplying to system is a rising
curve and needs some time to achieve the normal voltage. Power on reset sequence is as following.
Power-up: System detects the power voltage up and waits for power stable.
External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
3.3 WATCHDOG RESET
Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program.
Under error condition, system is in unknown situation and watchdog can’t be clear by program before watchdog timer
overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and
returns normal mode. Watchdog reset sequence is as following.
Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the
system is reset.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
Watchdog timer application note is as following.
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information.
3.4 BROWN OUT RESET
The brown out reset is a power dropping condition. The power drops from normal voltage to low voltage by external
factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well
or executing program error.
VDD
System Work
Well Area
V1
V2
V3
System Work
Error Area
VSS
Brown Out Reset Diagram
SONiX TECHNOLOGY CO., LTD
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Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
The power dropping might through the voltage range that’s the system dead-band. The dead-band means the power
range can’t offer the system minimum operation power requirement. The above diagram is a typical brown out reset
diagram. There is a serious noise under the VDD, and VDD voltage drops very deep. There is a dotted line to separate
the system working area. The above area is the system work well area. The below area is the system work error area
called dead-band. V1 doesn’t touch the below area and not effect the system operation. But the V2 and V3 is under the
below area and may induce the system error occurrence. Let system under dead-band includes some conditions.
DC application:
The power source of DC application is usually using battery. When low battery condition and MCU drive any loading,
the power drops and keeps in dead-band. Under the situation, the power won’t drop deeper and not touch the system
reset voltage. That makes the system under dead-band.
AC application:
In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC
noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating
induces noise and overlaps with the DC power. VDD drops by the noise, and the system works under unstable power
situation.
The power on duration and power down duration are longer in AC application. The system power on sequence protects
the power on successful, but the power down situation is like DC low battery condition. When turn off the AC power,
the VDD drops slowly and through the dead-band for a while.
3.4.1 THE SYSTEM OPERATING VOLTAGE
To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system
executing rate and power level. Different system executing rates have different system minimum operating voltage.
The electrical characteristic section shows the system voltage to executing rate relationship.
System Mini.
Operating Voltage.
Vdd (V)
Normal Operating
Area
Dead-Band Area
Reset Area
System Reset
Voltage.
System Rate (Fcpu)
Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is
decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even
higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system
reset voltage.
3.4.2 LOW VOLTAGE DETECTOR (LVD)
VDD
Power
LVD Detect Voltage
VSS
Power is below LVD Detect
Voltage and System Reset.
System Normal Run
System Status
System Stop
Power On
Delay Time
SONiX TECHNOLOGY CO., LTD
Page 46
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and
is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by
each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to
improve brown out reset is depend on application requirement and environment. If the power variation is very deep,
violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and
make system work error, the LVD can’t be the protection and need to other reset methods. More detail LVD information
is in the electrical characteristic section.
The LVD is three levels design (1.8V/2.4V/3.3V) and controlled by LVD code option. The 1.8V LVD is always enable for
power on reset and Brown Out reset. The 2.4V LVD includes LVD reset function and flag function to indicate VDD
status function. The 3.3V includes flag function to indicate VDD status. LVD flag function can be an easy low battery
detector. LVD24, LVD33 flags indicate VDD voltage level. For low battery detect application, only checking LVD24,
LVD33 status to be battery status. This is a cheap and easy solution.
0EFH
STKP
Read/Write
After Reset
Bit 7
GIE
R/W
0
Bit 6
LVD24
R
-
Bit 5
LVD33
R
-
Bit 6
LVD24: LVD24 low voltage detect indicator.
0 = Vdd > LVD24 detect level.
1 = Vdd < LVD24 detect level.
Bit 5
LVD33: LVD33 low voltage detect indicator.
0 = Vdd > LVD33 detect level.
1 = Vdd < LVD33 detect level.
LVD
1.8V Reset
2.4V Flag
2.4V Reset
3.3V Flag
LVD_L
Available
-
Bit 4
-
Bit 3
-
LVD Code Option
LVD_M
Available
Available
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
LVD_H
Available
Available
Available
LVD_L
If VDD < 1.8V, system will be reset.
Disable LVD24 and LVD33 bit of PFLAG register.
LVD_M
If VDD < 1.8V, system will be reset.
Enable LVD24 bit of PFLAG register. If VDD > 2.4V, LVD24 is “0”. If VDD 2.4V, LVD24 is “0”. If VDD 3.3V, LVD33 is “0”. If VDD R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external
reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power
system, the current must be considered to whole system power consumption.
Note: Under unstable power condition as brown out reset, “Zener diode rest circuit” and “Voltage bias
reset circuit” can protects system no any error occurrence as power dropping. When power drops below
the reset detect voltage, the system reset would be triggered, and then system executes reset sequence.
That makes sure the system work well under unstable power situation.
3.6.5 External Reset IC
VDD
VDD
Bypass
Capacitor
0.1uF
Reset
IC
RST
RST
MCU
VSS
VSS
VCC
GND
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good
effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can
improve all power variation.
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4 SYSTEM CLOCK
4.1 OVERVIEW
The micro-controller is a dual clock system including high-speed and low-speed clocks. The high-speed clock includes
internal high-speed oscillator and external oscillators selected by “High_CLK” code option. The low-speed clock is from
internal low-speed oscillator controlled by “CLKMD” bit of OSCM register. Both high-speed clock and low-speed clock
can be system clock source through a divider to decide the system clock rate.
High-speed oscillator
Internal high-speed oscillator is 16MHz RC type called “IHRC” and “IHRC_RTC”.
External high-speed oscillator includes crystal/ceramic (4MHz, 12MHz, 32KHz) and RC type.
Low-speed oscillator
Internal low-speed oscillator is 16KHz RC type called “ILRC”.
System clock block diagram
STPHX
XIN
XOUT
HOSC
High_Fcpu Code Option
CLKMD
Fosc
Fhosc.
Fcpu = Fhosc/1 ~ Fhosc/128
Fcpu
Fosc
CPUM[1:0]
Flosc.
Low_Fcpu Code Option
Fcpu = Flosc/1 ~ Flosc/8
HOSC: High_Clk code option.
Fhosc: External high-speed clock / Internal high-speed RC clock.
Flosc: Internal low-speed RC clock (about 16KHz@3V and @5V).
Fosc: System clock source.
Fcpu: Instruction cycle.
4.2 FCPU (INSTRUCTION CYCLE)
The system clock rate is instruction cycle called “Fcpu” which is divided from the system clock source and decides the
system operating rate. Fcpu rate is selected by High_Fcpu code option and the range is Fhosc/1~Fhosc/128 under
system normal mode. If the system high clock source is external 4MHz crystal, and the High_Fcpu code option is
Fhosc/4, the Fcpu frequency is 4MHz/4 = 1MHz. Under system slow mode, the Fcpu range is Flosc/1~Flosc/8
controlled by Low_Fcpu code option, If Low_Fcpu code option is Flosc/4, the Fcpu frequency is 16KHz/4=4KHz.
4.3 NOISE FILTER
The Noise Filter controlled by “Noise_Filter” code option is a low pass filter and supports external oscillator including
RC and crystal modes. The purpose is to filter high rate noise coupling on high clock signal from external oscillator.
In high noisy environment, enable “Noise_Filter” code option is the strongly recommendation to reduce noise
effect.
4.4 SYSTEM HIGH-SPEED CLOCK
The system high-speed clock has internal and external two-type. The external high-speed clock includes 4MHz, 12MHz,
32KHz crystal/ceramic and RC type. These high-speed oscillators are selected by “High_CLK” code option. The
internal high-speed clock supports real time clock (RTC) function. Under “IHRC_RTC” mode, the internal high-speed
clock and external 32KHz oscillator active. The internal high-speed clock is the system clock source, and the external
32KHz oscillator is the RTC clock source to supply a accurately real time clock rate.
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4.4.1 HIGH_CLK CODE OPTION
For difference clock functions, Sonix provides multi-type system high clock options controlled by “High_CLK” code
option. The High_CLK code option defines the system oscillator types including IHRC_16M, IHRC_RTC, RC, 32K X’tal,
12M X’tal and 4M X’tal. These oscillator options support different bandwidth oscillator.
IHRC_16M: The system high-speed clock source is internal high-speed 16MHz RC type oscillator. In the mode,
XIN and XOUT pins are bi-direction GPIO mode, and not to connect any external oscillator device.
IHRC_RTC: The system high-speed clock source is internal high-speed 16MHz RC type oscillator. The RTC
clock source is external low-speed 32768Hz crystal. The XIN and XOUT pins are defined to drive external
32768Hz crystal and disables GPIO function.
RC: The system high-speed clock source is external low cost RC type oscillator. The RC oscillator circuit only
connects to XIN pin, and the XOUT pin is bi-direction GPIO mode.
32K X’tal: The system high-speed clock source is external low-speed 32768Hz crystal. The option only supports
32768Hz crystal and the RTC function is workable.
12M X’tal: The system high-speed clock source is external high-speed crystal/ceramic. The oscillator bandwidth
is 10MHz~16MHz.
4M X’tal: The system high-speed clock source is external high-speed crystal/resonator. The oscillator bandwidth
is 1MHz~10MHz.
For power consumption under “IHRC_RTC” mode, the internal high-speed oscillator and internal low–speed oscillator
stops and only external 32KHz crystal actives under green mode. The condition is the watchdog timer can’t be
“Always_On” option, or the internal low-speed oscillator actives.
4.4.2 INTERNAL HIGH-SPEED OSCILLATOR RC TYPE (IHRC)
The internal high-speed oscillator is 16MHz RC type. The accuracy is ±2% under commercial condition. When the
“High_CLK” code option is “IHRC_16M” or “IHRC_RTC”, the internal high-speed oscillator is enabled.
IHRC_16M: The system high-speed clock is internal 16MHz oscillator RC type. XIN/XOUT pins are general
purpose I/O pins.
IHRC_RTC: The system high-speed clock is internal 16MHz oscillator RC type, and the real time clock is external
32768Hz crystal. XIN/XOUT pins connect with external 32768Hz crystal.
4.4.3 EXTERNAL HIGH-SPEED OSCILLATOR
The external high-speed oscillator includes 4MHz, 12MHz, 32KHz and RC type. The 4MHz, 12MHz and 32KHz
oscillators support crystal and ceramic types connected to XIN/XOUT pins with 20pF capacitors to ground. The RC
type is a low cost RC circuit only connected to XIN pin. The capacitance is not below 100pF, and use the resistance to
decide the frequency.
4.4.4 EXTERNAL OSCILLATOR APPLICATION CIRCUIT
CRYSTAL/CERAMIC
RC Type
XOUT
XIN
XIN
CRYSTAL
C
20pF
XOUT
MCU
C
C
MCU
VDD
VSS
VDD
20pF
R
VSS
VCC
VCC
GND
GND
Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of
micro-controller. Connect the R and C as near as possible to the VDD pin of micro-controller.
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4.5 SYSTEM LOW-SPEED CLOCK
The system low clock source is the internal low-speed oscillator built in the micro-controller. The low-speed oscillator
uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common
condition, the frequency of the RC oscillator is about 16KHz.
The internal low RC supports watchdog clock source and system slow mode controlled by “CLKMD” bit of OSCM
register.
Flosc = Internal low RC oscillator (about 16KHz).
Slow mode Fcpu = Flosc/ 1 ~ Flosc/8 controlled by Low_Fcpu code option.
When watchdog timer is disabled and system is in power down mode, the internal low RC stops.
Example: Stop internal low-speed oscillator by power down mode as watchdog timer disable
B0BSET
FCPUM0
; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
4.6 OSCM REGISTER
The OSCM register is an oscillator control register. It controls oscillator status, system mode.
095H
OSCM
Read/Write
After reset
Bit 7
0
-
Bit 6
0
-
Bit 5
0
-
Bit 4
CPUM1
R/W
0
Bit 3
CPUM0
R/W
0
Bit 2
CLKMD
R/W
0
Bit 1
STPHX
R/W
0
Bit 1
STPHX: External high-speed oscillator control bit.
0 = External high-speed oscillator free run.
1 = External high-speed oscillator free run stop. Internal low-speed RC oscillator is still running.
Bit 2
CLKMD: System high/Low clock mode control bit.
0 = Normal (dual) mode. System clock is high clock.
1 = Slow mode. System clock is internal low clock.
Bit[4:3]
CPUM[1:0]: CPU operating mode control bits.
00 = normal.
01 = sleep (power down) mode.
10 = green mode.
11 = reserved.
Bit 0
0
-
“STPHX” bit controls internal high speed RC type oscillator and external oscillator operations. When “STPHX=0”, the
external oscillator or internal high speed RC type oscillator active. When “STPHX=1”, the external oscillator or internal
high speed RC type oscillator are disabled. The STPHX function is depend on different high clock options to do
different controls.
IHRC_16M: “STPHX=1” disables internal high speed RC type oscillator.
IHRC_RTC: “STPHX=1” disables internal high speed RC type oscillator, and external 32768Hz crystal
keeps oscillating.
RC, 4M, 12M, 32K: “STPHX=1” disables external oscillator.
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4.7 SYSTEM CLOCK MEASUREMENT
Under design period, the users can measure system clock speed by software instruction cycle (Fcpu). This way is
useful in RC mode.
Example: Fcpu instruction cycle of external oscillator.
B0BSET
P0M.0
; Set P0.0 to be output mode for outputting Fcpu toggle signal.
B0BSET
B0BCLR
JMP
P0.0
P0.0
@B
; Output Fcpu toggle signal in low-speed clock mode.
; Measure the Fcpu frequency by oscilloscope.
@@:
Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC
frequency.
4.8 SYSTEM CLOCK TIMING
Parameter
Hardware configuration time
Oscillator start up time
Symbol
Tcfg
Tost
Oscillator warm-up time
Tosp
Description
2048*FILRC
The start-up time is depended on oscillator’s material,
factory and architecture. Normally, the low-speed
oscillator’s start-up time is lower than high-speed
oscillator. The RC type oscillator’s start-up time is faster
than crystal type oscillator.
Oscillator warm-up time of reset condition.
2048*Fhosc
(Power on reset, LVD reset, watchdog reset, external
reset pin active.)
Oscillator warm-up time of power down mode wake-up
condition.
2048*Fhosc ……Crystal/resonator type oscillator, e.g.
32768Hz crystal, 4MHz crystal, 16MHz crystal…
32*Fhosc……RC type oscillator, e.g. external RC type
oscillator, internal high-speed RC type oscillator.
Typical
128ms @ FILRC = 16KHz
-
64ms @ Fhosc = 32KHz
512us @ Fhosc = 4MHz
128us @ Fhosc = 16MHz
X’tal:
64ms @ Fhosc = 32KHz
512us @ Fhosc = 4MHz
128us @ Fhosc = 16MHz
RC:
8us @ Fhosc = 4MHz
2us @ Fhosc = 16MHz
Power On Reset Timing
Vdd
Vp
Power On Reset
Flag
Oscillator
Tcfg
Fcpu
(Instruction Cycle)
Tost
Tosp
External Reset Pin Reset Timing
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Reset pin falling edge trigger system reset.
External Reset Pin
Reset pin returns to high status.
External Reset
Flag
Oscillator
Tcfg
Tost
Tosp
Fcpu
(Instruction Cycle)
System is under reset
status.
Watchdog Reset Timing
Watchdog timer overflow.
Watchdog Reset
Flag
Oscillator
Tcfg
Tost
Tosp
Fcpu
(Instruction Cycle)
Power Down Mode Wake-up Timing
Edge trigger system wake-up.
Wake-up Pin
Falling Edge
Wake-up Pin
Rising Edge
Oscillator
Tost
Tosp
Fcpu
(Instruction Cycle)
System inserts into power down mode.
Green Mode Wake-up Timing
Edge trigger system wake-up.
Wake-up Pin
Falling Edge
Wake-up Pin
Rising Edge
Timer
Timer overflow.
...
0xFD
0xFE
0xFF
0x00
0x01
0x02
...
...
...
...
...
Oscillator
Fcpu
(Instruction Cycle)
System inserts into green mode.
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Oscillator Start-up Time
The start-up time is depended on oscillator’s material, factory and architecture. Normally, the low-speed oscillator’s
start-up time is lower than high-speed oscillator. The RC type oscillator’s start-up time is faster than crystal type
oscillator.
RC Oscillator
Tost
Ceramic/Resonator
Tost
Crystal
Tost
Low Speed Crystal
(32K, 455K)
Tost
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5 SYSTEM OPERATION MODE
5.1 OVERVIEW
The chip builds in four operating mode for difference clock rate and power saving reason. These modes control
oscillators, op-code operation and analog peripheral devices’ operation.
Normal mode: System high-speed operating mode.
Slow mode: System low-speed operating mode.
Power down mode: System power saving mode (Sleep mode).
Green mode: System ideal mode.
Operating Mode Control Block
One of reset trigger sources actives.
Wake-up condition:
P0, P1 input status is level changing.
MSP matched device address.
One of reset trigger sources actives.
Power Down Mode
CPUM1, CPUM0 = 01.
CLKMD = 1
Reset Control Block
Normal Mode
CLKMD = 0
Slow Mode
CPUM1, CPUM0 = 10.
Wake-up condition:
P0, P1 input status is level changing.
T0 timer counter is overflow.
Green Mode
Wake-up condition:
P0, P1 input status is level changing.
T0 timer counter is overflow.
One of reset trigger sources actives.
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Operating Mode Clock Control Table
Operating
Mode
IHRC
ILRC
Ext. Osc.
CPU instruction
T0 timer
TC0 timer
(Timer, Event counter,
PWM)
TC1 timer
(Timer, Event counter,
PWM)
TC2 timer
(Timer, Event counter,
PWM)
T1 timer
(Timer, Event counter)
SIO
MSP
UART
ADC
Watchdog timer
Internal interrupt
External interrupt
Wakeup source
Normal Mode
IHRC, IHRC_RTC:
Running
Ext. OSC: Disable
Running
IHRC: Disable
IHRC_RTC, Ext. OSC:
Running
Executing
Active
By T0ENB
Slow Mode
IHRC, IHRC_RTC: By
STPHX
Ext. OSC: Disable
Running
IHRC: Disable
IHRC_RTC: Running
Ext. OSC: By STPHX
Executing
Active
By T0ENB
Green Mode
IHRC, IHRC_RTC: By
STPHX
Ext. OSC: Disable
Running
IHRC: By STPHX
IHRC_RTC: Running
Ext. OSC: By STPHX
Stop
Active
By T0ENB
Power Down Mode
Stop
Stop
Stop
Stop
Inactive
Active
By TC0ENB
Active
By TC0ENB
Active
By TC0ENB
Inactive
Active
By TC1ENB
Active
By TC1ENB
Active
By TC1ENB
Inactive
Active
By TC2ENB
Active
By TC2ENB
Active
By TC2ENB
Inactive
Active
By T1ENB
Active as enable
Active as enable
Active as enable
Active as enable
By Watch_Dog
Code option
All active
All active
-
Active
By T1ENB
Inactive
Inactive
Inactive
Active as enable
By Watch_Dog
Code option
All active
All active
-
Active
By T1ENB
Inactive
Inactive
Inactive
Active as enable
By Watch_Dog
Code option
All active
All active
P0, P1, T0, Reset
Inactive
Inactive
Inactive
Inactive
Inactive
By Watch_Dog
Code option
All inactive
All inactive
P0, P1, MSP, Reset
Ext.Osc: External high-speed oscillator (XIN/XOUT).
IHRC: Internal high-speed oscillator RC type.
ILRC: Internal low-speed oscillator RC type.
Note:
1. SIO, MSP and UART inactive in slow mode and green mode, because the clock source doesn’t exist.
Use firmware to disable SIO, MSP, UART function before inserting slow mode and green mode.
2. In IHRC_RTC mode, STPHX only controls IHRC, not Ext. 32K. STPHX=0, IHRC actives. STPHX=1, IHRC
stops.
5.2 NORMAL MODE
The Normal Mode is system high clock operating mode. The system clock source is from high speed oscillator. The
program is executed. After power on and any reset trigger released, the system inserts into normal mode to execute
program. When the system is wake-up from power down mode, the system also inserts into normal mode. In normal
mode, the high speed oscillator actives, and the power consumption is largest of all operating modes.
The program is executed, and full functions are controllable.
The system rate is high speed.
The high speed oscillator and internal low speed RC type oscillator active.
Normal mode can be switched to other operating modes through OSCM register.
Power down mode is wake-up to normal mode.
Slow mode is switched to normal mode.
Green mode from normal mode is wake-up to normal mode.
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5.3 SLOW MODE
The slow mode is system low clock operating mode. The system clock source is from internal low speed RC type
oscillator. The slow mode is controlled by CLKMD bit of OSCM register. When CLKMD=0, the system is in normal
mode. When CLKMD=1, the system inserts into slow mode. The high speed oscillator won’t be disabled automatically
after switching to slow mode, and must be disabled by SPTHX bit to reduce power consumption. In slow mode, the
system rates are Flosc/1, Flosc/2, Flosc/4, Flosc/8 (Flosc is internal low speed RC type oscillator frequency) controlled
by code option.
The program is executed, and full functions are controllable.
The system rate is low speed (Flosc/1, Flosc/2, Flosc/4, Flosc/8 controlled by code option).
The internal low speed RC type oscillator actives, and the high speed oscillator is controlled by STPHX=1. In slow
mode, to stop high speed oscillator is strongly recommendation.
Slow mode can be switched to other operating modes through OSCM register.
Power down mode from slow mode is wake-up to normal mode.
Normal mode is switched to slow mode.
Green mode from slow mode is wake-up to slow mode.
5.4 POWER DOWN MDOE
The power down mode is the system ideal status. No program execution and oscillator operation. Only internal
regulator actives to keep all control gates status, register status and SRAM contents. The power down mode is waked
up by P0, P1 hardware level change trigger. P0 wake-up function is always enables, and P1 wake-up function is
controlled by P1W register. Any operating modes into power down mode, the system is waked up to normal mode.
Inserting power down mode is controlled by CPUM0 bit of OSCM register. When CPUM0=1, the system inserts into
power down mode. After system wake-up from power down mode, the CPUM0 bit is disabled (zero status)
automatically, and the WAKE bit set as “1”.
The program stops executing, and full functions are disabled.
All oscillators including external high speed oscillator, internal high speed oscillator and internal low speed
oscillator stop.
The system inserts into normal mode after wake-up from power down mode.
The power down mode wake-up source is P0 and P1 level change trigger.
After system wake-up from power down mode, the WAKE bit set as “1” and cleared by program.
If wake-up source is external interrupt source, the WAKE bit won’t be set, and external interrupt IRQ bit is set.
The system issues external interrupt request and executes interrupt service routine.
Note: If the system is in normal mode, to set STPHX=1 to disable the high clock oscillator. The system is
under no system clock condition. This condition makes the system stay as power down mode, and can
be wake-up by P0, P1 level change trigger.
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5.5 GREEN MODE
The green mode is another system ideal status not like power down mode. In power down mode, all functions and
hardware devices are disabled. But in green mode, the system clock source keeps running, so the power consumption
of green mode is larger than power down mode. In green mode, the program isn’t executed, but the timer with wake-up
function actives as enabled, and the timer clock source is the non-stop system clock. The green mode has 2 wake-up
sources. One is the P0, P1 level change trigger wake-up. The other one is internal timer with wake-up function
occurring overflow. That’s mean users can setup one fix period to timer, and the system is waked up until the time out.
Inserting green mode is controlled by CPUM1 bit of OSCM register. When CPUM1=1, the system inserts into green
mode. After system wake-up from green mode, the CPUM1 bit is disabled (zero status) automatically, and the WAKE
bit set as “1”.
The program stops executing, and full functions are disabled.
Only the timer with wake-up function actives.
The oscillator to be the system clock source keeps running, and the other oscillators operation is depend on
system operation mode configuration.
If inserting green mode from normal mode, the system insets to normal mode after wake-up.
If inserting green mode from slow mode, the system insets to slow mode after wake-up.
The green mode wake-up sources are P0, P1 level change trigger and unique time overflow.
After system wake-up from power down mode, the WAKE bit set as “1” and cleared by program.
If wake-up source is external interrupt source, the WAKE bit won’t be set, and external interrupt IRQ bit is set.
The system issues external interrupt request and executes interrupt service routine.
If the function clock source is system clock, the functions are workable as enabled and under green mode, e.g.
Timer, PWM, event counter…But the functions doesn’t has wake-up function.
Note: Sonix provides “GreenMode” macro to control green mode operation. It is necessary to use
“GreenMode” macro to control system inserting green mode.
The macro includes three instructions. Please take care the macro length as using BRANCH type
instructions, e.g. bts0, bts1, b0bts0, b0bts1, ins, incms, decs, decms, cmprs, jmp, or the routine would
be error.
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5.6 OPERATING MODE CONTROL MACRO
Sonix provides operating mode control macros to switch system operating mode easily.
Macro
Length
Description
SleepMode
1-word
The system insets into Sleep Mode (Power Down Mode).
GreenMode
3-word
The system inserts into Green Mode.
SlowMode
2-word
The system inserts into Slow Mode and stops high speed oscillator.
Slow2Normal
5-word
The system returns to Normal Mode from Slow Mode. The macro includes
operating mode switch, enable high speed oscillator, high speed oscillator
warm-up delay time.
Example: Switch normal/slow mode to power down (sleep) mode.
; Declare “SleepMode” macro directly.
SleepMode
Example: Switch normal mode to slow mode.
; Declare “SlowMode” macro directly.
SlowMode
Example: Switch slow mode to normal mode (The external high-speed oscillator stops).
; Declare “Slow2Normal” macro directly.
Slow2Normal
Example: Switch normal/slow mode to green mode.
; Declare “GreenMode” macro directly.
GreenMode
Example: Switch normal/slow mode to green mode and enable T0 wake-up function.
; Set T0 timer wakeup function.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
B0BCLR
B0BCLR
B0BSET
FT0IEN
FT0ENB
A,#20H
T0M,A
A,#74H
T0C,A
FT0IEN
FT0IRQ
FT0ENB
; Go into green mode
GreenMode
; To disable T0 interrupt service
; To disable T0 timer
;
; To set T0 clock = Fcpu / 64
; To set T0C initial value = 74H (To set T0 interval = 10 ms)
; To disable T0 interrupt service
; To clear T0 interrupt request
; To enable T0 timer
; Declare “GreenMode” macro directly.
Example: Switch normal/slow mode to green mode and enable T0 wake-up function with RTC.
CLR
B0BSET
B0BSET
T0C
FT0TB
FT0ENB
; Go into green mode
GreenMode
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; Clear T0 counter.
; Enable T0 RTC function.
; To enable T0 timer.
; Declare “GreenMode” macro directly.
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5.7 WAKEUP
5.7.1 OVERVIEW
Under power down mode (sleep mode) or green mode, program doesn’t execute. The wakeup trigger can wake the
system up to normal mode or slow mode. The wakeup trigger sources are external trigger (P0/P1 level change) and
internal trigger (T0 timer overflow). The wakeup function builds in interrupt operation issued IRQ flag and trigger
system executing interrupt service routine as system wakeup occurrence.
Power down mode is waked up to normal mode. The wakeup trigger is only external trigger (P0/P1 level change)
Green mode is waked up to last mode (normal mode or slow mode). The wakeup triggers are external trigger
(P0/P1 level change) and internal trigger (T0 timer overflow).
Wakeup interrupt function issues WAKEIRQ as system wakeup from power down mode or green mode. If
WAKEIEN is “1” meaning enable, the wakeup event triggers program counter point to interrupt vector (ORG 8)
executing interrupt service routine.
Note: If wake-up source is external interrupt source, the WAKE bit won’t be set, and external interrupt
IRQ bit is set. The system issues external interrupt request and executes interrupt service routine.
5.7.2 WAKEUP TIME
When the system is in power down mode (sleep mode), the high clock oscillator stops. When waked up from power
down mode, MCU waits for 2048 external high-speed oscillator clocks and 32 internal high-speed oscillator clocks as
the wakeup time to stable the oscillator circuit. After the wakeup time, the system goes into the normal mode.
Note: Wakeup from green mode is no wakeup time because the clock doesn’t stop in green mode.
The value of the external high clock oscillator wakeup time is as the following.
The Wakeup time = 1/Fosc * 2048 (sec) + high clock start-up time
Example: In power down mode (sleep mode), the system is waked up. After the wakeup time, the system goes
into normal mode. The wakeup time is as the following.
The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz)
The total wakeup time = 0.512 ms + oscillator start-up time
The value of the internal high clock oscillator RC type wakeup time is as the following.
The Wakeup time = 1/Fosc * 32 (sec) + high clock start-up time
Example: In power down mode (sleep mode), the system is waked up. After the wakeup time, the system goes
into normal mode. The wakeup time is as the following.
The wakeup time = 1/Fosc * 32 = 2 us
(Fhosc = 16MHz)
Note: The high clock start-up time is depended on the VDD and oscillator type of high clock.
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5.7.3 P1W WAKEUP CONTROL REGISTER
Under power down mode (sleep mode) and green mode, the I/O ports with wakeup function are able to wake the
system up to normal mode. The wake-up trigger edge is level changing. When wake-up pin occurs rising edge or falling
edge, the system is waked up by the trigger edge. The Port 0 and Port 1 have wakeup function. Port 0 wakeup function
always enables, but the Port 1 is controlled by the P1W register.
09EH
P1W
Read/Write
After reset
Bit[7:0]
Bit 7
P17W
R/W
0
Bit 6
P16W
R/W
0
Bit 5
P15W
R/W
0
Bit 4
P14W
R/W
0
Bit 3
P13W
R/W
0
Bit 2
P12W
R/W
0
Bit 1
P11W
R/W
0
Bit 0
P10W
R/W
0
P10W~P17W: Port 1 wakeup function control bits.
0 = Disable P1n wakeup function.
1 = Enable P1n wakeup function.
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6 INTERRUPT
6.1 OVERVIEW
This MCU provides 13 interrupt sources, including 2 external interrupt (INT0/INT1) and 11 internal interrupt
(T0/T1/TC0/TC1/TC2/SIO/MSP/UTX/URX/WAKE/ADC). The external interrupt can wakeup the chip while the system is
switched from power down mode to high-speed normal mode, and interrupt request is latched until return to normal
mode. Once interrupt service is executed, the GIE bit in STKP register will clear to “0” for stopping other interrupt
request. On the contrast, when interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’ request.
The interrupt request signals are stored in INTRQ register.
INTEN Interrupt Enable Register
P00IRQ
INT0 Trigger
P01IRQ
INT1 Trigger
T0IRQ
T0 Time Out
T1IRQ
T1 Time Out
TC0IRQ
TC0 Time Out
TC1 Time Out
INTRQ
13-Bit
TC2 Time Out
SIO Transmitter End
Latchs
UART Transmit End
UART Receive End
MSP
ADC Converting End
WAKE
TC1IRQ
Interrupt
TC2IRQ
Enable
SIOIRQ
Gating
Interrupt Vector Address
(0008H~0014H)
Global Interrupt Request Signal
UTXIRQ
URXIRQ
MSPIRQ
ADCIRQ
WAKEIRQ
Note:
1. The GIE bit must enable during all interrupt operation.
2. Use “bts0/1 instruction” to detect external asynchronous signal (such as IO status, event counter
flag) when GIE=1, we strongly recommend the following amendments.
Step1: Use “MOV instruction” fetch signal to useless register or RAM.
Step2: Judge useless register or RAM using “bts0/1 instruction”.
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6.2 INTERRUPT OPERATION
Interrupt operation is controlled by IRQ and IEN bits. The IRQ is interrupt source event indicator, no matter what
interrupt function status (enable or disable). The IEN control the system interrupt execution. If IEN = 0, the system
won’t jump to interrupt vector to execute interrupt routine. If IEN = 1, the system executes interrupt operation when
each of interrupt IRQ flags actives.
IEN = 1 and IRQ = 1, the program counter points to interrupt vector and execute interrupt service routine.
When any interrupt requests occurs, the system provides to jump to interrupt vector and execute interrupt routine. The
first procedure is “PUSH” operation. The end procedure after interrupt service routine execution is “POP” operation.
The “PUSH” and “POP” operations aren’t through instruction (PUSH, POP) and executed by hardware automatically.
“PUSH” operation: PUSH operation saves the contents of ACC and working registers (0x80~0x8F) into
hardware buffers. PUSH operation executes before program counter points to interrupt vector. The RAM
bank keeps the status of main routine and doesn’t switch to bank 0 automatically. The RAM bank is
selected by program.
“POP” operation: POP operation reloads the contents of ACC and working registers (0x80~0x8F) from
hardware buffers. POP operation executes as RETI instruction executed. The RAM bank switches to last
status of main routine after reloading RBANK content.
0x80~0x87 working registers include L, H, R, Z, Y, X, PFLAG, RBANK, W0~W7.
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6.3 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including eleven internal interrupts, two external interrupts enable control
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is
incremented and program jump to ORG 8~14 to execute interrupt service routines. The program exits the interrupt
service routine when the returning interrupt service routine instruction (RETI) is executed.
09AH
INTEN0
Read/Write
After reset
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 6
T1IEN
R/W
0
Bit 5
TC2IEN
R/W
0
Bit 4
TC1IEN
R/W
0
Bit 3
TC0IEN
R/W
0
Bit 2
T0IEN
R/W
0
Bit 1
P01IEN
R/W
0
Bit 0
P00IEN
R/W
0
Bit 3
UTXIEN
R/W
0
Bit 2
URXIEN
R/W
0
Bit 1
SIOIEN
R/W
0
Bit 0
WAKEIEN
R/W
0
P00IEN: External P0.0 interrupt (INT0) control bit.
0 = Disable INT0 interrupt function.
1 = Enable INT0 interrupt function.
P01IEN: External P0.1 interrupt (INT1) control bit.
0 = Disable INT1 interrupt function.
1 = Enable INT1 interrupt function.
T0IEN: T0 timer interrupt control bit.
0 = Disable T0 interrupt function.
1 = Enable T0 interrupt function.
TC0IEN: TC0 timer interrupt control bit.
0 = Disable TC0 interrupt function.
1 = Enable TC0 interrupt function.
TC1IEN: TC1 timer interrupt control bit.
0 = Disable TC1 interrupt function.
1 = Enable TC1 interrupt function.
TC2IEN: TC2 timer interrupt control bit.
0 = Disable TC2 interrupt function.
1 = Enable TC2 interrupt function.
T1IEN: T1 timer interrupt control bit.
0 = Disable T1 interrupt function.
1 = Enable T1 interrupt function.
ADCIEN: ADC interrupt control bit.
0 = Disable ADC interrupt function.
1 = Enable ADC interrupt function.
09BH
INTEN1
Read/Write
After reset
Bit 0
Bit 7
ADCIEN
R/W
0
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
MSPIEN
R/W
0
WAKEIEN: Wakeup interrupt control bit.
0 = Disable wakeup interrupt function.
1 = Enable wakeup interrupt function.
SIOIEN: SIO interrupt control bit.
0 = Disable SIO interrupt function.
1 = Enable SIO interrupt function.
URXIEN: UART receive interrupt control bit.
0 = Disable UART receive interrupt function.
1 = Enable UART receive interrupt function.
UTXIEN: UART transmit interrupt control bit.
0 = Disable UART transmit interrupt function.
1 = Enable UART transmit interrupt function.
MSPIEN: MSP interrupt control bit.
0 = Disable MSP interrupt function.
1 = Enable MSP interrupt function.
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6.4 INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the
interrupt requests occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests
occurring by the register and do the routine corresponding of the interrupt request.
097H
INTRQ0
Read/Write
After reset
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 1
Bit 2
Bit 3
Bit 4
Bit 6
T1IRQ
R/W
0
Bit 5
TC2IRQ
R/W
0
Bit 4
TC1IRQ
R/W
0
Bit 3
TC0IRQ
R/W
0
Bit 2
T0IRQ
R/W
0
Bit 1
P01IRQ
R/W
0
Bit 0
P00IRQ
R/W
0
Bit 3
UTXIRQ
R/W
0
Bit 2
URXIRQ
R/W
0
Bit 1
SIOIRQ
R/W
0
Bit 0
WAKEIRQ
R/W
0
P00IRQ: External P0.0 interrupt (INT0) request flag.
0 = None INT0 interrupt request.
1 = INT0 interrupt request.
P01IRQ: External P0.1 interrupt (INT1) request flag.
0 = None INT1 interrupt request.
1 = INT1 interrupt request.
T0IRQ: T0 timer interrupt request flag.
0 = None T0 interrupt request.
1 = T0 interrupt request.
TC0IRQ: TC0 timer interrupt request flag.
0 = None TC0 interrupt request.
1 = TC0 interrupt request.
TC1IRQ: TC1 timer interrupt request flag.
0 = None TC1 interrupt request.
1 = TC1 interrupt request.
TC2IRQ: TC2 timer interrupt request flag.
0 = None TC2 interrupt request.
1 = TC2 interrupt request.
T1IRQ: T1 timer interrupt request flag.
0 = None T1 interrupt request.
1 = T1 interrupt request.
ADCIRQ: ADC interrupt request flag.
0 = None ADC interrupt request.
1 = ADC interrupt request.
098H
INTRQ1
Read/Write
After reset
Bit 0
Bit 7
ADCIRQ
R/W
0
Bit 7
Bit 6
Bit 5
Bit 4
MSPIRQ
R/W
0
WAKEIRQ: Wakeup interrupt request flag.
0 = None wakeup interrupt request.
1 = Wakeup interrupt request.
SIOIRQ: SIO interrupt request flag.
0 = None SIO interrupt request.
1 = SIO interrupt request.
URXIRQ: UART receive interrupt request flag.
0 = None UART receive interrupt request.
1 = UART receive interrupt request.
UTXIRQ: UART transmit interrupt request flag.
0 = None UART transmit interrupt request.
1 = UART transmit interrupt request.
MSPIRQ: MSP interrupt request flag.
0 = None MSP interrupt request.
1 = MSP interrupt request.
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6.5 GIE GLOBAL INTERRUPT OPERATION
GIE is the global interrupt control bit. All interrupts start work after the GIE = 1 It is necessary for interrupt service
request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8~14)
and the stack add 1 level.
0EFH
STKP
Read/Write
After reset
Bit 7
Bit 7
GIE
R/W
0
Bit 6
LVD24
R
Bit 5
LVD33
R
Bit 4
-
Bit 3
-
Bit 2
STKPB2
R/W
1
Bit 1
STKPB1
R/W
1
Bit 0
STKPB0
R/W
1
GIE: Global interrupt control bit.
0 = Disable global interrupt.
1 = Enable global interrupt.
Example: Set global interrupt control bit (GIE).
B0BSET
FGIE
; Enable GIE
Note: The GIE bit must enable during all interrupt operation.
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6.6 EXTERNAL INTERRUPT OPERATION (INT0~INT1)
Sonix provides 2 sets external interrupt sources in the micro-controller. INT0 and INT1 are external interrupt trigger
sources and build in edge trigger configuration function. When the external edge trigger occurs, the external interrupt
request flag will be set to “1” when the external interrupt control bit enabled. If the external interrupt control bit is
disabled, the external interrupt request flag won’t active when external edge trigger occurrence. When external
interrupt control bit is enabled and external interrupt edge trigger is occurring, the program counter will jump to the
interrupt vector (ORG 0x0009, 0x000A) and execute interrupt service routine.
The external interrupt builds in wake-up latch function. That means when the system is triggered wake-up from power
down mode, the wake-up source is external interrupt source (P0.0 or P0.1), and the trigger edge direction matches
interrupt edge configuration, the trigger edge will be latched, and the system executes interrupt service routine fist after
wake-up.
09FH
PEDGE
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit[3:2]
P01G[1:0]: INT1 edge trigger select bits.
00 = reserved,
01 = rising edge,
10 = falling edge,
11 = rising/falling bi-direction.
Bit[1:0]
P00G[1:0]: INT0 edge trigger select bits.
00 = reserved,
01 = rising edge,
10 = falling edge,
11 = rising/falling bi-direction.
Bit 4
-
Bit 3
P01G1
R/W
1
Bit 2
P01G0
R/W
0
Bit 1
P00G1
R/W
1
Bit 0
P00G0
R/W
0
Example: Setup INT0 interrupt request and bi-direction edge trigger.
MOV
A, #03H
B0MOV
PEDGE, A
; Set INT0 interrupt trigger as bi-direction edge.
B0BSET
B0BCLR
B0BSET
FP00IEN
FP00IRQ
FGIE
Example: INT0 interrupt service routine.
ORG
9
JMP
INT_SERVICE
INT_SERVICE:
…
; Enable INT0 interrupt service
; Clear INT0 interrupt request flag
; Enable GIE
; Interrupt vector
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FP00IRQ
EXIT_INT
; Check P00IRQ
; P00IRQ = 0, exit interrupt vector
B0BCLR
…
FP00IRQ
; Reset P00IRQ
; INT0 interrupt service routine
EXIT_INT:
…
RETI
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; Pop routine to load ACC and PFLAG from buffers.
; Exit interrupt vector
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6.7 T0 INTERRUPT OPERATION
When the T0C counter occurs overflow, the T0IRQ will be set to “1” however the T0IEN is enable or disable. If the
T0IEN = 1, the trigger event will make the T0IRQ to be “1” and the system enter interrupt vector. If the T0IEN = 0, the
trigger event will make the T0IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the
operation under multi-interrupt situation.
Example: T0 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FT0IEN
FT0ENB
A, #20H
T0M, A
A, #74H
T0C, A
; Disable T0 interrupt service
; Disable T0 timer
;
; Set T0 clock = Fcpu / 64
; Set T0C initial value = 74H
; Set T0 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FT0IEN
FT0IRQ
FT0ENB
; Enable T0 interrupt service
; Clear T0 interrupt request flag
; Enable T0 timer
B0BSET
FGIE
; Enable GIE
Example: T0 interrupt service routine.
ORG
JMP
0BH
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FT0IRQ
EXIT_INT
; Check T0IRQ
; T0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
…
…
FT0IRQ
A, #74H
T0C, A
; Reset T0IRQ
; Reset T0C.
; T0 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
Note: In RTC mode, don’t reset T0C in interrupt service routine.
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6.8 TC0 INTERRUPT OPERATION
When the TC0C counter overflows, the TC0IRQ will be set to “1” no matter the TC0IEN is enable or disable. If the
TC0IEN and the trigger event TC0IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC0IEN = 0, the trigger event TC0IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC0IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
Example: TC0 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FTC0IEN
FTC0ENB
A, #10H
TC0M, A
A, #74H
TC0C, A
; Disable TC0 interrupt service
; Disable TC0 timer
;
; Set TC0 clock = Fcpu / 64
; Set TC0C initial value = 74H
; Set TC0 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FTC0IEN
FTC0IRQ
FTC0ENB
; Enable TC0 interrupt service
; Clear TC0 interrupt request flag
; Enable TC0 timer
B0BSET
FGIE
; Enable GIE
Example: TC0 interrupt service routine.
ORG
JMP
0CH
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FTC0IRQ
EXIT_INT
; Check TC0IRQ
; TC0IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
…
…
FTC0IRQ
A, #74H
TC0C, A
; Reset TC0IRQ
; Reset TC0C.
; TC0 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6.9 TC1 INTERRUPT OPERATION
When the TC1C counter overflows, the TC1IRQ will be set to “1” no matter the TC1IEN is enable or disable. If the
TC1IEN and the trigger event TC1IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC1IEN = 0, the trigger event TC1IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC1IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
Example: TC1 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FTC1IEN
FTC1ENB
A, #10H
TC1M, A
A, #74H
TC1C, A
; Disable TC1 interrupt service
; Disable TC1 timer
;
; Set TC1 clock = Fcpu / 64
; Set TC1C initial value = 74H
; Set TC1 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FTC1IEN
FTC1IRQ
FTC1ENB
; Enable TC1 interrupt service
; Clear TC1 interrupt request flag
; Enable TC1 timer
B0BSET
FGIE
; Enable GIE
Example: TC1 interrupt service routine.
ORG
JMP
0DH
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FTC1IRQ
EXIT_INT
; Check TC1IRQ
; TC1IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
…
…
FTC1IRQ
A, #74H
TC1C, A
; Reset TC1IRQ
; Reset TC1C.
; TC1 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6.10 TC2 INTERRUPT OPERATION
When the TC2C counter overflows, the TC2IRQ will be set to “1” no matter the TC2IEN is enable or disable. If the
TC2IEN and the trigger event TC2IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC2IEN = 0, the trigger event TC2IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC2IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
Example: TC2 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
MOV
B0MOV
FTC2IEN
FTC2ENB
A, #10H
TC2M, A
A, #74H
TC2C, A
; Disable TC2 interrupt service
; Disable TC2 timer
;
; Set TC2 clock = Fcpu / 64
; Set TC2C initial value = 74H
; Set TC2 interval = 10 ms
B0BSET
B0BCLR
B0BSET
FTC2IEN
FTC2IRQ
FTC2ENB
; Enable TC2 interrupt service
; Clear TC2 interrupt request flag
; Enable TC2 timer
B0BSET
FGIE
; Enable GIE
Example: TC2 interrupt service routine.
ORG
JMP
0EH
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FTC2IRQ
EXIT_INT
; Check TC2IRQ
; TC2IRQ = 0, exit interrupt vector
B0BCLR
MOV
B0MOV
…
…
FTC2IRQ
A, #74H
TC2C, A
; Reset TC2IRQ
; Reset TC2C.
; TC2 interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6.11 T1 INTERRUPT OPERATION
When the T1C (T1CH, T1CL) counter occurs overflow, the T1IRQ will be set to “1” however the T1IEN is enable or
disable. If the T1IEN = 1, the trigger event will make the T1IRQ to be “1” and the system enter interrupt vector. If the
T1IEN = 0, the trigger event will make the T1IRQ to be “1” but the system will not enter interrupt vector. Users need to
care for the operation under multi-interrupt situation.
Example: T1 interrupt request setup.
B0BCLR
B0BCLR
MOV
B0MOV
CLR
CLR
FT1IEN
FT1ENB
A, #20H
T1M, A
T1CH
T1CL
; Disable T1 interrupt service
; Disable T1 timer
;
; Set T1 clock = Fcpu / 32 and falling edge trigger.
B0BSET
B0BCLR
B0BSET
FT1IEN
FT1IRQ
FT1ENB
; Enable T1 interrupt service
; Clear T1 interrupt request flag
; Enable T1 timer
B0BSET
FGIE
; Enable GIE
Example: T1 interrupt service routine.
ORG
JMP
0FH
INT_SERVICE
; Interrupt vector
B0BTS1
JMP
FT1IRQ
EXIT_INT
; Check T1IRQ
; T1IRQ = 0, exit interrupt vector
B0BCLR
B0MOV
B0MOV
B0MOV
B0MOV
CLR
CLR
…
…
FT1IRQ
A, T1CH
T1CHBUF, A
A, T1CL
T1CLBUF, A
T1CH
T1CL
; Reset T1IRQ
INT_SERVICE:
; Save pulse width.
; T1 interrupt service routine
EXIT_INT:
RETI
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; Exit interrupt vector
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6.12 ADC INTERRUPT OPERATION
When the ADC converting successfully, the ADCIRQ will be set to “1” no matter the ADCIEN is enable or disable. If the
ADCIEN and the trigger event ADCIRQ is set to be “1”. As the result, the system will execute the interrupt vector. If
the ADCIEN = 0, the trigger event ADCIRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector
even when the ADCIEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
Example: ADC interrupt request setup.
B0BCLR
FADCIEN
; Disable ADC interrupt service
MOV
B0MOV
MOV
B0MOV
A, #10110000B
ADM, A
A, #00000000B
ADR, A
;
; Enable P4.0 ADC input and ADC function.
; Set ADC converting rate = Fcpu/16
B0BSET
B0BCLR
B0BSET
FADCIEN
FADCIRQ
FGIE
; Enable ADC interrupt service
; Clear ADC interrupt request flag
; Enable GIE
B0BSET
FADS
; Start ADC transformation
Example: ADC interrupt service routine.
ORG
JMP
10H
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FADCIRQ
EXIT_INT
; Check ADCIRQ
; ADCIRQ = 0, exit interrupt vector
B0BCLR
…
…
FADCIRQ
; Reset ADCIRQ
; ADC interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
SONiX TECHNOLOGY CO., LTD
Page 76
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
6.13 SIO INTERRUPT OPERATION
When the SIO converting successfully, the SIOIRQ will be set to “1” no matter the SIOIEN is enable or disable. If the
SIOIEN and the trigger event SIOIRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
SIOIEN = 0, the trigger event SIOIRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the SIOIEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
Example: SIO interrupt request setup.
B0BSET
B0BCLR
B0BSET
FSIOIEN
FSIOIRQ
FGIE
; Enable SIO interrupt service
; Clear SIO interrupt request flag
; Enable GIE
Example: SIO interrupt service routine.
ORG
JMP
11H
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FSIOIRQ
EXIT_INT
; Check SIOIRQ
; SIOIRQ = 0, exit interrupt vector
B0BCLR
…
…
FSIOIRQ
; Reset SIOIRQ
; SIO interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
SONiX TECHNOLOGY CO., LTD
Page 77
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
6.14 UART INTERRUPT OPERATION
When the UART transmitter successfully, the URXIRQ/UTXIRQ will be set to “1” no matter the URXIEN/UTXIEN is
enable or disable. If the URXIEN/UTXIEN and the trigger event URXIRQ/UTXIRQ is set to be “1”. As the result, the
system will execute the interrupt vector. If the URXIEN/UTXIEN = 0, the trigger event URXIRQ/UTXIRQ is still set to be
“1”. Moreover, the system won’t execute interrupt vector even when the URXIEN/UTXIEN is set to be “1”. Users need
to be cautious with the operation under multi-interrupt situation.
Example: UART receive and transmit interrupt request setup.
B0BSET
B0BCLR
FURXIEN
FURXIRQ
; Enable UART receive interrupt service
; Clear UART receive interrupt request flag
B0BSET
B0BCLR
B0BSET
FUTXIEN
FUTXIRQ
FGIE
; Enable UART transmit interrupt service
; Clear UART transmit interrupt request flag
; Enable GIE
Example: UART receive interrupt service routine.
ORG
JMP
13H
INT_SERVICE
; Interrupt vector
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
JMP
FURXIRQ
EXIT_INT
; Check RXIRQ
; RXIRQ = 0, exit interrupt vector
B0BCLR
…
…
FURXIRQ
; Reset RXIRQ
; UART receive interrupt service routine
EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
SONiX TECHNOLOGY CO., LTD
Page 78
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
6.15 MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt
request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt
event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. In addition, which
means the IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be
logic “1”. The IRQ and its trigger event relationship is as the below table.
Interrupt Name
WAKEIRQ
P00IRQ
P01IRQ
T0IRQ
TC0IRQ
TC1IRQ
TC2IRQ
T1IRQ
ADCIRQ
SIOIRQ
MSPIRQ
RXIRQ
TXIRQ
Trigger Event Description
Wake-up from power down or green mode
P0.0 trigger controlled by PEDGE
P0.1 trigger controlled by PEDGE
T0C overflow
TC0C overflow
TC1C overflow
TC2C overflow
T1CH, T1CL overflow
ADC converting end.
SIO transmitter successfully.
MSP transmitter successfully.
UART transmit successfully.
UART receive successfully.
For multi-interrupt conditions, two things need to be taking care of. One is that it is multi-vector and each of interrupts
points to unique vector. Two is users have to define the interrupt vector. The following example shows the way to
define the interrupt vector in the program memory.
Example: Check the interrupt request under multi-interrupt operation
ORG
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
JMP
8
ISR_WAKE
ISR_INT0
ISR_INT1
ISR_T0
ISR_TC0
ISR_TC1
ISR_TC2
ISR_T1
ISR_ADC
ISR_SIO
ISR_MSP
ISR_UART_RX
ISR_UART_TX
ISR_WAKE:
; Interrupt vector
; WAKE-UP interrupt service routine
RETI
ISR_INT0:
RETI
ISR_INT1:
RETI
…
…
ISR_UART_TX:
; Exit interrupt vector
; INT0 interrupt service routine
;
; Exit interrupt vector
; INT1 interrupt service routine
; Exit interrupt vector
; UART_TX interrupt service routine
RETI
SONiX TECHNOLOGY CO., LTD
; Exit interrupt vector
Page 79
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
7 I/O PORT
7.1 OVERVIEW
The micro-controller builds in 27 pin I/O. Most of the I/O pins are mixed with analog pins and special function pins. The
I/O shared pin list is as following.
I/O Pin
Name
Type
P0.0
I/O
P0.1
I/O
P0.2
I/O
P0.3
I/O
P0.4
P0.5
P0.6
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P4[7:0]
P5.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P5.1
I/O
P5.2
I/O
P5.3
I/O
Shared Pin
Shared Pin Control Condition
Name
Type
INT0
TC0
INT1
TC1
URX
TC2
UTX
T1
RST
XOUT
XIN
EICK
EIDA
SDA
SCL
SDO
SDI
SCK
SCS
AIN[7:0]
AIN[8]
AIN[9]
PWM0
AIN[10]
PWM1
AIN[11]
PWM2
DC
DC
DC
DC
DC
DC
DC
DC
DC
AC
AC
DC
DC
DC
DC
DC
DC
DC
DC
AC
AC
AC
DC
AC
DC
AC
DC
P00IEN=1
TC0CKS=1, TC0ENB=1
P01IEN=1
TC1CKS=1, TC1ENB=1
URXEN=1
TC2CKS=1, TC2ENB=1
UTXEN=1
T1CKS=1, T1ENB=1
Reset_Pin code option = Reset
High_CLK code option = IHRC_RTC, 32K, 4M, 12M
High_CLK code option = IHRC_RTC, RC, 32K, 4M, 12M
Embedded ICE mode.
Embedded ICE mode.
MSPENB=1
MSPENB=1
SENB=1
SENB=1
SENB=1
SENB=1
ADENB=1,GCHS=1,CHS[3:0]=0000b~0111b
ADENB=1,GCHS=1,CHS[3:0]=1000b
ADENB=1,GCHS=1,CHS[3:0]=1001b
TC0ENB=1, PWM0OUT=1
ADENB=1,GCHS=1,CHS[3:0]=1010b
TC0ENB=1, PWM1OUT=1
ADENB=1,GCHS=1,CHS[3:0]=1011b
TC0ENB=1, PWM2OUT=1
* DC: Digital Characteristic. AC: Analog Characteristic. HV: High Voltage Characteristic.
SONiX TECHNOLOGY CO., LTD
Page 80
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
7.2 I/O PORT MODE
The port direction is programmed by PnM register. When the bit of PnM register is “0”, the pin is input mode. When the
bit of PnM register is “1”, the pin is output mode.
0A0H
P0M
Read/Write
After reset
Bit 7
-
Bit 6
P06M
R/W
0
Bit 5
P05M
R/W
0
Bit 4
P04M
R/W
0
Bit 3
P03M
R/W
0
Bit 2
P02M
R/W
0
Bit 1
P01M
R/W
0
Bit 0
P00M
R/W
0
0A1H
P1M
Read/Write
After reset
Bit 7
P17M
R/W
0
Bit 6
P16M
R/W
0
Bit 5
P15M
R/W
0
Bit 4
P14M
R/W
0
Bit 3
P13M
R/W
0
Bit 2
P12M
R/W
0
Bit 1
P11M
R/W
0
Bit 0
P10M
R/W
0
0A4H
P4M
Read/Write
After reset
Bit 7
P47M
R/W
0
Bit 6
P46M
R/W
0
Bit 5
P45M
R/W
0
Bit 4
P44M
R/W
0
Bit 3
P43M
R/W
0
Bit 2
P42M
R/W
0
Bit 1
P41M
R/W
0
Bit 0
P40M
R/W
0
0A5H
P5M
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
P53M
R/W
0
Bit 2
P52M
R/W
0
Bit 1
P51M
R/W
0
Bit 0
P50M
R/W
0
Bit [7:0]
PnM[7:0]: Pn mode control bits. (n = 0~5).
0 = Pn is input mode.
1 = Pn is output mode.
Note: Users can program them by bit control instructions (B0BSET, B0BCLR).
Example: I/O mode selecting
CLR
CLR
CLR
P0M
P4M
P5M
; Set all ports to be input mode.
MOV
B0MOV
B0MOV
B0MOV
A, #0FFH
P0M, A
P4M,A
P5M, A
; Set all ports to be output mode.
B0BCLR
P4M.0
; Set P4.0 to be input mode.
B0BSET
P4M.0
; Set P4.0 to be output mode.
SONiX TECHNOLOGY CO., LTD
Page 81
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
7.3 I/O PULL UP REGISTER
The I/O pins build in internal pull-up resistors and only support I/O input mode. The port internal pull-up resistor is
programmed by PnUR register. When the bit of PnUR register is “0”, the I/O pin’s pull-up is disabled. When the bit of
PnUR register is “1”, the I/O pin’s pull-up is enabled.
0ACH
P0UR
Read/Write
After reset
Bit 7
-
Bit 6
P06R
R/W
0
Bit 5
P05R
R/W
0
Bit 4
P04R
R/W
0
Bit 3
P03R
R/W
0
Bit 2
P02R
R/W
0
Bit 1
P01R
R/W
0
Bit 0
P00R
R/W
0
0ADH
P1UR
Read/Write
After reset
Bit 7
P17R
R/W
0
Bit 6
P16R
R/W
0
Bit 5
P15R
R/W
0
Bit 4
P14R
R/W
0
Bit 3
P13R
R/W
0
Bit 2
P12R
R/W
0
Bit 1
P11R
R/W
0
Bit 0
P10R
R/W
0
0B0H
P4UR
Read/Write
After reset
Bit 7
P47R
R/W
0
Bit 6
P46R
R/W
0
Bit 5
P45R
R/W
0
Bit 4
P44R
R/W
0
Bit 3
P43R
R/W
0
Bit 2
P42R
R/W
0
Bit 1
P41R
R/W
0
Bit 0
P40R
R/W
0
0B1H
P5UR
Read/Write
After reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P53R
R/W
0
Bit 2
P52R
R/W
0
Bit 1
P51R
R/W
0
Bit 0
P50R
R/W
0
Example: I/O Pull up Register
MOV
B0MOV
B0MOV
B0MOV
A, #0FFH
P0UR, A
P4UR,A
P5UR, A
SONiX TECHNOLOGY CO., LTD
; Enable Port0, 4, 5 Pull-up register,
;
Page 82
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
7.4 I/O PORT DATA REGISTER
0A6H
P0
Read/Write
After reset
Bit 7
-
Bit 6
P06
R/W
0
Bit 5
P05
R/W
0
Bit 4
P04
R/W
0
Bit 3
P03
R/W
0
Bit 2
P02
R/W
0
Bit 1
P01
R/W
0
Bit 0
P00
R/W
0
0A7H
P1
Read/Write
After reset
Bit 7
P17
R/W
0
Bit 6
P16
R/W
0
Bit 5
P15
R/W
0
Bit 4
P14
R/W
0
Bit 3
P13
R/W
0
Bit 2
P12
R/W
0
Bit 1
P11
R/W
0
Bit 0
P10
R/W
0
0AAH
P4
Read/Write
After reset
Bit 7
P47
R/W
0
Bit 6
P46
R/W
0
Bit 5
P45
R/W
0
Bit 4
P44
R/W
0
Bit 3
P43
R/W
0
Bit 2
P42
R/W
0
Bit 1
P41
R/W
0
Bit 0
P40
R/W
0
0ABH
P5
Read/Write
After reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P53
R/W
0
Bit 2
P52
R/W
0
Bit 1
P51
R/W
0
Bit 0
P50
R/W
0
Note: The P04 keeps “1” when external reset enable by code option.
Example: Read data from input port.
B0MOV
A, P0
B0MOV
A, P4
B0MOV
A, P5
Example: Write data to output port.
MOV
A, #0FFH
B0MOV
P0, A
B0MOV
P4, A
B0MOV
P5, A
Example: Write one bit data to output port.
B0BSET
P4.0
B0BSET
P5.3
B0BCLR
B0BCLR
P4.0
P5.3
SONiX TECHNOLOGY CO., LTD
; Read data from Port 0
; Read data from Port 4
; Read data from Port 5
; Write data FFH to all Port.
; Set P4.0 and P5.3 to be “1”.
; Set P4.0 and P5.3 to be “0”.
Page 83
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
7.5 PORT 4, PORT 5 ADC SHARE PIN
The Port 4, Port 5 are shared with ADC input function and no Schmitt trigger structure. Only one pin of port 4, port 5
can be configured as ADC input in the same time by ADM register. The other pins of port 4, port 5 are digital I/O pins.
Connect an analog signal to COMS digital input pin, especially the analog signal level is about 1/2 VDD will cause extra
current leakage. In the power down mode, the above leakage current will be a big problem. Unfortunately, if users
connect more than one analog input signal to port 4 or port 5 will encounter above current leakage situation. P4CON is
Port4 Configuration register. P5CON is Port5 Configuration register. Write “1” into P4CON.n or P5CON.n will configure
related port 4 or port 5 pin will be set as input mode and disable pull-up resistor.
0C6H
P4CON
Read/Write
After reset
Bit [7:0]
Bit 6
P4CON6
R/W
0
Bit 5
P4CON5
R/W
0
Bit 4
P4CON4
R/W
0
Bit 3
P4CON3
R/W
0
Bit 2
P4CON2
R/W
0
Bit 1
P4CON1
R/W
0
Bit 0
P4CON0
R/W
0
Bit 2
P5CON2
R/W
0
Bit 1
P5CON1
R/W
0
Bit 0
P5CON0
R/W
0
P4CON [7:0]: P4.n configuration control bits.
0 = P4.n can be a digital I/O pin.
1 = P4.n will be set as input mode and disable pull-up resistor.
0C7H
P5CON
Read/Write
After reset
Bit [3:0]
Bit 7
P4CON7
R/W
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P5CON3
R/W
0
P5CON [3:0]: P5.n configuration control bits.
0 = P5.n can be a digital I/O pin.
1 = P5.n will be set as input mode and disable pull-up resistor.
Port 4 and Port 5 ADC analog input is controlled by GCHS and CHSn bits of ADM register. If GCHS = 0, P4.n and P5.n
are general purpose bi-direction I/O port. If GCHS = 1, P4.n and P5.n pointed by CHSn is ADC analog signal input pin.
0C8H
ADM
Read/Write
After reset
Bit 7
ADENB
R/W
0
Bit 6
ADS
R/W
0
Bit 5
EOC
R/W
0
Bit 4
GCHS
R/W
0
Bit 3
CHS3
R/W
0
Bit 2
CHS2
R/W
0
Bit 1
CHS1
R/W
0
Bit 4
GCHS: Global channel select bit.
0 = Disable AIN channel.
1 = Enable AIN channel.
Bit [3:0]
CHS [3:0]: ADC input channels select bit.
0000 = AIN0, 0001 = AIN1, 0010 = AIN2, 0011 = AIN3, 0100 = AIN4, 0101 = AIN5, 0110 = AIN6,
0111 = AIN7, 1000 = AIN8, 1001 = AIN9, 1010 = AIN10, 1011 = AIN11.
Bit 0
CHS0
R/W
0
Note: For P4.n and P5.n general purpose I/O function, users should make sure of P4.n and P5.n’s ADC
channel are disabled, or P4.n and P5.n are automatically set as ADC analog input when GCHS = 1 and
CHS[3:0] point to P4.n and P5.n.
SONiX TECHNOLOGY CO., LTD
Page 84
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
Example: Set P4.1 to be general purpose input mode. P4CON.1 must be set as “0”.
; Check GCHS and CHS [3:0] status.
;If CHS[3:0] point to P4.1 (CHS[3:0] = 0001B), set
B0BCLR
FGCHS
GCHS=0
;If CHS[3:0] don’t point to P4.1 (CHS[3:0] ≠ 0001B), don’t
care GCHS status.
; Clear P4CON.
B0BCLR
; Enable P4.1 input mode.
B0BCLR
P4CON.1
; Enable P4.1 digital function.
P4M.1
; Set P4.1 as input mode.
Example: Set P4.1 to be general purpose output. P4CON.1 must be set as “0”.
; Check GCHS and CHS [3:0] status.
; If CHS [3:0] point to P4.1 (CHS [3:0] = 0001B), set
B0BCLR
FGCHS
GCHS=0.
; If CHS [3:0] don’t point to P4.1 (CHS [3:0] ≠ 0001B),
don’t care GCHS status.
; Clear P4CON.
B0BCLR
P4CON.1
; Set P4.1 output buffer to avoid glitch.
B0BSET
P4.1
; or
B0BCLR
P4.1
; Enable P4.1 output mode.
B0BSET
P4M.1
SONiX TECHNOLOGY CO., LTD
; Enable P4.1 digital function.
; Set P4.1 buffer as “1”.
; Set P4.1 buffer as “0”.
; Set P4.1 as input mode.
Page 85
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
7.6 OPEN-DRAIN REGISTER
P0.2, P0.3, P1.0~P1.7 built in open-drain function. These pins must be set as output mode when enable open-drain
function. Open-drain external circuit is as following.
M CU1
M CU2
U
U
VCC
Pull -up Resistor
Open-drain pin
Open-drain pin
The pull-up resistor is necessary. Open-drain output high is driven by pull-up resistor. Output low is sunken by MCU’s
pin.
09CH
P0OC
Read/Write
After reset
Bit [1:0]
Bit 7
P17OC
R/W
0
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
P03OC
R/W
0
Bit 0
P02OC
R/W
0
Bit 6
P16OC
R/W
0
Bit 5
P15OC
R/W
0
Bit 4
P14OC
R/W
0
Bit 3
P13OC
R/W
0
Bit 2
P12OC
R/W
0
Bit 1
P11OC
R/W
0
Bit 0
P10OC
R/W
0
P10OC~P17OC: P1.0~P1.7 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
Example: Enable P1.0 to open-drain mode and output high.
B0BSET
P1.0
; Set P1.0 buffer high.
B0BSET
B0BSET
P10M
P10OC
; Enable P1.0 output mode.
; Enable P1.0 open-drain function.
Example: Disable open-drain mode.
B0BCLR
Bit 6
-
P02OC, P03OC: P0.2, P0.3 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
09DH
P1OC
Read/Write
After reset
Bit [7:0]
Bit 7
-
P10OC
; Disable P1.0 open-drain function.
Note: After disable open-drain function, I/O mode returns to last I/O mode.
SONiX TECHNOLOGY CO., LTD
Page 86
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
8 TIMERS
8.1 WATCHDOG TIMER
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, watchdog timer overflow signal raises and resets MCU. Watchdog timer
clock source is internal low-speed oscillator 16KHz RC type and through programmable pre-scaler controlled by
WDT_CLK code option.
Watchdog timer interval time = 256 * 1/ (Internal Low-Speed oscillator frequency/WDT Pre-scalar) …sec
= 256 / (16KHz/WDT Pre-scaler) …sec
Internal low-speed oscillator
Flosc=16KHz
WDT pre-scaler
Flosc/4
Flosc/8
Flosc/16
Flosc/32
Watchdog interval time
256/(16000/4)=64ms
256/(16000/8)=128ms
256/(16000/16)=256ms
256/(16000/32)=512ms
The watchdog timer has three operating options controlled “WatchDog” code option.
Disable: Disable watchdog timer function.
Enable: Enable watchdog timer function. Watchdog timer actives in normal mode and slow mode. In power down
mode and green mode, the watchdog timer stops.
Always_On: Enable watchdog timer function. The watchdog timer actives and not stop in power down mode and
green mode.
Note: In high noisy environment, the “Always_On” option of watchdog operations is the strongly
recommendation to make the system reset under error situations and re-start again.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.
096H
WDTR
Read/Write
After reset
Bit 7
WDTR7
W
0
Bit 6
WDTR6
W
0
Bit 5
WDTR5
W
0
Bit 4
WDTR4
W
0
Bit 3
WDTR3
W
0
Bit 2
WDTR2
W
0
Bit 1
WDTR1
W
0
Bit 0
WDTR0
W
0
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the
main routine of the program.
Main:
MOV
B0MOV
…
CALL
CALL
…
JMP
A, #5AH
WDTR, A
; Clear the watchdog timer.
SUB1
SUB2
MAIN
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Example: Clear watchdog timer by “@RST_WDT” macro of Sonix IDE.
Main:
@RST_WDT
…
CALL
CALL
…
JMP
; Clear the watchdog timer.
SUB1
SUB2
MAIN
Watchdog timer application note is as following.
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
…
…
JMP $
Err:
; Check I/O.
; Check RAM
; I/O or RAM error. Program jump here and don’t
; clear watchdog. Wait watchdog timer overflow to reset IC.
Correct:
MOV
B0MOV
…
CALL
CALL
…
…
…
JMP
A, #5AH
WDTR, A
; I/O and RAM are correct. Clear watchdog timer and
; execute program.
; Clear the watchdog timer.
SUB1
SUB2
MAIN
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8.2 T0 8-BIT BASIC TIMER
8.2.1 OVERVIEW
The T0 timer is an 8-bit binary up timer with basic timer function. The basic timer function supports flag indicator
(T0IRQ bit) and interrupt operation (interrupt vector). The interval time is programmable through T0M, T0C registers
and supports RTC function. The T0 builds in green mode wake-up function. When T0 timer overflow occurs under
green mode, the system will be waked-up to last operating mode.
8-bit programmable up counting timer: Generate time-out at specific time intervals based on the selected clock
frequency.
Interrupt function: T0 timer function supports interrupt function. When T0 timer occurs overflow, the T0IRQ
actives and the system points program counter to interrupt vector to do interrupt sequence.
RTC function: T0 supports RTC function. The RTC clock source is from external low speed 32K oscillator when
T0TB=1. RTC function is only available in High_Clk code option = "IHRC_RTC".
Green mode function: T0 timer keeps running in green mode and wakes up system when T0 timer overflows.
T0 Rate
(Fcpu/2~Fcpu/256)
T0ENB
Load T0C Value by Program.
T0TB
Fcpu
T0C 8-Bit Binary Up Counting Counter
T0IRQ Interrupt Flag
(T0 timer overflow.)
CPUM0,1
RTC
T0ENB
Note: In RTC mode, the T0 interval time is fixed at 0.5 sec and T0C is 256 counts.
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8.2.2 T0 Timer Operation
T0 timer is controlled by T0ENB bit. When T0ENB=0, T0 timer stops. When T0ENB=1, T0 timer starts to count. T0C
increases “1” by timer clock source. When T0 overflow event occurs, T0IRQ flag is set as ”1” to indicate overflow and
cleared by program. The overflow condition is T0C count from full scale (0xFF) to zero scale (0x00). T0 doesn’t build in
double buffer, so load T0C by program when T0 timer overflows to fix the correct interval time. If T0 timer interrupt
function is enabled (T0IEN=1), the system will execute interrupt procedure. The interrupt procedure is system program
counter points to interrupt vector (ORG 000BH) and executes interrupt service routine after T0 overflow occurrence.
Clear T0IRQ by program is necessary in interrupt procedure. T0 timer can works in normal mode, slow mode and
green mode. In green mode, T0 keeps counting, set T0IRQ and wakes up system when T0 timer overflows.
Clock
Source
T0C
...
0x00 or “n”
by program
0x01
or n+1
0x02
or n+2
0x02
or n+2
...
...
0xFE
0xFF
0x00 or “n”
by program
...
T0IRQ
T0 timer overflows. T0IRQ set as “1”.
Reload T0C by program.
T0IRQ is cleared by program.
T0 clock source is Fcpu (instruction cycle) through T0rate[2:0] pre-scalar to decide Fcpu/2~Fcpu/256. T0 length is 8-bit
(256 steps), and the one count period is each cycle of input clock.
T0rate[2:0]
Fhosc=16MHz,
Fcpu=Fhosc/4
T0 Clock
T0 Interval Time
Fhosc=4MHz,
Fcpu=Fhosc/4
max. (ms) Unit (us) max. (ms) Unit (us)
000b
001b
010b
011b
100b
101b
110b
111b
-
Fcpu/256
Fcpu/128
Fcpu/64
Fcpu/32
Fcpu/16
Fcpu/8
Fcpu/4
Fcpu/2
32768Hz/64
16.384
8.192
4.096
2.048
1.024
0.512
0.256
0.128
-
SONiX TECHNOLOGY CO., LTD
64
32
16
8
4
2
1
0.5
-
65.536
32.768
16.384
8.192
4.096
2.048
1.024
0.512
-
Page 90
256
128
64
32
16
8
4
2
-
IHRC_RTC mode
max.
(sec)
0.5
Unit (ms)
1.953
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
8.2.3 T0M MODE REGISTER
T0M is T0 timer mode control register to configure T0 operating mode including T0 pre-scaler, clock source…These
configurations must be setup completely before enabling T0 timer.
0B2H
T0M
Read/Write
After reset
Bit 7
T0ENB
R/W
0
Bit 6
T0rate2
R/W
0
Bit 5
T0rate1
R/W
0
Bit 4
T0rate0
R/W
0
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
T0TB
R/W
0
Bit 0
T0TB: RTC clock source control bit.
0 = Disable RTC (T0 clock source from Fcpu).
1 = Enable RTC.
Bit [6:4]
T0RATE[2:0]: T0 timer clock source select bits.
000 = Fcpu/256, 001 = Fcpu/128, 010 = Fcpu/64, 011 = Fcpu/32, 100 = Fcpu/16, 101 = Fcpu/8, 110 =
Fcpu/4,111 = Fcpu/2.
Bit 7
T0ENB: T0 counter control bit.
0 = Disable T0 timer.
1 = Enable T0 timer.
Note: T0RATE is not available in RTC mode. The T0 interval time is fixed at 0.5 sec.
8.2.4 T0C COUNTING REGISTER
T0C is T0 8-bit counter. When T0C overflow occurs, the T0IRQ flag is set as “1” and cleared by program. The T0C
decides T0 interval time through below equation to calculate a correct value. It is necessary to write the correct value to
T0C register, and then enable T0 timer to make sure the first cycle correct. After one T0 overflow occurs, the T0C
register is loaded a correct value by program.
0B3H
T0C
Read/Write
After reset
Bit 7
T0C7
R/W
0
Bit 6
T0C6
R/W
0
Bit 5
T0C5
R/W
0
Bit 4
T0C4
R/W
0
Bit 3
T0C3
R/W
0
Bit 2
T0C2
R/W
0
Bit 1
T0C1
R/W
0
Bit 0
T0C0
R/W
0
The equation of T0C initial value is as following.
T0C initial value = 256 - (T0 interrupt interval time * T0 clock rate)
Example: To calculation T0C to obtain 10ms T0 interval time. T0 clock source is Fcpu = 4MHz/4 = 1MHz.
Select T0RATE=001 (Fcpu/128).
T0 interval time = 10ms. T0 clock rate = 4MHz/4/128
T0C initial value = 256 - (T0 interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 128)
= 256 - (10-2 * 4 * 106 / 4 / 128)
= B2H
Note: In RTC mode, T0C is 256 counts and generatesT0 0.5 sec interval time. Don’t change T0C value in
RTC mode.
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8.2.5 T0 TIMER OPERATION EXPLAME
T0 TIMER CONFIGURATION:
; Reset T0 timer.
MOV
B0MOV
A, #0x00
T0M, A
; Clear T0M register.
; Set T0 clock source and T0 rate.
A, #0nnn0000b
MOV
B0MOV
T0M, A
; Set T0C register for T0 Interval time.
A, #value
MOV
B0MOV
T0C, A
; Clear T0IRQ
B0BCLR
FT0IRQ
; Enable T0 timer and interrupt function.
B0BSET
FT0IEN
B0BSET
FT0ENB
T0 works in RTC mode:
; Reset T0 timer.
MOV
B0MOV
A, #0x00
T0M, A
; Set T0 RTC function.
B0BSET
FT0TB
; Enable T0 interrupt function.
; Enable T0 timer.
; Clear T0M register.
; Clear T0C.
CLR
T0C
B0BCLR
FT0IRQ
; Clear T0IRQ
; Enable T0 timer and interrupt function.
B0BSET
FT0IEN
B0BSET
FT0ENB
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; Enable T0 interrupt function.
; Enable T0 timer.
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8.3 TC0 8-BIT TIMER/COUNTER
8.3.1 OVERVIEW
The TC0 timer is an 8-bit binary up timer with basic timer, event counter and PWM functions. The basic timer function
supports flag indicator (TC0IRQ bit) and interrupt operation (interrupt vector). The interval time is programmable
through TC0M, TC0C, TC0R registers. The event counter is changing TC0 clock source from system clock
(Fcpu/Fhosc) to external clock like signal (e.g. continuous pulse, R/C type oscillating signal…). TC0 becomes a counter
to count external clock number to implement measure application. TC0 also builds in duty/cycle programmable PWM.
The PWM cycle and resolution are controlled by TC0 timer clock rate, TC0R and TC0D registers, so the PWM with
good flexibility to implement IR carry signal, motor control and brightness adjuster…The main purposes of the TC0
timer are as following.
8-bit programmable up counting timer: Generate time-out at specific time intervals based on the selected clock
frequency.
Interrupt function: TC0 timer function supports interrupt function. When TC0 timer occurs overflow, the TC0IRQ
actives and the system points program counter to interrupt vector to do interrupt sequence.
Event Counter: The event counter function counts the external clock counts.
Duty/cycle programmable PWM: The PWM is duty/cycle programmable controlled by TC0R and TC0D
registers.
Green mode function: All TC0 functions (timer, PWM, event counter, auto-reload) keep running in green mode
and no wake-up function.
TC0 Rate
(Fcpu/1~Fcpu/128)
TC0R Reload
Data Buffer
Up Counting
Reload Value
TC0CKS0
Load
Fcpu
TC0CKS1
TC0ENB
Fhosc
TC0 Time Out
TC0C
8-Bit Binary Up
Counting Counter
PWM0OUT
P0.0 (Schmitter Trigger)
PWM
S
CPUM0,1
P5.1 Pin
Compare
R
TC0D
Data Buffer
P5.1 GPIO
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8.3.2 TC0 TIMER OPERATION
TC0 timer is controlled by TC0ENB bit. When TC0ENB=0, TC0 timer stops. When TC0ENB=1, TC0 timer starts to
count. Before enabling TC0 timer, setup TC0 timer’s configurations to select timer function modes, e.g. basic timer,
interrupt function…TC0C increases “1” by timer clock source. When TC0 overflow event occurs, TC0IRQ flag is set
as ”1” to indicate overflow and cleared by program. The overflow condition is TC0C count from full scale (0xFF) to zero
scale (0x00). In difference function modes, TC0C value relates to operation. If TC0C value changing effects operation,
the transition of operations would make timer function error. So TC0 builds in double buffer to avoid these situations
happen. The double buffer concept is to flash TC0C during TC0 counting, to set the new value to TC0R (reload buffer),
and the new value will be loaded from TC0R to TC0C after TC0 overflow occurrence automatically. In the next cycle,
the TC0 timer runs under new conditions, and no any transitions occur. The auto-reload function is no any control
interface and always actives as TC0 enables. If TC0 timer interrupt function is enabled (TC0IEN=1), the system will
execute interrupt procedure. The interrupt procedure is system program counter points to interrupt vector (ORG 000CH)
and executes interrupt service routine after TC0 overflow occurrence. Clear TC0IRQ by program is necessary in
interrupt procedure. TC0 timer can works in normal mode, slow mode and green mode. But in green mode, TC0 keep
counting, set TC0IRQ and outputs PWM, but can’t wake-up system.
Clock
Source
TC0C
...
0x00
or TC0R
0x01
0x02
0x03
...
...
0xFE
0xFF
TC0R
...
TC0IRQ
TC0 timer overflows. TC0IRQ set as “1”.
Reload TC0C from TC0R automatically.
TC0IRQ is cleared by program.
TC0 provides different clock sources to implement different applications and configurations. TC0 clock source includes
Fcpu (instruction cycle), Fhosc (high speed oscillator) and external input pin (P0.0) controlled by TC0CKS[1:0] bits.
TC0CKS0 bit selects the clock source is from Fcpu or Fhosc. If TC0CKS0=0, TC0 clock source is Fcpu through
TC0rate[2:0] pre-scalar to decide Fcpu/1~Fcpu/128. If TC0CKS0=1, TC0 clock source is Fhosc through TC0rate[2:0]
pre-scalar to decide Fcpu/1~Fcpu/128. TC0CKS1 bit controls the clock source is external input pin or controlled by
TC0CKS0 bit. If TC0CKS1=0, TC0 clock source is selected by TC0CKS0 bit. If TC0CKS1=1, TC0 clock source is
external input pin that means to enable event counter function. TC0rate[2:0] pre-scalar is unless when TC0CKS0=1 or
TC0CKS1=1 conditions. TC0 length is 8-bit (256 steps), and the one count period is each cycle of input clock.
TC0CKS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TC0 Interval Time
Fhosc=16MHz,
Fhosc=4MHz,
TC0rate[2:0] TC0 Clock
Fcpu=Fhosc/4
Fcpu=Fhosc/4
max. (ms) Unit (us) max. (ms) Unit (us)
000b
Fcpu/128
8.192
32
32.768
128
001b
Fcpu/64
4.096
16
16.384
64
010b
Fcpu/32
2.048
8
8.192
32
011b
Fcpu/16
1.024
4
4.096
16
100b
Fcpu/8
0.512
2
2.048
8
101b
Fcpu/4
0.256
1
1.024
4
110b
Fcpu/2
0.128
0.5
0.512
2
111b
Fcpu/1
0.064
0.25
0.256
1
000b
Fhosc/128
2.048
8
8.192
32
001b
Fhosc/64
1.024
4
4.096
16
010b
Fhosc/32
0.512
2
2.048
8
011b
Fhosc/16
0.256
1
1.024
4
100b
Fhosc/8
0.128
0.5
0.512
2
101b
Fhosc/4
0.064
0.25
0.256
1
110b
Fhosc/2
0.032
0.125
0.128
0.5
111b
Fhosc/1
0.016
0.0625
0.064
0.25
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8.3.3 TC0M MODE REGISTER
TC0M is TC0 timer mode control register to configure TC0 operating mode including TC0 pre-scalar, clock source,
PWM function…These configurations must be setup completely before enabling TC0 timer.
0B4H
TC0M
Read/Write
After reset
Bit 7
TC0ENB
R/W
0
Bit 6
TC0rate2
R/W
0
Bit 5
TC0rate1
R/W
0
Bit 4
TC0rate0
R/W
0
Bit 3
TC0CKS1
R/W
0
Bit 2
TC0CKS0
R/W
0
Bit 1
-
Bit 0
PWM0OUT
R/W
0
Bit 0
PWM0OUT: PWM output control bit.
0 = Disable PWM output function, and P5.1 is GPIO mode.
1 = Enable PWM output function, and P5.1 outputs PWM signal.
Bit 2
TC0CKS0: TC0 clock source select bit.
0 = Fcpu.
1 = Fhosc.
Bit 3
TC0CKS1: TC0 clock source select bit.
0 = Internal clock (Fcpu and Fhosc controlled by TC0CKS0 bit).
1 = External input pin (P0.0/INT0) and enable event counter function. TC0rate[2:0] bits are useless.
Bit [6:4]
TC0RATE[2:0]: TC0 timer clock source select bits.
TC0CKS0=0 -> 000 = Fcpu/128, 001 = Fcpu/64, 010 = Fcpu/32, 011 = Fcpu/16, 100 = Fcpu/8, 101 = Fcpu/4,
110 = Fcpu/2,111 = Fcpu/1.
TC0CKS0=1 -> 000 = Fhosc/128, 001 = Fhosc/64, 010 = Fhosc/32, 011 = Fhosc/16, 100 = Fhosc/8,
101 = Fhosc/4, 110 = Fhosc/2,111 = Fhosc/1.
Bit 7
TC0ENB: TC0 counter control bit.
0 = Disable TC0 timer.
1 = Enable TC0 timer.
8.3.4 TC0C COUNTING REGISTER
TC0C is TC0 8-bit counter. When TC0C overflow occurs, the TC0IRQ flag is set as “1” and cleared by program. The
TC0C decides TC0 interval time through below equation to calculate a correct value. It is necessary to write the correct
value to TC0C register and TC0R register first time, and then enable TC0 timer to make sure the fist cycle correct.
After one TC0 overflow occurs, the TC0C register is loaded a correct value from TC0R register automatically, not
program.
0B5H
TC0C
Read/Write
After reset
Bit 7
TC0C7
R/W
0
Bit 6
TC0C6
R/W
0
Bit 5
TC0C5
R/W
0
Bit 4
TC0C4
R/W
0
Bit 3
TC0C3
R/W
0
Bit 2
TC0C2
R/W
0
Bit 1
TC0C1
R/W
0
Bit 0
TC0C0
R/W
0
The equation of TC0C initial value is as following.
TC0C initial value = 256 - (TC0 interrupt interval time * TC0 clock rate)
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8.3.5 TC0R AUTO-RELOAD REGISTER
TC0 timer builds in auto-reload function, and TC0R register stores reload data. When TC0C overflow occurs, TC0C
register is loaded data from TC0R register automatically. Under TC0 timer counting status, to modify TC0 interval time
is to modify TC0R register, not TC0C register. New TC0C data of TC0 interval time will be updated after TC0 timer
overflow occurrence, TC0R loads new value to TC0C register. But at the first time to setup TC0M, TC0C and TC0R
must be set the same value before enabling TC0 timer. TC0 is double buffer design. If new TC0R value is set by
st
program, the new value is stored in 1 buffer. Until TC0 overflow occurs, the new value moves to real TC0R buffer.
This way can avoid any transitional condition to affect the correctness of TC0 interval time and PWM output signal.
0B6H
TC0R
Read/Write
After reset
Bit 7
TC0R7
W
0
Bit 6
TC0R6
W
0
Bit 5
TC0R5
W
0
Bit 4
TC0R4
W
0
Bit 3
TC0R3
W
0
Bit 2
TC0R2
W
0
Bit 1
TC0R1
W
0
Bit 0
TC0R0
W
0
The equation of TC0R initial value is as following.
TC0R initial value = 256 - (TC0 interrupt interval time * TC0 clock rate)
Example: To calculation TC0C and TC0R value to obtain 10ms TC0 interval time. TC0 clock source is
Fcpu = 16MHz/16 = 1MHz. Select TC0RATE=000 (Fcpu/128).
TC0 interval time = 10ms. TC0 clock rate = 16MHz/16/128
TC0C/TC0R initial value = 256 - (TC0 interval time * input clock)
= 256 - (10ms * 16MHz / 16 / 128)
= 256 - (10-2 * 16 * 106 / 16 / 128)
= B2H
8.3.6 TC0D PWM DUTY REGISTER
TC0D register’s purpose is to decide PWM duty. In PWM mode, TC0R controls PWM’s cycle, and TC0D controls the
duty of PWM. The operation is base on timer counter value. When TC0C = TC0D, the PWM high duty finished and
exchange to low level. It is easy to configure TC0D to choose the right PWM’s duty for application.
0B7H
TC0D
Read/Write
After Reset
Bit 7
TC0D7
R/W
0
Bit 6
TC0D6
R/W
0
Bit 5
TC0D5
R/W
0
Bit 4
TC0D4
R/W
0
Bit 3
TC0D3
R/W
0
Bit 2
TC0D2
R/W
0
Bit 1
TC0D1
R/W
0
Bit 0
TC0D0
R/W
0
The equation of TC0D initial value is as following.
TC0D initial value = TC0R + (PWM high pulse width period / TC0 clock rate)
Example: To calculate TC0D value to obtain 1/3 duty PWM signal. The TC0 clock source is Fcpu =
16MHz/16= 1MHz. Select TC0RATE=000 (Fcpu/128).
TC0R = B2H. TC0 interval time = 10ms. So the PWM cycle is 100Hz. In 1/3 duty condition, the high pulse width is
about 3.33ms.
TC0D initial value = B2H + (PWM high pulse width period / TC0 clock rate)
= B2H + (3.33ms * 16MHz / 16 / 128)
= B2H + 1AH
= CCH
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8.3.7 TC0 EVENT COUNTER
TC0 event counter is set the TC0 clock source from external input pin (P0.0). When TC0CKS1=1, TC0 clock source is
switch to external input pin (P0.0). TC0 event counter trigger direction is falling edge. When one falling edge occurs,
TC0C will up one count. When TC0C counts from 0xFF to 0x00, TC0 triggers overflow event. The external event
counter input pin’s wake-up function of GPIO mode is disabled when TC0 event counter function enabled to avoid
event counter signal trigger system wake-up and not keep in power saving mode. The external event counter input
pin’s external interrupt function is also disabled when TC0 event counter function enabled, and the P00IRQ bit keeps
“0” status. The event counter usually is used to measure external continuous signal rate, e.g. continuous pulse, R/C
type oscillating signal…These signal phase don’t synchronize with MCU’s main clock. Use TC0 event to measure it
and calculate the signal rate in program for different applications.
External Input Signel
TC0C
...
0x00
or TC0R
0x01
0x02
0x03
...
...
0xFE
0xFF
TC0R
...
TC0IRQ
TC0 timer overflows. TC0IRQ set as “1”.
Reload TC0C from TC0R automatically.
TC0IRQ is cleared by program.
8.3.8 PULSE WIDTH MODULATION (PWM)
The PWM is duty/cycle programmable design to offer various PWM signals. When TC0 timer enables and PWM0OUT
bit sets as “1” (enable PWM output), the PWM output pin (P5.1) outputs PWM signal. One cycle of PWM signal is high
pulse first, and then low pulse outputs. TC0R register controls the cycle of PWM, and TC0D decides the duty (high
pulse width length) of PWM. TC0C initial value is TC0R reloaded when TC0 timer enables and TC0 timer overflows.
When TC0C count is equal to TC0D, the PWM high pulse finishes and exchanges to low level. When TC0 overflows
(TC0C counts from 0xFF to 0x00), one complete PWM cycle finishes. The PWM exchanges to high level for next cycle.
The PWM is auto-reload design to load TC0C from TC0R automatically when TC0 overflows and the end of PWM’s
cycle, to keeps PWM continuity. If modify the PWM cycle by program as PWM outputting, the new cycle occurs at next
cycle when TC0C loaded from TC0R.
Enable TC0 and PWM.
TC0C is loaded from TC0R.
PWM outputs high status.
TC0C
TC0R
TC0R
+1
TC0C = TC0D.
PWM exchanges to low status.
TC0R
+2
...
TC0D
-2
TC0D
-1
TC0D
...
0xFD
TC0C overflows from 0xFF to 0x00.
TC0C is loaded from TC0R.
PWM exchanges to high status.
0xFE
0xFF
TC0R
TC0R
+1
TC0R
+2
...
PWM Output
One complete cycle of PWM.
Next cycle.
The resolution of PWM is decided by TC0R. TC0R range is from 0x00~0xFF. If TC0R = 0x00, PWM’s resolution is
1/256. If TC0R = 0x80, PWM’s resolution is 1/128. TC0D controls the high pulse width of PWM for PWM’s duty. When
TC0C = TC0D, PWM output exchanges to low status. TC0D must be greater than TC0R, or the PWM signal keeps low
status. When PWM outputs, TC0IRQ still actives as TC0 overflows, and TC0 interrupt function actives as TC0IEN = 1.
But strongly recommend be careful to use PWM and TC0 timer together, and make sure both functions work well.
The PWM output pin is shared with GPIO and switch to output PWM signal as PWM0OUT=1 automatically. If
PWM0OUT bit is cleared to disable PWM, the output pin exchanges to last GPIO mode automatically. It easily to
implement carry signal on/off operation, not to control TC0ENB bit.
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PWM Output
PWM0OUT=0.
PWM0OUT=1. The pin exchanges to output
mode and outputs PWM signal automatically.
PWM0OUT=0. The pin exchanges
to last GPIO mode (output low).
PWM0OUT=1.
PWM0OUT=0.
PWM0OUT=1. The pin exchanges to output
mode and outputs PWM signal automatically.
PWM0OUT=0. The pin exchanges
to last GPIO mode (output high).
PWM0OUT=1.
PWM Output
High impendence (floating)
PWM Output
PWM0OUT=0.
PWM0OUT=1. The pin exchanges to output
mode and outputs PWM signal automatically.
PWM0OUT=0. The pin exchanges
to last GPIO mode (input).
PWM0OUT=1.
8.3.9 TC0 TIMER OPERATION EXPLAME
TC0 TIMER CONFIGURATION:
; Reset TC0 timer.
CLR
TC0M
; Clear TC0M register.
; Set TC0 clock source and TC0 rate.
A, #0nnn0n00b
MOV
B0MOV
TC0M, A
; Set TC0C and TC0R register for TC0 Interval time.
A, #value
MOV
B0MOV
TC0C, A
B0MOV
TC0R, A
; TC0C must be equal to TC0R.
; Clear TC0IRQ
B0BCLR
FTC0IRQ
; Enable TC0 timer and interrupt function.
B0BSET
FTC0IEN
B0BSET
FTC0ENB
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; Enable TC0 interrupt function.
; Enable TC0 timer.
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TC0 EVENT COUNTER CONFIGURATION:
; Reset TC0 timer.
CLR
TC0M
; Clear TC0M register.
; Enable TC0 event counter.
B0BSET
FTC0CKS1
; Set TC0 clock source from external input pin (P0.0).
; Set TC0C and TC0R register for TC0 Interval time.
A, #value
MOV
B0MOV
TC0C, A
B0MOV
TC0R, A
; TC0C must be equal to TC0R.
; Clear TC0IRQ
B0BCLR
FTC0IRQ
; Enable TC0 timer and interrupt function.
B0BSET
FTC0IEN
B0BSET
FTC0ENB
; Enable TC0 interrupt function.
; Enable TC0 timer.
TC0 PWM CONFIGURATION:
; Reset TC0 timer.
CLR
TC0M
; Clear TC0M register.
; Set TC0 clock source and TC0 rate.
A, #0nnn0n00b
MOV
B0MOV
TC0M, A
; Set TC0C and TC0R register for PWM cycle.
A, #value1
MOV
B0MOV
TC0C, A
B0MOV
TC0R, A
; Set TC0D register for PWM duty.
A, #value2
MOV
B0MOV
TC0D, A
; Enable PWM and TC0 timer.
B0BSET
B0BSET
FTC0ENB
FPWM0OUT
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; TC0C must be equal to TC0R.
; TC0D must be greater than TC0R.
; Enable TC0 timer.
; Enable PWM.
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8.4 TC1 8-BIT TIMER/COUNTER
8.4.1 OVERVIEW
The TC1 timer is an 8-bit binary up timer with basic timer, event counter and PWM functions. The basic timer function
supports flag indicator (TC1IRQ bit) and interrupt operation (interrupt vector). The interval time is programmable
through TC1M, TC1C, TC1R registers. The event counter is changing TC1 clock source from system clock
(Fcpu/Fhosc) to external clock like signal (e.g. continuous pulse, R/C type oscillating signal…). TC1 becomes a counter
to count external clock number to implement measure application. TC1 also builds in duty/cycle programmable PWM.
The PWM cycle and resolution are controlled by TC1 timer clock rate, TC1R and TC1D registers, so the PWM with
good flexibility to implement IR carry signal, motor control and brightness adjuster…The main purposes of the TC1
timer are as following.
8-bit programmable up counting timer: Generate time-out at specific time intervals based on the selected clock
frequency.
Interrupt function: TC1 timer function supports interrupt function. When TC1 timer occurs overflow, the TC1IRQ
actives and the system points program counter to interrupt vector to do interrupt sequence.
Event Counter: The event counter function counts the external clock counts.
Duty/cycle programmable PWM: The PWM is duty/cycle programmable controlled by TC1R and TC1D
registers.
Green mode function: All TC1 functions (timer, PWM, event counter, auto-reload) keep running in green mode
and no wake-up function.
TC1R Reload
Data Buffer
TC1 Rate
(Fcpu/1~Fcpu/128)
TC1CKS0
Up Counting
Reload Value
Load
TC1CKS1
TC1ENB
Fcpu
TC1 Time Out
TC1C
8-Bit Binary Up
Counting Counter
Fhosc
PWM0OUT
P0.1 (Schmitter Trigger)
PWM
S
CPUM0,1
P5.2 Pin
Compare
TC1D
Data Buffer
R
P5.2 GPIO
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8.4.2 TC1 TIMER OPERATION
TC1 timer is controlled by TC1ENB bit. When TC1ENB=0, TC1 timer stops. When TC1ENB=1, TC1 timer starts to
count. Before enabling TC1 timer, setup TC1 timer’s configurations to select timer function modes, e.g. basic timer,
interrupt function…TC1C increases “1” by timer clock source. When TC1 overflow event occurs, TC1IRQ flag is set
as ”1” to indicate overflow and cleared by program. The overflow condition is TC1C count from full scale (0xFF) to zero
scale (0x00). In difference function modes, TC1C value relates to operation. If TC1C value changing effects operation,
the transition of operations would make timer function error. So TC1 builds in double buffer to avoid these situations
happen. The double buffer concept is to flash TC1C during TC1 counting, to set the new value to TC1R (reload buffer),
and the new value will be loaded from TC1R to TC1C after TC1 overflow occurrence automatically. In the next cycle,
the TC1 timer runs under new conditions, and no any transitions occur. The auto-reload function is no any control
interface and always actives as TC1 enables. If TC1 timer interrupt function is enabled (TC1IEN=1), the system will
execute interrupt procedure. The interrupt procedure is system program counter points to interrupt vector (ORG 000DH)
and executes interrupt service routine after TC1 overflow occurrence. Clear TC1IRQ by program is necessary in
interrupt procedure. TC1 timer can works in normal mode, slow mode and green mode. But in green mode, TC1 keep
counting, set TC1IRQ and outputs PWM, but can’t wake-up system.
Clock
Source
TC1C
...
0x00
or TC1R
0x01
0x02
0x03
...
...
0xFE
0xFF
TC1R
...
TC1IRQ
TC1 timer overflows. TC1IRQ set as “1”.
Reload TC1C from TC1R automatically.
TC1IRQ is cleared by program.
TC1 provides different clock sources to implement different applications and configurations. TC1 clock source includes
Fcpu (instruction cycle), Fhosc (high speed oscillator) and external input pin (P0.1) controlled by TC1CKS[1:0] bits.
TC1CKS0 bit selects the clock source is from Fcpu or Fhosc. If TC1CKS0=0, TC1 clock source is Fcpu through
TC1rate[2:0] pre-scalar to decide Fcpu/1~Fcpu/128. If TC1CKS0=1, TC0 clock source is Fhosc through TC1rate[2:0]
pre-scalar to decide Fcpu/1~Fcpu/128. TC1CKS1 bit controls the clock source is external input pin or controlled by
TC1CKS0 bit. If TC1CKS1=0, TC1 clock source is selected by TC1CKS0 bit. If TC1CKS1=1, TC0 clock source is
external input pin that means to enable event counter function. TC1rate[2:0] pre-scalar is unless when TC1CKS0=1 or
TC1CKS1=1 conditions. TC1 length is 8-bit (256 steps), and the one count period is each cycle of input clock.
TC1CKS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TC1 Interval Time
Fhosc=16MHz,
Fhosc=4MHz,
TC1rate[2:0] TC1 Clock
Fcpu=Fhosc/4
Fcpu=Fhosc/4
max. (ms) Unit (us) max. (ms) Unit (us)
000b
Fcpu/128
8.192
32
32.768
128
001b
Fcpu/64
4.096
16
16.384
64
010b
Fcpu/32
2.048
8
8.192
32
011b
Fcpu/16
1.024
4
4.096
16
100b
Fcpu/8
0.512
2
2.048
8
101b
Fcpu/4
0.256
1
1.024
4
110b
Fcpu/2
0.128
0.5
0.512
2
111b
Fcpu/1
0.064
0.25
0.256
1
000b
Fhosc/128
2.048
8
8.192
32
001b
Fhosc/64
1.024
4
4.096
16
010b
Fhosc/32
0.512
2
2.048
8
011b
Fhosc/16
0.256
1
1.024
4
100b
Fhosc/8
0.128
0.5
0.512
2
101b
Fhosc/4
0.064
0.25
0.256
1
110b
Fhosc/2
0.032
0.125
0.128
0.5
111b
Fhosc/1
0.016
0.0625
0.064
0.25
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8.4.3 TC1M MODE REGISTER
TC1M is TC1 timer mode control register to configure TC1 operating mode including TC1 pre-scalar, clock source,
PWM function…These configurations must be setup completely before enabling TC1 timer.
0B8H
TC1M
Read/Write
After reset
Bit 7
TC1ENB
R/W
0
Bit 6
TC1rate2
R/W
0
Bit 5
TC1rate1
R/W
0
Bit 4
TC1rate0
R/W
0
Bit 3
TC1CKS1
R/W
0
Bit 2
TC1CKS0
R/W
0
Bit 1
-
Bit 0
PWM1OUT
R/W
0
Bit 0
PWM1OUT: PWM output control bit.
0 = Disable PWM output function, and P5.2 is GPIO mode.
1 = Enable PWM output function, and P5.2 outputs PWM signal.
Bit 2
TC1CKS0: TC1 clock source select bit.
0 = Fcpu.
1 = Fhosc.
Bit 3
TC1CKS1: TC1 clock source select bit.
0 = Internal clock (Fcpu and Fhosc controlled by TC1CKS0 bit).
1 = External input pin (P0.1/INT1) and enable event counter function. TC0rate[2:0] bits are useless.
Bit [6:4]
TC1RATE[2:0]: TC1 timer clock source select bits.
TC1CKS0=0 -> 000 = Fcpu/128, 001 = Fcpu/64, 010 = Fcpu/32, 011 = Fcpu/16, 100 = Fcpu/8, 101 = Fcpu/4,
110 = Fcpu/2,111 = Fcpu/1.
TC1CKS0=1 -> 000 = Fhosc/128, 001 = Fhosc/64, 010 = Fhosc/32, 011 = Fhosc/16, 100 = Fhosc/8,
101 = Fhosc/4, 110 = Fhosc/2,111 = Fhosc/1.
Bit 7
TC1ENB: TC1 counter control bit.
0 = Disable TC1 timer.
1 = Enable TC1 timer.
8.4.4 TC1C COUNTING REGISTER
TC1C is TC1 8-bit counter. When TC1C overflow occurs, the TC1IRQ flag is set as “1” and cleared by program. The
TC1C decides TC1 interval time through below equation to calculate a correct value. It is necessary to write the correct
value to TC1C register and TC1R register first time, and then enable TC1 timer to make sure the fist cycle correct.
After one TC1 overflow occurs, the TC1C register is loaded a correct value from TC1R register automatically, not
program.
0B9H
TC1C
Read/Write
After reset
Bit 7
TC1C7
R/W
0
Bit 6
TC1C6
R/W
0
Bit 5
TC1C5
R/W
0
Bit 4
TC1C4
R/W
0
Bit 3
TC1C3
R/W
0
Bit 2
TC1C2
R/W
0
Bit 1
TC1C1
R/W
0
Bit 0
TC1C0
R/W
0
The equation of TC1C initial value is as following.
TC1C initial value = 256 - (TC1 interrupt interval time * TC1 clock rate)
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8.4.5 TC1R AUTO-RELOAD REGISTER
TC1 timer builds in auto-reload function, and TC1R register stores reload data. When TC1C overflow occurs, TC1C
register is loaded data from TC1R register automatically. Under TC1 timer counting status, to modify TC1 interval time
is to modify TC1R register, not TC1C register. New TC1C data of TC1 interval time will be updated after TC1 timer
overflow occurrence, TC1R loads new value to TC1C register. But at the first time to setup T0M, TC1C and TC1R must
be set the same value before enabling TC1 timer. TC1 is double buffer design. If new TC1R value is set by program,
st
the new value is stored in 1 buffer. Until TC1 overflow occurs, the new value moves to real TC1R buffer. This way can
avoid any transitional condition to affect the correctness of TC1 interval time and PWM output signal.
0BAH
TC1R
Read/Write
After reset
Bit 7
TC1R7
W
0
Bit 6
TC1R6
W
0
Bit 5
TC1R5
W
0
Bit 4
TC1R4
W
0
Bit 3
TC1R3
W
0
Bit 2
TC1R2
W
0
Bit 1
TC1R1
W
0
Bit 0
TC1R0
W
0
The equation of TC1R initial value is as following.
TC1R initial value = 256 - (TC1 interrupt interval time * TC1 clock rate)
Example: To calculation TC1C and TC1R value to obtain 10ms TC1 interval time. TC1 clock source is
Fcpu = 16MHz/16 = 1MHz. Select TC1RATE=000 (Fcpu/128).
TC1 interval time = 10ms. TC1 clock rate = 16MHz/16/128
TC1C/TC1R initial value = 256 - (TC1 interval time * input clock)
= 256 - (10ms * 16MHz / 16 / 128)
= 256 - (10-2 * 16 * 106 / 16 / 128)
= B2H
8.4.6 TC1D PWM DUTY REGISTER
TC1D register’s purpose is to decide PWM duty. In PWM mode, TC1R controls PWM’s cycle, and TC1D controls the
duty of PWM. The operation is base on timer counter value. When TC1C = TC1D, the PWM high duty finished and
exchange to low level. It is easy to configure TC1D to choose the right PWM’s duty for application.
0BBH
TC1D
Read/Write
After Reset
Bit 7
TC1D7
R/W
0
Bit 6
TC1D6
R/W
0
Bit 5
TC1D5
R/W
0
Bit 4
TC1D4
R/W
0
Bit 3
TC1D3
R/W
0
Bit 2
TC1D2
R/W
0
Bit 1
TC1D1
R/W
0
Bit 0
TC1D0
R/W
0
The equation of TC1D initial value is as following.
TC1D initial value = TC1R + (PWM high pulse width period / TC1 clock rate)
Example: To calculate TC1D value to obtain 1/3 duty PWM signal. The TC1 clock source is Fcpu =
16MHz/16 = 1MHz. Select TC1RATE=000 (Fcpu/128).
TC1R = B2H. TC1 interval time = 10ms. So the PWM cycle is 100Hz. In 1/3 duty condition, the high pulse width is
about 3.33ms.
TC1D initial value = B2H + (PWM high pulse width period / TC1 clock rate)
= B2H + (3.33ms * 16MHz / 16 / 128)
= B2H + 1AH
= CCH
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8.4.7 TC1 EVENT COUNTER
TC1 event counter is set the TC1 clock source from external input pin (P0.1). When TC1CKS1=1, TC1 clock source is
switch to external input pin (P0.1). TC1 event counter trigger direction is falling edge. When one falling edge occurs,
TC1C will up one count. When TC1C counts from 0xFF to 0x00, TC1 triggers overflow event. The external event
counter input pin’s wake-up function of GPIO mode is disabled when TC1 event counter function enabled to avoid
event counter signal trigger system wake-up and not keep in power saving mode. The external event counter input
pin’s external interrupt function is also disabled when TC1 event counter function enabled, and the P01IRQ bit keeps
“0” status. The event counter usually is used to measure external continuous signal rate, e.g. continuous pulse, R/C
type oscillating signal…These signal phase don’t synchronize with MCU’s main clock. Use TC1 event to measure it
and calculate the signal rate in program for different applications.
External Input Signel
TC1C
...
0x00
or TC1R
0x01
0x02
0x03
...
...
0xFE
0xFF
TC1R
...
TC1IRQ
TC1 timer overflows. TC1IRQ set as “1”.
Reload TC1C from TC1R automatically.
TC1IRQ is cleared by program.
8.4.8 PULSE WIDTH MODULATION (PWM)
The PWM is duty/cycle programmable design to offer various PWM signals. When TC1 timer enables and PWM1OUT
bit sets as “1” (enable PWM output), the PWM output pin (P5.2) outputs PWM signal. One cycle of PWM signal is high
pulse first, and then low pulse outputs. TC1R register controls the cycle of PWM, and TC1D decides the duty (high
pulse width length) of PWM. TC1C initial value is TC1R reloaded when TC1 timer enables and TC1 timer overflows.
When TC1C count is equal to TC1D, the PWM high pulse finishes and exchanges to low level. When TC1 overflows
(TC1C counts from 0xFF to 0x00), one complete PWM cycle finishes. The PWM exchanges to high level for next cycle.
The PWM is auto-reload design to load TC1C from TC1R automatically when TC1 overflows and the end of PWM’s
cycle, to keeps PWM continuity. If modify the PWM cycle by program as PWM outputting, the new cycle occurs at next
cycle when TC1C loaded from TC1R.
Enable TC1 and PWM.
TC1C is loaded from TC1R.
PWM outputs high status.
TC1C
TC1R
TC1R
+1
TC1C = TC1D.
PWM exchanges to low status.
TC1R
+2
...
TC1D
-2
TC1D
-1
TC1D
...
0xFD
TC1C overflows from 0xFF to 0x00.
TC1C is loaded from TC1R.
PWM exchanges to high status.
0xFE
0xFF
TC1R
TC1R
+1
TC1R
+2
...
PWM Output
One complete cycle of PWM.
Next cycle.
The resolution of PWM is decided by TC1R. TC1R range is from 0x00~0xFF. If TC1R = 0x00, PWM’s resolution is
1/256. If TC1R = 0x80, PWM’s resolution is 1/128. TC1D controls the high pulse width of PWM for PWM’s duty. When
TC1C = TC1D, PWM output exchanges to low status. TC1D must be greater than TC1R, or the PWM signal keeps low
status. When PWM outputs, TC1IRQ still actives as TC1 overflows, and TC1 interrupt function actives as TC1IEN = 1.
But strongly recommend be careful to use PWM and TC1 timer together, and make sure both functions work well.
The PWM output pin is shared with GPIO and switch to output PWM signal as PWM1OUT=1 automatically. If
PWM1OUT bit is cleared to disable PWM, the output pin exchanges to last GPIO mode automatically. It easily to
implement carry signal on/off operation, not to control TC1ENB bit.
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PWM Output
PWM1OUT=0.
PWM1OUT=1. The pin exchanges to output
mode and outputs PWM signal automatically.
PWM1OUT=0. The pin exchanges
to last GPIO mode (output low).
PWM1OUT=1.
PWM1OUT=0.
PWM1OUT=1. The pin exchanges to output
mode and outputs PWM signal automatically.
PWM1OUT=0. The pin exchanges
to last GPIO mode (output high).
PWM1OUT=1.
PWM Output
High impendence (floating)
PWM Output
PWM1OUT=0.
PWM1OUT=1. The pin exchanges to output
mode and outputs PWM signal automatically.
PWM1OUT=0. The pin exchanges
to last GPIO mode (input).
PWM1OUT=1.
8.4.9 TC1 TIMER OPERATION EXPLAME
TC1 TIMER CONFIGURATION:
; Reset TC1 timer.
CLR
TC1M
; Clear TC1M register.
; Set TC1 clock source and TC1 rate.
A, #0nnn0n00b
MOV
B0MOV
TC1M, A
; Set TC1C and TC1R register for TC1 Interval time.
A, #value
MOV
B0MOV
TC1C, A
B0MOV
TC1R, A
; TC1C must be equal to TC1R.
; Clear TC1IRQ
B0BCLR
FTC1IRQ
; Enable TC1 timer and interrupt function.
B0BSET
FTC1IEN
B0BSET
FTC1ENB
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; Enable TC1 interrupt function.
; Enable TC1 timer.
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TC1 EVENT COUNTER CONFIGURATION:
; Reset TC1 timer.
CLR
TC1M
; Clear TC1M register.
; Enable TC1 event counter.
B0BSET
FTC1CKS1
; Set TC1 clock source from external input pin (P0.1).
; Set TC1C and TC1R register for TC1 Interval time.
A, #value
MOV
B0MOV
TC1C, A
B0MOV
TC1R, A
; TC1C must be equal to TC1R.
; Clear TC1IRQ
B0BCLR
FTC1IRQ
; Enable TC1 timer and interrupt function.
B0BSET
FTC1IEN
B0BSET
FTC1ENB
; Enable TC1 interrupt function.
; Enable TC1 timer.
TC1 PWM CONFIGURATION:
; Reset TC1 timer.
CLR
TC1M
; Clear TC1M register.
; Set TC1 clock source and TC1 rate.
A, #0nnn0n00b
MOV
B0MOV
TC1M, A
; Set TC1C and TC1R register for PWM cycle.
A, #value1
MOV
B0MOV
TC1C, A
B0MOV
TC1R, A
; Set TC1D register for PWM duty.
A, #value2
MOV
B0MOV
TC1D, A
; Enable PWM and TC1 timer.
B0BSET
B0BSET
FTC1ENB
FPWM1OUT
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; TC1C must be equal to TC1R.
; TC1D must be greater than TC1R.
; Enable TC1 timer.
; Enable PWM.
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8.5 TC2 8-BIT TIMER/COUNTER
8.5.1 OVERVIEW
The TC2 timer is an 8-bit binary up timer with basic timer, event counter and PWM functions. The basic timer function
supports flag indicator (TC2IRQ bit) and interrupt operation (interrupt vector). The interval time is programmable
through TC2M, TC2C, TC2R registers. The event counter is changing TC2 clock source from system clock
(Fcpu/Fhosc) to external clock like signal (e.g. continuous pulse, R/C type oscillating signal…). TC2 becomes a counter
to count external clock number to implement measure application. TC2 also builds in duty/cycle programmable PWM.
The PWM cycle and resolution are controlled by TC2 timer clock rate, TC2R and TC2D registers, so the PWM with
good flexibility to implement IR carry signal, motor control and brightness adjuster…The main purposes of the TC2
timer are as following.
8-bit programmable up counting timer: Generate time-out at specific time intervals based on the selected clock
frequency.
Interrupt function: TC2 timer function supports interrupt function. When TC2 timer occurs overflow, the TC2IRQ
actives and the system points program counter to interrupt vector to do interrupt sequence.
Event Counter: The event counter function counts the external clock counts.
Duty/cycle programmable PWM: The PWM is duty/cycle programmable controlled by TC2R and TC2D
registers.
Green mode function: All TC2 functions (timer, PWM, event counter, auto-reload) keep running in green mode
and no wake-up function.
TC2 Rate
(Fcpu/1~Fcpu/128)
TC2R Reload
Data Buffer
Up Counting
Reload Value
TC2CKS0
Load
Fcpu
TC2CKS1
TC2ENB
Fhosc
TC2 Time Out
TC2C
8-Bit Binary Up
Counting Counter
PWM2OUT
P0.2 (Schmitter Trigger)
PWM
S
CPUM0,1
P5.3 Pin
Compare
TC2D
Data Buffer
R
P5.3 GPIO
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8.5.2 TC2 TIMER OPERATION
TC2 timer is controlled by TC2ENB bit. When TC2ENB=0, TC2 timer stops. When TC2ENB=1, TC2 timer starts to
count. Before enabling TC2 timer, setup TC2 timer’s configurations to select timer function modes, e.g. basic timer,
interrupt function…TC2C increases “1” by timer clock source. When TC2 overflow event occurs, TC2IRQ flag is set
as ”1” to indicate overflow and cleared by program. The overflow condition is TC2C count from full scale (0xFF) to zero
scale (0x00). In difference function modes, TC2C value relates to operation. If TC2C value changing effects operation,
the transition of operations would make timer function error. So TC2 builds in double buffer to avoid these situations
happen. The double buffer concept is to flash TC2C during TC2 counting, to set the new value to TC2R (reload buffer),
and the new value will be loaded from TC2R to TC2C after TC2 overflow occurrence automatically. In the next cycle,
the TC2 timer runs under new conditions, and no any transitions occur. The auto-reload function is no any control
interface and always actives as TC2 enables. If TC2 timer interrupt function is enabled (TC2IEN=1), the system will
execute interrupt procedure. The interrupt procedure is system program counter points to interrupt vector (ORG 000EH)
and executes interrupt service routine after TC2 overflow occurrence. Clear TC2IRQ by program is necessary in
interrupt procedure. TC2 timer can works in normal mode, slow mode and green mode. But in green mode, TC2 keep
counting, set TC2IRQ and outputs PWM, but can’t wake-up system.
Clock
Source
TC2C
...
0x00
or TC2R
0x01
0x02
0x03
...
...
0xFE
0xFF
TC2R
...
TC2IRQ
TC2 timer overflows. TC2IRQ set as “1”.
Reload TC2C from TC2R automatically.
TC2IRQ is cleared by program.
TC2 provides different clock sources to implement different applications and configurations. TC2 clock source includes
Fcpu (instruction cycle), Fhosc (high speed oscillator) and external input pin (P0.2) controlled by TC2CKS[1:0] bits.
TC2CKS0 bit selects the clock source is from Fcpu or Fhosc. If TC2CKS0=0, TC0 clock source is Fcpu through
TC2rate[2:0] pre-scalar to decide Fcpu/1~Fcpu/128. If TC2CKS0=1, TC2 clock source is Fhosc through TC2rate[2:0]
pre-scalar to decide Fcpu/1~Fcpu/128. TC2CKS1 bit controls the clock source is external input pin or controlled by
TC2CKS0 bit. If TC2CKS1=0, TC2 clock source is selected by TC2CKS0 bit. If TC2CKS1=1, TC2 clock source is
external input pin that means to enable event counter function. TC2rate[2:0] pre-scalar is unless when TC2CKS0=1 or
TC2CKS1=1 conditions. TC2 length is 8-bit (256 steps), and the one count period is each cycle of input clock.
TC2CKS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TC2 Interval Time
Fhosc=16MHz,
Fhosc=4MHz,
TC2rate[2:0] TC2 Clock
Fcpu=Fhosc/4
Fcpu=Fhosc/4
max. (ms) Unit (us) max. (ms) Unit (us)
000b
Fcpu/128
8.192
32
32.768
128
001b
Fcpu/64
4.096
16
16.384
64
010b
Fcpu/32
2.048
8
8.192
32
011b
Fcpu/16
1.024
4
4.096
16
100b
Fcpu/8
0.512
2
2.048
8
101b
Fcpu/4
0.256
1
1.024
4
110b
Fcpu/2
0.128
0.5
0.512
2
111b
Fcpu/1
0.064
0.25
0.256
1
000b
Fhosc/128
2.048
8
8.192
32
001b
Fhosc/64
1.024
4
4.096
16
010b
Fhosc/32
0.512
2
2.048
8
011b
Fhosc/16
0.256
1
1.024
4
100b
Fhosc/8
0.128
0.5
0.512
2
101b
Fhosc/4
0.064
0.25
0.256
1
110b
Fhosc/2
0.032
0.125
0.128
0.5
111b
Fhosc/1
0.016
0.0625
0.064
0.25
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8.5.3 TC2M MODE REGISTER
TC2M is TC2 timer mode control register to configure TC2 operating mode including TC2 pre-scalar, clock source,
PWM function…These configurations must be setup completely before enabling TC2 timer.
0BCH
TC2M
Read/Write
After reset
Bit 7
TC2ENB
R/W
0
Bit 6
TC2rate2
R/W
0
Bit 5
TC2rate1
R/W
0
Bit 4
TC2rate0
R/W
0
Bit 3
TC2CKS1
R/W
0
Bit 2
TC2CKS0
R/W
0
Bit 1
-
Bit 0
PWM2OUT
R/W
0
Bit 0
PWM2OUT: PWM output control bit.
0 = Disable PWM output function, and P5.3 is GPIO mode.
1 = Enable PWM output function, and P5.3 outputs PWM signal.
Bit 2
TC2CKS0: TC2 clock source select bit.
0 = Fcpu.
1 = Fhosc.
Bit 3
TC2CKS1: TC2 clock source select bit.
0 = Internal clock (Fcpu and Fhosc controlled by TC2CKS0 bit).
1 = External input pin (P0.2/INT2) and enable event counter function. TC2rate[2:0] bits are useless.
Bit [6:4]
TC2RATE[2:0]: TC2 timer clock source select bits.
TC2CKS0=0 -> 000 = Fcpu/128, 001 = Fcpu/64, 010 = Fcpu/32, 011 = Fcpu/16, 100 = Fcpu/8, 101 = Fcpu/4,
110 = Fcpu/2,111 = Fcpu/1.
TC2CKS0=1 -> 000 = Fhosc/128, 001 = Fhosc/64, 010 = Fhosc/32, 011 = Fhosc/16, 100 = Fhosc/8,
101 = Fhosc/4, 110 = Fhosc/2,111 = Fhosc/1.
Bit 7
TC2ENB: TC0 counter control bit.
0 = Disable TC2 timer.
1 = Enable TC2 timer.
8.5.4 TC2C COUNTING REGISTER
TC2C is TC2 8-bit counter. When TC2C overflow occurs, the TC2IRQ flag is set as “1” and cleared by program. The
TC2C decides TC2 interval time through below equation to calculate a correct value. It is necessary to write the correct
value to TC2C register and TC2R register first time, and then enable TC2 timer to make sure the fist cycle correct.
After one TC2 overflow occurs, the TC2C register is loaded a correct value from TC2R register automatically, not
program.
0BDH
TC2C
Read/Write
After reset
Bit 7
TC2C7
R/W
0
Bit 6
TC2C6
R/W
0
Bit 5
TC2C5
R/W
0
Bit 4
TC2C4
R/W
0
Bit 3
TC2C3
R/W
0
Bit 2
TC2C2
R/W
0
Bit 1
TC2C1
R/W
0
Bit 0
TC2C0
R/W
0
The equation of TC2C initial value is as following.
TC2C initial value = 256 - (TC2 interrupt interval time * TC2 clock rate)
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8.5.5 TC2R AUTO-RELOAD REGISTER
TC2 timer builds in auto-reload function, and TC2R register stores reload data. When TC2C overflow occurs, TC2C
register is loaded data from TC2R register automatically. Under TC2 timer counting status, to modify TC2 interval time
is to modify TC2R register, not TC2C register. New TC2C data of TC2 interval time will be updated after TC2 timer
overflow occurrence, TC2R loads new value to TC2C register. But at the first time to setup TC2M, TC2C and TC2R
must be set the same value before enabling TC2 timer. TC2 is double buffer design. If new TC2R value is set by
st
program, the new value is stored in 1 buffer. Until TC2 overflow occurs, the new value moves to real TC2R buffer.
This way can avoid any transitional condition to affect the correctness of TC2 interval time and PWM output signal.
0BEH
TC2R
Read/Write
After reset
Bit 7
TC2R7
W
0
Bit 6
TC2R6
W
0
Bit 5
TC2R5
W
0
Bit 4
TC2R4
W
0
Bit 3
TC2R3
W
0
Bit 2
TC2R2
W
0
Bit 1
TC2R1
W
0
Bit 0
TC2R0
W
0
The equation of TC2R initial value is as following.
TC2R initial value = 256 - (TC2 interrupt interval time * TC2 clock rate)
Example: To calculation TC2C and TC2R value to obtain 10ms TC2 interval time. TC2 clock source is
Fcpu = 16MHz/16 = 1MHz. Select TC0RATE=000 (Fcpu/128).
TC2 interval time = 10ms. TC2 clock rate = 16MHz/16/128
TC2C/TC2R initial value = 256 - (TC2 interval time * input clock)
= 256 - (10ms * 16MHz / 16 / 128)
= 256 - (10-2 * 16 * 106 / 16 / 128)
= B2H
8.5.6 TC2D PWM DUTY REGISTER
TC2D register’s purpose is to decide PWM duty. In PWM mode, TC2R controls PWM’s cycle, and TC2D controls the
duty of PWM. The operation is base on timer counter value. When TC2C = TC2D, the PWM high duty finished and
exchange to low level. It is easy to configure TC2D to choose the right PWM’s duty for application.
0BFH
TC2D
Read/Write
After Reset
Bit 7
TC2D7
R/W
0
Bit 6
TC2D6
R/W
0
Bit 5
TC2D5
R/W
0
Bit 4
TC2D4
R/W
0
Bit 3
TC2D3
R/W
0
Bit 2
TC2D2
R/W
0
Bit 1
TC2D1
R/W
0
Bit 0
TC2D0
R/W
0
The equation of TC2D initial value is as following.
TC2D initial value = TC2R + (PWM high pulse width period / TC2 clock rate)
Example: To calculate TC2D value to obtain 1/3 duty PWM signal. The TC2 clock source is Fcpu =
16MHz/16= 1MHz. Select TC2RATE=000 (Fcpu/128).
TC2R = B2H. TC2 interval time = 10ms. So the PWM cycle is 100Hz. In 1/3 duty condition, the high pulse width is
about 3.33ms.
TC2D initial value = B2H + (PWM high pulse width period / TC2 clock rate)
= B2H + (3.33ms * 16MHz / 16 / 128)
= B2H + 1AH
= CCH
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8.5.7 TC2 EVENT COUNTER
TC2 event counter is set the TC2 clock source from external input pin (P0.2). When TC2CKS1=1, TC2 clock source is
switch to external input pin (P0.2). TC2 event counter trigger direction is falling edge. When one falling edge occurs,
TC2C will up one count. When TC2C counts from 0xFF to 0x00, TC2 triggers overflow event. The external event
counter input pin’s wake-up function of GPIO mode is disabled when TC2 event counter function enabled to avoid
event counter signal trigger system wake-up and not keep in power saving mode. The external event counter input
pin’s external interrupt function is also disabled when TC2 event counter function enabled, and the P02IRQ bit keeps
“0” status. The event counter usually is used to measure external continuous signal rate, e.g. continuous pulse, R/C
type oscillating signal…These signal phase don’t synchronize with MCU’s main clock. Use TC2 event to measure it
and calculate the signal rate in program for different applications.
External Input Signel
TC2C
...
0x00
or TC2R
0x01
0x02
0x03
...
...
0xFE
0xFF
TC2R
...
TC2IRQ
TC2 timer overflows. TC2IRQ set as “1”.
Reload TC2C from TC2R automatically.
TC2IRQ is cleared by program.
8.5.8 PULSE WIDTH MODULATION (PWM)
The PWM is duty/cycle programmable design to offer various PWM signals. When TC2 timer enables and PWM2OUT
bit sets as “1” (enable PWM output), the PWM output pin (P5.3) outputs PWM signal. One cycle of PWM signal is high
pulse first, and then low pulse outputs. TC2R register controls the cycle of PWM, and TC2D decides the duty (high
pulse width length) of PWM. TC2C initial value is TC2R reloaded when TC2 timer enables and TC2 timer overflows.
When TC2C count is equal to TC2D, the PWM high pulse finishes and exchanges to low level. When TC2 overflows
(TC2C counts from 0xFF to 0x00), one complete PWM cycle finishes. The PWM exchanges to high level for next cycle.
The PWM is auto-reload design to load TC2C from TC2R automatically when TC2 overflows and the end of PWM’s
cycle, to keeps PWM continuity. If modify the PWM cycle by program as PWM outputting, the new cycle occurs at next
cycle when TC2C loaded from TC2R.
Enable TC2 and PWM.
TC2C is loaded from TC2R.
PWM outputs high status.
TC2C
TC2R
TC2R
+1
TC2C = TC2D.
PWM exchanges to low status.
TC2R
+2
...
TC2D
-2
TC2D
-1
TC2D
...
0xFD
TC2C overflows from 0xFF to 0x00.
TC2C is loaded from TC2R.
PWM exchanges to high status.
0xFE
0xFF
TC2R
TC2R
+1
TC2R
+2
...
PWM Output
One complete cycle of PWM.
Next cycle.
The resolution of PWM is decided by TC2R. TC2R range is from 0x00~0xFF. If TC2R = 0x00, PWM’s resolution is
1/256. If TC2R = 0x80, PWM’s resolution is 1/128. TC2D controls the high pulse width of PWM for PWM’s duty. When
TC2C = TC2D, PWM output exchanges to low status. TC2D must be greater than TC2R, or the PWM signal keeps low
status. When PWM outputs, TC2IRQ still actives as TC2 overflows, and TC2 interrupt function actives as TC2IEN = 1.
But strongly recommend be careful to use PWM and TC2 timer together, and make sure both functions work well.
The PWM output pin is shared with GPIO and switch to output PWM signal as PWM2OUT=1 automatically. If
PWM2OUT bit is cleared to disable PWM, the output pin exchanges to last GPIO mode automatically. It easily to
implement carry signal on/off operation, not to control TC2ENB bit.
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PWM Output
PWM2OUT=0.
PWM2OUT=1. The pin exchanges to output
mode and outputs PWM signal automatically.
PWM2OUT=0. The pin exchanges
to last GPIO mode (output low).
PWM2OUT=1.
PWM2OUT=0.
PWM2OUT=1. The pin exchanges to output
mode and outputs PWM signal automatically.
PWM2OUT=0. The pin exchanges
to last GPIO mode (output high).
PWM2OUT=1.
PWM Output
High impendence (floating)
PWM Output
PWM2OUT=0.
PWM2OUT=1. The pin exchanges to output
mode and outputs PWM signal automatically.
PWM2OUT=0. The pin exchanges
to last GPIO mode (input).
PWM2OUT=1.
8.5.9 TC2 TIMER OPERATION EXPLAME
TC2 TIMER CONFIGURATION:
; Reset TC2 timer.
CLR
TC2M
; Clear TC2M register.
; Set TC2 clock source and TC2 rate.
A, #0nnn0n00b
MOV
B0MOV
TC2M, A
; Set TC2C and TC2R register for TC2 Interval time.
A, #value
MOV
B0MOV
TC2C, A
B0MOV
TC2R, A
; TC2C must be equal to TC2R.
; Clear TC2IRQ
B0BCLR
FTC2IRQ
; Enable TC2 timer and interrupt function.
B0BSET
FTC2IEN
B0BSET
FTC2ENB
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; Enable TC2 interrupt function.
; Enable TC2 timer.
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TC2 EVENT COUNTER CONFIGURATION:
; Reset TC2 timer.
CLR
TC2M
; Clear TC2M register.
; Enable TC2 event counter.
B0BSET
FTC2CKS1
; Set TC2 clock source from external input pin (P0.2).
; Set TC2C and TC2R register for TC2 Interval time.
A, #value
MOV
B0MOV
TC2C, A
B0MOV
TC2R, A
; TC2C must be equal to TC2R.
; Clear TC2IRQ
B0BCLR
FTC2IRQ
; Enable TC2 timer and interrupt function.
B0BSET
FTC2IEN
B0BSET
FTC2ENB
; Enable TC2 interrupt function.
; Enable TC2timer.
TC0 PWM CONFIGURATION:
; Reset TC2 timer.
CLR
TC2M
; Clear TC2M register.
; Set TC2 clock source and TC2 rate.
A, #0nnn0n00b
MOV
B0MOV
TC2M, A
; Set TC2C and TC2R register for PWM cycle.
A, #value1
MOV
B0MOV
TC2C, A
B0MOV
TC2R, A
; Set TC2D register for PWM duty.
A, #value2
MOV
B0MOV
TC2D, A
; Enable PWM and TC2 timer.
B0BSET
B0BSET
FTC2ENB
FPWM2OUT
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; TC2C must be equal to TC2R.
; TC2D must be greater than TC2R.
; Enable TC2 timer.
; Enable PWM.
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8-Bit Flash Micro-Controller with Embedded ICE and ISP
8.6 T1 16-BIT TIMER WITH CAPTURE TIMER FUNCTION
8.6.1 OVERVIEW
The T1 timer is a 16-bit binary up timer with basic timer and capture timer functions. The basic timer function supports
flag indicator (T1IRQ bit) and interrupt operation (interrupt vector). The interval time is programmable through T1M,
T1CH/T1CL 16-bit counter registers. The capture timer supports high pulse width measurement, low pulse width
measurement, cycle measurement and continuous duration from P0.3. T1 becomes a timer meter to count external
signal time parameters to implement measure application. The main purposes of the T1 timer are as following.
16-bit programmable up counting timer: Generate time-out at specific time intervals based on the selected
clock frequency.
16-bit measurement: Measure the input signal pulse width and cycle depend on the T1 clock time base to
decide the capture timer’s resolution. The capture timer builds in programmable trigger edge selection to decide
the start-stop trigger event.
16-bit capture timer: The 16-bit event counter to detect event source for accumulative capture timer function.
The event counter is up counting design.
Interrupt function: T1 timer function and capture timer function support interrupt function. When T1 timer occurs
overflow or capture timer stops counting, the T1IRQ actives and the system points program counter to interrupt
vector to do interrupt sequence.
Green mode function: All T1 functions (timer, capture timer…) keeps running in green mode, but no wake-up
function. Timer IRQ actives as any IRQ trigger occurrence, e.g. timer overflow…
T1CH
Buffer
T1 Rate
T1CKS
Fcpu
Fhosc
T1CL
Buffer
Read T1CL Register
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷128
Write T1CL Register
T1ENB
T1ENB
Stop T1 Counting
Trigger T1CH, T1CL
Timer Start to Count and
0
Stop Counting.
CPUM0,1
1
01
P0.3
T1IRQ Interrupt Flag
(T1 timer overflow.)
(Capture timer stop)
T1CH,T1CL 16-Bit Binary Up Counting Counter
10
1
0
CPTMD
Stop CPT Counting
11
CPTEN
CPTMD
CPT Counter Overflow.
00
CPTCH, CPTCL 16-bit Event Counter, Binary Up Counting Counter
CPTG[1:0]
CPTStart
8.6.2 T1 TIMER OPERATION
T1 timer is controlled by T1ENB bit. When T1ENB=0, T1 timer stops. When T1ENB=1, T1 timer starts to count. Before
enabling T1 timer, setup T1 timer’s configurations to select timer function modes, e.g. basic timer, interrupt
function…T1 16-bit counter (T1CH, T1CL) increases “1” by timer clock source. When T1 overflow event occurs, T1IRQ
flag is set as ”1” to indicate overflow and cleared by program. The overflow condition is T1CH, T1CL count from full
scale (0xFFFF) to zero scale (0x0000). T1 doesn’t build in double buffer, so load T1CH, T1CL by program when T1
timer overflows to fix the correct interval time. If T1 timer interrupt function is enabled (T1IEN=1), the system will
execute interrupt procedure. The interrupt procedure is system program counter points to interrupt vector (ORG 000FH)
and executes interrupt service routine after T1 overflow occurrence. Clear T1IRQ by program is necessary in interrupt
procedure. T1 timer can works in normal mode, slow mode and green mode.
Clock
Source
T1CH, T1CL
...
0x0000 or “n”
by program
0x0001
or n+1
0x0002
or n+2
0x0002
or n+2
...
...
0xFFFE 0xFFFF
0x0000 or “n”
by program
...
T1IRQ
T1 timer overflows. T1IRQ set as “1”.
Reload T1CH, T1CL by program.
T1IRQ is cleared by program.
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T1 provides different clock sources to implement different applications and configurations. T1 clock source includes
Fcpu (instruction cycle) and Fhosc (high speed oscillator) controlled by T1CKS bit. T1CKS bit selects the clock source
is from Fcpu or Fhosc. If T1CKS=0, T1 clock source is Fcpu through T1rate[2:0] pre-scalar to decide Fcpu/1~Fcpu/128.
If T1CKS=1, T1 clock source is Fhosc through T1rate[2:0] pre-scalar to decide Fcpu/1~Fcpu/128. T1 length is 16-bit
(65536 steps), and the one count period is each cycle of input clock.
T1CKS
T1rate[2:0]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
000b
001b
010b
011b
100b
101b
110b
111b
000b
001b
010b
011b
100b
101b
110b
111b
T1 Interval Time
Fhosc=16MHz,
Fhosc=4MHz,
T1 Clock
Fcpu=Fhosc/4
Fcpu=Fhosc/4
max. (ms) Unit (us) max. (ms) Unit (us)
Fcpu/128 2097.152
32
8388.608
128
Fcpu/64
1048.576
16
4194.304
64
Fcpu/32
524.288
8
2097.152
32
Fcpu/16
262.144
4
1048.576
16
Fcpu/8
131.072
2
524.288
8
Fcpu/4
65.536
1
262.144
4
Fcpu/2
32.768
0.5
131.072
2
Fcpu/1
16.384
0.25
65.536
1
Fhosc/128 524.288
8
2097.152
32
Fhosc/64
262.144
4
1048.576
16
Fhosc/32
131.072
2
524.288
8
Fhosc/16
65.536
1
262.144
4
Fhosc/8
32.768
0.5
131.072
2
Fhosc/4
16.384
0.25
65.536
1
Fhosc/2
8.192
0.125
32.768
0.5
Fhosc/1
4.096
0.0625
16.384
0.25
8.6.3 T1M MODE REGISTER
T1M is T1 timer mode control register to configure T1 operating mode including T1 pre-scalar, clock source, capture
parameters…These configurations must be setup completely before enabling T1 timer.
0C0H
T1M
Read/Write
After reset
Bit 7
T1ENB
R/W
0
Bit 6
T1rate2
R/W
0
Bit 5
T1rate1
R/W
0
Bit 4
T1rate0
R/W
0
Bit 3
T1CKS
R/W
0
Bit 2
Bit 1
Bit 0
Bit 7
T1ENB: T1 counter control bit.
0 = Disable T1 timer.
1 = Enable T1 timer.
Bit [6:4]
T1RATE[2:0]: T1 timer clock source select bits.
T1CKS=0 -> 000 = Fcpu/128, 001 = Fcpu/64, 010 = Fcpu/32, 011 = Fcpu/16, 100 = Fcpu/8, 101 = Fcpu/4,
110 = Fcpu/2,111 = Fcpu/1.
T1CKS=1 -> 000 = Fhosc/128, 001 = Fhosc/64, 010 = Fhosc/32, 011 = Fhosc/16, 100 = Fhosc/8,
101 = Fhosc/4, 110 = Fhosc/2,111 = Fhosc/1.
Bit 3
T1CKS: T1 clock source control bit.
0 = Fcpu.
1 = Fhosc.
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8.6.4 T1CH, T1CL 16-bit COUNTING REGISTERS
T1 counter is 16-bit counter combined with T1CH and T1CL registers. When T1 timer overflow occurs, the T1IRQ flag
is set as “1” and cleared by program. The T1CH, T1CL decide T1 interval time through below equation to calculate a
correct value. It is necessary to write the correct value to T1CH and T1CL registers, and then enable T1 timer to make
sure the fist cycle correct. After one T1 overflow occurs, the T1CH and T1CL registers are loaded correct values by
program.
0C1H
T1CL
Read/Write
After reset
0C2H
T1CH
Read/Write
After Reset
Bit 7
T1CL7
R/W
0
Bit 7
T1CH7
R/W
0
Bit 6
T1CL6
R/W
0
Bit 6
T1CH6
R/W
0
Bit 5
T1CL5
R/W
0
Bit 4
T1CL4
R/W
0
Bit 3
T1CL3
R/W
0
Bit 2
T1CL2
R/W
0
Bit 1
T1CL1
R/W
0
Bit 0
T1CL0
R/W
0
Bit 5
T1CH5
R/W
0
Bit 4
T1CH4
R/W
0
Bit 3
T1CH3
R/W
0
Bit 2
T1CH2
R/W
0
Bit 1
T1CH1
R/W
0
Bit 0
T1CH0
R/W
0
The T1 timer counter length is 16-bit and points to T1CH and T1CL registers. The timer counter is double buffer design.
The core bus is 8-bit, so access 16-bit data needs a latch flag to avoid the transient status affect the 16-bit data
mistake occurrence. Under write mode, the write T1CH is the latch control flag. Under read mode, the read T1CL is the
latch control flag. So, write T1 16-bit counter is to write T1CH first, and then write T1CL. The 16-bit data is written to
16-bit counter buffer after executing writing T1CL. Read T1 16-bit counter is to read T1CL first, and then read T1CH.
The 16-bit data is dumped to T1CH, T1CL after executing reading T1CH.
Read T1 counter buffer sequence is to read T1CL first, and then read T1CH.
Write T1 counter buffer sequence is to write T1CH first, and then write T1CL.
The equation of T1 16-bit counter (T1CH, T1CL) initial value is as following.
T1CH, T1CL initial value = 65536 - (T1 interrupt interval time * T1 clock rate)
Example: To calculation T1CH and T1CL values to obtain 500ms T1 interval time. T1 clock source is Fcpu
= 16MHz/16 = 1MHz. Select T1RATE=000 (Fcpu/128).
T1 interval time = 500ms. T1 clock rate = 16MHz/16/128
T1 16-bit counter initial value = 65536 - (T1 interval time * input clock)
= 65536 - (500ms * 16MHz / 16 / 128)
= 65536 - (500*10-3 * 16 * 106 / 16 / 128)
= F0BDH (T1CH = F0H, T1CL = BDH)
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8.6.5 T1 CPATURE TIMER
The 16-bit capture timer is controlled by CPTEN bit, but the T1 must be enabled. Set T1ENB=1 and CPTEN=1 to
enable capture timer function. The capture timer is a pure counter and no clock source to decide interval time.
Capture timer input source is P0.3 pin. CPTG[1:0] bits select capture timer functions.
CPTG[1:0] = 00: Capture Timer Function.
CPTG[1:0] = 01: Measure P0.3 high pulse width.
CPTG[1:0] = 10: Measure P0.3 low pulse width.
CPTG[1:0] = 11: Measure P0.3 cycle.
These functions must be combined T1 timer function to implement. The capture timer can measure high pulse width,
low pulse width, cycle and capture duration of input signal (P0.3) controlled by CPTG[1:0]. CPTStart bit is to execute
capture timer function. When CPTStart is set as “1”, the capture timer waits the right trigger edge to active 16-bit
counter. The trigger edge finds, and the 16-bit counter starts to count which clock source is T1. When the second right
edge finds, the 16-counter stops, CPTStart is cleared and the T1IRQ actives.
8.6.5.1Capture Timer
The capture timer function controlled by CPTG[1:0] bits. Set CPTG[1:0] = 00 to enable capture timer function. The
capture timer function’s purpose is to measure the period of a continuous signal. The function includes two modes for
difference speed signal controlled by CPTMD bit. To start capture timer operation is set CPTStart bit as “1”, and the
trigger source is the first rising edge of the P0.3 input signal. Before the first rising edge, the capture timer and T1 timer
keeps ideal status and wait the riding edge event. When catch the first edge, the capture timer and T1 timer start to
count. Each of overflow event occurs (controlled by CPTMD bit), the capture timer and T1 timer stop counting,
CPTStart bit is cleared, and T1IRQ is set as “1”. If T1IEN = 1, the system executes T1 interrupt function and service
routine.
Capture timer counting trigger source is the rising edge of input signal.
Input Signal
16-bit Capture Timer
n
n+1
n+2
n+3
n+4
n+5
CPTMD = 0, Low-speed mode (T1ENB = 1. CPTEN = 1. CPTG[1:0] = 00.)
Input signal rate < T1 timer rate. Use T1 timer to measure input signal continuous duration. Set capture timer initial
value (CPTCH, CPTCL = “m”) and clear T1 counter (T1CH, T1CL = 0x0000) by program. Set CPTSatrt bit (“1”) to start
capture timer counting. Capture timer and T1 start counting at the first rising edge of input signal. When capture timer
overflow occurs (0xFFFF to 0x0000), T1 stops counting, CPTStart is cleared (“0”) automatically, and the T1IRQ sets as
“1”. The T1 16-bit counter value (T1CH, T1CL = “n”) is the continuous signal’s duration.
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CPTMD = 1, High-speed mode (T1ENB = 1. CPTEN = 1. CPTG[1:0] = 00.)
Input signal rate > T1 timer rate. Set a unique timer by T1 timer to measure input signal counts. Set T1 timer initial
value (T1CH, T1CL = “m”) and clear capture timer counter (CPTCH, CPTCL = 0x0000) by program. Set CPTSatrt bit
(“1”) to start capture timer counting. Capture timer and T1 start counting at the first rising edge of input signal. When T1
timer overflow occurs (0xFFFF to 0x0000), capture timer stops counting, CPTStart is cleared (“0”) automatically, and
the T1IRQ sets as “1”. The capture timer 16-bit counter value (CPTCH, CPTCL = “n”) is the continuous signal’s counts.
8.6.5.2High Pulse Width Measurement
T1ENB = 1. CPTEN = 1. CPTG[1:0] = 01.
Input Signal
T1 16-bit Counter
(T1CH, T1CL)
Un-know Data 0x????
0x0000
Initialization
1
2
n-1
n
0x0000
Initialization
1
T1 is counting.
CPTStart = 1
Rising Edge
T1 starts to count.
Falling Edge
T1 stops counting.
CPTStart = 0
“n” is the high pulse width period.
Read it by program through T1CH, T1CL
registers.
The high pulse width measurement is using rising edge to trigger T1 timer counting and falling edge to stop T1 timer. If
set CPTStart bit at high pulse duration, the capture timer will measure next high pulse until the rising edge occurrence.
When the end of measuring high pulse width and T1 timer stops, the T1IRQ sets as “1”, the T1 interrupt executes as
T1IEN=1, and T1CH, T1CL 16-bit counter stores the period of high pulse width.
8.6.5.3Low Pulse Width Measurement
T1ENB = 1. CPTEN = 1. CPTG[1:0] = 10.
Input Signal
T1 16-bit Counter
(T1CH, T1CL)
Un-know Data 0x????
0x0000
Initialization
1
2
n-1
n
0x0000
Initialization
1
T1 is counting.
CPTStart = 1
Falling Edge
T1 starts to count.
Rising Edge
T1 stops counting.
CPTStart = 0
“n” is the low pulse width period.
Read it by program through T1CH, T1CL
registers.
The low pulse width measurement is using falling edge to start T1 timer counting and rising edge to stop T1 timer. If set
CPTStart bit at low pulse duration, the capture timer will measure next low pulse until the falling edge occurrence.
When the end of measuring low pulse width and T1 timer stops, the T1IRQ sets as “1”, the T1 interrupt executes as
T1IEN=1, and T1CH, T1CL 16-bit counter stores the period of low pulse width.
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8.6.5.4Input Cycle Measurement
T1ENB = 1. CPTEN = 1. CPTG[1:0] = 11.
Input Signal
T1 16-bit Counter
(T1CH, T1CL)
Un-know Data 0x????
0x0000
Initialization
1
2
n-1
0x0000
Initialization
n
1
T1 is counting.
CPTStart = 1
Rising Edge
T1 starts to count.
Rising Edge
T1 stops counting.
CPTStart = 0
“n” is the cycle of input signal.
Read it by program through T1CH, T1CL
registers.
The cycle measurement is using rising edge to start and stop T1 timer. If set CPTStart bit at high or low pulse duration,
the capture timer will measure next cycle until the rising edge occurrence. When the end of measuring cycle and T1
timer stops, the T1IRQ sets as “1”, the T1 interrupt executes as T1IEN=1, and T1CH, T1CL 16-bit counter stores the
period of input cycle.
8.6.6 CAPTURE TIMER CONTROL REGISTERS
C3H
CPTM
Read/Write
After Reset
Bit 7
CPTEN
R/W
0
Bit 6
Bit 5
Bit 7
CPTEN: Capture timer function control bit.
0 = Disable.
1 = Enable. T1EN must be enabled.
Bit 3
CPTMD: Capture timer mode control bit.
0 = CPT overflow mode.
1 = T1 overflow mode.
Bit 2
CPTStart: Capture timer counter control bit.
0 = Process end.
1 = Start to count and processing.
Bit [1:0]
CPTG[1:0]: Capture timer function control bit.
00 = Capture timer function.
01 = High pulse width measurement.
10 = Low pulse width measurement.
11 = Cycle measurement.
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Page 119
Bit 3
CPTMD
R/W
0
Bit 2
CPTStart
R/W
0
Bit 1
CPTG1
R/W
0
Bit 0
CPTG0
R/W
0
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
C4H
CPTCL
Read/Write
After Reset
Bit 7
CPTC7
R/W
0
Bit 6
CPTC6
R/W
0
Bit 5
CPTC5
R/W
0
Bit 4
CPTC4
R/W
0
Bit 3
CPTC3
R/W
0
Bit 2
CPTC2
R/W
0
Bit 1
CPTC1
R/W
0
Bit 0
CPTC0
R/W
0
C5H
CPTCH
Read/Write
After Reset
Bit 7
CPTC15
R/W
0
Bit 6
CPTC14
R/W
0
Bit 5
CPTC13
R/W
0
Bit 4
CPTC12
R/W
0
Bit 3
CPTC11
R/W
0
Bit 2
CPTC10
R/W
0
Bit 1
CPTC9
R/W
0
Bit 0
CPTC8
R/W
0
The capture timer counter length is 16-bit and points to CPTCH and CPTCL registers. The timer counter is double
buffer design. The core bus is 8-bit, so access 16-bit data needs a latch flag to avoid the transient status affect the
16-bit data mistake occurrence. Under write mode, the write CPTCL is the latch control flag. Under read mode, the
read CPTCL is the latch control flag. So, write 16-bit counter is to write CPTCH first, and then write CPTCL. The 16-bit
data is written to 16-bit counter buffer after executing writing CPTCL. Read 16-bit counter is to read CPTCL first, and
then read CPTCH. The 16-bit data is dumped to CPTCH, CPTCL after executing reading CPTCL.
Read capture timer counter buffer sequence is to read CPTCL first, and then read CPTCH.
Write capture timer counter buffer sequence is to write CPTCH first, and then write CPTCL.
8.6.7 T1 TIMER OPERATION EXPLAME
T1 TIMER CONFIGURATION:
; Reset T1 timer.
MOV
B0MOV
A, #0x00
T1M, A
; Clear T1M register.
; Set T1 clock rate.
MOV
B0MOV
A, #0nnn0000b
T1M, A
; T1rate[2:0] bits.
; Set T1CH, T1CL registers for T1 Interval time.
A, #value1
MOV
B0MOV
T1CH, A
A, #value2
MOV
B0MOV
T1CL, A
; Set high byte first.
; Set low byte.
; Clear T1IRQ
B0BCLR
FT1IRQ
; Enable T1 timer and interrupt function.
B0BSET
FT1IEN
B0BSET
FT1ENB
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; Enable T1 interrupt function.
; Enable T1 timer.
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Version 2.1
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T1 CAPTURE TIMER FOR CONTINUOUS SIGNAL MEASUREMENT CONFIGURATION:
; Reset T1 timer.
CLR
T1M
; Clear T1M register.
; Set T1 clock rate and select/enable T1 capture timer.
A, #0nnnm000b
MOV
; “nnn” is T1rate[2:0] for T1 clock rate selection.
B0MOV
T1M, A
; “m” is T1 clock source control bit.
A, #000000mmb
MOV
; “mm” is CPTG[1:0] for T1 capture timer function selection.
B0MOV
CPTM, A
; CPTG[1:0] = 00b, enable T1 capture timer.
; CPTG[1:0] = 01b/10b/11b, enable pulse width or cycle
measurement.
; Select capture timer high-speed/low-speed mode.
B0BCLR
FCPTMD
; or
B0BSET
FCPTMD
; Clear T1CH, T1CL.
CLR
CLR
T1CH
T1CL
; CPT overflow mode.
; T1 overflow mode.
; Clear high byte first.
; Clear low byte.
; Set CPTCH, CPTCL 16-bit capture timer for continuous signal measurement.
A, #value1
MOV
; Set high nibble first.
B0MOV
CPTCH, A
A, #value2
MOV
; Set low byte.
B0MOV
CPTCL, A
; Clear T1IRQ
B0BCLR
FT1IRQ
; Enable T1 timer, interrupt function and T1 capture timer function.
B0BSET
FT1IEN
; Enable T1 interrupt function.
B0BSET
FT1ENB
; Enable T1 timer.
B0BSET
FCPTEN
; Enable T1 capture function.
; Set capture timer start bit.
B0BSET
FCPTStart
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T1 CAPTURE TIMER FOR SINGLE CYCLE MEASUREMENT CONFIGURATION:
; Reset T1 timer.
MOV
B0MOV
A, #0x00
T1M, A
; Clear T1M register.
; Set T1 clock rate, select input source, and select/enable T1 capture timer.
A, #0nnnm000b
MOV
; “nnn” is T1rate[2:0] for T1 clock rate selection.
B0MOV
T1M, A
; “m” is T1 clock source control bit.
A, #000000mmb
MOV
; “mm” is CPTG[1:0] for T1 capture timer function selection.
B0MOV
CPTM, A
; CPTG[1:0] = 00b, capture timer function.
; CPTG[1:0] = 01b, high pulse width measurement.
; CPTG[1:0] = 10b, low pulse width measurement.
; CPTG[1:0] = 11b, cycle measurement.
; Clear T1CH, T1CL.
CLR
CLR
T1CH
T1CL
; Clear high byte first.
; Clear low byte.
; Clear T1IRQ
B0BCLR
FT1IRQ
; Enable T1 timer, interrupt function and T1 capture timer function.
B0BSET
FT1IEN
; Enable T1 interrupt function.
B0BSET
FT1ENB
; Enable T1 timer.
B0BSET
FCPTEN
; Enable T1 capture function.
; Set capture timer start bit.
B0BSET
FCPTStart
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9 12 CHANNEL ANALOG TO DIGITAL
CONVERTER (ADC)
9.1 OVERVIEW
The analog to digital converter (ADC) is SAR structure with 12-input sources and up to 1024-step resolution to transfer
analog signal into 10-bits digital buffers. The ADC builds in 12-channel input source (AIN0~AIN11) to measure 12
different analog signal sources controlled by CHS[3:0] and GCHS bits. The ADC resolution can be selected 8-bit and
10-bit resolutions through ADLEN bit. The ADC converting rate can be selected by ADCKS[1:0] bits to decide ADC
converting time. The ADC reference high voltage is AVREFH pin. It is necessary to set P4, P5 as input mode without
pull-up resistor by program. After setup ADENB and ADS bits, the ADC starts to convert analog signal to digital data.
When the conversion is complete, the ADC circuit will set EOC and ADCIRQ bits to “1” and the digital data outputs in
ADB and ADR registers. If the ADCIEN = 1, the ADC interrupt request occurs and executes interrupt service routine
when ADCIRQ = 1 after ADC converting. If ADC interrupt function is enabled (ADCIEN=1), the system will execute
interrupt procedure. The interrupt procedure is system program counter points to interrupt vector (ORG 0010H) and
executes interrupt service routine after finishing ADC converting. Clear ADCIRQ by program is necessary in interrupt
procedure.
AVREFH
P4.0
P4.1
P4.2
ADCKS[1:0]
P4.3
P4.4
ADLEN
P4CON
P5CON CHS[3:0]
P4.5
ADC High
Reference
Voltage
ADC
Clock
Counter
GCHS
SAR ADC
Analog ENGINE
P4.6
Input
ADC
Offset
Calibration
P4.7
P5.0
ADENB ADS
8/10
ADB[9:0]
EOC
ADCIRQ
ADT[4:0],
ADTS[1:0]
P5.1
P5.2
P5.3
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9.2 ADC MODE REGISTER
ADM is ADC mode control register to configure ADC configurations including ADC start, ADC channel selection, ADC
high reference voltage source and ADC processing indicator…These configurations must be setup completely before
starting ADC converting.
0C8H
ADM
Read/Write
After reset
Bit 7
ADENB
R/W
0
Bit 6
ADS
R/W
0
Bit 5
EOC
R/W
0
Bit 4
GCHS
R/W
0
Bit 3
CHS3
R/W
0
Bit 2
CHS2
R/W
0
Bit 1
CHS1
R/W
0
Bit 7
ADENB: ADC control bit. In power saving mode, disable ADC to reduce power consumption.
0 = Disable ADC function.
1 = Enable ADC function.
Bit 6
ADS: ADC start control bit. ADS bit is cleared after ADC processing automatically.
0 = ADC converting stops.
1 = Start to execute ADC converting.
Bit 5
EOC: ADC status bit. EOC bit must be cleared by program before ADC start.
0 = ADC progressing.
1 = End of converting and reset ADS bit.
Bit 4
GCHS: ADC global channel select bit.
0 = Disable AIN channel.
1 = Enable AIN channel.
Bit [3:0]
CHS[3:0]: ADC input channel select bit.
0000 = AIN0, 0001 = AIN1, 0010 = AIN2, 0011 = AIN3, 0100 = AIN4, 0101 = AIN5, 0110 = AIN6,
0111 = AIN7, 1000 = AIN8, 1001 = AIN9, 1010 = AIN10, 1011 = AIN11, 1100 ~ 1111= Reserved.
Bit 0
CHS0
R/W
0
ADR register includes ADC mode control and ADC low-nibble data buffer. ADC configurations including ADC clock rate
and ADC resolution. These configurations must be setup completely before starting ADC converting.
0CAH
ADR
Read/Write
After reset
Bit 7
-
Bit 6
ADCKS1
R/W
0
Bit 5
ADLEN
R/W
0
Bit 4
ADCKS0
R/W
0
Bit 6,4
ADCKS [1:0]: ADC’s clock rate select bit.
00 = Fcpu/16, 01 = Fcpu/8, 10 = Fcpu/1, 11 = Fcpu/2
Bit 5
ADLEN: ADC’s resolution select bits.
0 = 8-bit.
1 = 10-bit.
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Bit 3
-
Bit 2
-
Bit 1
ADB1
R
-
Bit 0
ADB0
R
-
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
9.3 ADC DATA BUFFER REGISTERS
ADC data buffer is 10-bit length to store ADC converter result. The high byte is ADB register, and the low-nibble is
ADR[1:0] bits. The ADB register is only 8-bit register including bit2~bit9 ADC data. To combine ADB register and the
low-nibble of ADR will get full 10-bit ADC data buffer. The ADC data buffer is a read-only register and the initial status
is unknown after system reset.
ADB[9:2]: In 8-bit ADC mode, the ADC data is stored in ADB register.
ADB[9:0]: In 10-bit ADC mode, the ADC data is stored in ADB and ADR registers.
0C9H
ADB
Read/Write
After reset
Bit[7:0]
Bit 6
ADB8
R
-
Bit 5
ADB7
R
-
Bit 4
ADB6
R
-
Bit 3
ADB5
R
-
Bit 2
ADB4
R
-
Bit 1
ADB3
R
-
Bit 0
ADB2
R
-
Bit 1
ADB1
R
-
Bit 0
ADB0
R
-
ADB[7:0]: 8-bit ADC data buffer and the high-byte data buffer of 10-bit ADC.
0CAH
ADR
Read/Write
After reset
Bit [3:0]
Bit 7
ADB9
R
-
Bit 7
-
Bit 6
ADCKS1
R/W
0
Bit 5
ADLEN
R/W
0
Bit 4
ADCKS0
R/W
0
Bit 3
Bit 2
ADB [3:0]: 12-bit low-nibble ADC data buffer.
The AIN input voltage v.s. ADB output data
AIN n
0/1024*VREFH
1/1024*VREFH
.
.
.
1022/1024*VREFH
1023/1024*VREFH
ADB9
0
0
.
.
.
1
1
ADB8
0
0
.
.
.
1
1
ADB7
0
0
.
.
.
1
1
ADB6
0
0
.
.
.
1
1
ADB5
0
0
.
.
.
1
1
ADB4
0
0
.
.
.
1
1
ADB3
0
0
.
.
.
1
1
ADB2
0
0
.
.
.
1
1
ADB1
0
0
.
.
.
1
1
ADB0
0
1
.
.
.
0
1
For different applications, users maybe need more than 8-bit resolution but less than 10-bit. To process the ADB and
ADR data can make the job well. First, the ADC resolution must be set 10-bit mode and then to execute ADC converter
routine. Then delete the LSB of ADC data and get the new resolution result. The table is as following.
ADC Resolution
8-bit
9-bit
10-bit
ADB9
O
O
O
ADB8
O
O
O
ADB7
O
O
O
ADB
ADB6
ADB5
O
O
O
O
O
O
ADB4
O
O
O
ADB3
O
O
O
ADB2
O
O
O
ADR
ADB1
ADB0
x
x
O
x
O
O
Note: The initial status of ADC data buffer including ADB register and ADR low-nibble after the system
reset is unknown.
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9.4 ADC OPERATION DESCRIPTION AND NOTIC
9.4.1 ADC SIGNAL FORMAT
ADC sampling voltage range is limited by high/low reference voltage. The ADC low reference voltage is Vss and not
changeable. The ADC high reference voltage is AVREFH pin. ADC reference voltage range limitation is “(ADC high
reference voltage – low reference voltage) ≧ 2V”. ADC low reference voltage is Vss = 0V. So ADC high
reference voltage range is 2V~Vdd. The range is ADC external high reference voltage range.
ADC Internal Low Reference Voltage = 0V.
ADC External High Reference Voltage = 2V~Vdd.
ADC sampled input signal voltage must be from ADC low reference voltage to ADC high reference. If the ADC input
signal voltage is over the range, the ADC converting result is error (full scale or zero).
ADC Low Reference Voltage ≦ ADC Sampled Input Voltage ≦ ADC High Reference Voltage
9.4.2 ADC CONVERTING TIME
The ADC converting time is from ADS=1 (Start to ADC convert) to EOC=1 (End of ADC convert). The converting time
duration is depend on ADC resolution and ADC clock rate. 10-bit ADC’s converting time is 1/(ADC clock /4)*14 sec,
and the 8-bit ADC converting time is 1/(ADC clock /4)*12 sec. ADC clock source is Fcpu and includes Fcpu/1, Fcpu/2,
Fcpu/8 and Fcpu/16 controlled by ADCKS[1:0] bits.
The ADC converting time affects ADC performance. If input high rate analog signal, it is necessary to select a high
ADC converting rate. If the ADC converting time is slower than analog signal variation rate, the ADC result would be
error. So to select a correct ADC clock rate and ADC resolution to decide a right ADC converting rate is very important.
10-bit ADC conversion time = 1/(ADC clock rate/4)*14 sec
ADLEN
ADCKS1, ADC Clock
ADCKS0
Rate
00
Fcpu/16
01
Fcpu/8
10
Fcpu
11
Fcpu/2
1 (10-bit)
Fcpu=4MHz
ADC Converting
ADC Converting
time
Rate
1/(4MHz/16/4)*14
4.464KHz
= 224 us
1/(4MHz/8/4)*14
8.929KHz
= 112 us
1/(4MHz/4)*14
71.43KHz
= 14 us
1/(4MHz/2/4)*14
35.71KHz
= 28 us
Fcpu=16MHz
ADC Converting
ADC Converting
time
Rate
1/(16MHz/16/4)*14
17.857KHz
= 56 us
1/(16MHz/8/4)*14
35.71KHz
= 28 us
1/(16MHz/4)*14
286KHz
= 3.5 us
1/(16MHz/2/4)*14
143KHz
= 7 us
8-bit ADC conversion time = 1/(ADC clock rate/4)*12 sec
ADLEN
ADCKS1, ADC Clock
ADCKS0
Rate
00
Fcpu/16
01
Fcpu/8
10
Fcpu
11
Fcpu/2
0 (8-bit)
Fcpu=4MHz
ADC Converting
ADC Converting
time
Rate
1/(4MHz/16/4)*12
5.208KHz
= 192 us
1/(4MHz/8/4)*12
10.416KHz
= 96 us
1/(4MHz/4)*12
83.333KHz
= 12 us
1/(4MHz/2/4)*12
41.667KHz
= 24 us
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Fcpu=16MHz
ADC Converting
ADC Converting
time
Rate
1/(16MHz/16/4)*12
20.833KHz
= 48 us
1/(16MHz/8/4)*12
41.667KHz
= 24 us
1/(16MHz/4)*12
333.333KHz
= 3 us
1/(16MHz/2/4)*12
166.667KHz
= 6 us
Version 2.1
SN8F27E60 Series
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9.4.3 ADC PIN CONFIGURATION
ADC input channels are shared with Port4 and Port5. ADC channel selection is through ADCHS[3:0] bit. ADCHS[3:0]
value points to the ADC input channel directly. ADCHS[3:0]=0000 selects AIN0. ADCHS[3:0]=0001 selects
AIN1……Only one pin of Port4 and Port5 can be configured as ADC input in the same time. The pins of Port4 and
Port5 configured as ADC input channel must be set input mode, disable internal pull-up and enable P4CON and
P5CON first by program. After selecting ADC input channel through ADCHS[3:0], set GCHS bit as “1” to enable ADC
channel function.
The GPIO mode of ADC input channels must be set as input mode.
The internal pull-up resistor of ADC input channels must be disabled.
P4CON and P5CON bits of ADC input channel must be set.
ADC input pins are shared with digital I/O pins. Connect an analog signal to COMS digital input pin, especially, the
analog signal level is about 1/2 VDD will cause extra current leakage. In the power down mode, the above leakage
current will be a big problem. Unfortunately, if users connect more than one analog input signal to Port4 or Port5 will
encounter above current leakage situation. P4CON/P5CON is Port4/Port5 configuration register. Write “1” into P4CON
[7:0] and P5CON [3:0] will configure related Port4/Port5 pin will be set as input mode and disable pull-up resistor.
0C6H
P4CON
Read/Write
After reset
Bit[7:0]
Bit 6
P4CON6
R/W
0
Bit 5
P4CON5
R/W
0
Bit 4
P4CON4
R/W
0
Bit 3
P4CON3
R/W
0
Bit 2
P4CON2
R/W
0
Bit 1
P4CON1
R/W
0
Bit 0
P4CON0
R/W
0
Bit 2
P5CON2
R/W
0
Bit 1
P5CON1
R/W
0
Bit 0
P5CON0
R/W
0
P4CON[7:0]: P4.n configuration control bits.
0 = P4.n can be a digital I/O pin.
1 = P4.n will be set as input mode and disable pull-up resistor.
0C7H
P5CON
Read/Write
After reset
Bit[3:0]
Bit 7
P4CON7
R/W
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
P5CON3
R/W
0
P5CON[3:0]: P5.n configuration control bits.
0 = P5.n can be a digital I/O pin.
1 = P5.n will be set as input mode and disable pull-up resistor.
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9.4.4 ADC OPERATION EXAMLPE
ADC CONFIGURATION:
; Reset ADC.
CLR
ADM
; Set ADC clock rate and ADC resolution.
A, #0nmn0000b
MOV
B0MOV
ADR, A
; Set ADC input channel configuration.
A, #value1
MOV
B0MOV
P4CON, A
A, #value2
MOV
B0MOV
P4M, A
A, #value3
MOV
B0MOV
P4UR, A
; Clear TC0M register.
; nn: ADCKS[1:0] for ADC clock rate.
; m: ADLEN for ADC reolution.
; Set P4CON for ADC input channel.
; Set ADC input channel as input mode.
; Disable ADC input channel’s internal pull-up resistor.
; Enable ADC.
B0BSET
FADENB
; Execute ADC 100us warm-up time delay loop.
CALL
100usDLY
; Select ADC input channel.
MOV
OR
A, #value
ADM, A
; Enable ADC input channel.
B0BSET
FGCHS
; Enable ADC interrupt function.
B0BCLR
FADCIRQ
B0BSET
FADCIEN
; 100us delay loop.
; Set ADCHS[3:0] for ADC input channel selection.
; Clear ADC interrupt flag.
; Enable ADC interrupt function.
; Start to execute ADC converting.
B0BSET
FADS
Note:
1. When ADENB is enabled, the system must be delay 100us to be the ADC warm-up time by program,
and then set ADS to do ADC converting. The 100us delay time is necessary after ADENB setting (not
ADS setting), or the ADC converting result would be error. Normally, the ADENB is set one time when
the system under normal run condition, and do the delay time only one time.
2. In power saving situation like power down mode and green mode, and not using ADC function, to
disable ADC by program is necessary to reduce power consumption.
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ADC CONVERTING OPERATION:
; ADC Interrupt disable mode.
@@:
B0BTS1
JMP
B0MOV
B0MOV
MOV
AND
B0MOV
…
CLR
FEOC
@B
A, ADB
BUF1,A
A, #00000011b
A, ADR
BUF2,A
FEOC
; ADC Interrupt enable mode.
ORG 8
INT_SR:
B0BTS1
JMP
B0MOV
B0MOV
MOV
AND
B0MOV
…
CLR
JMP
; Check ADC processing flag.
; EOC=0: ADC is processing.
; EOC=1: End of ADC processing. Process ADC result.
; End of processing ADC result.
; Clear ADC processing flag for next ADC converting.
; Interrupt vector.
; Interrupt service routine.
FADCIRQ
EXIT_INT
A, ADB
BUF1,A
A, #00000011b
A, ADR
BUF2,A
FEOC
INT_EXIT
; Check ADC interrupt flag.
; ADCIRQ=0: Not ADC interrupt request.
; ADCIRQ=1: End of ADC processing. Process ADC result.
; End of processing ADC result.
; Clear ADC processing flag for next ADC converting.
INT_EXIT:
RETI
; Exit interrupt service routine.
Note: ADS is cleared when the end of ADC converting automatically. EOC bit indicates ADC processing
status immediately and is cleared when ADS = 1. Users needn’t to clear it by program.
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9.5 ADC APPLICATION CIRCUIT
External High
Reference Voltage
C
B
AVREFH
47uF
0.1uF
MCU
Analog Signal Input
AINn/P4.n
0.1uF
VSS
A
VCC
Main Power Trunk
GND
The analog signal is inputted to ADC input pin “AINn/P4.n”. The ADC input signal must be through a 0.1uF capacitor
“A”. The 0.1uF capacitor is set between ADC input pin and VSS pin, and must be on the side of the ADC input pin as
possible. Don’t connect the capacitor’s ground pin to ground plain directly, and must be through VSS pin. The capacitor
can reduce the power noise effective coupled with the analog signal.
The external high reference source (AVREFH) must be through a 47uF ”C” capacitor first, and then 0.1uF capacitor “B”.
These capacitors are set between AVREFH pin and VSS pin, and must be on the side of the AVREFH pin as possible.
Don’t connect the capacitor’s ground pin to ground plain directly, and must be through VSS pin.
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10 Universal Asynchronous
Receiver/Transmitter (UART)
10.1 OVERVIEW
The UART interface is an universal asynchronous receiver/transmitter method. The serial interface is applied to low
speed data transfer and communicate with low speed peripheral devices. The UART transceiver of Sonix 8-bit MCU
allows RS232 standard and supports one byte data length. The transfer format has start bit, 8-bit data, parity bit and
stop bit. Programmable baud rate supports different speed peripheral devices. UART I/O pins support push-pull and
open-drain structures controlled by register.
The UART features include the following:
Full-duplex, 2-wire asynchronous data transfer.
Programmable baud rate.
8-bit data length.
Odd and even parity bit.
End-of-Transfer interrupt.
Support DMX512 protocol.
Support break pocket function.
Support wide range baud rate.
URXPS URXPEN
URXM
CPUM1,0
URXPC
URRXD1 8-bit Buffer
Parity
URX
Check
URXEN
URRXD2 8-bit Buffer
URXEN
UART Baud Rate
Fhosc
Control Block
URXS1,0 and RX interrupt
UART I/O Counter
TX interrupt
(Pre-scaler and Divider)
UTXEN
UTXPS UTXPEN
UTXM
UTXEN
UTXPC
URTXD1 8-bit Buffer
Parity
UTX
Check
CPUM1,0
URTXD2 8-bit Buffer
UART Interface Structure Diagram
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10.2 UART OPERATION
The UART RX and TX pins are shared with GPIO. When UART enables (URXEN=1, UTXEN=1), the UART shared
pins transfers to UART purpose and disable GPIO function automatically. When UART disables, the UART pins returns
to GPIO last status. The UART data buffer length supports 1-byte.
The UART supports interrupt function. URXIEN/UTXIEN are UART transfer interrupt function control bit. URXIEN=0,
disable UART receiver interrupt function. UTXIEN=0, disable UART transmitter interrupt function. URXIEN=1, enable
UART receiver interrupt function. UTXIEN=1, enable UART transmitter interrupt function. When UART interrupt
function enable, the program counter points to interrupt vector (ORG 0013H/0014H) to do UART interrupt service
routine after UART operating. URXIRQ/UTXIRQ is UART interrupt request flag, and also to be the UART operating
status indicator when URXIEN=0 or UTXIEN=0, but cleared by program. When UART operation finished, the
URXIRQ/UTXIRQ would be set to “1”.
The UART also builds in “Busy Bit” to indicate UART bus status. URXBZ bit is UART RX operation indicator. UTXBZ bit
is UART TX operation indicator. If bus is transmitting, the busy bit is “1” status. If bus is finishing operation or in idle
status, the busy bit is “0” status.
UART TX operation is controlled by loading UTXD data buffer. After UART TX configuration, load transmitted data into
UTXD 8-bit buffer, and then UART starts to transmit the pocket following UART TX configuration.
UART RX operation is controlled by receiving the start bit from master terminal. After UART RX configuration, URX pin
detects the falling edge of start bit, and then UART starts to receive the pocket from master terminal.
UART provides URXPC bit and UFMER bit to check received pocket. URXPC bit is received parity bit checker. If
received parity is error, URXPC sets as “1”. If URXPC bit is zero after receiving pocket, the parity is correct. UFMER bit
is received stream frame checker. The stream frame error definition includes “Start bit error”, “Stop bit error”, “Stream
length error”, “UART baud rate error”... Each of frame error conditions makes UFMER bit sets as “1” after receiving
pocket.
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10.3 UART BAUD RATE
UART clock is 2-stage structure including a pre-scaler and an 8-bit buffer. UART clock source is generated from
system oscillator called Fhosc. Fhosc passes through UART pre-scaler to get UART main clock called Fuart. UART
pre-scaler has 8 selections (Fhosc/1, Fhosc/2, Fhosc/4, Fhosc/8, Fhosc/16, Fhosc/32, Fhosc/64, Fhosc/128) and 3-bit
control bits (URS[2:0]). UART main clock (Fuart) purposes are the front-end clock and through UART 8-bit buffer
(URCR) to obtain UART processing clock and decide UART baud rate.
UART Pre-scaler
Selection,
URS[2:0]
000b
001b
010b
011b
100b
101b
110b
111b
0E6H
URCR
Read/Write
After reset
Bit 7
URCR7
R/W
0
Bit 6
URCR6
R/W
0
UART Main
Clock Rate
Fuart
(Fhosc=16MHz)
Fhosc/1
Fhosc/2
Fhosc/4
Fhosc/8
Fhosc/16
Fhosc/32
Fhosc/64
Fhosc/128
16MHz
8MHz
4MHz
2MHz
1MHz
0.5MHz
0.25MHz
0.125MHz
Bit 5
URCR5
R/W
0
Bit 4
URCR4
R/W
0
Bit 3
URCR3
R/W
0
Bit 2
URCR2
R/W
0
Bit 1
URCR1
R/W
0
Bit 0
URCR0
R/W
0
The UART baud rate clock source is Fhosc and divided by pre-scalar. The equation is as following.
UART Baud Rate = 1/2 *(Fuart * 1/(256 - URCR))…bps
Fhosc = 16MHz
Baud Rate
UART Pre-scaler
URS[2:0]
URCR (Hex)
1200
2400
4800
9600
19200
38400
51200
57600
102400
115200
128000
250000
Fhosc/32
Fhosc/32
Fhosc/32
Fhosc/32
Fhosc/32
Fhosc/1
Fhosc/1
Fhosc/1
Fhosc/1
Fhosc/1
Fhosc/1
Fhosc/1
101b
101b
101b
101b
101b
000b
000b
000b
000b
000b
000b
000b
30
98
CC
E6
F3
30
64
75
B2
BB
C1
E0
Accuracy
(%)
-0.16%
-0.16%
-0.16%
-0.16%
-0.16%
-0.16%
-0.16%
0.08%
-0.16%
-0.64%
0.80%
0.00%
Note:
1. We strongly recommend not to set URCR = 0xFF, or UART operation would be error.
2. If Noise_Filter code option is “Enable”, we strongly recommend to set Fcpu as Fhosc/2~Fhosc/16, or
UART operation would be error. If Noise_Filter code option is “Disable”, the limitation doesn’t exist.
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10.4 UART TRANSFER FORMAT
The UART transfer format includes “Bus idle status”, “Start bit”, “8-bit Data”, “Parity bit” and “Stop bit” as following.
Start
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
P
Stop
UART Transfer Format with Parity Bit
Start
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Stop
UART Transfer Format without Parity Bit
Bus Idle Status: The bus idle status is the bus non-operating status. The UART receiver bus idle status of MCU is
floating status and tied high by the transmitter device terminal. The UART transmitter bus idle status of MCU is high
status. The UART bus will be set when URXEN and UTXEN are enabled.
Start Bit: UART is a asynchronous type of communication and need a attention bit to offer receiver the transfer starting.
The start bit is a simple format which is high to low edge change and the duration is one bit period. The start bit is
easily recognized by the receiver.
8-bit Data: The data format is 8-bit length, and LSB transfers first following start bit. The one bit data duration is the
unit of UART baud rate controlled by register.
Parity Bit: The parity bit purpose is to detect data error condition. It is an extra bit following the data stream. The parity
bit includes odd and even check methods controlled by URXPS/UTXPS bits. After receiving data and parity bit, the
parity check executes automatically. The URXPC bit indicates the parity check result. The parity bit function is
controlled by URXPEN/UTXPEN bits. If the parity bit function is disabled, the UART transfer contents remove the parity
bit and the stop bit follows the data stream directly.
Stop Bit: The stop bit is like start bit using a simple format to indicate the end of UART transfer. The stop bit format is
low to high edge change and the duration is one bit period.
10.5 BREAK POCKET
The break pocket is an empty stream to reset UART bus. Break pocket is like a long time zero pocket, and the period is
88us~1s.
88us ~ 1s
Break
TX Break Pocket: UART builds in a UTXBRK bit to transmit Break pocket. When UTXEN = 1 (enable UART TX
function), set UTXBRK bit to transmit Break pocket. When Break pocket finishes transmitting, UTXIRQ is set as “1”,
and UTXBRK is cleared automatically. The period of transmitted break pocket is 25 UART baud rate clocks. If YART
baud rate is 250000bps, the break pocket period is 100us.
UART TX Break Pocket Period = 25/UART Baud Rate…sec
RX Break Pocket:
UART receives break pocket will get a frame error signal because the data period is longer than typical UART duration.
UART can’t receive a complete data pocket. After receiving a UART pocket, the break pocket is still output low. UART
issues frame error flag (UFMER = 1) and URXIRQ. Maybe the parity bit is error in parity mode. UART changes to initial
status until detecting next start bit.
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10.6 ABNORMAL POCKET
The abnormal pocket occurs in UART RX mode. Break pocket is one abnormal pocket of the UART architecture. The
abnormal pocket includes Stream period error, start bit error, stop bit error…When UART receives abnormal pocket,
the UFMER bit will be set “1”, and UART issues URXIRQ. The system finds the abnormal pocket through firmware.
UART changes to initial status until detecting next start bit.
Start bit is error.
URX Pin
bit0
Start
bit1
bit2
bit3
bit4
bit5
bit6
bit7
P
Stop
UART check the start bit is error and issue UFMER flag, but the UART still finishes receiving the pocket.
Start bit is error.
URX Pin
bit0
Start
bit1
bit2
bit3
bit4
bit5
bit6
bit7
P
Stop
UART check the stop bit is error and issue UFMER flag, but the UART still finishes receiving the pocket.
URX Pin
UART RX
Processor
bit0
Start
Start
b
0
b
1
b
2
b
3
bit1
b
4
b
5
b
6
bit2
b
7
p
bit3
bit4
bit5
bit6
Stop
If the host’s UART baud rate isn’t match to receiver terminal, the received pocket is error. But it is not easy to
differentiate the pocket is correct or not, because the received error pocket maybe match UART rule, but the data is
error. Use checking UFMER bit and URXPC bit status to decide the stream. If the two conditions seem like correct, but
the pocket is abnormal, UART will accept the pocket as correct one.
10.7 UART RECEIVER CONTROL REGISTER
0E5H
URRX
Read/Write
After reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit [2:0]
Bit 7
URXEN
R/W
0
Bit 6
URXPEN
R/W
0
Bit 5
URXPS
R/W
0
Bit 4
URXPC
R/W
0
Bit 3
UFMER
R/W
0
Bit 2
URS2
R/W
0
Bit 1
URS1
R/W
0
Bit 0
URS0
R/W
0
URXEN: UART RX control bit.
0 = Disable UART RX. URX pin is GPIO mode or returns to GPIO status.
1 = Enable UART RX. URX pin exchanges from GPIO mode to UART RX mode.
URXPEN: UART RX parity bit control bit.
0 = Disable UART RX parity bit function. The data stream doesn’t include parity bit.
1 = Enable UART RX parity bit function. The data stream includes parity bit.
UTXPS: UART RX parity bit format control bit.
0 = UART RX parity bit format is even parity.
1 = UART RX parity bit format is odd parity.
URXPC: UART RX parity bit checking flag.
0 = Parity bit is correct or no parity function.
1 = Parity bit is error.
UFMER: UART RX stream frame error flag bit.
0 = Collect UART frame.
1 = UART frame is error including start/stop bit, stream length.
URS[2:0]: UART per-scalar select bit.
000 = Fhosc/1, 001 = Fhosc/2, 010 = Fhosc/4, 011 = Fhosc/8, 100 = Fhosc/16, 101 = Fhosc/32,
110 = Fhosc/64, 111 = Fhosc/128.
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10.8 UART TRANSMITTER CONTROL REGISTER
0E4H
URTX
Read/Write
After reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 7
UTXEN
R/W
0
Bit 6
UTXPEN
R/W
0
Bit 5
UTXPS
R/W
0
Bit 4
UTXBRK
R/W
0
Bit 3
URXBZ
R
0
Bit 2
UTXBZ
R
0
Bit 1
-
Bit 0
-
UTXEN: UART TX control bit.
0 = Disable UART TX. UTX pin is GPIO mode or returns to GPIO status.
1 = Enable UART TX. UTX pin exchanges from GPIO mode to UART TX mode and idle high status.
UTXPEN: UART TX parity bit control bit.
0 = Disable UART TX parity bit function. The data stream doesn’t include parity bit.
1 = Enable UART TX parity bit function. The data stream includes parity bit.
UTXPS: UART TX parity bit format control bit.
0 = UART TX parity bit format is even parity.
1 = UART TX parity bit format is odd parity.
UTXBRK: UART TX BREAK pocket control bit.
0 = End of transmitting UART BREAK pocket.
1 = Start to transmit UART BREAK pocket.
URXBZ: UART RX operating status flag.
0 = UART RX is idle or the end of processing.
1 = UART RX is busy and processing.
UTXBZ: UART TX operating status flag.
0 = UART TX is idle or the end of processing.
1 = UART TX is busy and processing.
Note: URXBZ and UTXBZ bits are UART operating indicators. After setting UART RX/TX operations, set
(2*Fcpu/Fuart)*NOP instruction is necessary, and then check UART status through URXBZ and UTXBZ
bits.
10.9 UART DATA BUFFER
0E7H
Bit 7
Bit 6
Bit 5
UTXD
UTXD7
UTXD6
UTXD5
Read/Write
R/W
R/W
R/W
After Reset
0
0
0
Bit [7:0] UTXD: UART transmitted data buffer.
Bit 4
UTXD4
R/W
0
Bit 3
UTXD3
R/W
0
Bit 2
UTXD2
R/W
0
Bit 1
UTXD1
R/W
0
Bit 0
UTXD0
R/W
0
0E8H
Bit 7
Bit 6
Bit 5
URXD
UTXD27
UTXD26
UTXD25
Read/Write
R/W
R/W
R/W
After Reset
0
0
0
Bit [7:0] URXD: UART received data buffer.
Bit 4
UTXD24
R/W
0
Bit 3
UTXD23
R/W
0
Bit 2
UTXD22
R/W
0
Bit 1
UTXD21
R/W
0
Bit 0
UTXD20
R/W
0
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SN8F27E60 Series
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10.10 UART OPERATION EXAMLPE
UART TX Configuration:
; Select parity bit function.
B0BCLR
;or
B0BSET
FUTXPEN
; Disable UART TX parity bit function.
FUTXPEN
; Enable UART TX parity bit function.
FUTXPS
; UART TX parity bit format is even parity.
FUTXPS
; UART TX parity bit format is odd parity.
; Set UART baud rate.
MOV
B0MOV
MOV
B0MOV
A, #value1
URRX, A
A, #value2
URCR, A
; Set UART pre-scaler URS[2:0].
; Enable UART TX pin.
B0BSET
FUTXEN
; Enable UART TX function and UART TX pin.
; Select parity bit format.
B0BCLR
;or
B0BSET
; Enable UART TX interrupt function.
B0BCLR
FUTXIRQ
B0BSET
FUTXIEN
; Load TX data buffer and execute TX transmitter.
A, #value3
MOV
B0MOV
UTXD, A
; Clear UART TX interrupt flag.
; Enable UART TX interrupt function.
; Load 8-bit data to UTXD data buffer.
;After loading UTXD, UART TX starts to transmit.
; One instruction delay for UTXBZ flag.
NOP
; Check TX operation.
B0BTS0
JMP
JMP
; Set UART baud rate 8-bit buffer.
FUTXBZ
CHKTX
ENDTX
; Check UTXBZ bit.
; UTXBZ=1, TX is operating.
; UTXBZ=0, the end of TX.
Note: UART TX operation is started through loading UTXD data buffer.
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Transmit Break Pocket:
; Select parity bit function.
B0BCLR
;or
B0BSET
FUTXPEN
; Disable UART TX parity bit function.
FUTXPEN
; Enable UART TX parity bit function.
FUTXPS
; UART TX parity bit format is even parity.
FUTXPS
; UART TX parity bit format is odd parity.
; Set UART baud rate.
MOV
B0MOV
MOV
B0MOV
A, #value1
URRX, A
A, #value2
URCR, A
; Set UART pre-scaler URS[2:0].
; Enable UART TX pin.
B0BSET
FUTXEN
; Enable UART TX function and UART TX pin.
; Select parity bit format.
B0BCLR
;or
B0BSET
; Set UART baud rate 8-bit buffer.
; Enable UART TX interrupt function.
B0BCLR
FUTXIRQ
B0BSET
FUTXIEN
; Clear UART TX interrupt flag.
; Enable UART TX interrupt function.
; Start UART break pocket.
B0BSET
NOP
FUTXBRK
; Transmit UART break pocket.
; One instruction delay for UTXBZ flag.
FUTXBZ
CHKTX
ENDTX
; Check UTXBZ bit.
; UTXBZ=1, TX is operating.
; UTXBZ=0, the end of TX.
; Check TX operation.
B0BTS0
JMP
JMP
Note: UART TX break pocket is controlled by UTXBRK bit and needn’t load UTXD buffer.
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UART RX Configuration:
; Select parity bit function.
B0BCLR
;or
B0BSET
FURXPEN
; Disable UART RX parity bit function.
FURXPEN
; Enable UART RX parity bit function.
FURXPS
; UART RX parity bit format is even parity.
FURXPS
; UART RX parity bit format is odd parity.
; Set UART baud rate.
MOV
B0MOV
MOV
B0MOV
A, #value1
URRX, A
A, #value2
URCR, A
; Set UART pre-scaler URS[2:0].
; Enable UART RX pin.
B0BSET
FURXEN
; Enable UART RX function and UART RX pin.
; Select parity bit format.
B0BCLR
;or
B0BSET
; Set UART baud rate 8-bit buffer.
; Enable UART RX interrupt function.
B0BCLR
FURXIRQ
B0BSET
FURXIEN
NOP
; Clear UART RX interrupt flag.
; Enable UART RX interrupt function.
; One instruction delay for URXBZ flag.
; Check RX operation.
B0BTS0
JMP
JMP
; Check URXBZ bit.
; URXBZ=1, RX is operating.
; URXBZ=0, the end of RX.
FURXBZ
CHKRX
ENDRX
Note: UART RX operation is started as start bit transmitted from master terminal.
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11 SERIAL INPUT/OUTPUT TRANSCEIVER
(SIO)
11.1 OVERVIEW
The SIO (serial input/output) transceiver is a serial communicate interface for data exchanging from one MCU to one
MCU or other hardware peripherals. It is a simple 8-bit interface without a major definition of protocol, packet or control
bits. The SIO transceiver includes three pins, clock (SCK), data input (SI) and data output (SO) to send data between
master and slaver terminals. The SIO interface builds in 8-mode which are the clock idle status, the clock phases and
data fist bit direction. The 8-bit mode supports most of SIO/SPI communicate format.
The SIO features include the following:
Full-duplex, 3-wire synchronous data transfer.
Master (SCK is clock output) or Slave (SCK is clock input) operation.
MSB/LSB first data transfer.
st
nd
The start phase of data sampling location selection is 1 -phase or 2 -phase controlled register.
SCK, SI, SO are programmable open-drain output pin for multiple salve devices application.
Two programmable bit rates (Only in master mode).
End-of-Transfer interrupt.
11.2 SIO OPERATION
The SIOM register can control SIO operating function, such as: transmit/receive, clock rate, data transfer direction, SIO
clock idle status and clock control phase and starting this circuit. This SIO circuit will transmit or receive 8-bit data
automatically by setting SENB and START bits in SIOM register. The SIO data buffer is double buffer design. When
the SIO operating, the SIOB register stores transfer data and one internal buffer stores receive data. When SIO
operation is successfully, the internal buffer reloads into SIOB register automatically. The SIO 8-bit counter and SIOR
register are designed to generate SIO’s clock source with auto-reload function. The 3-bit I/O counter can monitor the
operation of SIO and announce an interrupt request after transmitting/ receiving 8-bit data. After transferring 8-bit data,
this circuit will be disabled automatically and re-transfer data by programming SIOM register. CPOL bit is designed to
control SIO clock idle status. CPHA bit is designed to control the clock edge direction of data receive. CPOL and CPHA
bits decide the SIO format. The SIO data transfer direction is controlled by MLSB bit to decide MSB first or LSB first.
SENB
MLSB
SI
8-bit Receive Buffer
SENB
MLSB
SO
SIOB 8-bit Buffer
SENB
SCLKMD
CPOL
CPHA
SCK
SIO 3-bit I/O Counter
SENB
SIO Time Out
SCSP
SCS
START
SCSEN,
SCLKMD=1
SENB
Fcpu
÷1
÷8
÷16
÷32
SIO 8-bit Counter
CPUM1,0
Srate1,0
Auto-Reload
SIOR Register
SIO Interface Structure Diagram
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The SIO supports 8-mode format controlled by MLSB, CPOL and CPHA bits. The edge direction is “Data Transfer
Edge”. When setting rising edge that means to receive and transmit one bit data at SCK rising edge, and data
transition is at SCK falling edge. When setting falling edge, that means to receive and transmit one bit data at SCK
falling edge, and data transition is at SCK rising edge.
“CPHA” is the clock phase bit controls the phase of the clock on which data is sampled. When CPHA=1, the SCK first
nd
st
edge is for data transition, and receive and transmit data is at SCK 2 edge. When CPHA=0, the 1 bit is fixed already,
and the SCK first edge is to receive and transmit data. The SIO data transfer timing as following figure:
M
L
S
B
0
C
P
O
L
0
C
P
H
A
Diagrams
1
0
1
0
1
0
1
1
0
1
bit4
bit3
bit2
bit1
bit0
SCK idle status = High.
The transfer first bit = MSB.
SCK data transfer edge = Rising
edge.
bit6
bit5
bit4
bit3
bit2
bit1
Bit7
SCK idle status = Low.
The transfer first bit = MSB.
SCK data transfer edge = Rising
edge.
SCK idle status = High.
The transfer first bit = MSB.
SCK data transfer edge = Falling
edge.
SCK idle status = Low.
The transfer first bit = LSB.
SCK data transfer edge = Falling
edge.
Bit7
SCK idle status = High.
The transfer first bit = LSB.
SCK data transfer edge = Rising
edge.
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Next data
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Next data
0
1
bit1
bit2
bit3
bit4
bit5
bit6
1
bit0
1
bit5
0
bit0
1
bit6
1
bit7
0
bit0
SCK idle status = Low.
The transfer first bit = MSB.
SCK data transfer edge = Falling
edge.
1
bit7
0
Description
bit1
bit2
bit3
bit4
bit5
bit6
0
bit0
bit1
bit2
bit3
bit4
bit5
bit6
Bit7
Next data
bit0
bit1
bit2
bit3
bit4
bit5
bit6
Bit7
Next data
0
SCK idle status = Low.
The transfer first bit = LSB.
SCK data transfer edge = Rising
edge.
SCK idle status = High.
The transfer first bit = LSB.
SCK data transfer edge = Falling
edge.
SIO Data Transfer Timing
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The SIO supports interrupt function. SIOIEN is SIO interrupt function control bit. SIOIEN=0, disable SIO interrupt
function. SIOIEN=1, enable SIO interrupt function. When SIO interrupt function enable, the program counter points to
interrupt vector (ORG 0011H) to do SIO interrupt service routine after SIO operating. SIOIRQ is SIO interrupt request
flag, and also to be the SIO operating status indicator when SIOIEN = 0, but cleared by program. When SIO operation
finished, the SIOIRQ would be set to “1”, and the operation is the inverse status of SIO “START” control bit.
The SIOIRQ and SIO START bit indicating the end status of SIO operation is after one 8-bit data transferring. The
duration from SIO transfer end to SIOIRQ/START active is about “1/2*SIO clock”, means the SIO end indicator
doesn’t active immediately.
Note: The first step of SIO operation is to setup the SIO pins’ mode. Enable SENB, select CPOL and CPHA
bits. These bits control SIO pins’ mode.
SIO builds in chip selection function to implement SIO multi-device mode. One master communicating with several
slave devices in SIO bus, and the chip selection decides the pointed device. The chip selection pin is SCS pin and
controlled by SCSEN bit. The SCS function only supports salve mode (SCKMD=1). The SCS includes two phases
which are high active and low active controlled by SCSP bit. SCSP=1, SCS pin idle mode is high and low active.
SCSP=0, SCS pin idle mode is low and high active. SIO operation is controlled by START bit. In SCS enable mode, set
START bit doesn’t mean SIO active. The SCS condition is a necessary condition. If the SCS status doesn’t exist, the
SIO bus keeps idle status until SCS status meets configuration.
SIO builds in SIOBZ bit to indicate SIO processing status. SIOBZ=1 means SIO is processing. SIOBZ=0 means SIO is
in idle status or the end of SIO processing. When SIO bus starts to execute, the SIOBZ bit changes to logic high status.
When SIO bus finishes transmitting, the SIOBZ bit changes to logic low status. SIOBZ operation of different modes is
as below diagram.
Set START = 1
SIO Bus Active
SCS pin, SCSP=0
SCS pin, SCSP=1
SCK
SI
SO
SIOBZ
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11.3 SIOM MODE REGISTER
0E0H
SIOM
Read/Write
After reset
Bit 7
SENB
R/W
0
Bit 6
START
R/W
0
Bit 5
SRATE1
R/W
0
Bit 4
SRATE0
R/W
0
Bit 3
MLSB
R/W
0
Bit 2
SCKMD
R/W
0
Bit 1
CPOL
R/W
0
Bit 0
CPHA
R/W
0
Bit 7
SENB: SIO function control bit.
0 = Disable SIO function. SIO pins are GPIO.
1 = Enable SIO function. GPIO pins are SIO pins.
SIO pin structure can be push-pull structure and open-drain structure controlled by P1OC register.
Bit 6
START: SIO progress control bit.
0 = End of transfer.
1 = SIO transmitting.
Bit [5:4]
SRATE1,0: SIO’s transfer rate select bit. These 2-bits are workless when SCKMD=1.
00 = fcpu. 01 = fcpu/32. 10 = fcpu/16. 11 = fcpu/8.
Bit 3
MLSB: MSB/LSB transfer first.
0 = MSB transmit first.
1 = LSB transmit first.
Bit 2
SCKMD: SIO’s clock mode select bit.
0 = Internal. (Master mode)
1 = External. (Slave mode)
Bit 1
CPOL: SCK idle status control bit.
0 = SCK idle status is low status.
1 = SCK idle status is high status.
Bit 0
CPHA: The Clock Phase bit controls the phase of the clock on which data is sampled.
0 = Data receive at the first clock phase.
1 = Data receive at the second clock phase.
0E3H
SIOC
Read/Write
After reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
SIOBZ
R
0
Bit 1
SCSEN
R/W
0
Bit 0
SCSP
R/W
0
Bit 2
SIOBZ: SIO operating status flag.
0 = SIO is idle or end of processing.
1 = SIO is busy and processing.
Bit 1
SCSEN: SIO chip selection function control bit.
0 = Disable chip selection function. SCS pin keeps and returns to GPIO function.
1 = Enable chip selection function. SCS pin transmits SIO chip selection pin when SCKMD = 1, or keeps
GPIO mode.
Bit 0
SCSP: SIO chip selection direction control bit.
0 = Idle low and high active.
1 = Idle high and low active.
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Because SIO function is shared with GPIO. The following table shows the SIO pin mode mode behavior and setting
when SIO function enable and disable.
SENB=1 (SIO Function Enable)
SCKMD=1
GPIO will change to Input mode automatically, no matter what
SIO source = External clock
PnM setting.
SCK
SCKMD=0
GPIO will change to Output mode automatically, no matter what
SIO source = Internal clock
PnM setting.
SI
GPIO must be set as Input mode in PnM ,or the SIO function will be abnormal
SIO = Transmitter/Receiver
GPIO will change to Output mode automatically, no matter what
SO
PnM setting.
SCSEN=1, SCKMD=1.
GPIO will change to Input mode automatically, no matter what
SCS
Enable chip selection function.
PnM setting.
SENB=0 (SIO Function Disable)
GPIO
GPIO I/O mode are fully controlled by PnM when SIO function Disable
Note:
1. If SCKMD=1 for external clock, the SIO is in SLAVE mode. If SCKMD=0 for internal clock, the SIO is in
MASTER mode.
2. Don’t set SENB and START bits in the same time. That makes the SIO function error.
3. SIO pin can be push-pull structure and open-drain structure controlled by P1OC register.
4. SCS pin enabled condition is only SCKMD=1 and SCSEN=1. If SCKMD=0, SCSEN=1, the SCS pin is
still GPIO mode.
11.4 SIOB DATA BUFFER
0E2H
SIOB
Read/Write
After reset
Bit 7
SIOB7
R/W
0
Bit 6
SIOB6
R/W
0
Bit 5
SIOB5
R/W
0
Bit 4
SIOB4
R/W
0
Bit 3
SIOB3
R/W
0
Bit 2
SIOB2
R/W
0
Bit 1
SIOB1
R/W
0
Bit 0
SIOB0
R/W
0
SIOB is the SIO data buffer register. It stores serial I/O transmit and receive data. The system is single-buffered in the
transmit direction and double-buffered in the receive direction. This means that bytes to be transmitted cannot be
written to the SIOB Data Register before the entire shift cycle is completed. When receiving data, however, a received
byte must be read from the SIOB Data Register before the next byte has been completely shifted in. Otherwise, the
first byte is lost. Following figure shows a typical SIO transfer between two micro-controllers. Master MCU sends SCK
for initial the data transfer. Both master and slave MCU must work in the same clock edge direction, and then both
controllers would send and receive data at the same time.
SIO Master
SIO Slave
(SCKMD = 0)
(SCKMD = 1)
Read SIOB
SCK
SCK
SI
SO
2nd Receive Buffer
(Address = SIOB)
Shift Register
(SIOB)
Shift Register
(SIOB)
Write SIOB
Read SIOB
Write SIOB
SO
SI
Internal Bus
Internal Bus
2nd Receive Buffer
(Address = SIOB)
SIO Data Transfer Diagram
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11.5 SIOR REGISTER DESCRIPTION
0E1H
SIOR
Read/Write
After reset
Bit 7
SIOR7
W
0
Bit 6
SIOR6
W
0
Bit 5
SIOR5
W
0
Bit 4
SIOR4
W
0
Bit 3
SIOR3
W
0
Bit 2
SIOR2
W
0
Bit 1
SIOR1
W
0
Bit 0
SIOR0
W
0
The SIOR is designed for the SIO counter to reload the counted value when end of counting. It is like a post-scalar of
SIO clock source and let SIO has more flexible to setting SCK range. Users can set the SIOR value to setup SIO
transfer time. To setup SIOR value equation to desire transfer time is as following.
SCK frequency = (SIO rate / (256 - SIOR))/2
SIOR = 256 - ( 1 / ( 2 * SCK frequency ) * SIO rate )
Example: Setup the SIO clock to be 5KHz. Fhosc = 4MHz. SIO’s rate = Fcpu = Fhosc/4.
SIOR = 256 – (1/(2*5KHz) * 4MHz/4)
= 256 – (0.0001*1000000)
= 256 – 100
= 156
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12 MAIN SERIAL PORT (MSP)
12.1 OVERVIEW
The MSP (Main Serial Port) is a serial communication interface for data exchanging from one MCU to one MCU or
other hardware peripherals. These peripheral devices may be serial EEPROM, A/D converters, Display device, etc.
The MSP module can operate in one of two modes:
Master Tx,Rx Mode
Slave Tx,Rx mode (with general address call) for multiplex slave in single master situation.
The MSP features include the following:
2-wire synchronous data transfer/receiver.
Master (SCL is clock output) or Slave (SCL is clock input) operation.
SCL, SDA are programmable open-drain output pin for multiplex salve devices application.
Support 400K clock rate @ Fcpu=4MIPs.
End-of-Transfer/Receiver interrupt.
12.2 MSP STATUS REGISTER
0EAH
MSPSTAT
Read/Write
After reset
Bit 6
Bit 7
-
Bit 6
CKE
R/W
0
Bit 5
D_A
R
0
Bit 4
P
R
0
Bit 3
S
R
0
Bit 2
RED_WRT
R
0
Bit 1
-
Bit 0
BF
R
0
CKE: Slave Clock Edge Control bit
In Slave Mode: Receive Address or Data byte
0= Latch Data on SCL Rising Edge. (Default)
1= Latch Data on SCL Falling Edge.
Note:
1. In Slave Transmit mode, Address Received depended on CKE setting. Data Transfer on SCL
Falling Edge.
2. In Slave Receiver mode, Address and Data Received depended on CKE setting.
Bit 5
D_A_: Data/Address_ bit
0=Indicates the last byte received or transmitted was address.
1= Indicates the last byte received or transmitted was data.
Bit 4
P: Stop bit
0 = Stop bit was not detected.
1 = Indicates that a stop bit has been detected last.
Note:
Bit 3
It will be cleared when Start bit was detected.
S: Start bit.
0 = Start bit was not detected.
1 = Indicates that a start bit has been detected last
Note:
It will be cleared when STOP bit was detected.
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Bit 2
RED_WRT: Read/Write bit information.
This bit holds the R/W bit information following the last address match. This bit is only valid from the address
match to the next start bit, stop bit, or not ACK bit.
In slave mode:
0 = Write.
1 = Read.
In master mode:
0 = Transmit is not in progress.
1 = Transmit is in progress.
Or this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSP is in IDLE mode.
Bit 0
BF: Buffer Full Status bit
Receive
1 = Receive complete, MSPBUF is full.
0 = Receive not complete, MSPBUF is empty.
Transmit
1 = Data Transmit in progress (does not include the ACK and stop bits), MSPBUF is full.
0 = Data Transmit complete (does not include the ACK and stop bits), MSPBUF is empty.
12.3 MSP MODE REGISTER 1
0EBH
MSPM1
Read/Write
After reset
Bit 7
WCOL
R/W
0
Bit 6
MSPOV
R/W
0
Bit 5
MSPENB
R/W
0
Bit 4
CKP
R/W
0
Bit 3
SLRXCKP
R/W
0
Bit 2
MSPWK
R/W
0
Bit 1
-
Bit 0
MSPC
R/W
0
Bit 7
WCOL: Write Collision Detect bit
Master Mode:
0 = No collision
1 = A write to the SSPBUF register was attempted while the MSP conditions were not valid for a
transmission to be started
Slave Mode:
0 = No collision
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
Bit 6
PMSPOV: Receive Overflow Indicator bit
0 = No overflow.
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care”
in transmit mode. SSPOV must be cleared in software in either mode. (must be cleared in software)
Bit 5
MSPENB: MSP Communication Enable.
0 = Disables serial port and configures these pins as I/O port pins
1 = Enables serial port and configures SCL, SDA as the source of the serial port pins
Note: MSP status register will be clear after MSP Disable. So, user should setting MSP register again
before MSP Enable.
Ex: B0BCLR
FMSPENB
CALL
MSP_init_setting
B0BSET
FMSPENB
Bit 4
CKP: SCL Clock Priority Control bit
In MSP Slave mode
0 = Hold SCL keeping Low. (Ensure data setup time and Slave device ready.)
1 = Release SCL Clock
(Slave Transistor mode CKP function always enables, Slave Receiver CPK function control by SLRXCKP)
In MSP Master mode Unused.
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Bit 3
SLRXCKP: Slave Receiver mode SCL Clock Priority Control bit
In MSP Slave Receiver mode.
0 = Disable CKP function.
1 = Enable CKP function.
In MSP Slave and Slave Transistor mode Unused.
Bit 2
MSPWK: MSP Wake-up indication bit
0 = MCU NOT wake-up by MSP.
1 = MCU wake-up by MSP
Note: Clear MSPWK before entering Power down mode for indication the wake-up source from MSP or
not
Bit 0
MSPC: MSP mode Control register
0 = MSP operated on Slave mode, 7-bit address
1 = MSP operated on Master mode.
12.4 MSP MODE REGISTER 2
0ECH
MSPM2
Read/Write
After reset
Bit 7
GCEN
R/W
0
Bit 6
ACKSTAT
R/W
0
Bit 5
ACKDT
R/W
0
Bit 4
ACKEN
R/W
0
Bit 3
RCEN
R/W
0
Bit 2
PEN
R/W
0
Bit 1
RSEN
R/W
0
Bit 0
SEN
R/W
0
Bit 7
GCEN: General Call Enable bit (In Slave mode only)
0 = General call address disabled
1 = Enable interrupt when a general call address (0000h) is received.
Bit 6
ACKSTAT: Acknowledge Status bit (In master mode only)
In master transmit mode:
0 = Acknowledge was received from slave
1 = Acknowledge was not received from slave
Bit 5
ACKDT: Acknowledge Data bit. (In master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
0 = Acknowledge
1 = Not Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (In MSP master mode only)
In master receive mode:
0 = Acknowledge sequence idle
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit. Automatically
cleared by hardware.
bit 3
RCEN: Receive Enable bit (In master mode only)
0 = Receive idle
1 = Enables Receive mode for MSP
bit 2
PEN: Stop Condition Enable bit (In master mode only)
0 = Stop condition idle
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
bit 1
RSEN: Repeated Start Condition Enabled bit (In master mode only)
0 = Repeated Start condition idle.
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
bit 0
SEN: Start Condition Enabled bit (In master mode only)
0 = Start condition idle
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
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12.5 MSP MSPBUF REGISTER
MSPBUF initial value = 0000 0000
0EDH
Bit 7
Bit 6
MSPBUF
MSPBUF7 MSPBUF6
Read/Write
R/W
R/W
After reset
0
0
Bit 5
MSPBUF5
R/W
0
Bit 4
MSPBUF4
R/W
0
Bit 3
MSPBUF3
R/W
0
Bit 2
MSPBUF2
R/W
0
Bit 1
MSPBUF1
R/W
0
Bit 0
MSPBUF0
R/W
0
12.6 MSP MSPADR REGISTER
MSPADR initial value = 0000 0000
0EEH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MSPADR
MSPADR7 MSPADR6 MSPADR5 MSPADR4 MSPADR3 MSPADR2 MSPADR1 MSPADR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0
0
0
0
0
0
0
0
Bit [7:1]
7-bit Address.
Bit 0
Tx/Rx mode control bit.
0=Tx mode.
1=Rx mode.
12.7 SLAVE MODE OPERATION
When an address is matched or data transfer after and address match is received, the hardware automatically will
generate the acknowledge (ACK_) signal, and load MSPBUF (MSP buffer register) with the received data from
MSPSR.
There are some conditions that will cause MSP function will not reply ACK_ signal:
Data Buffer already full: BF=1 (MSPSTAT bit 0), when another transfer was received.
Data Overflow: MSPOV=1 (MSPM1 bit 6), when another transfer was received
When BF=1, means MSPBUF data is still not read by MCU, so MSPSR will not load data into MSPBUF, but MSPIRQ
and MSPOV bit will still set to 1. BF bit will be clear automatically when reading MSPBUF register. MSPOV bit must be
clear through by Software.
12.7.1 Addressing
When MSP Slave function has been enabled, it will wait a START signal occur. Following the START signal, 8-bit
address will shift into the MSPSR register. The data of MSPSR[7:1] is compare with MSPADR register on the falling
edge of eight SCL pulse, If the address are the same, the BF and SSPOV bit are both clear, the following event occur:
1.
2.
3.
4.
MSPSR register is loaded into MSPBUF on the falling edge of eight SCL pulse.
Buffer full bit (BF) is set to 1, on the falling edge of eight SCL pulse.
An ACK_ signal is generated.
MSP interrupt request MSPIRQ is set on the falling edge of ninth SCL pulse.
Status when Data is
Received
BF
MSPOV
0
0
*0
*1
1
0
1
1
Note:
MSPSP MSPBUF
Reply an ACK_ signal
Yes
Yes
No
No
Data Received Action Table
Yes
No
No
No
Set MSPIRQ
Yes
Yes
Yes
Yes
BF=0, MSPOV=1 shows the software is not set properly to clear Overflow register.
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12.7.2 Slave Receiving
When the R/W bit of address byte =0 and address is matched, the R/W bit of MSPSTAT is cleared. The address will be
load into MSPBUF. After reply an ACK_ signal, MSP will receive data every 8 clock. The CKP function enable or
disable (Default) is controlled by SLRXCKP bit and data latch edge -Rising edge (Default) or Falling edge is controlled
by CPE bit.
When overflow occur, no acknowledge signal replied which either BF=1 or MSPOV=1.
MSP interrupt is generated in every data transfer. The MSPIRQ bit must be clear by software.
Following is the Slave Receiving Diagram
SLRXCKP=0
Receiving Address
SDA
Receiving Data
R/W=0
ACK_ D7
A7 A6 A5 A4 A3 A2 A1
Receiving Data
ACK_
D6 D5 D4 D3 D2 D1 D0
ACK_
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
MSPIRQ
Terminate
by Master
BF
Cleared by Software
Read MSPBUF
SSPOV
MSPOV=1, Because MSPBUF still full (BF=1)
ACK_ not sent
SLRXCKP=1
ACK_ not sent
Receiving Address
SDA
Receiving Data
A7 A6 A5 A4 A3 A2 A1 R/W=0
ACK_
D7
Receiving Data
ACK_
D6 D5 D4 D3 D2 D1 D0
D7
ACK_
D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
MSPIRQ
7
8
9
P
Terminate
by Master
BF
SSPOV
Cleared by Software
Read MSPBUF
MSPOV=1, Because MSPBUF still full (BF=1)
CKP
Set CKP after
read MSPBUF
Set CKP,
NOT read MSPBUF
Set CKP
12.7.3 Slave Transmission
After address match, the following R/W bit is set, MSPSTAT bit 2 R/W will be set. The received address will be load to
MSPBUF and ACK_ will be sent at ninth clock then SCL will be hold low. Transmission data will be load into MSPBUF
which also load to MSPSR register. The Master should monitor SCL pin signal. The slave device may hold on the
master by keep CKP low. When set. After load MSPBUF, set CKP bit, MSPBUF data will shift out on the falling edge
on SCL signal. This will ensure the SDA signal is valid on the SCL high duty.
An MSP interrupt is generated on every byte transmission. The MSPIRQ will be set on the ninth clock of SCL. Clear
MSPIRQ by software. MSPSTAT register can monitor the status of data transmission.
In Slave transmission mode, an ACK_ signal from master-receiver is latched on rising edge of ninth clock of SCL. If
ACK_ = high, transmission is complete. Slave device will reset logic and waiting another START signal. If ACK_= low,
slave must load MSPBUF which also MSPSR, and set CKP=1 to start data transmission again.
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Receiving Address
SDA
R/W=0
ACK_
Transmission Data
R/W=1
A7 A6 A5 A4 A3 A2 A1
ACK_
D7
D6 D5 D4 D3 D2 D1 D0
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
P
9
MSPIRQ
BF
Cleared by Software
Interrupt Service Routine
MSPBUF is writing by Software
}
CKP
Set CKP after writing to MSPBUF
MSP Slave Transmission Timing Diagram
12.7.4 General Call Address
In MSP bus, the first 7-byte is the Slave address. Only the address match MSPADR the Slave will response an ACK_.
The exception is the general call address which can address all slave devices. When this address occur, all devices
should response an acknowledge.
The general call address is a special address which is reserved as all “0” of 7-bytes address. The general call address
function is control by GCEN bit. Set this bit will enable general call address and clear it will disable. When GECN=1,
following a START signal, 8-bit will shift into MSPSR and the address is compared with MSPADD and also the general
call address which fixed by hardware.
If the genera call address matches, the MSPSR data is transferred into MSPBUF, the BF flag bit is set, and in the
falling edge of the ninth clock (ACK_) MSPIRQ flag set for interrupt request. In the interrupt service routine, reading
MSPBUF can check if the address is the general call address or device specific.
Address compare to general call address
After ACK_, set interrupt
Receiving Data
SDA
R/W=0
ACK_ D7 D6 D5 D4 D3 D2 D1 D0
General Call Address
ACK_
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
MSPIRQ
BF
Cleared by Software
Read MSPBUF
SSPOV
GCEN
“0”
“1”
General Call Address Timing Diagram
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12.7.5 Slave Wake up
When MCU enter Power down mode, if MSBENB bit is still set, MCU can wake-up by matched device address.
The address of MSP bus following START bit, 8-byte address will shift into MSPSR, if address matched, an NOT
Acknowledge will response on the ninth clock of SCL and MCU will be wake-up, MSPWKset and start wake-up
procedure but MSPIRQ will not set and MSPSR data will not load to MSPUBF. After MCU finish wake-up procedure,
MSP will be in idle status and waiting master’s START signal. Control register BF, MSPIRQ, MSPOV and MSPBUF will
be the same status/data before power down.
If address not matches, a NOT acknowledge is still sent on the ninth clock of SCL, but MCU will be NOT wake-up and
still keep in power down mode.
Receiving Address
SDA
R/W ACK_
A7 A6 A5 A4 A3 A2 A1
SCL
S
1
2
3
4
5
6
7
8
P
9
MSPIRQ
“0”
BF
“0”
Wake-up
“0”
MSPWK
“0”
MCU
Mode
Power down mode
Clear MSPWK,
Set FCPUM0
(Power Down)
Normal Mode
MSP Wake-up Timing Diagram: Address NOT Matched
Receiving Address
SDA
Receiving Address
R/W ACK_
A7 A6 A5 A4 A3 A2 A1
Receiving Data
R/W=0
ACK_
ACK_ D7 D6 D5 D4 D3 D2 D1 D0
A7 A6 A5 A4 A3 A2 A1
SCL
S
1
2
3
4
5
6
7
8
P
9
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
MSPIRQ
BF
Cleared by Software
Read MSPBUF
Wake-up
MSPWK
MCU
Mode
Warm-up Time
Power down mode
Clear MSPWK,
Set FCPUM0
(Power Down)
MCU Wake-up
Start Warm-up
Normal mode (OP-code executing)
Clear MSPWK by Software
Normal mode
MSP Wake-up Timing Diagram: Address Matched
After into power down mode, we need to disable MSP and then enable MSP to reset MSP function and re-write the I2C
slave address.
Example:
B0BSET
B0BCLR
NOP
B0BSET
MOV
B0MOV
FCPUM0
FMSPENB
FMSPENB
A, #0xnn
MSPADR, A
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; Re-write the I2C slave address again.
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8-Bit Flash Micro-Controller with Embedded ICE and ISP
Note:
1.
MSP function only can work on Normal mode, when wake-up from power down mode, MCU must
operate in Normal mode before Master sent START signal.
2. In MSP wake-up, if the address not matches, MCU will keep in power down mode.
3. Clear MSPWK before enter power down mode by Software for wake-up indication.
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12.8 MASTER MODE
Master mode of MSP operation from a START signal and end by STOP signal.
The START (S) and STOP (P) bit are clear when reset or MSP function disabled.
In Master mode the SCL and SDA line are controlled by MSP hardware.
Following events will set MSP interrupt request (MSPIRQ), if MSPIEN set, interrupt occurs.
START condition
STOP condition
Data byte transmitted or received
Acknowledge Transmit.
Repeat START.
12.8.1 Mater Mode Support
Master mode enable when MSPC and MSPENB bit set. Once the Master mode enabled, the user had following six
options.
Send a START signal on SCL and SDA line.
Send a Repeat START signal on SCL and SDA line.
Write to MSPBUF register for Data or Address byte transmission
Send a STOP signal on SCL and SDA line.
Configuration MSP port for receive data
Send an Acknowledge at the end of a received byte of data.
12.8.2 MSP Rate Generator
In MSP Mode, the MSP rate generator’s reload value is located in the lower 7 bit of MSPADR register. When MRG is
loaded with the register, the MRG count down to 0 and stop until another reload has taken place. In MSP mater mode
MRG reload from MSPADR automatically. If Clock Arbitration occur for instance (SCL pin keep low by Slave device),
the MRG will reload when SCL pin is detected High.
SCL clock rate = Fcpu/(MSPADR)*2
For example, if we want to set 400Khz in 4Mhz Fcpu, the MSPADR have to set 0x05h.
MSPADR=4Mhz/400Khz*2=5
MSP Rate Generator Block Diagram
SDA shift in
next bit Data
SDA
DX-1
DX
No Clock
Arbitration
DX-2
Slave release SCL clock,
SCL allowed to transition high.
Clock
Arbitration
SCL
MRG
Down Counter
3
2
1
0
3
2
1
0
3
2
1
0
3
2
Fcpu/4
MRG Reload
SCL Is sampled High,
Reload occurred
and MRG down counter starts count
MRG Timing Diagram with and without Clock Arbitration (MSPADR=0x03)
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12.8.3 MSP Mater START Condition
To generate a START signal, user sets SEN bit (MSPM2.0). When SDA and SCL pin are both sampled High, MSP rate
generator reload MSPADR[6:0], and starts down counter. When SDA and SCL are both sampled high and MRG
overflow, SDA pin is drive low. When SCL sampled high, and SDA transmitted from High to Low is the START signal
and will set S bit (MSPSTAT.3). MRG reload again and start down counter. SEN bit will be clear automatically when
MRG overflow, the MRG is suspend leaving SDA line held low, and START condition is complete.
12.8.3.1WCOL Status Flag
If user write to MSPBUF when START condition processing, then WCOL is set and the content of MSPBUF data is
un-changed. (the writer doesn’t occur)
Write SEN here
SDA=1
SCL=1
Set S bit
(MSPSTAT.3)
Complete SRART signal,
Hardware clear SEN bit,
TMRG
TMRG
Set MSPIRQ bit
TMRG
SDA
1st-bit
2nd-bit
Write MSPBUF here
SCL
TMRG
TMRG
S
START Condition Timing Diagram
12.8.4 MSP Master mode Repeat START Condition
When MSP logic module is idle and RSEN set to 1, Repeat Start progress occurs. RSEN set and SCL pin is sampled
low, MSPADR[6:0] data reload to MSP rate generator and start down counter. The SDA pin is release to high in one
MSP rate generate counter (TMRG). When the MRG is overflow, if SDA is sampled high. SCL will be brought high. When
SCL is sampled high, MSPADR reload to MRG and start down counter. SDA and SCL must keep high in one T MRG
period. In the next TMRG period, SDA will be brought low when SCL is sampled high, then RSEN will clear automatically
by hardware and MRG will not reload, leaving SDA pin held low. Once detect SDA and SCL occur START condition,
the S bit will be set (MSPSTAT.3). MSPIRQ will not set until MRG overflow.
Note:
1. While any other event is progress, Set RSEN will take no effect.
2. A bus collision during the Repeat Start condition occurs: SDA is sampled low when SCL goes from
low to high.
12.8.4.1WCOL Status Flag
If user write to MSPBUF when Repeat START condition processing, then WCOL is set and the content of MSPBUF
data is un-changed. (the writer doesn’t occur)
SDA=1,
SCL=1
Write RSEN here
SDA
SDA=1
SCL no change
TMRG
Set S bit
TMRG
Complete of Start bit,
Hardare clear ESEN bit
and set MSPIRQ
TMRG
1st-bit
Write to MSPBUF here
TMRG
SCL
RS
=Repeat Start
Falling edge of ninth clock,
End of transmission
TMRG
Repeat Start Condition Timing Diagram
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12.8.5 Acknowledge Sequence Timing
An acknowledge sequence is enabled when set ACKEN (MSPM2.4). SCL is pulled low when set ACKEN and the
content of the acknowledge data bit is present on SDA pin. If user whished to reply a acknowledge, ACKDT bit should
be cleared. If not, set ACKDT bit before starting a acknowledge sequence. SCL pin will be release (brought high) when
MSP rate generator overflow. MSP rate generator start a TMRG period down counter, when SCL is sampled high. After
this period, SCL is pulled low, and ACKEN bit is clear automatically by hardware. When next MRG overflow again,
MSP goes into idle mode.
12.8.5.1WCOL Status Flag
If user write to MSPBUF when Acknowledge sequence processing, then WCOL bit is set and the content of MSPBUF
data is un-changed. (the writer doesn’t occur)
Acknowledge sequence start here
ACKEN cleared automatically
Write ACKEN=1, ACKNDT=0
TMRG
TMRG
D0
SDA
ACK_
8
SCL
9
MSPIRQ
Clear MSPIRQ
Clear MSPIRQ
by Software
by Software
Set MSPIRQ at the end of
Acknowledge sequence
Set MSPIRQ at
the end of receive
Acknowledge Sequence Timing Diagram
12.8.6 STOP Condition Timing
At the end of received/transmitted, a STOP signal present on SDA pin by setting the STOP bit register, PEN
(MSPM2.1). At the end of receive/transmit, SCL goes low on the failing edge of ninth clock. Master will set SDA go low,
when set PEN bit. When SDA is sampled low, MSP rate generator is reloaded and start count down to 0. When MRG
overflow, SCL pin is pull high. After one T MRG period, SDA goes High. When SDA is sampled high while SCL is high, bit
P is set. PEN bit is clear after next one T MRG period, and MSPIRQ is set.
12.8.6.1WCOL Status Flag
If user write to MSPBUF when a STOP condition is processing, then WCOL bit is set and the content of MSPBUF data
is un-changed. (the writer doesn’t occur)
Set PEN here
P bit is set
Falling edge of ninth edge
TMRG
SCL
PEN is clear by hardware and
MSPIRQ bit is set
P
SDA
TMRG
TMRG
TMRG
SCL goes high on next TMRG
SDA goes low before the rising edge of SCL
to set up STOP signal
STOP condition sequence Timing Diagram
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12.8.7 Clock Arbitration
Clock arbitration occurs when the master, during any receive, transmit or Repeat START, STOP condition that SCL pin
allowed to float high. When SCL pin is allowed float high, the master rate generator (MRG) suspended from counting
until the SCL pin is actually sampled high. When SCL is sampled high, the MRG is reloaded with the content of
MSPADR[6:0], and start down counter. This ensure that SCL high time will always be at least one MRG overflow time
in the event that the clock is held low by an external device.
MRG overflow, Releas SCL,
If SCL=1, Reload MRG with MSPADR
and start count down to measure high time Interval
MRG Overflow,
Release SCL, Slave device held the SCL low
SCL=1,
MRG Start counting clock high interval
SCL
SCL pin smapleed once every Fcpu/4,
Hold of MRG untial SCL Is sampled high
SDA
TMRG
TMRG
TMRG
Clock Arbitration sequence Timing Diagram
12.8.8 Master Mode Transmission
Transmission a data byte, 7-bit address or the eight bit data is accomplished by simply write to MSPBUF register. This
operation will set the Buffer Full flag BF and allow MSP rate generator start counting.
After write to MSPBUF, each bit of address will be shifted out on the falling edge of SCL until 7-bit address and R/W_
bit are complete. On the failing edge of eighth clock, the master will pull low SDA fort slave device respond with an
acknowledge. On the ninth clock falling edge, SDA is sampled to indicate the address already accept by slave device.
The status of the ACK bit is load into ACKSTAT status bit. Then MSPIRQ bit is set, the BF bit is clear and the MRG is
hold off until another write to the MSPBUF occurs, holding SCL low and allow SDA floating.
12.8.8.1BF Status Flag
In transmission mode, the BF bit is set when user writes to MSPBUF and is cleared automatically when all 8 bit data
are shift out.
12.8.8.2WCOL Flag
If user write to MSPBUF during Transmission sequence in progress, the WCOL bit is set and the content of MSPBUF
data will unchanged.
12.8.8.3ACKSTAT Status Flag
In transmission mode, the ACKSTAT bit is cleared when the slave has sent an acknowledge (ACK_=0), and is set
when slave does not acknowledge (ACK_=1). A slave send an acknowledge when it has recognized its address
(including general call), or when the slave has properly received the data.
Write SEN=1,
START condition begins
From Slave, Clear ACKSTAT
SEN=0
Transmit Address
SDA
Transmission Data
R/W=0
A7 A6 A5 A4 A3 A2 A1
ACKSTAT=1
ACK_
D7 D6 D5 D4 D3 D2 D1 D0
ACK_=0
Write address and R/W to MSPBUF
SCL held low,
Start transmit
while master response MSPIRQ
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
MSPIRQ
Cleared by Software
Cleared by Software service
routine of MSP interrupt
Cleared by Software
BF
Write MSPBUF
Write MSPBUF
SEN
PEN
SEN cleared by hardware,
after START condition
R/W_
MSP Master Transmission Mode Timing Diagram
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12.8.9 Master Mode Receiving
Master receiving mode is enable by set RCEN bit.
The MRG start counting and when SCL change state from low to high, the data is shifted into MSPSR. After the falling
edge of eighth clock, the receive enable bit (RCEN) is clear automatically, the contents of MSP are load into MSPBUF,
the BF flag is set, the MSPIRQ flag is set and MRG counter is suspended fro, counting, holding SCL low. The MSP is
now in IDLE mode and awaiting the next operation command. When the MSPBUF data is read by Software, the BF
flag is cleat automatically. By setting ACKEN bit, user can send an acknowledge bit at the end of receiving.
12.8.9.1BF Status Flag
In Reception mode, the BF bit is set when an address or data byte is loaded into MSPBUF from MSPSR. It is cleared
automatically when MSPBUF is read.
12.8.9.2MSPOV Flag
In receive operation, the MSPOV bit is set when another 8-bit are received into MSPSR, and the BF bit is already set
from previous reception
12.8.9.3WCOL Flag
If user write to MSPBUF when a receive is already progress, the WCOL bit is set and the content of MSPBUF data will
unchanged.
Write ACKEN=1
Start Acknowledge sequence,
SDA=ACKDT=0
Write SEN=1,
START condition begins
From Slave, Clear ACKSTAT
SEN=0
Transmit Address to Slave
SDA
R/W=1
A7 A6 A5 A4 A3 A2 A1
ACK from Master
SDA=ACKDT=0
RCEN cleared
automatically
Write RCEN=1
Write PEN=1 here
RCEN cleared
automatically
Write RCEN=1,
Start next receive
Receiving Data from Slave
ACK_=0
Write ACKEN=1
Start Acknowledge sequence,
SDA=ACKDT=1
Receiving Data from Slave
D7 D6 D5 D4 D3 D2 D1
D0
ACK_
D6 D6 D5 D4 D3 D2 D1
D0
Write address and R/W to MSPBUF
Start transmit
ACK_
ACK_ is not
sent
SCL
S
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
4
5
6
7
8
P
9
Data shifted in failing edgeof SCL
Set MSPIRQ
Set MSPIRQ at the end of
at the end of receive
Acknowledge sequence
Set MSPIRQ at the end of receive
MSPIRQ
Cleared by Software
3
Cleared by Software
Master terminal transfer
P bit and MSPIRQ bit is set
Set MSPIRQ at the end of
Acknowledge sequence
Cleared by Software
BF
Last bit is shifted into MSPSR,
MSPBUF is not read.
Write MSPBUF
MSPOV
MSPBUF is still full,
MSPOV set
ACKEN
MSP Master Receiving Mode Timing Diagram
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13 IN SYSTEM PROGRAM FLASH ROM
Note: During ISP operating, EIDA pin must be “high status” (output high or input high), can’t be “low
status” (output low or input low), or EIDA GPIO function would be error.
13.1 OVERVIEW
The SN8F27E65 MCU integrated device feature in-system programmable (ISP) FLASH memory for convenient,
upgradeable code storage. The FLASH memory may be programmed via the SONiX 8 bit MCU programming interface
or by application code. The SN8F27E65 provides security options at the disposal of the designer to prevent
unauthorized access to information stored in FLASH memory. ISP Flash ROM provided user an easy way to storage
data into Flash ROM. The ISP concept is memory mapping idea that is to move RAM buffer to flash ROM. Choice
ROM/RAM address and executing ROM programming command – PECMD, after programming words which controlled
by PERAMCNT, PERAML/PERAMCNT data will be programmed into address PEROML/PEROMH.
RAM (byte)
RAM Address bit7 ~ bit0
X DATA0
X+1 DATA1
X+2 DATA2
X+3 DATA3
…
…
X+N DATAN
=>
Flash ROM (word)
ROM Address bit15 ~ bit8 bit7 ~ bit0
Y
DATA1
DATA0
Y+1
DATA3
DATA2
Y+2
Y+3
…
…
Y+M
DATAN
DATAN-1
During Flash program or erase operation, the MCU is stalled, although peripherals (Timers, WDT, I/O, PWM, etc.)
remain active. When PECMD register is set to execute ISP program and erase operations, the program counter stops,
op-code can’t be dumped from flash ROM, instruction stops operating, and program execution is hold not to active. At
this time hardware depends on ISP operation configuration to do flash ROM erasing and flash ROM programming
automatically. After ISP operation is finished, hardware releases system clock to make program counter running,
system returns to last operating mode, and the next instruction is executed. Recommend to add two “NOP” instructions
after ISP operations.
ISP flash ROM erase time = 25ms……1-page, 128-word.
ISP flash ROM program time = 28us……1-word.
ISP flash ROM program time = 56us……2-word.
…
ISP flash ROM program time = 448us……16-word.
…
ISP flash ROM program time = 896us……32-word.
Note:
1. Watch dog timer should be clear before the Flash write (program) or erase operation, or watchdog
timer would overflow and reset system during ISP operating.
2. Besides program execution, all functions keep operating during ISP operating, e.g. timer, ADC, SIO,
UART, MSP... All interrupt events still active and latch interrupt flags automatically. If any interrupt
request occurs during ISP operating, the interrupt request will be process by program after ISP
finishing.
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SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
13.2 ISP FLASH ROM ERASE OPERATION
ISP flash ROM erase operation is to clear flash ROM contents to blank status “1”. Erasing ROM length is 128-word and
has ROM page limitation. ISP flash ROM erase ROM map is as following:
ROM address bit0~bit6 (hex)
0000 0001 0002
…
0010 0011
…
0050 0051
…
0070 0071
…
007E 007F
This page includes reset vector and interrupt sector. We strongly recommend to reserve the area not to do ISP
0000
erase.
0080
One ISP Erase Page
0100
One ISP Erase Page
0180
One ISP Erase Page
0200
One ISP Erase Page
0280
One ISP Erase Page
…
One ISP Erase Page
0F00
One ISP Erase Page
0F80
One ISP Erase Page
1000
One ISP Erase Page
1080
One ISP Erase Page
1100
One ISP Erase Page
1180
One ISP Erase Page
…
One ISP Erase Page
1600
One ISP Erase Page
1680
One ISP Erase Page
1700
One ISP Erase Page
1780 This page includes ROM reserved area. We strongly recommend to reserve the area not to do ISP erase.
ROM address bit7~bit15 (hex)
ISP ROM
MAP
ISP flash ROM erase density is 128-word which limits erase page boundary. The first 128-word of flash ROM
(0x0000~0x007F) includes reset vector and interrupt vectors related essential program operation, and the last page
128-word of flash ROM (0x1780~0x17FF) includes system reserved ROM area, we strongly recommend do not
execute ISP flash ROM erase operation in the two pages. Flash ROM area 0x0080~0x177F includes 46-page for ISP
flash ROM erase operation.
The first step to do ISP flash ROM erase is to address ROM-page location. The address must be the head location of a
page area, e.g. 0x0080, 0x0100, 0x0180…0x1600, 0x1680 and 0x1700. PEROML [7:0] and PEROMH [7:0] define the
target starting address [15:0] of flash ROM. Write the start address into PEROML and PEROMH registers, set PECMD
register to “0xC3”, and the system start to execute ISP flash ROM erase operation.
Example : Use ISP flash ROM erase to clear 0x0080~0x00FF contents of flash ROM.
; Set erased start address 0x0080.
MOV
A, #0x80
B0MOV
PEROML, A
MOV
A, #0x00
B0MOV
PEROMH, A
; Clear watchdog timer.
MOV
B0MOV
; Move low byte address 0x80 to PEROML.
;Move high byte address 0x00 to PEROMH
A,#0X5A
WDTR,A
; Start to execute ISP flash ROM erase operation.
MOV
A,#0XC3
B0MOV
PECMD, A
NOP
NOP
; Start to page erase.
; NOP Delay
; The end of ISP flash ROM erase operation.
The two “NOP” instructions make a short delay to let system stable after ISP flash ROM erase operation.
Note: Don’t execute ISP flash ROM erase operation for the first page and the last page, or affect program
operation.
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Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
13.3 ISP FLASH ROM PROGRAM OPERATION
ISP flash ROM program operation is to write data into flash ROM by program. Program ROM doesn’t limit written ROM
address and length, but limits 32-word density of one page. The number of ISP flash ROM program operation can be
1-word ~ 32-word at one time, but these words must be in the same page. ISP flash ROM program ROM map is as
following:
ISP ROM
MAP
ROM address bit5~bit15 (hex)
0000
0020
0040
0060
0080
00A0
00C0
00E0
0100
0120
…
1000
1020
…
1700
1720
…
1780
ROM address bit0~bit4 (hex)
0000
0001
0002
…
000F
0010
…
001E
001F
This page includes reset vector and interrupt sector. We strongly recommend to reserve the area not to do
ISP erase.
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
One ISP Program Page
This page includes ROM reserved area. We strongly recommend to reserve the area not to do ISP erase.
ISP flash ROM program page density is 32-word which limits program page boundary. The first 32-word of flash ROM
(0x0000~0x001F) includes reset vector and interrupt vectors related essential program operation, and the last page
32-word of flash ROM (0x1780~0x17FF) includes system reserved ROM area, we strongly recommend do not execute
ISP flash ROM program operation in the two pages. Flash ROM area 0x0020~0x177F includes 187-page for ISP flash
ROM program operation.
ISP flash ROM program operation is a simple memory mapping operation. The first step is to plan a RAM area to store
programmed data and keeps the RAM address for IS RAM addressing. The second step is to plan a ROM area will be
programmed from RAM area in ISP flash ROM program operation. The RAM addressing is through PERAML[9:0]
10-bit buffer to configure the start RAM address. The RAM data storage sequence is down-up structure. The first RAM
data is the low byte data of the first word of flash ROM. The second RAM data is the high byte data of the first word of
ROM, and so on.
ISP programming length is 1-word~32-word. ISP flash ROM programming length is controlled by PERAMCNT[7:3] bits
which is 5-bit format. Before ISP ROM programming execution, set the length by program. PEROML [7:0] and
PEROMH [7:0] define the target starting address [15:0] of flash ROM. Write the start address into PEROML and
PEROMH registers, set PECMD register to “0x5A”, and the system start to execute ISP flash ROM program operation.
If the programming length is over ISP flash ROM program page boundary, the hardware immediately stops
programming flash ROM after finishing programming the last word of the ROM page. So it is very important to plan
right ROM address and programming length.
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SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
Case 1: 32-word ISP program. RAM buffer length is 64-byte and RAM address is X ~ X+63. PERAMCNT[7:3]
=11111b meets a complete one page 32-word of flash ROM. The page address of flash ROM is Y ~ Y+31. The Y
is the start address and set to PEROML, PEROMH registers.
RAM (byte)
Flash ROM (word)
RAM Address
ROM Address
bit7 ~ bit0
bit15 ~ bit8
bit7 ~ bit0
64-byte
32-word
The head of the page.
DATA1
DATA0
X DATA0
Y
The start address of ISP.
DATA3
DATA2
X+1 DATA1
Y+1
=>
…
…
X+2 DATA2
Y+2
…
…
X+3 DATA3
Y+3
…
…
…
…
…
…
…
X+62 DATA62
…
The end of the page.
DATA63
DATA62
X+63 DATA63
Y+31
The end address of ISP.
Case 2: 16-word ISP program: RAM buffer length is 32-byte. PERAMCNT [7:3] =01111b meets 16-word of flash
ROM. The page address of flash ROM is Y ~ Y+31, but the start address isn’t the head of the page. Define the
start address is Y+10 and set to PEROML, PEROMH registers. The programmed flash ROM area is Y+10~Y+25
addresses.
RAM (byte)
RAM Address
bit7 ~ bit0
32-byte
X DATA0
X+1 DATA1
X+2 DATA2
X+3 DATA3
…
…
X+30 DATA30
X+31 DATA31
=>
Flash ROM (word)
ROM Address
bit15 ~ bit8
bit7 ~ bit0
32-word
Y
Y+1
…
DATA1
DATA0
Y+10
DATA3
DATA2
Y+11
…
…
…
DATA31
DATA30
Y+25
…
Y+30
Y+31
The head of the page.
The start address of ISP.
The end address of ISP.
The end of the page.
Case 3: Follow above case and change the ROM start address to Y+20. The programmed flash ROM area is
Y+20~Y+35 addresses. The ROM range is out of the page boundary. After ISP flash ROM operation, the last
4-word data can’t be written into flash ROM successfully. The programming length is over ISP flash ROM
program page boundary, the hardware immediately stops programming flash ROM after finishing programming
the last word (Y+31) of the ROM page.
RAM (byte)
RAM Address
bit7 ~ bit0
32-byte
X DATA0
X+1 DATA1
X+2 DATA2
X+3 DATA3
…
…
X+30 DATA30
X+31 DATA31
=>
Flash ROM (word)
ROM Address
bit15 ~ bit8
bit7 ~ bit0
32-word
Y
Y+1
…
DATA1
DATA0
Y+20
DATA3
DATA2
Y+21
…
…
…
DATA21
DATA20
Y+30
Y+31
SONiX TECHNOLOGY CO., LTD
DATA23
Page 162
DATA22
The head of the page.
The start address of ISP.
The end of the page.
The end address of ISP.
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
Example : Use ISP flash ROM program to program 32-word data to flash ROM as case 1. Set RAM buffer
start address is 0x010. Set flash ROM programmed start address is 0x0020.
; Load data into 64-byte RAM buffer.
…
…
; Set RAM start address of 64-byte buffer.
MOV
A, #0x10
B0MOV
PERAML, A
MOV
A, #0x00
B0MOV
PERAMCNT, A
; Set PERAML[7:0] to 0x20.
; Set PERAML[9:8] to 00b.
; Set ISP program length to 32-word.
MOV
A, #11111000b
OR
PERAMCNT, A
; Set PERAMCNT[7:3] to 11111b.
; Set programmed start address of flash ROM to 0x0020..
MOV
A, #0x20
B0MOV
PEROML, A
MOV
A, #0x00
B0MOV
PEROMH, A
; Clear watchdog timer.
MOV
B0MOV
; Move low byte address 0x20 to PEROML.
;Move high byte address 0x00 to PEROMH
A,#0X5A
WDTR,A
; Start to execute ISP flash ROM program operation.
MOV
A,#0X5A
B0MOV
PECMD, A
NOP
NOP
; Start to program flash ROM.
; NOP Delay
; The end of ISP flash ROM program operation.
The two “NOP” instructions make a short delay to let system stable after ISP flash ROM program operation.
Note: Don’t execute ISP flash ROM program operation for the first page and the last page, or affect
program operation.
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SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
13.4 ISP PROGRAM/ERASE CONTROL REGISTER
0DBH
PECMD
Read/Write
After reset
Bit [7:0]
Bit 7
PECMD7
W
-
Bit 6
PECMD6
W
-
Bit 5
PECMD5
W
-
Bit 4
PECMD4
W
-
Bit 3
PECMD3
W
-
Bit 2
PECMD2
W
-
Bit 1
PECMD1
W
-
Bit 0
PECMD0
W
-
PECMD [7:0]: ISP operation control register.
0x5A: Page Program (32 words / page).
0xC3: Page Erase (128 words / page).
Others: Reserved.
Note: Before executing ISP program and erase operations, clear PECMD register is necessary. After ISP
configuration, set ISP operation code in “MOV A,I” and “B0MOV M,A” instructions to start ISP
operations.
13.5 ISP ROM ADDRESS REGISTER
ISP ROM address length is 16-bit and separated into PEROML and PEROMH registers. Before ISP execution, set the
head address of ISP ROM by program.
0DCH
PEROML
Read/Write
After reset
Bit [7:0]
Bit 7
PEROML7
R/W
0
Bit 5
PEROML5
R/W
0
Bit 4
PEROML4
R/W
0
Bit 3
PEROML3
R/W
0
Bit 2
PEROML2
R/W
0
Bit 1
PEROML1
R/W
0
Bit 0
PEROML0
R/W
0
PEROML[7:0]: The low byte buffer of ISP ROM address.
0DDH
Bit 7
PEROMH PEROMH7
Read/Write
R/W
After reset
0
Bit [7:0]
Bit 6
PEROML6
R/W
0
Bit 6
PEROMH6
R/W
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PEROMH5 PEROMH4 PEROMH3 PEROMH2 PEROMH1 PEROMH0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
PEROMH[7:0]: The high byte buffer of ISP ROM address.
13.6 ISP RAM ADDRESS REGISTER
ISP RAM address length is 10-bit and separated into PERAML register and PERAMCNT[1:0] bits. Before ISP
execution, set the head address of ISP RAM by program.
0DEH
PERAML
Read/Write
After reset
Bit [7:0]
Bit 7
PERAML7
R/W
0
Bit 6
PERAML6
R/W
0
Bit 5
PERAML5
R/W
0
Bit 4
PERAML4
R/W
0
Bit 3
PERAML3
R/W
0
Bit 2
PERAML2
R/W
0
Bit 1
PERAML1
R/W
0
Bit 0
PERAML0
R/W
0
Bit 4
Bit 3
Bit 2
-
Bit 1
PERAML9
R/W
0
Bit 0
PERAML8
R/W
0
PERAML[7:0]: ISP RAM address [7:0].
0DFH
Bit 7
Bit 6
Bit 5
PERAMCNT PERAMCNT7 PERAMCNT6 PERAMCNT5 PERAMCNT4 PERAMCNT3
Read/Write
After reset
Bit [1:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
PERAMCNT[1:0]: ISP RAM address [9:8].
SONiX TECHNOLOGY CO., LTD
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Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
13.7 ISP ROM PROGRAMMING LENGTH REGISTER
ISP programming length is 1-word ~ 32-word. ISP ROM programming length is controlled by PERAMCNT[7:3] bits
which is 5-bit format. Before ISP ROM programming execution, set the length by program.
0DFH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PERAMCNT PERAMCNT7 PERAMCNT6 PERAMCNT5 PERAMCNT4 PERAMCNT3
Read/Write
After reset
Bit [7:3]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit 2
-
Bit 1
PERAML9
R/W
0
Bit 0
PERAML8
R/W
0
PERAMCNT[7:3]: ISP ROM programming length control register.
ISP programming length = PERAMCNT[7:3] + 1
PERAMCNT[7:3]=0: ISP programming length is 1-word.
PERAMCNT[7:3]=1: ISP programming length is 2-word.
…
…
PERAMCNT[7:3]=30: ISP programming length is 31-word.
PERAMCNT[7:3]=31: ISP programming length is 32-word.
Note: Defines the number of words wanted to be programmed. The maximum PERAMCNT [7:3] is 01FH,
which program 32 words (64 bytes RAM) to the Flash. The minimum PERAMCNT [7:3] is 00H, which
program only 1 word to the Flash.
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SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
14 INSTRUCTION TABLE
Field
M
O
V
E
A
R
I
T
H
M
E
T
I
C
L
O
G
I
C
P
R
O
C
E
S
S
B
R
A
N
C
H
Mnemonic
MOV
A,M
MOV
M,A
B0MOV A,M
B0MOV M,A
MOV
A,I
B0MOV M,I
XCH
A,M
B0XCH
A,M
MOVC
Description
AM
MA
A M (bank 0)
M (bank 0) A
AI
M I, “M” only supports 0x80~0x87 registers (e.g. PFLAG,R,Y,Z…)
A M
A M (bank 0)
R, A ROM [Y,Z]
C
-
DC
-
Z
-
Cycle
1
1
1
1
1
1
1+N
1+N
2
ADC
ADC
ADD
ADD
B0ADD
ADD
SBC
SBC
SUB
SUB
SUB
DAA
MUL
AND
AND
AND
OR
OR
OR
XOR
XOR
XOR
COM
COMM
A,M
M,A
A,M
M,A
M,A
A,I
A,M
M,A
A,M
M,A
A,I
A A + M + C, if occur carry, then C=1, else C=0
M A + M + C, if occur carry, then C=1, else C=0
A A + M, if occur carry, then C=1, else C=0
M A + M, if occur carry, then C=1, else C=0
M (bank 0) M (bank 0) + A, if occur carry, then C=1, else C=0
A A + I, if occur carry, then C=1, else C=0
A A - M - /C, if occur borrow, then C=0, else C=1
M A - M - /C, if occur borrow, then C=0, else C=1
A A - M, if occur borrow, then C=0, else C=1
M A - M, if occur borrow, then C=0, else C=1
A A - I, if occur borrow, then C=0, else C=1
To adjust ACC’s data format from HEX to DEC.
R, A A * M, The LB of product stored in Acc and HB stored in R register. ZF affected by Acc.
A A and M
M A and M
A A and I
A A or M
M A or M
A A or I
A A xor M
M A xor M
A A xor I
A M (1’s complement).
M M (1’s complement).
-
-
1
1+N
1
1+N
1+N
1
1
1+N
1
1+N
1
1
2
1
1+N
1
1
1+N
1
1
1+N
1
1
1
SWAP
SWAPM
RRC
RRCM
RLC
RLCM
CLR
BCLR
BSET
B0BCLR
B0BSET
CMPRS
CMPRS
INCS
INCMS
INC
INCM
DECS
DECMS
DEC
DECM
BTS0
BTS1
B0BTS0
B0BTS1
TS0M
JMP
CALL
CALLHL
M
M
M
M
M
M
M
M.b
M.b
M.b
M.b
A,I
A,M
M
M
M
M
M
M
M
M
M.b
M.b
M.b
M.b
M
d
d
A (b3~b0, b7~b4) M(b7~b4, b3~b0)
M(b3~b0, b7~b4) M(b7~b4, b3~b0)
A RRC M
M RRC M
A RLC M
M RLC M
M0
M.b 0
M.b 1
M(bank 0).b 0
M(bank 0).b 1
ZF,C A - I, If A = I, then skip next instruction
ZF,C A – M, If A = M, then skip next instruction
A M + 1, If A = 0, then skip next instruction
M M + 1, If M = 0, then skip next instruction
A M + 1.
M M + 1.
A M - 1, If A = 0, then skip next instruction
M M - 1, If M = 0, then skip next instruction
A M – 1.
M M – 1.
If M.b = 0, then skip next instruction
If M.b = 1, then skip next instruction
If M(bank 0).b = 0, then skip next instruction
If M(bank 0).b = 1, then skip next instruction
If M = 0, Z = 1. Else Z = 0.
PC15/14 RomPages1/0, PC13~PC0 d
Stack PC15~PC0, PC15/14 RomPages1/0, PC13~PC0 d
Stack PC15~PC0, PC15~PC8 H register, PC7~PC0 L register
-
-
-
A,M
A,M
M,A
A,I
A,M
M,A
A,I
A,M
M,A
A,I
M
M
SONiX TECHNOLOGY CO., LTD
Page 166
-
-
1
1+N
1
1+N
1
1+N
1
1+N
1+N
1+N
1+N
1+S
1+S
1+ S
1+N+S
1
1+N
1+ S
1+N+S
1
1+N
1+S
1+S
1+S
1+S
1
2
2
2
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
CALLYZ
Stack PC15~PC0, PC15~PC8 Y register, PC7~PC0 Z register
M
RET
PC Stack
I
RETI
PC Stack, and to enable global interrupt
S
RETLW
I
PC Stack, and load I to ACC.
C
NOP
No operation
Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1.
2. If branch condition is true then “S = 1”, otherwise “S = 0”.
SONiX TECHNOLOGY CO., LTD
Page 167
-
-
-
2
2
2
2
1
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
15 ELECTRICAL CHARACTERISTIC
15.1 ABSOLUTE MAXIMUM RATING
Supply voltage (Vdd) SN8F27E60 series…………………..…………………………………………………….……………… - 0.3V ~ 6.0V
Supply voltage (Vdd) SN8F27E60L series………………..………………………..…………………………….……………… - 0.3V ~ 3.6V
Input in voltage (Vin)……………………………………………..………………………………………………….… Vss – 0.2V ~ Vdd + 0.2V
Operating ambient temperature (Topr)
SN8F27E65, SN8F27E64, SN8F27E62… ……..…………………………………………………………………..….. –40C ~ + 85C
SN8F27E65L, SN8F27E64L, SN8F27E63L , SN8F27E62L….……………………………………………………… –40C ~ + 85C
Junction temperature (Tjun) ………………….…………………………………………………………………………...…… –40C ~ + 115C
Storage ambient temperature (Tstor) ………………………………………………………………………………………… –40C ~ + 125C
15.2 ELECTRICAL CHARACTERISTIC
SN8F27E60 Series DC CHARACTERISTIC
(All of voltages refer to Vss, Vdd = 5.0V, Fosc = 16MHz, ambient temperature is 25C unless otherwise note.)
PARAMETER
SYM.
DESCRIPTION
MIN.
TYP.
1.8
-40C~85C, Fcpu = 16MHz, ISP is inactive.
Operating voltage
Vdd
2.5
-40C~85C, Fcpu = 16MHz, ISP actives.
RAM Data Retention voltage
Vdr
1.5
*Vdd rise rate
Vpor Vdd rise rate to ensure internal power-on reset
0.05
Input Low Voltage
ViL
All input ports, Reset pin, XIN/XOUT pins.
Vss
Input High Voltage
ViH
All input ports, Reset pin, XIN/XOUT pins.
0.7*Vdd
Output Low Voltage
VoL IoL1=15mA, IoL2=23mA.
Vss
Output High Voltage
VoH IoH1=10mA, IoH2=13mA.
Vdd-0.5
I/O port input leakage current
Ilekg Pull-up resistor disable, Vin = Vdd
Vin = Vss , Vdd = 3V, XIN/XOUT pins.
120
240
Rup1
Vin = Vss , Vdd = 5V, XIN/XOUT pins.
60
120
I/O port pull-up resistor
Vin = Vss , Vdd = 3V, P0/P1/P4/P5 pins.
100
200
Rup2
Vin = Vss , Vdd = 5V, P0/P1/P4/P5 pins.
50
100
IoH1 Vop = Vdd – 0.5V, XIN/XOUT pins.
5
10
I/O output source current
IoH2 Vop = Vdd – 0.5V, P0/P1/P4/P5 pins.
5
13
IoL1 Vop = Vss + 0.5V, XIN/XOUT pins.
8
15
I/O output sink current
IoL2 Vop = Vss + 0.5V, P0/P1/P4/P5 pins.
8
23
*INTn trigger pulse width
Tint0 INT0 interrupt request pulse width
2/fcpu
Vdd= 3V, Fcpu = 16MHz
6.8
Vdd= 5V, Fcpu = 16MHz
7
Vdd= 3V, Fcpu = 4MHz
2.1
Vdd= 5V, Fcpu = 4MHz
2.2
Run Mode
Idd1
(No loading)
Vdd= 3V, Fcpu = 1MHz
0.85
Vdd= 5V, Fcpu = 1MHz
0.87
Vdd= 3V, Fcpu = 32KHz/4
120
Vdd= 5V, Fcpu = 32KHz/4
140
Slow Mode
Vdd= 3V, ILRC=16KHz
110
Supply Current
Idd2 (Internal low RC,
(Disable ADC)
Vdd= 5V, ILRC=16KHz
130
Stop high clock)
Vdd= 3V
90
Idd3 Sleep Mode
Vdd= 5V
100
Vdd= 3V, IHRC=16MHz
450
Vdd= 5V, IHRC=16MHz
500
Green Mode
Vdd= 3V, Ext. 32KHz X’tal
110
Idd4 (No loading,
Vdd= 5V, Ext. 32KHz X’tal
130
Watchdog Disable)
Vdd= 3V, ILRC=16KHz
110
Vdd= 5V, ILRC=16KHz
120
15.68
16
25C, Vdd=2.4V~ 5.5V
Internal Hihg RC
Internal High Oscillator Freq.
Fihrc
(IHRC)
15.4
16
-40C~85C,Vdd=2.4V~ 5.5V
1.7
1.8
Low voltage reset level. 25C
Vdet0
1.6
1.8
Low voltage reset level. -40C~85C
2.3
2.4
Low voltage reset/indicator level. 25C
LVD Voltage
Vdet1
2.2
2.4
Low voltage reset/indicator level. -40C~85C
3.2
3.3
Low voltage reset/indicator level. 25C
Vdet2
3.1
3.3
Low voltage reset/indicator level. -40C~85C
MAX.
5.5
5.5
0.3*Vdd
Vdd
Vss+0.5
Vdd
2
360
180
300
150
-
UNIT
V
V
V
V/ms
V
V
V
V
uA
-
uA
16.32
16.5
1.9
2.0
2.5
2.6
3.4
3.5
uA
uA
uA
uA
uA
uA
uA
uA
MHz
MHz
V
V
V
V
V
V
K
mA
cycle
mA
mA
mA
mA
mA
mA
uA
uA
uA
“ *” These parameters are for design reference, not tested.
SONiX TECHNOLOGY CO., LTD
Page 168
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
SN8F27E60L Series DC CHARACTERISTIC
(All of voltages refer to Vss, Vdd = 3.0V, Fosc = 16MHz, ambient temperature is 25C unless otherwise note.)
PARAMETER
SYM.
DESCRIPTION
MIN.
TYP.
1.8
3.0
-40C~85C, Fcpu = 16MHz, ISP is inactive.
Operating voltage
Vdd
2.5
3.0
-40C~85C, Fcpu = 16MHz, ISP actives.
RAM Data Retention voltage
Vdr
1.5
*Vdd rise rate
Vpor Vdd rise rate to ensure internal power-on reset
0.05
Input Low Voltage
ViL
All input ports, Reset pin, XIN/XOUT pins.
Vss
Input High Voltage
ViH
All input ports, Reset pin, XIN/XOUT pins.
0.7*Vdd
Output Low Voltage
VoL IoL1=9mA, IoL2=14mA.
Vss
Output High Voltage
VoH IoH1=7mA, IoH2=8mA.
Vdd-0.5
I/O port input leakage current
Ilekg Pull-up resistor disable, Vin = Vdd
Rup1 Vin = Vss , XIN/XOUT pins.
120
240
I/O port pull-up resistor
Rup2 Vin = Vss , P0/P1/P4/P5 pins.
100
200
IoH1 Vop = Vdd – 0.5V, XIN/XOUT pins.
3
7
I/O output source current
IoH2 Vop = Vdd – 0.5V, P0/P1/P4/P5 pins.
4
8
IoL1 Vop = Vss + 0.5V, XIN/XOUT pins.
4
9
I/O output sink current
IoL2 Vop = Vss + 0.5V, P0/P1/P4/P5 pins.
7
14
*INTn trigger pulse width
Tint0 INT0 interrupt request pulse width
2/fcpu
Vdd= 3V, Fcpu = 16MHz
7
Vdd= 3V, Fcpu = 4MHz
1.9
Run Mode
Idd1
(No loading)
Vdd= 3V, Fcpu = 1MHz
0.73
Vdd= 3V, Fcpu = 32KHz/4
35
Slow Mode
Supply Current
Idd2 (Internal low RC,
Vdd= 3V, ILRC=16KHz
25
(Disable ADC)
Stop high clock)
Idd3 Sleep Mode
Vdd= 3V
1
Vdd= 3V, IHRC=16MHz
400
Green Mode
Idd4 (No loading,
Vdd= 3V, Ext. 32KHz X’tal
20
Watchdog Disable) Vdd= 3V, ILRC=16KHz
5
15.68
16
25C, Vdd=2.4V~ 3.3V
Internal Hihg RC
Internal High Oscillator Freq.
Fihrc
(IHRC)
15.4
16
-40C~85C,Vdd=2.4V~ 3.3V
1.7
1.8
Low voltage reset level. 25C
Vdet0
1.6
1.8
Low voltage reset level. -40C~85C
2.3
2.4
Low voltage reset/indicator level. 25C
LVD Voltage
Vdet1
2.2
2.4
Low voltage reset/indicator level. -40C~85C
3.2
3.3
Low voltage reset/indicator level. 25C
Vdet2
3.1
3.3
Low voltage reset/indicator level. -40C~85C
MAX.
3.3
3.3
0.3*Vdd
Vdd
Vss+0.5
Vdd
2
360
300
-
UNIT
V
V
V
V/ms
V
V
V
V
uA
-
uA
3
16.32
16.5
1.9
2.0
2.5
2.6
3.4
3.5
uA
uA
uA
uA
MHz
MHz
V
V
V
V
V
V
K
mA
cycle
mA
mA
mA
uA
“ *” These parameters are for design reference, not tested.
ADC CHARACTERISTIC
(All of voltages refer to Vss, Vdd = 5.0V, Fosc = 4MHz,Fcpu=1MHz,ambient temperature is 25C unless otherwise note.)
PARAMETER
SYM.
DESCRIPTION
MIN.
TYP.
MAX.
UNIT
AIN0 ~ AIN11 input voltage
Vani
Vdd = 5.0V
0
Avrefh
V
ADC reference Voltage
Vref
2
V
*ADC enable time
Tast
Ready to start convert after set ADENB = “1”
100
us
Vdd=5.0V
0.6
mA
*ADC current consumption
IADC
Vdd=3.0V
0.4
mA
VDD=5.0V
8M
Hz
ADC Clock Frequency
FADCLK
VDD=3.0V
5M
Hz
ADC Conversion Cycle Time
FADCYL VDD=2.4V~5.5V
64
1/FADCLK
VDD=5.0V
125
K/sec
ADC Sampling Rate
FADSMP
(Set FADS=1 Frequency)
VDD=3.0V
80
K/sec
Differential Nonlinearity
DNL VDD=5.0V , AVREFH=3.2V, FADSMP =7.8K
-1
+1
LSB
Integral Nonlinearity
INL
VDD=5.0V , AVREFH=3.2V, FADSMP =7.8K
-1
+1
LSB
No Missing Code
NMC VDD=5.0V , AVREFH=3.2V, FADSMP =7.8K
9
10
Bits
Non-trimmed
-10
0
+10
mV
ADC offset Voltage
VADCoffset
Trimmed
-2
0
+2
mV
“ *” These parameters are for design reference, not tested.
SONiX TECHNOLOGY CO., LTD
Page 169
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
FLASH MEMORY CHARACTERISTIC
(All of voltages refer to Vss, Vdd = 5.0V, Fosc = 4MHz,Fcpu=1MHz,ambient temperature is 25C unless otherwise note.)
PARAMETER
SYM.
DESCRIPTION
MIN.
TYP.
MAX.
Read mode
1.8
Vdd
Supply Voltage
Vdd1
Erase/Program
2.5
Vdd
Ten1 Erase + Program, -10C~85C
20K
*100K
Endurance time
Ten2 Erase + Program, -40C~-10C
20K
*70K
Page erase current
Ier
Vdd1=2.5V
2.5
5
Program current
Ipg
Vdd1=2.5V
3.5
7
Page erase time
Ter
Vdd = 2.5V, 1-page (128-word).
30
Tpg1 Vdd = 2.5V, ISP setup time.
380
Program time
Tpg2 Vdd = 2.5V, 1-word program.
30
UNIT
V
V
Cycle
Cycle
mA
mA
ms
us
us
“ *” These parameters are for design reference, not tested.
15.3 CHARACTERISTIC GRAPHS
The Graphs in this section are for design guidance, not tested or guaranteed. In some graphs, the data presented are
outside specified operating range. This is for information only and devices are guaranteed to operate properly only
within the specified range.
SONiX TECHNOLOGY CO., LTD
Page 170
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
16 DEVELOPMENT TOOL
SONIX provides an Embedded ICE emulator system to offer SN8F27E65 firmware development. The platform is a
in-circuit debugger and controlled by SONIX M2IDE software on Microsoft Windows platform. The platform includes
Smart Development Adapter, SN8F27E65 Starter-kit and M2IDE software to build a high-speed, low cost, powerful and
multi-task development environment including emulator, debugger and programmer. To execute emulation is like run
real chip because the emulator circuit integrated in SN8F27E65 to offer a real development environment.
SN8F27E65 Embedded ICE Emulator System:
SN8F27E65
Starter-kit
Modular Cable to
Starter-kit or
Target Board
USB Cable to PC
Sonix Embedded ICE
Smart Development Adapter
Sonix IDE/C-Studio
SN8F27E65 Embedded ICE Emulator includes:
Smart Development Adapter.
USB cable to provide communications between the Smart Development Adapter and a PC.
SN8F27E65 Starter-Kit.
Modular cable to connect the Smart Development Adapter and SN8F27E65 Starter-Kit or target board.
CD-ROM with M2IDE software (M2IDE V124 or greater).
SN8F27E65 Embedded ICE Emulator Feature:
Target’s Operating Voltage: 1.8V~5.5V.
Up to 6 hardware break points.
System clock rate up to 16MHz (Fcpu=16mips).
Oscillator supports internal high speed RC, internal low speed RC, external crystal/resonator and external RC.
SN8F27E65 Embedded ICE Emulator Limitation:
EIDA and EICK pins are shared with GPIO pins. In embedded ICE mode, the shared GPI function can’t work. We
strongly recommend planning the two pins as simple function which can be verified without debugger platform.
SONiX TECHNOLOGY CO., LTD
Page 171
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
16.1 SMART DEVELOPMENT ADAPTER
Smart Development Adapter is a high speed emulator for Sonix Embedded ICE type flash MCU. It debugs and
programs Sonix flash MCU and transfers MCU’s system status, RAM data and system register between M2IDE and
Sonix flash MCU through USB interface. The other terminal connected to SN8F27E65 Starter-kit or Target board is a
4-wire serial interface. In addition to debugger functions, the Smart Starter-Kit system also may be used as a
programmer to load firmware from PC to MCU for engineering production, even mass production.
Smart Development Adapter communication with SN8F27E65 flash MCU is through a 4-wire bus. The pin definition of
the Modular cable is as following:
VSS
EIDA
EICK
VDD
Application
Target Board
IC Socket
The modular cable can be inserted into SN8F27E65 Starter-Kit plugged into the target board or inserted into a
matching socket at the target device on the target board.
SN8F27E65
Starter-kit
USB Cable to PC
Modular Cable
I/O connectors
connect to
IC Socket of target
Sonix Embedded ICE
Smart Development Adapter
If the target board of application is designed and ready, the modular cable can be inserted into the target directly to
replace SN8F27E65 Starter-Kit. Design the 4-wire interface connected with SN8F27E65 IC to build a real application
environment. In the mode, set SN8F27E65 IC on the target is necessary, or the emulation would be error without MCU.
Embedded ICE
4-wire Interface
SN8F27E65
Real Chip
Application
Target Board
USB Cable to PC
Modular Cable to
Starter-kit or
Target Board
Sonix Embedded ICE
Smart Development Adapter
EIDA and EICK share with P1.0/P1.1 GPIO. In emulation mode, EIDA and EICK are Embedded ICE interface and not
execute GPIO functions. The P1.0/P1.1 GPIO status still display on M2IDE window to simulate P1.0/P1.1 program
execution.
SONiX TECHNOLOGY CO., LTD
Page 172
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
16.2 SN8F27E65 STARTER-KIT
SN8F27E65 Starter-kit is an easy-development platform. It includes SN8F27E65 real chip and I/O connectors to input
signal or drive extra device of user’s application. It is a simple platform to develop application as target board not ready.
The starter-kit can be replaced by target board, because SN8F27E65 integrates embedded ICE in-circuit debugger
circuitry. The schematic and outline of SN8F27E65 Starter-Kit is as following:
J1
DC 7.5V
U1 7805CT
D1
1
2
1
IN
OUT
3
C1
100u/16V
GND
1N4004
C2
0.1u
VDD_50
JP2
C3
22u/16V
VDD_50
VDD
VDD_33
VDD_EXT
C4
0.1u
VDD_50
VDD_SW
VDD_33
VDD_Ext
2
VSS
3
JP1
VDD_Ext
VDD_Ext
VDD_Ext
VDD_Ext
1
2
3
4
1
2
3
4
VDD_EXT
SW1
VDD_SW 1
U2
AIC1117_33
VIN
2
VDD
1
3
5
7
9
POWER
2
VOUT
VDD_33
D2
PWR LED
GND
VDD_50 3
JP4
D3
MCU LED
C5
JP3
2
4
6
8
10
VSS
P1.1
P1.0
VDD
VSS
VSS
VSS
VSS
1
2
3
4
VSS
DEBUG
1
22u/16V
R1
470
VSS
R2
470
VSS
VSS
U3
P0.3
P0.2
P0.1
P0.0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P5.3
P5.2
P5.1
P5.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P0.3
P0.2
P0.1
P0.0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P5.3
P5.2
P5.1
P5.0
P0.4
P0.5
P0.6
VSS
VREG
VDD3V
AVDD/VDD
AVREFH
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P0.4
P0.5
P0.6
VSS
VDD3V
VDD3V
AVREFH
VDD
VDD
JP5
C6
0.1u
VDD
AVREFH
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
C7
10u
C8
0.1u
VSS
C9
10u
R3
47K
VSS
R4
R
P0.0
P0.2
P0.4
P0.6
P0.4
P0.6
VDD
2
4
6
8
P0.1
P0.3
P0.5
VSS
JP9
URXP0.2
SDA P1.2
PORT0
1
3
P0.3 UTX
P1.3 SCL
2
4
UART/MSP
Y1
P0.5
P0.6
SW2
16M
C12
0.1u
1
3
5
7
C13
10u
C14
20p
C15
20p
VSS
C10
0.1u
RESET
VSS
JP6
C11
CAP
VSS
P1.0
P1.2
P1.4
P1.6
VSS
1
3
5
7
2
4
6
8
P1.1
P1.3
P1.5
P1.7
JP10
SDOP1.4
SCK P1.6
1
3
P1.5 SDI
P1.7 SCS
2
4
SIO
PORT1
SN8F27E65F
JP7
P4.0
P4.1
C16
0.1u
P4.2
C17
0.1u
P4.0
P4.2
P4.4
P4.6
P4.3
C18
0.1u
C19
0.1u
1
3
5
7
JP11
2
4
6
8
P4.1
P4.3
P4.5
P4.7
PWM0 P5.1
PWM2 P5.3
PORT4
JP12
JP8
P4.5
P5.2 PWM1
VSS
2
4
PWM
VSS
P4.4
1
3
P4.6
P4.7
P5.0
P5.1
P5.2
P5.0
P5.2
P5.3
1
3
2
4
P5.1
P5.3
VDD VDD
AVREFH AVREFH
1
3
VDD
AVREFH
2
4
VDD/AVREFH
PORT5
C20
0.1u
C21
0.1u
C22
0.1u
C23
0.1u
C24
0.1u
VSS
C25
0.1u
C26
0.1u
C27
0.1u
VSS
J1: DC 7.5V power adapter.
JP2: VDD power source is 5.0V or 3.3V or external power.
JP1/JP3: External power source.
SW1: Target power switch.
U3: SN8F27E65F real chip (Sonix standard option).
D2: Power LED.
D3: MCU LED.
C16~C27: 12-ch ADC capacitors.
SW2: External reset trigger source.
JP5~JP11: I/O connector.
Y1, C14, C15: External crystal/resonator oscillator components.
R4, C11: External RC type oscillator components.
JP12: VDD test pad and AVREFH connector.
SONiX TECHNOLOGY CO., LTD
Page 173
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
16.3 EMULATOR/DEBUGGER INSTALLATION
Install the M2IDE Software (V124 or greater).
Connect Smart Development Adapter with PC plugging in USB cable.
USB Cable to PC
Sonix Embedded ICE
Smart Development Adapter
Sonix IDE/C-Studio
Attach the modular cable between Smart Development Adapter and SN8F27E65 Starter-kit or target.
Embedded ICE
4-wire Interface
SN8F27E65
Starter-kit
SN8F27E65
Real Chip
Modular Cable to
Starter-kit or
Target Board
Sonix Embedded ICE
Smart Development Adapter
Application
Target Board
Modular Cable to
Starter-kit or
Target Board
Connect the power supplier to SN8F27E65 Starter-kit or target, and turn off the power.
Open M2IDE software and load firmware program (A project or a “.ASM” file).
Turn on the power switch of SN8F27E65 Starter-kit or target.
Embedded ICE emulator platform is installed, and start to execute debugger.
SONiX TECHNOLOGY CO., LTD
Page 174
Sonix Embedded ICE
Smart Development Adapter
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
16.4 PROGRAMMER INSTALLATION
Setup emulator/debugger environment first.
Compile the firmware program and generate a “.SN8” file.
Execute download (F8) function of M2IDE.
Open a “.SN8” file and press “Enter” to download firmware to SN8F27E65 Starter-kit or target.
Turn off the power of SN8F27E65 Starter-kit or target.
Disconnect SN8F27E65 Starter-kit or target from Smart Development Adapter.
Turn on the power of SN8F27E65 Starter-kit or target, and MCU works independently.
SONiX TECHNOLOGY CO., LTD
Page 175
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
17 ROM PROGRAMMING PIN
SN8F27E60 series MCUs Flash ROM erase/program/verify support SDA, MP-Pro writer and MP-III writer.
SDA: Embedded ICE interface.
MP-Pro writer: Plug on SN8F27E60 MCUs directly.
MP-III writer: For “L” version, the bias circuit must be set on the writer transition board.
17.1 MP-III WRITER TRANSITION BOARD SOCKET PIN ASSIGNMENT
MP-III Writer Transition Board:
Pin 1
Bias Circuit:
VDD
Connect to the VDD pin
of MP-III transition board.
Pin 48
48
75Ω
40
40
Bias Voltage
28
28
150Ω
18
18
14
Pin 25
GND
Connect to the GND pin
of MP-III transition board.
Pin 24
JP3 (Mapping to 48-pin text tool):
DIP 1
1
48
DIP48
DIP 2
2
47
DIP47
DIP 3
3
46
DIP46
DIP 4
4
45
DIP45
DIP 5
5
44
DIP44
DIP 6
6
43
DIP43
DIP 7
7
42
DIP42
DIP 8
8
41
DIP41
DIP 9
9
40
DIP40
DIP10
10
39
DIP39
DIP11
11
38
DIP38
DIP12
12
37
DIP37
DIP13
13
36
DIP36
DIP14
14
35
DIP35
DIP15
15
34
DIP34
DIP16
16
33
DIP33
DIP17
17
32
DIP32
DIP18
18
31
DIP31
DIP19
19
30
DIP30
DIP20
20
29
DIP29
DIP21
21
28
DIP28
DIP22
22
27
DIP27
DIP23
23
26
DIP26
DIP24
24
25
DIP25
SONiX TECHNOLOGY CO., LTD
Writer JP1/JP2:
VDD
1
2
GND
CLK
3
4
CE
PGM
5
6
OE
D1
7
8
D0
D3
9
10 D2
D5 11 12 D4
D7 13 14 D6
VDD 15 16 VPP
HLS 17 18 RST
- 19 20 ALSB/PDB
JP1 for Writer transition board
JP2 for dice and >48 pin package
Page 176
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
17.2 MP-III WRITER PROGRAMMING PIN MAPPING:
Chip Name
Writer Connector
JP1/JP2
JP1/JP2
Pin Number
Pin Name
1
VDD
2
GND
3
CLK
4
CE
5
PGM
6
OE
7
D1
8
D0
9
D3
10
D2
11
D5
12
D4
13
D7
14
D6
15
VDD
16
VPP
17
HLS
18
RST
19
20
ALSB/PDB
Bias Voltage
Chip Name
Writer Connector
JP1/JP2
JP1/JP2
Pin Number
Pin Name
1
VDD
2
GND
3
CLK
4
CE
5
PGM
6
OE
7
D1
8
D0
9
D3
10
D2
11
D5
12
D4
13
D7
14
D6
15
VDD
16
VPP
17
HLS
18
RST
19
20
ALSB/PDB
Bias Voltage
Programming Pin Information of SN8F27E65 Series
SN8F27E65P/U(DIP/S-DIP)
SN8F27E65LP/U(DIP/S-DIP)
IC and JP3 48-pin text tool Pin Assignment
IC
IC
JP3
IC
IC
JP3
Pin Number
Pin Name
Pin Number
Pin Number
Pin Name
Pin Number
30
VDD
38
31
VDD
39
1
VSS
9
1
VSS
9
23
P4.5
31
23
P4.5
31
22
P4.6
30
22
P4.6
30
21
P4.7
29
21
P4.7
29
20
P5.0
28
20
P5.0
28
32
VDD
40
Programming Pin Information of SN8F27E65 Series
SN8F27E65F(LQFP)
SN8F27E65LF(LQFP)
SN8F27E65J(QFN)
SN8F27E65LJ(QFN)
IC and JP3 48-pin text tool Pin Assignment
IC
IC
JP3
IC
IC
JP3
Pin Number
Pin Name
Pin Number
Pin Number
Pin Name
Pin Number
26
VDD
34
27
VDD
35
29
VSS
37
29
VSS
37
19
P4.5
27
19
P4.5
27
18
P4.6
26
18
P4.6
26
17
P4.7
25
17
P4.7
25
16
P5.0
24
16
P5.0
24
28
VDD
36
SONiX TECHNOLOGY CO., LTD
Page 177
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
Chip Name
Writer Connector
JP1/JP2
JP1/JP2
Pin Number
Pin Name
1
VDD
2
GND
3
CLK
4
CE
5
PGM
6
OE
7
D1
8
D0
9
D3
10
D2
11
D5
12
D4
13
D7
14
D6
15
VDD
16
VPP
17
HLS
18
RST
19
20
ALSB/PDB
Bias Voltage
Programming Pin Information of SN8F27E65 Series
SN8F27E64K/S/X(SKDIP/SOP/SSOP)
SN8F27E64LK/S/X(SKDIP/SOP/SSOP)
IC and JP3 48-pin text tool Pin Assignment
IC
IC
JP3
IC
IC
JP3
Pin Number
Pin Name
Pin Number
Pin Number
Pin Name
Pin Number
27
VDD
37
27
VDD
37
1
VSS
11
1
VSS
11
22
P4.5
32
22
P4.5
32
21
P4.6
31
21
P4.6
31
20
P4.7
30
20
P4.7
30
19
P5.0
29
19
P5.0
29
28
VDD
38
Chip Name
Writer Connector
JP1/JP2
JP1/JP2
Pin Number
Pin Name
1
VDD
2
GND
3
CLK
4
CE
5
PGM
6
OE
7
D1
8
D0
9
D3
10
D2
11
D5
12
D4
13
D7
14
D6
15
VDD
16
VPP
17
HLS
18
RST
19
20
ALSB/PDB
Bias Voltage
Programming Pin Information of SN8F27E65 Series
SN8F27E64J(QFN)
SN8F27E64LJ(QFN)
IC and JP3 48-pin text tool Pin Assignment
IC
IC
JP3
IC
IC
JP3
Pin Number
Pin Name
Pin Number
Pin Number
Pin Name
Pin Number
23
VDD
33
23
VDD
33
25
VSS
35
25
VSS
35
18
P4.5
28
18
P4.5
28
17
P4.6
27
17
P4.6
27
16
P4.7
26
16
P4.7
26
15
P5.0
25
15
P5.0
25
24
VDD
34
SONiX TECHNOLOGY CO., LTD
Page 178
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
Chip Name
Writer Connector
JP1/JP2
JP1/JP2
Pin Number
Pin Name
1
VDD
2
GND
3
CLK
4
CE
5
PGM
6
OE
7
D1
8
D0
9
D3
10
D2
11
D5
12
D4
13
D7
14
D6
15
VDD
16
VPP
17
HLS
18
RST
19
20
ALSB/PDB
Bias Voltage
Programming Pin Information of SN8F27E65 Series
SN8F27E62P/S(PDIP/SOP)
SN8F27E62LP/S(PDIP/SOP)
IC and JP3 48-pin text tool Pin Assignment
IC
IC
JP3
IC
IC
JP3
Pin Number
Pin Name
Pin Number
Pin Number
Pin Name
Pin Number
19
VDD
33
19
VDD
33
1
VSS
15
1
VSS
15
16
P4.5
30
16
P4.5
30
15
P4.6
29
15
P4.6
29
14
P4.7
28
14
P4.7
28
13
P5.0
27
13
P5.0
27
20
VDD
34
Chip Name
Writer Connector
JP1/JP2
JP1/JP2
Pin Number
Pin Name
1
VDD
2
GND
3
CLK
4
CE
5
PGM
6
OE
7
D1
8
D0
9
D3
10
D2
11
D5
12
D4
13
D7
14
D6
15
VDD
16
VPP
17
HLS
18
RST
19
20
ALSB/PDB
Bias Voltage
Programming Pin Information of SN8F27E65 Series
SN8F27E63LJ(QFN)
IC and JP3 48-pin text tool Pin Assignment
IC
IC
JP3
IC
IC
Pin Number
Pin Name
Pin Number
Pin Number
Pin Name
21
VSS
33
17
P4.5
29
16
P4.6
28
15
P4.7
27
13
P5.0
25
20
VDD
32
SONiX TECHNOLOGY CO., LTD
Page 179
JP3
Pin Number
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
18 Marking Definition
18.1 INTRODUCTION
There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit
MCU for order or obtain information. This definition is only for Blank Flash ROM MCU.
18.2 MARKING INDETIFICATION SYSTEM
SN8 X PART No. X X X
Material
B = PB-Free Package
G = Green Package
Temperature
Range
Shipping
Package
Device
SONiX TECHNOLOGY CO., LTD
- = -40℃ ~ 85℃
W=Wafer, H=Dice
P=P-DIP, K=SKDIP
S=SOP, X=SSOP
F=LQFP, J=QFN
27E65, 27E65L
27E64, 27E64L
27E63L
27E62, 27E62L
ROM Type
F = Flash
Title
SONiX 8-bit MCU Production
Page 180
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
18.3 MARKING EXAMPLE
Wafer, Dice:
Name
S8F27E65W
SN8F27E65H
Device
27E65
27E65
Package
Wafer
Dice
Temperature
-40℃~85℃
-40℃~85℃
Material
-
Device
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
Package
P-DIP
LQFP
QFN
S-DIP
P-DIP
LQFP
QFN
S-DIP
SK-DIP
SOP
SSOP
QFN
SK-DIP
SOP
SSOP
QFN
QFN
P-DIP
SOP
P-DIP
SOP
Temperature
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
Material
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Green Package
Device
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
27E65
Package
P-DIP
LQFP
QFN
S-DIP
P-DIP
LQFP
QFN
S-DIP
SK-DIP
SOP
SSOP
QFN
SK-DIP
SOP
SSOP
QFN
QFN
P-DIP
SOP
Temperature
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
-40℃~85℃
Material
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
PB-Free Package
Green Package:
Name
SN8F27E65PG
SN8F27E65FG
SN8F27E65JG
SN8F27E65UG
SN8F27E65LPG
SN8F27E65LFG
SN8F27E65LJG
SN8F27E65LUG
SN8F27E64KG
SN8F27E64SG
SN8F27E64XG
SN8F27E64JG
SN8F27E64LKG
SN8F27E64LSG
SN8F27E64LXG
SN8F27E64LJG
SN8F27E63LJG
SN8F27E62PG
SN8F27E62SG
SN8F27E62LPG
SN8F27E62LSG
ROM Type
FLASH
FLASH
ROM Type
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
PB-Free Package:
Name
SN8F27E65PB
SN8F27E65FB
SN8F27E65JB
SN8F27E65UB
SN8F27E65LPB
SN8F27E65LFB
SN8F27E65LJB
SN8F27E65LUB
SN8F27E64KB
SN8F27E64SB
SN8F27E64XB
SN8F27E64JB
SN8F27E64LKB
SN8F27E64LSB
SN8F27E64LXB
SN8F27E64LJB
SN8F27E63LJB
SN8F27E62PB
SN8F27E62SB
ROM Type
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
SONiX TECHNOLOGY CO., LTD
Page 181
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
SN8F27E62LPB
SN8F27E62LSB
FLASH
FLASH
27E65
27E65
P-DIP
SOP
-40℃~85℃
-40℃~85℃
PB-Free Package
PB-Free Package
18.4 DATECODE SYSTEM
X X X X XXXXX
SONiX Internal Use
Day
1=01
2=02
....
9=09
A=10
B=11
....
Month
1=January
2=February
....
9=September
A=October
B=November
C=December
Year
SONiX TECHNOLOGY CO., LTD
03= 2003
04= 2004
05= 2005
06= 2006
....
Page 182
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
19 PACKAGE INFORMATION
19.1 P-DIP 32 PIN
SYMBOLS
MIN
NOR
MAX
MIN
(inch)
A
A1
A2
D
E
E1
L
0.015
0.150
1.645
MAX
(mm)
0.220
0.160
1.660
0.381
3.81
41.783
0.540
0.115
0.155
1.650
0.600 BSC
0.545
0.130
0.550
0.150
ｅB
0.630
0.650
θ°
0°
7°
SONiX TECHNOLOGY CO., LTD
NOR
5.588
4.064
42.164
13.716
2.921
3.937
41.91
15.24 BSC
13.843
3.302
0.670
16.002
16.51
17.018
15°
0°
7°
15°
Page 183
13.97
3.81
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
19.2 LQFP 32 PIN
SYMBOLS
A
A1
A2
c1
D
D1
MIN
NOR
MAX
MIN
(inch)
0.002
0.053
0.004
NOR
MAX
(mm)
BSC E
0.004
0.055
0.005
0.354 BSC
0.276 BSC
0.354 BSC
0.063
0.006
0.057
0.006
0.05
1.35
0.09
0.1
1.4
0.125
9 BSC
7 BSC
9 BSC
E1
0.276 BSC
7 BSC
e
0.031 BSC
0.8 BSC
1.6
0.15
1.45
0.16
b
0.012
0.015
0.018
0.3
0.375
0.45
L
0.018
0.024
0.030
0.45
0.6
0.75
L1
0.039 REF
SONiX TECHNOLOGY CO., LTD
1 REF
Page 184
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
19.3 QFN 5X5 32 PIN
A
A1
A3
b
D
E
e
L
K
0.028
0.000
0.014
0.008
NOR
(inch)
0.030
0.001
0.008 REF.
0.010
0.200
0.200
0.02 BSC
0.016
-
PAD SIZE
114x114 MIL
134x134 MIL
MIN
2.60
3.10
D2 (mm)
NOR
2.70
3.20
SYMBOLS
MIN
0.007
0.193
0.193
SONiX TECHNOLOGY CO., LTD
MAX
MIN
0.031
0.002
0.70
0.000
0.012
0.201
0.201
0.180
4.90
4.90
0.018
-
0.350
0.20
NOR
(mm)
0.75
0.020
0.203 REF.
0.250
5.00
5.00
0.50 BSC
0.400
-
MAX
2.75
3.25
MIN
2.60
3.10
E2 (mm)
NOR
2.70
3.20
Page 185
MAX
0.80
0.050
0.300
5.10
5.10
0.450
-
MAX
2.75
3.25
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
19.4 S-DIP 32 PIN
SYMBOLS
A
A1
A2
A3
b
b1
B1
c
c1
D
E1
e
eA
eB
eC
L
MIN
0.165
0.043
0.126
0.058
0.017
0.017
0.010
0.009
1.094
0.343
0.400
0.000
0.118
NOR
(inch)
0.173
0.130
0.060
0.018
0.039BSC
0.010
1.102
0.350
0.07BSC
0.4BSC
-
SONiX TECHNOLOGY CO., LTD
MAX
MIN
0.181
0.134
0.062
0.021
0.019
4.20
1.10
3.20
1.47
0.44
0.43
0.012
0.010
1.110
0.358
0.25
0.24
27.8
8.70
0.466
0.033
-
10.16
0
3.00
Page 186
NOR
(mm)
4.40
3.30
1.52
0.46
1.00BSC
0.25
28.00
8.90
1.778BSC
10.16BSC
-
MAX
4.60
3.40
1.57
0.53
0.48
0.31
0.26
28.20
9.10
11.84
0.84
-
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
19.5 SK-DIP 28 PIN
SYMBOLS
MIN
NOR
MAX
MIN
(inch)
A
A1
A2
D
E
E1
L
0.015
0.114
1.390
MAX
(mm)
0.210
0.135
1.400
0.381
2.896
35.306
0.283
0.115
0.130
1.390
0.310
0.288
0.130
0.293
0.150
ｅB
0.330
0.350
θ°
0°
7°
SONiX TECHNOLOGY CO., LTD
NOR
5.334
3.429
35.560
7.188
2.921
3.302
35.306
7.874
7.315
3.302
0.370
8.382
8.890
9.398
15°
0°
7°
15°
Page 187
7.442
3.810
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
19.6 SOP 28 PIN
SYMBOLS
A
A1
D
E
H
L
θ°
MIN
NOR
MAX
MIN
(inch)
0.093
0.004
0.697
0.291
0.394
0.016
0°
SONiX TECHNOLOGY CO., LTD
0.099
0.008
0.705
0.295
0.407
0.033
4°
NOR
MAX
(mm)
0.104
0.012
0.713
0.299
0.419
0.050
8°
Page 188
2.362
0.102
17.704
7.391
10.008
0.406
0°
2.502
0.203
17.907
7.493
10.325
0.838
4°
2.642
0.305
18.110
7.595
10.643
1.270
8°
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
19.7 SSOP 28 PIN
SYMBOLS
A
A1
A2
b
C
D
E
E1
[e]
L
R
θ°
MIN
0.00
0.06
0.01
0.00
0.39
0.29
0.20
0.02
0.00
0°
NOR
(inch)
0.07
0.40
0.31
0.21
0.0259BSC
0.04
4°
SONiX TECHNOLOGY CO., LTD
MAX
MIN
0.08
0.01
0.07
0.01
0.01
0.41
0.32
0.22
0.05
1.63
0.22
0.09
9.90
7.40
5.00
0.04
8°
0.63
0.09
0°
Page 189
NOR
(mm)
1.75
10.20
7.80
5.30
0.65BSC
0.90
4°
MAX
2.13
0.25
1.88
0.38
0.20
10.50
8.20
5.60
1.03
8°
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
19.8 QFN 4X4 28 PIN
SYMBOLS
A
A1
A3
b
D
E
e
L
K
PAD SIZE
115x115 MIL
MIN
0.014
0.008
NOR
(inch)
0.030
0.001
0.008 REF.
0.008
0.16 BSC
0.16 BSC
0.016 BSC
0.016
-
MIN
2.50
D2 (mm)
NOR
2.60
0.003
0.000
0.006
SONiX TECHNOLOGY CO., LTD
MAX
MIN
0.031
0.002
0.07
0.00
0.010
0.15
0.018
-
0.35
0.20
MAX
2.65
Page 190
MIN
2.50
NOR
(mm)
0.75
0.02
0.20 REF.
0.20
4.00 BSC
4.00 BSC
0.40 BSC
0.40
E2 (mm)
NOR
2.60
MAX
0.80
0.05
0.25
0.45
-
MAX
2.65
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
19.9 QFN 4X4 24 PIN
SONiX TECHNOLOGY CO., LTD
Page 191
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
19.10 P-DIP 20 PIN
SYMBOLS
MIN
NOR
MAX
MIN
(inch)
A
A1
A2
D
E
E1
L
0.015
0.125
0.980
MAX
(mm)
0.210
0.135
1.060
0.381
3.175
24.892
0.245
0.115
0.130
1.030
0.300
0.250
0.130
0.255
0.150
ｅB
0.335
0.355
θ°
0°
7°
SONiX TECHNOLOGY CO., LTD
NOR
5.334
3.429
26.924
6.223
2.921
3.302
26.162
7.620
6.350
3.302
0.375
8.509
9.017
9.525
15°
0°
7°
15°
Page 192
6.477
3.810
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
19.11 SOP 20 PIN
SYMBOLS
A
A1
D
E
H
L
θ°
MIN
NOR
MAX
MIN
(inch)
0.093
0.004
0.496
0.291
0.394
0.016
0°
SONiX TECHNOLOGY CO., LTD
0.099
0.008
0.502
0.295
0.407
0.033
4°
NOR
MAX
(mm)
0.104
0.012
0.508
0.299
0.419
0.050
8°
Page 193
2.362
0.102
12.598
7.391
10.008
0.406
0°
2.502
0.203
12.751
7.493
10.325
0.838
4°
2.642
0.305
12.903
7.595
10.643
1.270
8°
Version 2.1
SN8F27E60 Series
8-Bit Flash Micro-Controller with Embedded ICE and ISP
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or
design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed,
intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a
situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such
unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries,
affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising
out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use
even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
Corporate Headquarters:
10F-1, No.36, Taiyuan Street, Chupei City, Hsinchu, Taiwan
TEL :(886)3-5600-888 FAX :(886)3-5600-889
Taipei Sales Office:
15F-2, No.171 Song Ted Road, Taipei, Taiwan
TEL:(886)2-2759-1980 FAX:(886)2-2759-8180
mkt@sonix.com.tw | sales@sonix.com.tw
Hong Kong Sales Office:
Unit 2603, 26/F CCT Telecom Building, No. 11 Wo Shing Street,
Fo Tan, New Territories, Hong Kong
TEL:(852)2723-8086 FAX:(852)2723-9179
hk@sonix.com.tw
Shenzhen Contact Office:
High Tech Industrial Park, Shenzhen, China
TEL:(86)755-2671-9666 FAX:(86)755-2671-9786
mkt@sonix.com.tw | sales@sonix.com.tw
Sonix Japan Office:
Kobayashi bldg. 2F, 4-8-27,Kudanminami, Chiyodaku,Tokyo,
102-0074, Japan
TEL:(81)3-6272-6070 FAX:(81)3-6272-6165
jpsales@sonix.com.tw
FAE Support via Email:
8-bit Microcontroller Products: sa1fae@sonix.com.tw
All Products: fae@sonix.com.tw
SONiX TECHNOLOGY CO., LTD
Page 194
Version 2.1
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