SN8F570212TG

SONiX Technology Co., Ltd. SN8F5702 Series Datasheet 8051-based Microcontroller SN8F5702 SN8F570200 SN8F570202 SN8F570210 SN8F570211 SN8F570212 SN8F570213 SN8F5702 Series www.sonix.com.tw 1 Device Overview 1.1 Features - Enhanced 8051 microcontroller with reduced instruction cycle time (up to 12 times 80C51) - Up to 32 MHz flexible CPU frequency - Internal 32 MHz Clock Generator (IHRC) - 4 KB non-volatileflash memory (IROM) with in-system program support - 256 bytes internal RAM (IRAM) - 13 interrupt sources with priority levels control and unique interrupt vectors - 12 internal interrupts - 1external interrupts: INT0 - 1 set of DPTR - 2 set 8/16-bit timers with 4 operation modes - 1set16-bit timers with 4 comparison output (PWM) and capture channels - 1set16-bit PWM generators: - each PWM generator has 4output channels with inverters and dead-band control - 12-bit SAR ADC with 10 external and2internal channels, and 4 internal reference voltages - SPI, UART, I2Cinterface with SMBus Support - On-Chip Debug Support: Single-wire debug interface 2hardware breakpoints Unlimited software breakpoints ROM data security/protection - Watchdog and programmable external reset - 1.8V low voltage detectors - Wide supply voltage (1.8 V – 5.5 V) and temperature (-40 °C to 85 °C) range 1.2 Applications - Brushless DC motor - Home automation - Household - Other PWM Channels I2C SPI UART ADC ext. Channels OPA CMP Ext. INT SN8F5702 18 8 V V V 10 - - 1 SN8F570212 14 6 V V TX*(1) 8 - - 1 SN8F570210 12 5 - - V 6 - - 1 SOP14 SN8F570211 12 5 V - TX*(1) 6 - - 1 SOP14 SN8F570213 12 5 - - V 6 - - 1 SOP14 SN8F570200 8 3 - - TX *(1) 5 - - 1 MSOP10 SN8F570202 6 3 - - TX*(1) 4 - - 1 SOP8 Package Types I/O 1.3 Features Selection Table DIP20,SOP20 TSSOP20, QFN20 SOP16,TSSOP16, QFN16 *(1)Only support UART TX mode. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Device Overview 2 SN8F5702 Series www.sonix.com.tw 1.4 Block Diagram On-chip Debug Support 8051-based CPU ALU Accumulator PC, SP, DPTR System Clock and Power Management Controller Reset and Power-on Controller ISR 256 Bytes IRAM 32 MHz IHRC On-chip High Clock Generator Timers ADC 4KB On-chip Non-volatile Memory PWM Generators SPI, UART, I2C GPIO / Pin-sharing Controller Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Device Overview 3 www.sonix.com.tw SN8F5702 Series 2 Table of Contents 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Device Overview...................................................................................................................... 2 Table of Contents..................................................................................................................... 4 Revision History ....................................................................................................................... 5 Pin Assignments ...................................................................................................................... 7 CPU ....................................................................................................................................... 15 Special Function Registers ..................................................................................................... 21 Reset and Power-on Controller .............................................................................................. 29 System Clock and Power Management .................................................................................. 35 System Operating Mode ........................................................................................................ 43 Interrupt................................................................................................................................ 48 GPIO ...................................................................................................................................... 59 External Interrupt .................................................................................................................. 63 Timer 0 and Timer 1 .............................................................................................................. 65 Timer 2 .................................................................................................................................. 72 PWM ..................................................................................................................................... 82 ADC ....................................................................................................................................... 90 UART ................................................................................................................................... 101 SPI ....................................................................................................................................... 110 I2C ....................................................................................................................................... 116 In-System Program .............................................................................................................. 130 Electrical Characteristics ...................................................................................................... 134 Instruction Set ..................................................................................................................... 137 Development Environment .................................................................................................. 142 SN8F5702 Starter-Kit ........................................................................................................... 144 ROM Programming Pin ........................................................................................................ 147 Ordering Information .......................................................................................................... 152 Package Information ............................................................................................................ 154 Appendix: Reference Document .......................................................................................... 164 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Table of Contents 4 SN8F5702 Series www.sonix.com.tw 3 Revision History Revision Date Description 1.0 Sep.2015 First issue 1.1 Oct. 2015 1. 2. 3. 4. 5. Modify timer section and electrical characteristic section. Modify SN8F57023/SN8F57024 pin assignment. Add program memory security section, special function register section and noise filter section. Modify minimum requirement in debug interface section. Update electrical characteristics 1.2 Nov. 2015 1. Update package type 1.3 Nov. 2015 1. 2. 3. 4. SN8F57021 was renamed SN8F570210. SN8F57022 was renamed SN8F570200. SN8F57023 was renamed SN8F570211. SN8F57024 was renamed SN8F570212. 1.4 Nov. 2015 1. Modify SN8F570200 pin assignment 1.5 Dec. 2015 1. 2. Modify electrical characteristic in IHRC section. Add power saving description in UART/SPI/I2C section. 1.6 Apr. 2016 1. 2. 3. 4. 5. Add Timer 2 capture function waveform to illustrate operation. Special Function Registers adds Register Declaration section. Add Appendix: Reference Document chapter. Add ROM Programming Pin chapter. Add QFN20 and SOP14 package type. 1.7 Aug. 2016 1. 2. I2C example modify. Modify Power Management section and In-System Program section. Modify PW1M & PW1YH/L registersdescription. Add SOP8 package type. Add ADC internal reference range. 3. 4. 5. 1.8 Nov. 2016 1. 2. Modify feature table and I2C status code. Add UART Baud Rate Table, WDT description in watchdog reset section and QFN16 package type. 1.9 Dec. 2016 1. Modify electrical characteristic section. 2.0 Sep. 2017 1. 2. Add pincircuitdiagrams section. Add package information. 2.1 Nov. 2017 1. Modify LVD related content. 2.2 Dec. 2017 1. Add design note description. 2.3 Jul.2018 1. Modify QFN16 3x3 dimension. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Revision History 5 SN8F5702 Series www.sonix.com.tw 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. Modify P0OC register in UART section. Repair an error, omission, etc. Add Pin Characteristic section. Modify Internal & External RAM section description. Modify Program Memory section description. Modify Configuration of Reset and Power-on Controller section description. Modify System clock section description. Add High Speed Clock and Real time clocksection. Add System clock timing section. Add System Operating Mode chapter. Modify Interrupt Priority section description. Interrupt chapter adds example section. Modify UART chapter description and baud rate table. I2C chapter adds protocol description diagram and modifies the clock rate table. Debug Interface chapter was renamed Development Environment chapter. Modify Development Environment chapter description. Add Development Tool section. Add SN5702 Starter-kit chapter. Modify ROM Programming Pin chapter description. Add MP5 Hardware Connecting, SN-Link ISP Programming and SN-Link ISP Programming Pin Mapping sections. Update Device Nomenclature section. SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Revision History 6 SN8F5702 Series www.sonix.com.tw 4 Pin Assignments 4.1 SN8F5702P/S/T (DIP20/SOP20/TSSOP20) VSS T2CC0/T2COM0/P00 T2CC1/T2COM1/P01 SSN/RST/P02 SCL/T2CC2/T2COM2/P03 SDA/T2CC3/T2COM3/P04 PWM10/UTX/P05 PWM20/URX/P06 T2/P07 T2RL/AIN9/P20 1 2 3 4 5 6 7 8 9 10 U 20 19 18 17 16 15 14 13 12 11 VDD P10/AIN0/AVREFH/ INT0 P11/AIN1/SWAT P12/AIN2 P13/AIN3/SCK P14/AIN4/PWM11/MOSI P15/AIN5/PWM21/MISO P16/AIN6 P17/AIN7 P21/AIN8 ⃝ P11/AIN1/SWAT P10/AIN0/AVREFH/ INT0 VDD VSS T2CC0/T2COM0/P00 4.2 SN8F5702J (QFN20) 20 19 18 17 16 T2CC1/T2COM1/P01 1 SSN/RST/P02 2 SCL/T2CC2/T2COM2/P03 3 SDA/T2CC3/T2COM3/P04 4 PWM10/UTX/P05 5 15 14 13 12 11 T2/P07 9 10 P17/AIN7 PWM20/URX/P06 8 P21/AIN8 7 T2RL/AIN9/P20 6 P12/AIN2 P13/AIN3/SCK P14/AIN4/PWM11/MOSI P15/AIN5/PWM21/MISO P16/AIN6 14 13 12 11 10 9 8 VDD P10/AIN0/INT0/AVREFH P11/AIN1/SWAT P12/AIN2 P13/AIN3/SCK P14/AIN4/PWM11/MOSI P20/AIN9/T2RL 4.3 SN8F570210S (SOP14) VSS T2CC0/T2COM0/P00 T2CC1/T2COM1/P01 SSN/RST/P02 PWM10/UTX/P05 PWM20/URX/P06 T2/P07 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 1 2 3 4 5 6 7 U Pin Assignments 7 SN8F5702 Series www.sonix.com.tw 4.4 SN8F570211S (SOP14) VSS T2CC0/T2COM0/P00 SSN/RST/P02 SCL/T2CC2/T2COM2/P03 SDA/T2CC3/T2COM3/P04 PWM10/UTX/P05 T2/P07 1 2 3 4 5 6 7 U 14 13 12 11 10 9 8 VDD P10/AIN0/INT0/AVREFH P11/AIN1/SWAT P12/AIN2 P13/AIN3/SCK P14/AIN4/PWM11/MOSI P20/AIN9/T2RL 1 2 3 4 5 6 7 U 14 13 12 11 10 9 8 VSS P10/AIN0/INT0/AVREFH P11/AIN1/SWAT P12/AIN2 P13/AIN3/SCK P14/AIN4/PWM11/MOSI P20/AIN9/T2RL 4.5 SN8F570213S (SOP14) VDD T2CC0/T2COM0/P00 T2CC1/T2COM1/P01 SSN/RST/P02 PWM10/UTX/P05 PWM20/URX/P06 T2/P07 4.6 SN8F570212S/T (SOP16/TSSOP16) VSS T2CC0/T2COM0/P00 SSN/RST/P02 SCL/T2CC2/T2COM2/P03 SDA/T2CC3/T2COM3/P04 PWM10/UTX/P05 T2/P07 T2RL/AIN9/P20 1 2 3 4 5 6 7 8 U 16 15 14 13 12 11 10 9 VDD P10/AIN0/AVREFH/ INT0 P11/AIN1/SWAT P12/AIN2 P13/AIN3/SCK P14/AIN4/PWM11/MOSI P15/AIN5/PWM21/MISO P16/AIN6 ⃝ P10/AIN0/AVREFH/ INT0 VDD VSS T2CC0/T2COM0/P00 4.7 SN8F570212J (QFN16) 16 15 14 13 SSN/RST/P02 1 SCL/T2CC2/T2COM2/P03 2 SDA/T2CC3/T2COM3/P04 3 PWM10/UTX/P05 4 5 6 7 8 T2/P07 T2RL/AIN9/P20 P16/AIN6 P15/AIN5/PWM21/MISO Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 12 11 10 9 P11/AIN1/SWAT P12/AIN2 P13/AIN3/SCK P14/AIN4/PWM11/MOSI Pin Assignments 8 SN8F5702 Series www.sonix.com.tw 4.8 SN8F570200A (MSOP10) VDD VSS T2CC0/T2COM0/P00 SSN/RST/P02 PWM10/UTX/P05 1 2 3 4 5 U 10 9 8 7 6 P10/AIN0/AVREFH/ INT0 P11/AIN1/SWAT P12/AIN2 P13/AIN3/SCK P14/AIN4/PWM11/MOSI 1 2 3 4 U 8 7 6 5 VSS P12/AIN2 P14/AIN4/PWM11/MOSI P11/AIN1/SWAT 4.9 SN8F570202S (SOP8) VDD T2CC0/T2COM0/P00 PWM10/UTX/P05 INT0/AVREFH/AIN0/P10 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Pin Assignments 9 SN8F5702 Series www.sonix.com.tw 4.10 Pin Descriptions Power Pins Pin Name Type Description VDD Power Power supply VSS Power Ground (0 V) Pin Name Type P0.0 T2COM0 T2CC0 Digital I/O Digital Output Digital Input GPIO Timer 2: compare 0 output Timer 2:capture0 input P0.1 T2COM1 T2CC1 Digital I/O Digital Output Digital Input GPIO Timer 2: compare 1 output Timer 2:capture 1 input P0.2 Reset SSN Digital I/O Digital Input Digital Input P0.3 T2COM2 T2CC2 SCL Digital I/O Digital Output Digital Input Digital I/O GPIO Timer 2: compare 2 output Timer 2:capture 2 input I2C: clock output (master) clock input (slave) P0.4 T2COM3 T2CC3 SDA Digital I/O Digital Output Digital Input Digital I/O GPIO Timer 2: compare 3 output Timer 2:capture 3 input I2C: data pin P0.5 UTX PWM10 Digital I/O Digital Output Digital Output GPIO UART: transmission pin PWM: programmable PWM output P0.6 URX PWM20 Digital I/O Digital Input Digital Output GPIO UART: reception pin PWM: programmable PWM output P0.7 T2 Digital I/O Digital Input Port 0 Description GPIO System reset (active low) SPI: salve selection pin (slave mode) GPIO Timer 2: event counter input Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Pin Assignments 10 SN8F5702 Series www.sonix.com.tw Port 1 Pin Name Type Description P1.0 AIN0 INT0 AVREFH Digital I/O Analog Input Digital Input Analog Input GPIO ADC: input channel 0 INT0: external interrupt 0 ADC: external reference voltage P1.1 AIN1 SWAT Digital I/O Analog Input Digital I/O GPIO ADC: input channel 1 Debug interface P1.2 AIN2 Digital I/O Analog Input GPIO ADC: input channel 2 P1.3 AIN3 SCK Digital I/O Analog Input Digital I/O GPIO ADC: input channel 3 SPI: clock output (master) clock input (slave) P1.4 AIN4 MOSI PWM11 Digital I/O Analog Input Digital I/O Digital Output GPIO ADC: input channel 4 SPI: transmission pin (master) reception pin (slave) PWM: programmable PWM output P1.5 AIN5 MISO PWM21 Digital I/O Analog Input Digital I/O Digital Output GPIO ADC: input channel 5 SPI: reception pin (master) transmission pin (slave) PWM: programmable PWM output P1.6 AIN6 Digital I/O Analog Input GPIO ADC: input channel 6 P1.7 AIN7 Digital I/O Analog Input GPIO ADC: input channel 7 Port 2 Pin Name Type Description P2.0 AIN9 T2RL Digital I/O Analog Input Digital Input GPIO ADC: input channel 9 Timer 2: reload trigger input P2.1 AIN8 Digital I/O Analog Input GPIO ADC: input channel 8 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Pin Assignments 11 SN8F5702 Series www.sonix.com.tw 4.11 Port P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 Pin Characteristic OpenDrain V V V V V - Sink Current 100mA VSS+1.5V V V V V V V V - Sink Current 20mA VSS+0.5V V V V V V V V V V V V Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 External Interrupt Wakeup (Level change) V - V V V V V V V V V V V V V V V V - Shared Pin T2CC0/T2COM0 T2CC1/T2COM1 SSN/RST SCL/T2CC2/T2COM2 SDA/T2CC3/T2COM3 PWM10/UTX PWM20/URX T2 AIN0/AVREFH/INT0 AIN1/SWAT AIN2 AIN3/SCK AIN4/PWM11/MOSI AIN5/PWM21/MISO AIN6 AIN7 T2RL/AIN9 AIN8 Pin Assignments 12 SN8F5702 Series www.sonix.com.tw 4.12 Pin Circuit Diagrams Normal Bi-direction I/O Pin. Pull-Up Resistor PnM PnUR Pin I/O Input Bus PnM Output Latch I/O Output Bus Bi-direction I/O Pin Shared with Specific Digital Input Function, e.g. INT0, Event counter, SIO, UART. Pull-Up Resistor PnM Specific Input Function Control Bit PnUR Specific Input Bus Pin IO Input Bus PnM Output Latch Output Bus *. Specific Output Function Control Bit *. Some specific functions switch I/O direction directly, not through PnM register. Bi-direction I/O Pin Shared with Specific Digital Output Function, e.g. PWM, SIO, UART. Pull-Up Resistor PnM PnUR IO Input Bus Pin PnM Output Latch *. Specific Output Function Control Bit Output Bus Specific Output Bus Specific Output Function Control Bit *. Some specific functions switch I/O direction directly, not through PnM register. Bi-direction I/O Pin Shared with Specific Analog Input Function, e.g. ADC. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Pin Assignments 13 SN8F5702 Series www.sonix.com.tw Pull-Up Resistor *. Specific Analog Function Control Bit PnM PnUR I/O Input Bus Pin PnM Output Latch I/O Output Bus Analog IP Input Terminal *. Some specific functions switch I/O direction directly, not through PnM register. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Pin Assignments 14 SN8F5702 Series www.sonix.com.tw 5 CPU SN8F5000 family is an enhanced 8051 microcontroller (MCU). It is fully compatible with MCS-51 instructions, hence the ability to cooperate with modern development environment (e.g. Keil C51).Generally speaking, SN8F5000 CPU has 9.4 to 12.1 times faster than the original 8051 at the same frequency. 5.1 Memory Organization SN8F5702 builds in two on-chip memories: internal RAM (IRAM) and program memory (IROM). The internal RAM is a 256-byte RAM which has higher access performance (direct and indirect addressing). By contrast, the external RAM has 256-byte of size, but it requires a longer access period. The program memory is a 8 KB non-volatile memory and has a maximum 8 MHz speed limitation. 0x1FFF 8 KB Flash Memory 0x0000 0xFF 0x00 IROM 256 bytes RAM IRAM 5.2 Internal RAM (IRAM) 256 X 8-bit RAM (Internal Data Memory) Address 000h 01Fh 020h 02Fh 030h … … 07Fh 080h … … … 0FFh RAM Location 00h-7Fh of RAM is direct and indirect access RAM Work Register Area Bit Addressable Area General Purpose Area General Purpose Area (Indirect Access) Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Special Function Register (Direct Access) 080h-0FFh store special function registers. End of Bank 0 CPU 15 SN8F5702 Series www.sonix.com.tw The 256-byte data RAM in internal data memory is a standard 8051 RAM access configuration. The upper 128-byte RAM is general purpose RAM and can configure by direct addressing access and indirect addressing access. The lower 128-byte can be indirect access RAM in general purpose or direct access RAM in special function register (SFR).  0x0000-0x007F: General purpose RAM contains work register area and bit addressable area. In this area, direct or indirect addressing can be used.  0x0000-0x001F: Work register area includes 4-bank. Each bank has 8 work registers (R0 - R7) which is selected by RS0/RS1 in PSW register.  0x0020-0x002F: Bit addressable area. Bit Addressable Area In the bit addressable area, user can read or write any single bit in this range by using the unique address for that bit. Supports 16bytes bit addressable RAM area giving 128 addressable bits. Each bit has individual address in the range from 00H to 7FH. Thus, the bit can be addressed directly. Bit0 of the byte 20H has bit address 00H and Bit 7 of the byte 20H has bit address 07H. Bit0 of the byte 2FH has bit address 78H and Bit 7 of the byte 2FH has bit address 7FH. When set “SETB 42H”, it means the bit2 of the byte 28H is set.  Byte Address Bite 0 Bite 1 Bite 2 Bite 3 Bite 4 Bite 5 Bite 6 Bite 7 0x20 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x21 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x22 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x23 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x24 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x25 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x26 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x27 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x28 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x29 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x2A 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x2B 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x2C 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x2D 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x2E 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x2F 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x0080~0x00FF: General purpose area in indirect addressing access or special function register in direct addressing access. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 CPU 16 SN8F5702 Series www.sonix.com.tw 5.3 Program Memory (IROM) The program memory is a non-volatile storage area where stores code, look-up ROM table, and other data with occasional modification. It can be updated by debug tools like SN-Link3, and a program can also self-update via in-system program process (refer to In-system Program). Address 0000H 0001H 0002H 0003H 000BH 001BH 0023H 002BH 0043H 004BH 0053H 005BH 0063H 006BH 0083H 008BH 008CH . . . . 0FF6H 0FF7H . 0FFEH 0FFFH ROM Reset vector General purpose area INT0 Interrupt vector TIMER0 Interrupt vector TIMER1 Interrupt vector UART Interrupt vector TIMER2Interrupt vector I2C Interrupt vector SPI Interrupt vector T2COM0 Interrupt vector T2COM1 Interrupt vector T2COM2 Interrupt vector T2COM3Interrupt vector PWM1 Interrupt vector ADC Interrupt vector Comment Reset vector User program Interrupt vector User program General purpose area End of user program Reserved The ROM includes reset vector, Interrupt vector, general purpose area and reserved area. The reset vector is program beginning address. The interrupt vector is the head of interrupt service routine when any interrupt occurring. The general purpose area is main program area including main loop, sub-routines and data table.     0x0000 Reset vector: Program counter points to 0x0000 after any reset events (power on reset, reset pin reset, watchdog reset, LVD reset…). 0x0001~0x0002: General purpose area to process system reset operation. 0x0003~0x008B: Multi interrupt vector area. Each of interrupt events has a unique interrupt vector. 0x008C~0x0FBF: General purpose area for user program and ISP (EEPROM function). Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 CPU 17 www.sonix.com.tw SN8F5702 Series  0x0FC0~0x0FF5: General purpose area for user program. Do not execute ISP.  0x0FF6~0x0FFF: Reserved area. Do not execute ISP. ROM security rule is all address ROM data protected and outputs 0x0000. 5.4 Program Memory Security The SN8F5702 provides security options at the disposal of the designer to prevent unauthorized access to information stored in FLASH memory. When enable security option, the ROM code is secured and not dumped complete ROM contents. ROM security rule is all address ROM data protected and outputs 0x00. 5.5 Data Pointer A data pointer helps to specify the IROM address while performing MOVC instructions. The microcontroller has one set of data pointer (DPH/DPL). Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 CPU 18 SN8F5702 Series www.sonix.com.tw 5.6 Stack Stack can be assigned to any area of internal RAM (IRAM). However, it requires manual assignment to ensure its area does not overlap other RAM’s variables. An overflow and underflow stack could also mistakenly overwrite other RAM’s variables; thus, these factors should be considered while arrange the size of stack. 0x0B 0x0B 0x0B 0x0A PUSH→ 0x0A LCALL→ 0x0A 0x09 POP← 0x09 RET← 0x09 0x08 (empty) SP = 0x07 0x08 Data SP = 0x08 0x08 Address Data SP = 0x0A By default, stack pointer (SP register) points to 0x07 which means the stack area begin at IRAM address 0x08. In other word, if a planned stack area is assigned from IRAM address 0xC0, the appropriate SP register is anticipated to set at 0xBF after system reset. An assembly PUSH instruction costs one byte of stack. LCALL, ACALL instructions and interrupt respectively costs two bytes stack. POP-instruction decreases one count, and a RET/RETI subtract two counts of stack pointer.  Note: Stack and IRAM share the same area, Keil C51 compiler will not display “error” or “warning” when overlap condition is occurred so user must pay attention. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 CPU 19 SN8F5702 Series www.sonix.com.tw 5.7 Stack and Data Pointer Register Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SP SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 DPL DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 DPH DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 SP Register (0x81) Bit Field Type Initial Description 7..0 SP R/W 0x07 Stack pointer DPL Register (0x82) Bit Field Type Initial Description 7..0 DPL[7:0] R/W 0x00 Low byte of DPTR0 DPH Register (0x83) Bit Field Type Initial Description 7..0 DPH[7:0] R/W 0x00 High byte of DPTR0 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 CPU 20 SN8F5702 Series www.sonix.com.tw 6 Special Function Registers 6.1 Special Function Register Memory Map BIN 000 001 010 011 100 101 110 111 F8 - P0M P1M P2M - - - PFLAG F0 B P0UR P1UR P2UR - - - SRST E8 - - - - - - - - E0 ACC SPSTA SPCON SPDAT P0OC CLKSEL CLKCMD TCON0 D8 S0CON2 - I2CDAT I2CADR I2CCON I2CSTA SMBSEL SMBDST D0 PSW IEN4 ADM ADB ADR VREFH P1CON - C8 T2CON - CRCL CRCH TL2 TH2 - - C0 IRCON CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 B8 IEN1 IP1 S0RELH PW1DH PW1DL PW1A PW1CH IRCON2 B0 - - - - - - - - A8 IEN0 IP0 S0RELL PW1M PW1YL PW1YH PW1BL PW1BH A0 P2 - - - - - - - 98 S0CON S0BUF IEN2 - - P0CON P2CON - 90 P1 P1W - - PECMD PEROML PEROMH PERAM 88 TCON TMOD TL0 TL1 TH0 TH1 CKCON PEDGE 80 P0 SP DPL DPH - - WDTR PCON HEX  Note: All SFRs in the left-most column are bit-addressable. (Every 0x0/0x8-ending SFR addresses are bit-addressable). Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Special Function Registers 21 SN8F5702 Series www.sonix.com.tw 6.2 Special Function register Description 0x80 - 0x9F Registers Description Register Address Description P0 0x80 Port 0 data buffer. SP 0x81 Stack pointer register. DPL 0x82 Data pointer 0 low byte register. DPH 0x83 Data pointer 0 high byte register. - 0x84 - - 0x85 - WDTR 0x86 Watchdog timer clear register. PCON 0x87 System mode register. TCON 0x88 Timer 0 / 1 controls register. TMOD 0x89 Timer 0 / 1 mode register. TL0 0x8A Timer 0 counting low byte register. TL1 0x8B Timer 1 counting low byte register. TH0 0x8C Timer 0 counting high byte register. TH1 0x8D Timer 1 counting high byte register. CKCON 0x8E Extended cycle controls register. PEDGE 0x8F External interrupt edge controls register. P1 0x90 Port 1 data buffer. P1W 0x91 Port 1 wake-up controls register. - 0x92 - - 0x93 - PECMD 0x94 In-System Programcommand register. PEROML 0x95 In-System Program ROM address low byte PEROMH 0x96 In-System Program ROM address high byte PERAM 0x97 In-System Program RAM mapping address S0CON 0x98 UART control register. S0BUF 0x99 UART data buffer. IEN2 0x9A Interrupts enable register - 0x9B - - 0x9C - P0CON 0x9D Port 0configuration controls register. P2CON 0x9E Port 2configuration controls register. - 0x9F - Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Special Function Registers 22 SN8F5702 Series www.sonix.com.tw 0xA0 - 0xBF Registers Description Register Address Description P2 0xA0 Port 2 data buffer - 0xA1 - - 0xA2 - - 0xA3 - - 0xA4 - - 0xA5 - - 0xA6 - - 0xA7 - IEN0 0xA8 Interrupts enable register IP0 0xA9 Interrupts priority register. S0RELL 0xAA UART reload low byte register. PW1M 0xAB PW1 controls register. PW1YL 0xAC PW1 cycle controls buffer low byte. PW1YH 0xAD PW1 cycle controls buffer high byte. PW1BL 0xAE PW1 B point dead band controls buffer low byte. PW1BH 0xAF PW1 B point dead band controls buffer high byte. - 0xB0 - - 0xB1 - - 0xB2 - - 0xB3 - - 0xB4 - - 0xB5 - - 0xB6 - - 0xB7 - IEN1 0xB8 Interrupts enable register IP1 0xB9 Interrupts priority register. S0RELH 0xBA UART reload high byte register. PW1DL 0xBB PW1 duty controls buffer low byte. PW1DH 0xBC PW1 duty controls buffer high byte. PW1A 0xBD PW1 A point dead band controls buffer. PW1CH 0xBE PW1 channel control buffer. IRCON2 0xBF Interrupts request register. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Special Function Registers 23 SN8F5702 Series www.sonix.com.tw 0xC0 - 0xDF Registers Description Register Address Description IRCON 0xC0 Interrupts request register. CCEN 0xC1 Timer 2 Compare /capture enable register. CCL1 0xC2 Timer 2 Compare /capture module 1 low byte register. CCH1 0xC3 Timer 2 Compare /capture module 1 high byte register. CCL2 0xC4 Timer 2 Compare /capture module 2 low byte register. CCH2 0xC5 Timer 2 Compare /capture module 2 high byte register. CCL3 0xC6 Timer 2 Compare /capture module 3 low byte register. CCH3 0xC7 Timer 2 Compare /capture module 3 high byte register. T2CON 0xC8 Timer 2 controls register. - 0xC9 - CRCL 0xCA Timer 2 Compare/capture module 0 & reload function low byte register. CRCH 0xCB Timer 2 Compare/capture module 0 & reload function high byte register. TL2 0xCC Timer 2 counting low byte register. TH2 0xCD Timer 2 counting high byte register. - 0xCE - - 0xCF - PSW 0xD0 System flag register. IEN4 0xD1 Interrupts enable register ADM 0xD2 ADC controls register. ADB 0xD3 ADC data buffer. ADR 0xD4 ADC resolution selects register. VREFH 0xD5 ADC reference voltage controls register. P1CON 0xD6 Port 1 configuration controls register. - 0xD7 - S0CON2 0xD8 UART baud rate controls register. - 0xD9 - I2CDAT 0xDA I2C data buffer. I2CADR 0xDB Own I2C slave address. I2CCON 0xDC I2C interface operation control register. I2CSTA 0xDD I2C Status Code. SMBSEL 0xDE SMBus mode controls register. SMBDST 0xDF SMBus internal timeout register. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Special Function Registers 24 SN8F5702 Series www.sonix.com.tw 0xE0 - 0xFF Registers Description Register Address Description ACC 0xE0 Accumulator register. SPSTA 0xE1 SPI statuses register. SPCON 0xE2 SPI control register. SPDAT 0xE3 SPI data buffer. P0OC 0xE4 Open drain controls register. CLKSEL 0xE5 Clock switch selects register. CLKCMD 0xE6 Clock switch controls Register. TCON0 0xE7 Timer 0 / 1 clock controls register. - 0xE8 - - 0xE9 - - 0xEA - - 0xEB - - 0xEC - - 0xED - - 0xEE - - 0xEF - B 0xF0 Multiplication/ division instructiondata buffer. P0UR 0xF1 Port 0 pull-up resister controls register. P1UR 0xF2 Port 1 pull-up resister controls register. P2UR 0xF3 Port 2 pull-up resister controls register. - 0xF4 - - 0xF5 - - 0xF6 - SRST 0xF7 Software reset controlsregister. - 0xF8 - P0M 0xF9 Port 0 input/output mode register. P1M 0xFA Port 1 input/output mode register. P2M 0xFB Port 2 input/output mode register. - 0xFC - - 0xFD - - 0xFE - PFLAG 0xFF Reset flag register. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Special Function Registers 25 SN8F5702 Series www.sonix.com.tw 6.3 System Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACC ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0 B B7 B6 B5 B4 B3 B2 B1 B0 PSW CY AC F0 RS1 RS0 OV F1 P ACC Register (0xE0) Bit Field Type Initial Description 7..0 ACC[7:0] R/W 0x00 The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If the result of operating is overflow (OV) or there is carry (C or AC) and parity (P) occurrence, then these flags will be set to PSW register. B Register (0xF0) Bit Field Type Initial Description 7..0 B[7:0] R/W 0x00 The B register is used during multiplying and division instructions. It can also be used as a scratch-pad register to hold temporary data. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Special Function Registers 26 SN8F5702 Series www.sonix.com.tw PSW Register (0xD0) Bit Field Type Initial Description 7 CY R/W 0 Carry flag. 0: Addition without carry, subtraction with borrowing signal, rotation with shifting out logic “0”, comparison result < 0. 1: Addition with carry, subtraction without borrowing, rotation with shifting out logic “1”, comparison result ≥ 0. 6 AC R/W 0 Auxiliary carry flag. 0: If there is no a carry-out from 3rd bit of Accumulator in BCD operations. 1: If there is a carry-out from 3rd bit of Accumulator in BCD operations. 5 F0 R/W 0 General purpose flag 0. General purpose flag available for user. 4..3 RS[1:0] R/W 00 Register bank select control bit, used to select working register bank. 00: 00H – 07H (Bnak0) 01: 08H – 0FH (Bnak1) 10: 10H – 17H (Bnak2) 11: 18H – 1FH (Bnak3) 2 OV R/W 0 Overflow flag. 0: Non-overflow in Accumulator during arithmetic Operations. 1: overflow in Accumulator during arithmetic Operations. 1 F1 R/W 0 General purpose flag 1. General purpose flag available for user. 0 P R 0 Parity flag. Reflects the number of ‘1’s in the Accumulator. 0: if Accumulator contains an even number of ‘1’s. 1: Accumulator contains an odd number of ‘1’s. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Special Function Registers 27 SN8F5702 Series www.sonix.com.tw 6.4 RegisterDeclaration SN8F5702 has many registers to control various functions, but SFR name is not predefined in the C51 / A51 compiler. To make programming easier and therefore need to add header files to declare SFR name. When using the assembly code programs, please add the following sentence. 1 $NOMOD51;Do not recognize the 8051-specific predefined special register. 2 #include When using the C code programs, please add the following sentence. 1 #include After adding the header file, user can use name of registers to program. During compilation, the compiler will register name translate into register position through the header file. Different devices need to use a different header file to declare, but the option file is to use the same. Device Header file SN8F5702 SN8F5702.h SN8F570200 SN8F570200.h SN8F570202 SN8F570202.h SN8F570210 SN8F570210.h SN8F570211 SN8F570211.h SN8F570212 SN8F570212.h SN8F570213 SN8F570213.h Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Options file OPTIONS_SN8F5702.A51 Special Function Registers 28 www.sonix.com.tw 7 SN8F5702 Series Reset and Power-on Controller The reset and power-on controller has four reset sources: low voltage detectors (LVDs), watchdog, programmable external reset pin, and software reset.The first three sources would trigger an additional power-on sequence. Subsequently, the microcontroller initializes all registers and starts program execution with its reset vector (ROM address 0x0000). 7.1 Configuration of Reset and Power-on Controller SONiXpublishes an OPTIONS_SN8F5702.A51 file in SN-Link Driver for Keil C51.exe (downloadable on cooperative website: www.sonix.com.tw). Thisoptions file contains appropriate parameters of reset sources and CPU clock source selection, and is strongly recommended to add to Keil project. SN8F5000 Debug Tool Manualprovides the further detail of this configuration.       Program Memory Security CPU Clock Source Noise Filter Reset Source : VDD Voltage (Low Voltage Detection) Reset Source : External Reset / GPIO Shared Pin Reset Source : Watchdog Reset& Overflow Period Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Reset and Power-on Controller 29 SN8F5702 Series www.sonix.com.tw The code option is the system hardware configurations including oscillator type, noise filter option, watchdog timer operation, LVD option, reset pin option and flash ROM security control. The code option items are as following table: Code Option Content Function Description Program Memory Security Security Disable Disable ROM code Security function Security Enable Enable ROM code Security function CPU Clock Source IHRC 32MHz High speed internal 32MHz RC. LVD LVD_L LVD will reset chip if VDD is below 1.8V External Reset Reset with De-bounce Enable External reset pin with De-bounce Reset without De-bounce Enable External reset pin without De-bounce GPIO with P02 Enable P02 Always Watchdog timer is always on enable even in STOP mode and IDLE mode Enable Enable watchdog timer. Watchdog timer stops in STOP mode and IDLE mode Disable Disable Watchdog function 64ms Watchdog timer clock source F ILRC /4 128ms Watchdog timer clock source F ILRC /8 256ms Watchdog timer clock source F ILRC /16 512ms Watchdog timer clock source F ILRC /32 Watchdog Reset Watchdog Overflow Period 7.2 Power-on Sequence A power-on sequence would be triggered by LVD, watchdog, and external reset pin. It takes place between the end of reset signal and program execution. Overall, it includes two stages: power stabilization period, and clock stabilization period. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Reset and Power-on Controller 30 SN8F5702 Series www.sonix.com.tw VDD Power LVD Detect Level VSS VDD External Reset VSS External Reset High Detect External Reset Low Detect Watchdog Normal Run Watchdog Reset Watchdog Overflow Watchdog Stop System Normal Run System Status System Stop Power On Delay Time External Reset Delay Time Watchdog Reset Delay Time The power stabilization period spends 5 msin typical condition. Afterward the microcontroller fetches CPU Clock Source selectionautomatically. The selected clock source would be driven, and the system counts 4096 times of the clock period to ensure its reliability.  Note: In high power noise environment, user can put 10ohm resistor in the front of 0.1uF capacitor& VDD PAD to suppress power noise and avoid IC damage. 7.3 LVD Reset The low voltage detectors monitor VDD pin’s voltage at only one level: 1.8 V. Depend on low voltage detection configuration, the comparison result can be seen as a system reset signal. The table below lists low voltage detection configuration, LVD_L, and the results of VDD pin’s condition. VDD Power LVD Detect Voltage VSS Power is below LVD Detect Voltage and System Reset. System Normal Run System Status System Stop Power On Delay Time Condition LVD_L VDD ≤ 1.8 V Reset Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Reset and Power-on Controller 31 SN8F5702 Series www.sonix.com.tw 7.4 Watchdog Reset Watchdog is a periodic reset signal generator for the purpose of monitoring the execution flow.Its internal timer is expected to be cleared in a check point ofprogram flow; therefore, the actual reset signal would be generated only after a software problem occurs. Writing 0x5A to WDTR is the proper method to place a check point in program. 1 WDTR = 0x5A; Watchdog timer interval time = 256 * 1/ (Internal Low-Speed oscillator frequency/WDT Pre-scalar) = 256 / (F ILRC /WDT Pre-scaler) …sec Internal low-speed oscillator F ILRC =16 kHz WDT pre-scaler Watchdog interval time F ILRC /4 256/(16000/4)=64ms F ILRC /8 256/(16000/8)=128ms F ILRC /16 256/(16000/16)=256ms F ILRC /32 256/(16000/32)=512ms The operation mode of watchdog is configurable in options file: Always mode counts its internal timer in all CPU operation modes (normal, IDLE, SLEEP); Enable mode counts its internal timer during CPU stays in normal mode, and it would not trigger watchdog reset in IDLE and STOP modes; Disable mode suspends its internal timer at all CPU modes, and the watchdog would not trigger in this condition. When watchdog is operating in always mode, the system will consume additional power. 7.5 External Reset Pin Programmable external reset pin is configurable in options file. Once it is enabled, it monitors its shared pin’s logic level. A logical low (lower than 30% of VDD) would immediatelytrigger system reset until the input is recovered to high (lager than 70% of VDD). An optional de-bounce period can improve reset signal’s stability. Instead of immediate reset, the system reset requires an8-ms-long logic low to avoid bouncing from a button key. Any signal lower than de-bounce period would not affect the CPU’s execution. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Reset and Power-on Controller 32 SN8F5702 Series www.sonix.com.tw VDD VDD R1 47K ohm DIODE R2 RST 100 ohm MCU R1 47K ohm R2 C1 0.1uF C1 0.1uF RST 100 ohm VSS VSS  MCU VCC VCC GND GND Note: 1. The reset circuit is no any protection against unusual power or brown out reset on the left side of the figure. 2. The R2 100 ohm resistor of “Simply reset circuit” and “Diode & RC reset circuit” is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS) on the right side of the figure. 7.6 Software Reset A software reset would be generated after consecutively set SRSTREQ register.As a result, this procedure enables firmware’sabilityto reset microcontroller (e.g. reset after firmware update). The following sample C code repeatedly set the least bit of SRST register to perform software reset. 1 SRST = 0x01; 2 SRST = 0x01; 7.7 Reset and Power-on Controller Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PFLAG POR WDT RST - - - - - SRST - - - - - - - SRSTREQ WDTR WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Reset and Power-on Controller 33 SN8F5702 Series www.sonix.com.tw PFLAG Register Bit Field Type Initial Description 7 POR R - This bit is automatically set if the microcontroller has been reset by LVD. 6 WDT R - This bit is automatically set if the microcontroller has been reset by watchdog. 5 RST R - This bit is automatically set if the microcontroller has been reset by external reset pin. 4..3 Reserved R 0 0..2 Reserved R 0 SRST Register Bit Field Type Initial Description 7..1 Reserved R 0 0 SRSTREQ R/W 0 Consecutively set this bit for two times to trigger software reset. WDTR Register (0x86) Bit Field Type Initial Description 7..0 WDTR[7:0] W - Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Reset and Power-on Controller 34 SN8F5702 Series www.sonix.com.tw 8 System Clock and Power Management For power saving purpose, the microcontroller built in three different operation modes: normal, IDLE, and STOP mode. The normal mode means that CPU and peripheral functions are under normally execution.The system clock is based on the combination of source selection, clock divider, and program memory wait state.IDLE mode is the situation that temporarily suspends CPU clock and its execution, yet it remains peripherals’functionality (e.g. timers, PWM, SPI, UART, and I2C). By contrast, STOP mode disables all functions and clock generator until a wakeup signal to return normal mode. 8.1 System Clock The microcontroller includes an on-chip clock generator (IHRC 32MHz). The reset and power-on controller automatically loads clock source selection during power-on sequence. Therefore, the selected clock source is seen as ‘fosc’ domain which is a fixed frequency at any time. Subsequently, the selected clock source (fosc) is divided by 1 to 128 times which is controlled by CLKSEL register. The CPU input the divided clock as its operation base (named fcpu).Applying CLKSEL's setting when CLKCMD register be written0x69. 1 2 3 4 CKCON = 0x70; CLKSEL = 0x05; CLKCMD = 0x69; CKCON = 0x00; // For safely change system clock //Set fcpu = fosc / 4 //Apply CLKSEL’s setting // IROM fetch = fcpu / 1 ROM interface is built in between CPU and IROM (program memory). It optionally extends the data fetching cycle in order to support lower speed program memory. For example if the CPU is anticipated to run at 32 MHz and the IROM has to run at 8 MHz, three extended cyclemust be placed by CKCON register. IROM fetching cycle = Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 fcpu ≤ 8MHz, PWSC[2:0] = 0~7 PWSC[2:0]+1 System Clock and Power Management 35 SN8F5702 Series www.sonix.com.tw  Note: For user develop program in C language or assembly,the first line of the program “must be set” CKCON = 0x70and then set CLKSEL= 0x07~0x00, CLKMD= 0x69, CKCON= 0x00~0x70, this priority cannot be modified. System clock rate and program memory extended cycle limitation as follows. Code Option CPU Clock Source IHRC32M Fcpu = CLKSEL[2:0] IROM Fetch = CKCON[6:4] Only Support 000 =fosc / 128 001 =fosc / 64 010 =fosc / 32 011 =fosc / 16 100 =fosc / 8 101 =fosc / 4 Support 000 =fcpu / 1=>Recommend! 001 =fcpu / 2 010 =fcpu / 3 011 =fcpu / 4 100 =fcpu / 5 101 =fcpu / 6 110 = fcpu / 7 111 = fcpu / 8 8.2 High Speed Clock and Real time clock High-speed clock only has internal clock. The internal high-speed oscillator is 32MHz RC type.These high-speed oscillators are selected by SN8F5702_OPTIONS.A51.  IHRC32M: The system high-speed clock source is internal high-speed 32MHz RC type oscillator. 8.3 Power Management After the end of reset signal and power-on sequence, the CPU starts program execution at the speed of fcpu. Overall, the CPU and all peripherals are functional in this situation (categorized as normal mode). The least two bits of PCON register (IDLE at bit 0 and STOP at bit 1) control the microcontroller’s power management unit. If IDLE bit is set by program, only CPU clock source would be gated. Consequently, peripheral functions (such as timers, PWM, and I2C) and clock generator (IHRC 32 MHz) remain execution in this status. Any change from P0/P1 input and interrupt events can make the microcontroller turns Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 System Clock and Power Management 36 SN8F5702 Series www.sonix.com.tw back to normal mode, and the IDLE bit would be cleared automatically. Any function can work in IDLE mode. Only CPU is suspended The IDLE mode wake-up sources are P0/P1 level change trigger and any interrupt event.   If STOP bit is set, by contrast, CPU, peripheral functions, and clock generator are suspended. Data storage in registers and RAM would be kept in this mode. Any change from P0/P1 can wake up the microcontroller and resume system’s execution. STOP bit would be cleared automatically. CPU, peripheral functions, and clock generator are suspended. The STOP mode wake-up source is P0/P1 level change trigger.   For user who is develop program in C language, IDLE and STOP macros is strongly recommended to control the microcontroller’s system mode, instead of set IDLE and STOP bits directly. 1 2  IDLE(); STOP(); Note: Into IDLE mode or STOP mode by “Assembly Language” must be using MOV instruction. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 System Clock and Power Management 37 SN8F5702 Series www.sonix.com.tw 8.4 System Clock Timing Parameter Hardware configuration time Oscillator start up time Oscillator warm-up time Symbol Tcfg Tost Tosp 131072*F IHRC Description The start-up time is depended on oscillator’s material, factory and architecture. Normally, the low-speed oscillator’s start-up time is lower than high-speed oscillator. The RC type oscillator’s start-up time is faster than crystal type oscillator. Oscillator warm-up time of reset condition. 2048*F hosc+ 5*F ILRC (Power on reset, LVD reset, watchdog reset, external reset pin active.) Oscillator warm-up time of power down mode wake-up condition. 2048*F hosc+ 5*F ILRC ……Crystal/resonator type oscillator, e.g. 32768Hz crystal, 4MHz crystal, 16MHz crystal… 64*F hosc+ 5*F ILRC ……RC type oscillator, e.g. internal high-speed RC type oscillator. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Typical 4.096ms @ F IHRC = 32MHz - 825us @ F hosc = 4MHz 441us @ F hosc = 16MHz 377us @ F hosc = 32MHz X’tal: 825us @ F hosc = 4MHz 441us @ F hosc = 16MHz RC: 315us @ F hosc = 32MHz System Clock and Power Management 38 SN8F5702 Series www.sonix.com.tw  Power On Reset Timing Vdd Vp Power On Reset Flag Oscillator Tcfg Tost Tosp Fcpu (Instruction Cycle)  External Reset Pin Reset Timing Reset pin falling edge trigger system reset. External Reset Pin Reset pin returns to high status. External Reset Flag Oscillator Tcfg Tost Fcpu (Instruction Cycle) Tosp System is under reset status.  Watchdog Reset Timing Watchdog timer overflow. Watchdog Reset Flag Oscillator Tcfg Tost Fcpu (Instruction Cycle)  Tosp STOP Mode Wake-up Timing Edge trigger system wake-up. Wake-up Pin Falling Edge Wake-up Pin Rising Edge Oscillator Tost Tosp Fcpu (Instruction Cycle) System inserts into power down mode. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 System Clock and Power Management 39 SN8F5702 Series www.sonix.com.tw  IDLE Mode Wake-up Timing Edge trigger system wake-up. Wake-up Pin Falling Edge Wake-up Pin Rising Edge Timer Timer overflow. ... 0xFD 0xFE 0xFF 0x00 0x01 0x02 ... ... ... ... ... Oscillator Fcpu (Instruction Cycle) System inserts into green mode.  Oscillator Start-up Time The start-up time is depended on oscillator’s material, factory and architecture. Normally, the low-speed oscillator’s start-up time is lower than high-speed oscillator. RC Oscillator Tost Ceramic/Resonator Tost Crystal Tost Low Speed Crystal (32K, 455K) Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Tost System Clock and Power Management 40 SN8F5702 Series www.sonix.com.tw 8.5 System Clock and Power Management Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CKCON - PWSC2 PWSC1 PWSC0 ESYN EWSC2 EWSC1 EWSC0 CLKSEL - - - - - CLKSEL2 CLKSEL1 CLKSEL0 CLKCMD CMD7 CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 PCON SMOD - - - - GF0 STOP IDLE P1W P17W P16W P15W P14W P13W P12W P11W P10W CKCON Register (0x8E) Bit Field Type Initial 7 Reserved R 0 6..4 PWSC[2:0] R/W 111 Else Reserved R 0001 Description Extended cycle(s) applied to reading program memory 000: non 001: 1 cycle 010: 2 cycles 011: 3 cycles 100: 4 cycles 101: 5 cycles 110: 6 cycles 111: 7 cycles CLKSEL Register (0xE5) Bit Field Type Initial 7..3 Reserved R 0x00 2..0 CLKSEL[2:0] R/W 111 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Description CLKSEL would be applied by writing CLKCMD. 000: fcpu = fosc / 128 001: fcpu = fosc / 64 010: fcpu = fosc / 32 011: fcpu = fosc / 16 100: fcpu = fosc / 8 101: fcpu = fosc / 4 110: fcpu = fosc / 2 111: fcpu = fosc / 1 System Clock and Power Management 41 SN8F5702 Series www.sonix.com.tw CLKCMD Register (0xE6) Bit Field Type Initial Description 7..0 CMD[7:0] W 0x00 Writing 0x69 to apply CLKSEL’s setting. Type Initial Description PCON Register (0x87) Bit Field 7 Refer to other chapter(s) 6..3 Reserved R 0x00 2 GF0 R/W 0 General Purpose Flag 1 STOP R/W 0 1: Microcontroller switch to STOP mode 0 IDLE R/W 0 1: Microcontroller switch to IDLE mode P1W Register (0x91) Bit Field Type Initial Description 7..0 P1nW R/W 0 0: Disable P1.n wakeup functionality 1: Enable P1.n wakeup functionality Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 System Clock and Power Management 42 SN8F5702 Series www.sonix.com.tw 9 System Operating Mode The chip builds in three operating mode for difference clock rate and power saving reason. These modes control oscillators, op-code operation and analog peripheral devices’ operation.    Normal mode: System high-speed operating mode IDLE mode: System idle mode (Green mode) STOP mode: System power saving mode (Sleep mode) One of Reset trigger source active STOP mode One of Reset trigger source active Reset control block PCON.1 is “1” Wake-up condition: P0/P1 input status is level changing. Normal mode PCON.0 is “1” Wake-up condition: P0/P1 input status is level changing. All interrupt in EAL = 1 & function interrupt enable. IDLE mode One of Reset trigger source active Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 System Operating Mode 43 SN8F5702 Series www.sonix.com.tw The operating mode clock control as following table: OperatingMode IHRC Normal Mode IHRC: Running Ext. OSC: Disable IDLE Mode IHRC: Running Ext. OSC: Disable STOP Mode Stop Watchdog always: Running Other : stop ILRC Running Running CPU instruction Executing Stop Stop Timer 0 (Timer, Event counter) Active by TR0 Active by TR0 Inactive Timer 1 (Timer, Event counter) Active by TR1 Active by TR1 Inactive Timer 2 (Timer, capture, T2COM) Active as enable Active as enable Inactive PWM Active as enable Active as enable Inactive UART Active as enable Active as enable Inactive SPI Active as enable Active as enable Inactive I2C Active as enable Active as enable Inactive ADC Active as enable Active as enable Inactive Watchdog timer By Watchdog Code option By Watchdog Code option By Watchdog Code option Internal interrupt All active All active All inactive External interrupt All active All active All inactive P0, P1, Reset,All interrupt inEAL = 1 & function interrupt enable P0, P1, Reset Wakeup source   - IHRC: Internal high-speed oscillator RC type. ILRC: Internal low-speed oscillator RC type. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 System Operating Mode 44 www.sonix.com.tw SN8F5702 Series 9.1 Normal Mode The Normal Mode is system high clock operating mode. The system clock source is from high speed oscillator. The program is executed. After power on and any reset trigger released, the system inserts into normal mode to execute program. When the system is wake-up from STOP/IDLE mode, the system also inserts into normal mode. In normal mode, the high speed oscillator is active, and the power consumption is largest of all operating modes.      The program is executed, and full functions are controllable. The system rate is high speed. The high speed oscillator and internal low speed RC type oscillator are active. Normal mode can be switched to other operating modes through PCON register. STOP/IDLE mode is wake-up to normal mode. 9.2 STOP Mode The STOP mode is the system ideal status. No program execution and oscillator operation. Only internal regulator is active to keep all control gates status, register status and SRAM contents. The STOP mode is waked up by P0/P1 hardware level change trigger. P0 wake-up function is always enables. The STOP mode is wake-up to normal mode. Inserting STOP mode is controlled by stop bit of PCON register. When stop = 1, the system inserts into STOP Mode. After system wake-up from STOP mode, the stop bit is disabled (zero status) automatically.      The program stops executing, and full functions are disabled. All oscillators including external high/low speed oscillator, internal high speed oscillator and internal low speed oscillator stop. Only internal regulator is active to keep all control gates status, register status and SRAM contents. The system inserts into normal mode after wake-up from STOP mode. The STOP mode wake-up source is P0/P1 level change trigger. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 System Operating Mode 45 www.sonix.com.tw SN8F5702 Series 9.3 IDLE Mode The IDLE mode is another system ideal status not like STOP mode. In STOP mode, all functions and hardware devices are disabled. But in IDLE mode, the system clock source keeps running, so the power consumption of IDLE mode is larger than STOP mode. In IDLE mode, the program isn’t executed, but the timer with wake-up function is active as enabled, and the timer clock source is the non-stop system clock. The IDLE mode has 2 wake-up sources. One is the P0/P1 level change trigger wake-up. The other one is any interrupt in EAL = 1 & function interrupt enable. That’s mean users can setup any function with interrupt enable, and the system is waked up until the interrupt issue. Inserting IDLE mode is controlled by idle bit of PCON register. When idle = 1, the system inserts into IDLE mode. After system wake-up from IDLE mode, the idle bit is disabled (zero status) automatically.        The program stops executing, and full functions are disabled. Only the timer with wake-up function is active. The oscillator to be the system clock source keeps running, and the other oscillators operation is depend on system operation mode configuration. If inserting IDLE mode from normal mode, the system insets to normal mode after wake-up. The IDLE mode wake-up sources are P0/P1 level change trigger. If the function clock source is system clock, the functions are workable as enabled and under IDLE mode, e.g. Timer, PWM, event counter… All interrupt inEAL = 1 & function interrupt enable can wake-up in IDLE mode. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 System Operating Mode 46 SN8F5702 Series www.sonix.com.tw 9.4 Wake up Under STOP mode (sleep mode) or idle mode, program doesn’t execute. The wakeup trigger can wake the system up to normal mode. The wakeup trigger sources are external trigger (P0/P1 level change) and internal trigger (any interrupt in EAL = 1 & function interrupt enable). The wakeup function builds in interrupt operation issued request flag and trigger system executing interrupt service routine as system wakeup occurrence. When the system is in STOP mode the high clock oscillator stops. When waked up from STOP mode, MCU waits for 2048 external high-speed oscillator clocks + 5 internal low-speed oscillator clocks and 64 internal high-speed oscillator clocks + 5 internal low-speed oscillator clocks as the wakeup time to stable the oscillator circuit. After the wakeup time, the system goes into the normal mode. The value of the external high clock oscillator wakeup time is as the following. The Wakeup time = 1/Fosc * 2048 (sec) + 1/Flosc * 5 + high clock start-up time Example: In STOP mode (sleep mode), the system is waked up. After the wakeup time, the system goes into normal mode. The wakeup time is as the following. The wakeup time = 1/Fosc * 2048 + 1/Flosc * 5 = 0.825ms (Fosc = 4MHz) The total wakeup time = 0.825ms + oscillator start-up time The value of the internal high clock oscillator RC type wakeup time is as the following. The Wakeup time = 1/Fosc * 64 (sec) + 1/Flosc * 5 + high clock start-up time Example: In STOP mode (sleep mode), the system is waked up. After the wakeup time, the system goes into normal mode. The wakeup time is as the following. The wakeup time = 1/Fosc * 64 +1/Flosc * 5= 315 us (Fhosc = 32MHz)  Note: The high clock start-up time is depended on the VDD and oscillator type of high clock. Under STOP mode and green mode, the I/O ports with wakeup function are able to wake the system up to normal mode. The wake-up trigger edge is level changing in rising edge or falling edge. The Port 0 and Port 1 have wakeup function. Port 0 wakeup functions always enables, but the Port 1 is controlled by the P1W register. P1W Register (0x91) Bit Field Type Initial Description 7..0 P1nW R/W 0 0: Disable P1.n wakeup functionality 1: Enable P1.n wakeup functionality Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 System Operating Mode 47 SN8F5702 Series www.sonix.com.tw 10 Interrupt The MCU provides 13 interrupt sources (1 external and 12 interrupt) with 4 priority levels. Each interrupt source includes one or more interrupt request flag(s). When interrupt event occurs, the associated interrupt flag is set to logic 1. If both interrupt enable bit and global interrupt (EAL=1) are enabled, the interrupt request is generated and interrupt service routine (ISR) will be started. Most interrupt request flags must be cleared by software. However, some interrupt request flags can be cleared by hardware automatically. In the end, ISR is finished after complete the RETI instruction.The summary of interrupt source, interrupt vector, priority order and control bit are shown as the table below.  Interrupt Enable Interrupt Request (IRQ) IRQ Clearance Priority / Vector System Reset - - - 0 / 0x0000 INT0 EX0 IE0 Automatically 1 / 0x0003 PWM1 EPWM1 PWM1F By firmware 2 / 0x0083 I2C EI2C SI By firmware 3 / 0x0043 Timer 0 ET0 TF0 Automatically 4 / 0x000B ADC EADC ADCF By firmware 5 / 0x008B SPI ESPI SPIF / MODF By firmware 6 / 0x004B T2COM0 ET2C0 TF2C0 Automatically 7 / 0x0053 Timer 1 ET1 TF1 Automatically 8 / 0x001B T2COM1 ET2C1 TF2C1 Automatically 9 / 0x005B UART ES0 TI0 / RI0 By firmware 10 / 0x0023 T2COM2 ET2C1 TF2C2 Automatically 11 / 0x0063 Timer 2 ET2 / ET2RL TF2 / TF2RL By firmware 12 / 0x002B T2COM3 ET2C3 TF2C3 Automatically 13 / 0x006B Note: Don’t clear Interrupt request flags by firmware when Interrupt request flags can be cleared by hardware automatically. 10.1 Interrupt Operation Interrupt operation is controlled by interrupt request flag and interrupt enable bits. Interrupt request flag is interrupt source event indicator, no matter what interrupt function status (enable or disable). Both interrupt enable bit and global interrupt (EAL=1) are enabled, the system executes interrupt operation when each of interrupt request flags actives. The program counter points to interrupt vector (0x03 – 0x8B) and execute ISR. Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Interrupt 48 SN8F5702 Series www.sonix.com.tw 10.2 Interrupt Priority Each interrupt source has its specific default priority order. If two interrupts occurs simultaneously, the higher priority ISR will be service first. The lower priority ISR will be serviced after the higher priority ISR completes. The next ISR will be service after the previous ISR complete, no matter the priority order. For special priority needs, 4-level priority levels (Level 0 – Level 3) are used. All interrupt sources are classified into 6 priority groups (Group0 – Group5). Each group can be set one specific priority level. Priority level is selected by IP0/IP1 registers. Level 3 is the highest priority and Level 0 is the lowest. The interrupt sources inside the same group will share the same priority level. With the same priority level, the priority rule follows default priority. Priority Level IP1.x IP0.x Level 0 0 0 Level 1 0 1 Level 2 1 0 Level 3 1 1 The ISR with the higher priority level can be serviced first; even can break the on-going ISR with the lower priority level. The ISR with the lower priority level will be pending until the ISR with the higher priority level completes. Group Interrupt Source Group 0 INT0 PWM1 I2C Group 1 T0 ADC SPI Group 2 T2 COM0 Group 3 T1 T2 COM1 Group 4 UART T2 COM2 Group 5 T2 T2 COM3 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Interrupt 49 SN8F5702 Series www.sonix.com.tw When more than one interrupt request occur, the highest priority request must be executed first. Choose the highest priority request according natural priority and priority level. The steps are as the following: 1. Choose the groups which have the highest priority level between all groups. 2. Choose the group which is the highest nature priority between the groups with the highest priority level. 3. Choose the ISR which has the highest nature priority inside the group with the highest priority. Interrupt Priority Interrupt Priority Priority Level High High Level 3 Low Interrupt Group Group 0 Level 2 Group 1 Level 1 Group 2 Level 0 Group 3 Group 4 Low Higher priority level has higher priority Group 5 All groups within the same priority level IP0.0 = IP0.1 = IP0.2 = IP0.3 = IP0.4 = IP0.5 IP1.0 = IP1.1 = IP1.2 = IP1.3 = IP1.4 = IP1.5 As the example, group5 has the highest priority level and group0~group2 have the lowest priority level. It means the interrupt vector in group5 has the highest interrupt priority, the 2nd interrupt priority in group4 and the 3rd interrupt priority in group3. Group0~ group2 have the same priority level thus the nature priority rule will be followed. Therefore, interrupt priority will be group5> group4> group3> group0> group1> group2. MOV MOV Interrupt Priority High Low IP0, #00101000B IP0, #00110000B Priority Level ; Set group0 - group5 in different priority level. Interrupt Group 11 Group 5 10 Group 4 01 Group 3 00 Group 0 00 Group 1 00 Group 2 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Priority Level: GP5>GP4>GP3=GP2=GP1=GP0 Interrupt Priority: GP5>GP4>GP3>GP0>GP1>GP2 Interrupt 50 SN8F5702 Series www.sonix.com.tw IP0, IP1 Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IP0 - - IP05 IP04 IP03 IP02 IP01 IP00 IP1 - - IP15 IP14 IP13 IP12 IP11 IP10 IP0 Register (0XA9) Bit Field Type Initial Description 5..0 IP0[5:0] R/W 0 Interrupt priority. Each bit together with corresponding bit from IP1 register specifies the priority level of the respective interrupt priority group. Else Reserved R 0 IP1 Register(0XB9) Bit Field Type Initial Description 5..0 IP1[5:0] R/W 0 Interrupt priority. Each bit together with corresponding bit from IP0 register specifies the priority level of the respective interrupt priority group. Else Reserved R 0 10.3 Interrupt Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IEN0 EAL - ET2 ES0 ET1 - ET0 EX0 IEN1 ET2RL - ET2C3 ET2C2 ET2C1 ET2C0 ESPI EI2C IEN2 - - - - - - EADC - IEN4 EPWM1 - - - PWM1F - - - IRCON TF2RL TF2 TF2C3 TF2C2 TF2C1 TF2C0 - - IRCON2 - - - - - - ADCF TCON TF1 TR1 TF0 TR0 - - IE0 - S0CON SM0 SM1 SM20 REN0 TB80 RB80 TI0 RI0 SPSTA SPIF WCOL SSERR MODF - - - - I2CCON CR2 ENS1 STA STO SI AA CR1 CR0 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Interrupt 51 SN8F5702 Series www.sonix.com.tw IEN0 Register(0XA8) Bit Field Type Initial Description 7 EAL R/W 0 Enable all interrupt control bit. 0: Disable all interrupt function. 1: Enable all interrupt function. 5 ET2 R/W 0 T2 timerinterrupt control bit 0: Disable T2 interrupt function. 1: Enable T2 interrupt function. 4 ES0 R/W 0 UART interrupt control bit. 0: Disable UART interrupt function. 1: Enable UART interrupt function. 3 ET1 R/W 0 T1 timer interrupt control bit. 0: Disable T1 interrupt function. 1: Enable T1 interrupt function. 1 ET0 R/W 0 T0 timer interrupt control bit. 0: Disable T0 interrupt function. 1: Enable T0 interrupt function 0 EX0 R/W 0 External P1.0 interrupt (INT0) control bit. 0: Disable INT0 interrupt function. 1:Enable INT0 interrupt function. Else Reserved R 0 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Interrupt 52 SN8F5702 Series www.sonix.com.tw IEN1 Register(0XB8) Bit Field Type Initial Description 7 ET2RL R/W 0 T2Timer external reload interrupt control bit. 0: Disable T2external reload interrupt function. 1: Enable T2external reload interrupt function. 5 ET2C3 R/W 0 T2Timer COM3interrupt control bit. 0: Disable T2COM3 interrupt function. 1: Enable T2COM3 interrupt function. 4 ET2C2 R/W 0 T2Timer COM2 interrupt control bit. 0: Disable T2COM2 interrupt function. 1: Enable T2COM2 interrupt function. 3 ET2C1 R/W 0 T2Timer COM1interrupt control bit. 0: Disable T2COM1 interrupt function. 1: Enable T2COM1 interrupt function. 2 ET2C0 R/W 0 T2Timer COM0 interrupt control bit. 0: Disable T2COM0 interrupt function. 1: Enable T2COM0 interrupt function. 1 ESPI R/W 0 SPI interrupt control bit 0: Disable SPI interrupt function. 1: Enable SPI interrupt function. 0 EI2C R/W 0 I2C interrupt control bit. 0: Disable I2C interrupt function. 1: Enable I2C interrupt function. Else Reserved R 0 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Interrupt 53 SN8F5702 Series www.sonix.com.tw IEN2 Register (0X9A) Bit Field Type Initial Description 1 EADC R/W 0 ADC interrupt control bit. 0: Disable ADC interrupt function. 1: Enable ADC interrupt function. Else Reserved R 0 IEN4 Register (0XD1) Bit Field Type Initial Description 7 EPWM1 R/W 0 PWM1 interrupt control bit. 0 = Disable PWM1 interrupt function. 1 = Enable PWM1 interrupt function. 3 PWM1F R/W 0 PWM1interrupt request flag. 0: None PWM1 interrupt request 1:PWM1 interrupt request. Else Reserved R 0 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Interrupt 54 SN8F5702 Series www.sonix.com.tw IRCON Register (0xC0) Bit Field Type Initial Description 7 TF2RL R/W 0 T2 timer external reload interrupt request flag. 0: None TF2RL interrupt request 1: TF2RL interrupt request. 6 TF2 R/W 0 T2timer interrupt request flag. 0: None T2 interrupt request. 1: T2 interrupt request. 5 TF2C3 R/W 0 T2Timer COM3 interrupt request flag. 0: None T2COM3 interrupt request. 1: T2COM3 interrupt request. 4 TF2C2 R/W 0 T2Timer COM2 interrupt request flag. 0: None T2COM2 interrupt request. 1: T2COM2 interrupt request. 3 TF2C1 R/W 0 T2Timer COM1 interrupt request flag. 0: None T2COM1 interrupt request. 1: T2COM1 interrupt request. 2 TF2C0 R/W 0 T2Timer COM0 interrupt request flag. 0: None T2COM0 interrupt request. 1: T2COM0 interrupt request. Else Reserved R 0 IRCON2 Register (0XBF) Bit Field Type Initial Description 0 ADCF R/W 0 ADCinterrupt request flag. 0: None ADC interrupt request. 1:ADC interrupt request. Else Reserved R 0 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Interrupt 55 SN8F5702 Series www.sonix.com.tw TCON Register (0X88) Bit Field Type Initial Description 7 TF1 R/W 0 T1 timer external reload interrupt request flag. 0: None T1 interrupt request 1:T1 interrupt request. 5 TF0 R/W 0 T0 timer external reload interrupt request flag. 0: None T0 interrupt request 1:T0 interrupt request. 1 IE0 R 0 External P1.0 interrupt (INT0) request flag 0: None INT0 interrupt request. 1: INT0 interrupt request. Else Refer to other chapter(s) S0CON Register(0X98) Bit Field Type Initial Description 1 TI0 R/W 0 UART transmit interrupt request flag.It indicates completion of a serial transmission at UART. It is set by hardware at the end of bit 8 in mode 0 or at the beginning of a stop bit in other modes. It must be cleared by software. 0: None UART transmit interrupt request. 1:UART transmit interrupt request. 0 RI0 R/W 0 UART receive interrupt request flag.It is set by hardware aftercompletion of a serial reception at UART. It is set by hardware at the end of bit 8 in mode 0 or in the middle of a stop bit in other modes. It must be cleared by software. 0: None UART receive interrupt request. 1: UART receive interrupt request. Else Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Refer to other chapter(s) Interrupt 56 SN8F5702 Series www.sonix.com.tw SPSTA Register (0XE1) Bit Field Type Initial Description 7 SPIF R 0 SPI complete communication flag Set automatically at the end of communication Cleared automatically by reading SPSTA, SPDAT registers 4 MODF R 0 Mode fault flag Else Refer to other chapter(s) I2CCON Register(0XDC) Bit Field Type Initial Description 7 SI R/W 0 Serial interrupt flag The SI is set by hardware when one of 25 out of 26 possible I2C states is entered. The only state that does not set the SI is state F8h, which indicates that no relevant state information is available. The SI flag must be cleared by software. In order to clear the SI bit, ‘0’ must be written to this bit. Writing a ‘1’ to SI bit does not change value of the SI. Else Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Refer to other chapter(s) Interrupt 57 SN8F5702 Series www.sonix.com.tw 10.4 Example Defining Interrupt Vector. The interrupt service routine is following user assembly code program. START: ISR_T0: ISR_ADC: ISR_T1 ORG JMP … ORG JMP ORG JMP … ORG JMP … ORG … … JMP … 0 START ; 0000H ; Jump to user program address. 0X000B ISR_T0 0X001B ISR_T1 ; Jump to interrupt service routine address. 0X008B ISR_ADC 0X00EC ; 00ECH, The head of user program. ; User program. START ; End of user program. PUSH PUSH … POP POP RETI ACC PSW ; The head of interrupt service routine. ; Save ACC to stack buffer. ; Save PSW to stack buffer. PUSH PUSH … POP POP RETI … ACC PSW PUSH PUSH … POP POP RETI ACC PSW PSW ACC PSW ACC PSW ACC END Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 ; Load PSW from stack buffer. ; Load ACC from stack buffer. ; End of interrupt service routine. ; ; Save ACC to stack buffer. ; Save PSW to stack buffer. ; Load PSW from stack buffer. ; Load ACC from stack buffer. ; End of interrupt service routine. ; ; Save ACC to stack buffer. ; Save PSW to stack buffer. ; Load PSW from stack buffer. ; Load ACC from stack buffer. ; End of interrupt service routine. ; End of program. Interrupt 58 SN8F5702 Series www.sonix.com.tw 11 GPIO The microcontroller has up to 18 bidirectional general purpose I/O pin (GPIO). Unlike the original 8051 only has open-drain output, SN8F5702builds in push-pull output structure to improve its driving performance. 11.1 Input and Output Control The input and output direction control is configurable through P0M to P2M registers. These bits specify each pinthat is either input mode or output mode. Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P0M P07M P06M P05M P04M P03M P02M P01M P00M P1M P17M P16M P15M P14M P13M P12M P11M P10M P2M - - - - - - P21M P20M P0OC - - - P15OC P14OC P13OC P06OC P05OC P0M: 0xF9, P1M: 0xFA, P2M: 0xFB Bit Field Type Initial Description 7 P07M R/W 0 Mode selection of P0.7 0: Input mode 1: Output mode 6 P06M R/W 0 Mode selection of P0.6 0: Input mode 1: Output mode 5 P05M R/W 0 Mode selection of P0.5 0: Input mode 1: Output mode 4..0 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 et cetera GPIO 59 SN8F5702 Series www.sonix.com.tw P0OC Register (0xE4) Bit Field 7..5 Type Initial Description R/W 000 Refer to PWM chapter 4 P15OC R/W 0 P1.5 open-drain output mode 0: Disable 1: Enable, output high status becomes to input mode 3 P14OC R/W 0 P1.4 open-drain output mode 0: Disable 1: Enable, output high status becomes to input mode 2 P13OC R/W 0 P1.3 open-drain output mode 0: Disable 1: Enable, output high status becomes to input mode 1 P06OC R/W 0 P0.6 open-drain output mode 0: Disable 1: Enable, output high status becomes to input mode 0 P05OC R/W 0 P0.5 open-drain output mode 0: Disable 1: Enable, output high status becomes to input mode 11.2 Input Data and Output Data By a read operation from any registers of P0 to P2, the current pin’s logic level would be fetch to represent its external status. This operation remains functional even the pin is shared with other function like UART and I2C which can monitor the bus condition in some case. A write P0 to P2 register value would be latched immediately, yet the value would be outputted until the mapped P0M – P2M is set to output mode. If the pin is currently in output mode, any value set to P0 to P2 register would be presentedon the pin immediately. Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P0 P07 P06 P05 P04 P03 P02 P01 P00 P1 P17 P16 P15 P14 P13 P12 P11 P10 P2 - - - - - - P21 P20 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 GPIO 60 SN8F5702 Series www.sonix.com.tw P0: 0x80, P1: 0x90, P2: 0xA0 Bit Field Type Initial Description 7 P07 R/W 1 Read: P0.7 pin’s logic level Write 1/0: Output logic high or low (applied if P07M = 1) 6 P06 R/W 1 Read: P0.6 pin’s logic level Write 1/0: Output logic high or low (applied if P06M = 1) 5 P05 R/W 1 Read: P0.5 pin’s logic level Write 1/0: Output logic high or low (applied if P05M = 1) 4..0 et cetera 11.3 On-chip Pull-up Resisters The P0UR to P2UR registers are mapped to each pins’ internal 100 kΩ (in typical value) pull-up resister. Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P0UR P07UR P06UR P05UR P04UR P03UR P02UR P01UR P00UR P1UR P17UR P16UR P15UR P14UR P13UR P12UR P11UR P10UR P2UR - - - - - - P21UR P20UR P0UR: 0xF1, P1UR: 0xF2, P2UR: 0xF3 Bit Field Type Initial Description 7 P07UR R/W 0 On-chip pull-up resister control of P0.7 0: Disable* 1: Enable 6 P06UR R/W 0 On-chip pull-up resister control of P0.6 0: Disable* 1: Enable 5 P05UR R/W 0 On-chip pull-up resister control of P0.5 0: Disable* 1: Enable 4..0 et cetera * Recommended disable pull-up resister if the pin is output mode or analog function Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 GPIO 61 SN8F5702 Series www.sonix.com.tw 11.4 Pin Shared with Analog Function The microcontroller builds in analog functions, such as ADC.The Schmitt trigger of input channel is strongly recommended to switch off if the pin’s shared analog function is enabled. Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P0CON P0CON7 P1CON P1CON7 P1CON6 P1CON5 P1CON4 P1CON3 P1CON2 P1CON1 P1CON0 P2CON - - - - - - P2CON1 P2CON0 P2CON: 0x9E, P1CON: 0xD6, P0CON: 0x9D Bit Field Type Initial Description 7 P1CON7 R/W 0 Schmitt trigger control of P1.7 0: Enable 1: Disable 6 P1CON6 R/W 0 Schmitt trigger control of P1.6 0: Enable 1: Disable 5 P1CON5 R/W 0 Schmitt trigger control of P1.5 0: Enable 1: Disable 4..0 Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 et cetera GPIO 62 SN8F5702 Series www.sonix.com.tw 12 External Interrupt INT0 is external interrupt trigger sources. Build in edge trigger configuration function and edge direction is selected by PEDGE register. When both external interrupt (EX0) and global interrupt (EAL) are enabled, the external interrupt request flag (IE0) will be set to “1” as edge trigger event occurs. The program counter will jump to the interrupt vector (ORG 0x0003) and execute interrupt service routine. Interrupt request flag will be cleared by hardware before ISR is executed. 12.1 External Interrupt Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDGE - - - - - - EX0G1 EX0G0 IEN0 EAL - ET2 ES0 ET1 - ET0 EX0 TCON TF1 TR1 TF0 TR0 - - IE0 - PEDGE Register(0X8F) Bit Field Type Initial Description 1..0 EX0G[1:0] R/W 10 External interrupt 0 trigger edge control register. 00: Reserved. 01: Rising edge trigger. 10: Falling edge trigger (default) 11: Both rising and falling edge trigger Else Reserved R 0 IEN0 Register(0XA8) Bit Field Type Initial Description 7 EAL R/W 0 Enable all interrupt control bit. 0: Disable all interrupt function. 1: Enable all interrupt function. 0 EX0 R/W 0 External P1.0 interrupt (INT0) control bit. 0: Disable INT0 interrupt function. 1:Enable INT0 interrupt function. Else Copyright © 2018, SONiX Technology Co., Ltd. Datasheet Rev. 2.3 Refer to other chapter(s) External Interrupt 63 SN8F5702 Series www.sonix.com.tw TCON Register (0X88) Bit Field Type Initial Description 1 IE0 R/W 0 External P1.0 interrupt (INT0) request flag 0: None INT0 interrupt request. 1: INT0 interrupt request. Else  Refer to other chapter(s) Note: Before clear one of TF0, TF1 or IE0 flag manually by firmware, user must be made sure others request flag in TCON register doesn’t active. 12.2 Sample Code The following sample code demonstrates how to perform INT0 with interrupt. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 #define #define #define #define INT0Rsing INT0Falling INT0LeChge EINT0 (1