SN8P0112P

SN8P021X/8P011X SN8P021X/8P011X 8-bit microcontroller 1. GENERAL DESCRIPTION T he SN8P021X/8P011X is an 8-bit micro-controller utilized with CMOS technology fabrication and featured with low power consumption and high performance by its unique electronic structure. This chip is designed with the excellent IC structure, including the program memory up to 2K/1K-word OTP ROM, 64 bytes of the data memory, one 8-bit T0 basic timer, one 8-bit timer/event counter, a watch dog timer, three interrupt sources (T0, TC0, INT0), 13 I/O pins and 8 levels stack buffer. Besides, the user can choose desired oscillator configurations for the controller. There are three oscillator configurations to select for generating system clock, including high-performing crystal, ceramic resonator or cost-saving RC. 2. FEATURES ♦ Memory configuration OTP ROM size : 2048 * 16 bits for SN8P021X series OTP ROM size : 1024 * 16 bits for SN8P011X series RAM size : 64 * 8 bits. ♦ I/O pin configuration (Total 13 pins) One input port : 1 pin with wakeup function. Two Input/output ports : 12 pins. ♦ 56 powerful instructions All of instructions are 1 word with 1 or 2 cycles' execution. Execution time : 1 cycle uses 4 clocks of oscillator. All ROM area JMP instruction. All ROM area Subroutine CALL instruction. All ROM area lookup table function. (MOVC instruction) ♦ Three interrupt sources : Two internal interrupts : T0, TC0 One external interrupt : INT0 ♦ ♦ ♦ ♦ Eight levels stack buffer An 8-bit basic timer. An 8-bit timer/event counter. A watchdog timer. ♦ Acceptable oscillator type : Crystal or ceramic resonator up to 8MHz RC oscillator up to 2 MHz ♦ Package : PDIP : 16, 18, 20 SOP : 16, 18, 20 3. PIN ASSIGNMENT P1.1 INT0/P0.0 VPP/RST VSS P2.0 P2.1 P2.2 P2.3 1 U 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 SN8P0211P SN8P0211S SN8P0111P SN8P0111S P1.0 XIN XOUT VDD P2.7 P2.6 P2.5 P2.4 P1.2 P1.3 INT0/P0.0 VPP/RST VSS P2.0 P2.1 P2.2 P2.3 1 U 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 SN8P0212P SN8P0212S SN8P0112P SN8P0112S P1.1 P1.0 XIN XOUT VDD P2.7 P2.6 P2.5 P2.4 P1.2 1 U 20 P1.3 2 19 INT0/P0.0 3 18 VPP/RST 4 17 VSS 5 16 VSS 6 15 P2.0 7 14 P2.1 8 13 P2.2 9 12 P2.3 10 11 SN8P0213P SN8P0213S SN8P0113P SN8P0113S P1.1 P1.0 XIN XOUT VDD VDD P2.7 P2.6 P2.5 P2.4 SONiX TECHNOLOGY CO., LTD Page 1 Preliminary January 2000 SN8P021X/8P011X 4. BLOCK DIAGRAM PC IR FLAGS OTP ROM H-OSC TIMING GENERATOR ALU RAM ACC INTERRUPT CONTROL PORT 0 SYSTEM REGISTER TIMER & COUNTER PORT 1 PORT 2 5. PIN DESCRIPTION PIN NAME P1.0 ~ P1.3 RST/VPP TYPE I/O I DESCRIPTION Port 1.0 ~ Port 1.3 bi-direction pins. System reset inputs pin. Schmitt trigger structure, active “low”, normal stay to “high”. During program op-code, this pin be pull to 12.5Vdc to reset internal address counter and to write data into OTP-ROM. Power supply input pins. Port 2.0 ~ Port 2.7 bi-direction pins. Oscillator input pin. Oscillator output pin. Port 0.0 and INT0 trigger pin with schmitt trigger structure. VDD, VSS P2.0 ~ P2.7 XIN XOUT P0.0 / INT0 P I/O I O I Note : In order to reduce power consumption, the following procedure must be setup. a). In the SN8P0211/8P0111 version, P1.2 ~ P1.3 must be programmed to input mode with pull up resistor. SONiX TECHNOLOGY CO., LTD Page 2 Preliminary January 2000 SN8P021X/8P011X DISCLAIMER The information appearing in SONiX web pages (“this publication”) is believed to be accurate. However, this publication could contain technical inaccuracies or typographical errors. The reader should not assume that this publication is error-free or that it will be suitable for any particular purpose. SONiX makes no warranty, express, statutory implied or by description in this publication or other documents which are referenced by or linked to this publication. In no event shall SONiX be liable for any special, incidental, indirect or consequential damages of any kind, or any damages whatsoever, including, without limitation, those resulting from loss of use, data or profits, whether or not advised of the possibility of damage, and on any theory of liability, arising out of or in connection with the use or performance of this publication or other documents which are referenced by or linked to this publication. This publication was developed for products offered in Taiwan. SONiX may not offer the products discussed in this document in other countries. Information is subject to change without notice. Please contact SONiX or its local representative for information on offerings available. Integrated circuits sold by SONiX are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. The application circuits illustrated in this document are for reference purposes only. SONIX DISCLAIMS ALL WARRANTIES, INCLUDING THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SONIX reserves the right to halt production or alter the specifications and prices, and discontinue marketing the Products listed at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SONIX for such application. SONiX TECHNOLOGY CO., LTD Page 3 Preliminary January 2000