ACX306AK

ACX306AK 3.86cm (1.5 Type) NTSC/PAL Color LCD Panel Description The ACX306AK is a 3.86cm diagonal active matrix TFT-LCD panel addressed by low temperature polycrystalline silicon transistors with built-in peripheral driving circuitry. This panel provides full-color representation for NTSC and PAL systems. In addition, RGB dots are arranged in a delta pattern that provides smooth picture quality without fixed color patterns compared to vertical stripe and mosaic patterns. Features • Number of active dots: 118,000, 3.86cm (1.5 Type) in diagonal • Horizontal resolution: 240 TV lines • Optical transmittance: 6.5% (typ.) • High contrast ratio with normally white mode: 200 (typ.) • Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible) • Low voltage, low power consumption: 12V drive: 43mW (panel block, typ.) • Smooth pictures with a RGB delta arrangement • Supports NTSC/PAL • Built-in picture quality improvement circuit • Up/down and/or right/left inverse display function • LR (low reflectance) surface treatment provides an easy-to-see display even outdoors • Dirt-resistant surface treatment • Narrow frame Element Structure • Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline silicon transistors • Number of pixels Total number of dots: 494 (H) × 242 (V) = 119,548 Number of active dots: 490 (H) × 240 (V) = 117,600 • Module dimensions Package dimensions: 38 (W) × 32.6 (D) × 2.2 (H) (mm) Effective display dimensions: 31.115 (H) × 30.360 (V) (mm) Applications LCD monitors, etc. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00143-PS ACX306AK Block Diagram The panel block diagram is shown below. H Level Shifter & Shift Register COM CS V Shift Register LC Level Shifter Boost, Negative Voltage Generation Circuit Common Voltage 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GREEN Cext/Rext HCK2 HCK1 BLUE PSIG TEST RED RGT REF –2– TESTR TESTL TEST2 VDDG VSSG WIDE DWN COM VCK HST EN VDD VST VSS ACX306AK Absolute Maximum Ratings (Vss = 0V) • H driver supply voltage VDD, Cext/Rext –1.0 to +17 V • V driver boost supply voltage VDDG VDD – 1.0 to +18 V • V driver negative supply voltage VSSG –3.0 to +1.0 V • Common voltage of panel COM –1.0 to +17 V • H driver input pin voltage HST, HCK1, HCK2, RGT, WIDE –1.0 to +17 V • V driver input pin voltage VST, VCK, EN, DWN, REF –1.0 to +15 V • Video signal, uniformity improvement signal input pin voltage GREEN, RED, BLUE, PSIG –1.0 to +13 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –30 to +85 °C Operating Conditions of Panel Block 1. Input/output supply voltage conditions∗1 Item Supply voltage VDDG output voltage setting VSSG output voltage setting∗3 Symbol VDD Cext/Rext∗2 VDDG Min. 11.4 VDD – 3.4 14.0 –2.3 — Typ. 12.0 12.0 15.0 –1.8 10 (VSS = 0V) Max. 12.6 — 16.3 –1.5 160 Unit V V V V kΩ VSSG ∗2 Rext Resistor connected to Cext/Rext pin ∗1 The VDD typical voltage setting is noted as 12.0V in these specifications. ∗2 Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below. ∗3 For the VDDG, VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing Zener diode as shown in the figure below. The Cext/Rext value differs according to the rising time of the panel supply voltage. Rext Cext/Rext VDD ACX306AK VDD VSSG 1µF VSS Recommended voltage applied example Zener diode. (RD2.7UM is recommended) Voltage VDD Cext/Rext VDD – Cext/Rext Cext 7 text Time Set a Cext value that satisfies text > 1ms. VDDG 1µF Recommended voltage applied example Zener diode. (RD4.3UM is recommended) –3– ACX306AK 2. Panel input signal voltage conditions Item (Low) H/V driver input voltage REF input voltage Video signal center voltage∗4 Video signal input range∗4 Uniformity improvement signal∗4 (High) Symbol VIL VIH VREF VVC Vsig Vpsig Min. –0.3 2.6 VIH/2 – 0.3 5.8 1.0 VVC ± 2.3 VVC – 0.6 Typ. 0.0 3.0 VIH/2 6.0 VVC ± 4.0 VVC ± 2.5 VVC – 0.5 Max. 0.3 5.5 (VSS = 0V) Unit V V V V V V V VIH/2 + 0.3 6.2 VDDG – 4.0 (10.5V or less) VVC ± 2.7 VVC – 0.4 Common voltage of panel (Ta = 25°C) Vcom ∗4 Input video and uniformity improvement signals should be input the voltage amplitude symmetrical to VVC as shown in Fig. 1. PSIG waveform VVC Vpsig Fig. 1 Pin Description of Panel Block Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Symbol TESTL COM VST VCK EN DWN VDD VSS VDDG VSSG TEST2 WIDE Description Panel test output; no connection Common voltage input of panel Start pulse input for V shift register drive Clock input for V shift register drive Gate selection pulse enable input V shift register drive direction signal input Power supply input for V driver H and V driver GND Boost power supply setting for V driver Negative power supply setting for V driver No connection inside the panel. (with 1MΩ terminating resistor) Uniformity improvement signal control pulse input Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 –4– Symbol HST REF TEST Cext/ Rext HCK2 HCK1 PSIG Description Start pulse input for H shift register drive Level shifter circuit REF voltage input Panel test output; no connection Time constant power supply input for H shift register drive Clock input for H shift register drive Clock input for H shift register drive Uniformity improvement signal input GREEN Video signal (G) input to panel RED BLUE RGT TESTR Video signal (R) input to panel Video signal (B) input to panel H shift register drive direction signal input Panel test output; no connection ACX306AK Input Equivalent Circuits of Panel Block To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except the video signal input pins. All pins are connected to VSS with a high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.) (1) RED, GREEN, BLUE, PSIG VDD Input 1MΩ Signal line (2) HCK1, HCK2 VDD VDD H level shifter and shift register circuit 1MΩ HCK2 1MΩ HCK1 (3) WIDE, REF VDD VDD 350Ω Input 1MΩ REF 1MΩ 350Ω Level conversion circuit (4) HST VDD VDD 175Ω Input REF 175Ω 1MΩ 1MΩ Level conversion circuit (5) RGT, REF VDD VDD 2kΩ Input REF 2kΩ 1MΩ 1MΩ Level conversion circuit –5– ACX306AK (6) VST, VCK, EN, REF VDD 800Ω Input 1MΩ REF 1MΩ 800Ω VDD Level conversion circuit (7) DWN, REF VDD VDD 2kΩ Input 1MΩ REF 1MΩ 2kΩ Level conversion circuit (8) VDDG, VSSG VDD Boost, Negative voltage generation circuit VDDG, VSSG (9) COM Input 1MΩ LC (10) Cext/Rext VDD Cext/Rext 1MΩ H driver (11) TEST, TEST2 350Ω TEST VDD 350Ω TEST2 1MΩ 1MΩ (12) TESTL, TESTR 4MΩ TESTL VDD TESTR –6– ACX306AK Clock Timing Conditions of Panel Block Item HST rise time HST HST fall time HST data setup time HST data hold time HCKn∗5 rise time HCK HCKn∗5 fall time HCK1 fall to HCK2 rise time HCK1 rise to HCK2 fall time VST rise time VST VST fall time VST data setup time VST data hold time VCK VCK rise time VCK fall time EN rise time EN EN fall time EN fall to VCK rise/fall time EN pulse width WIDE rise time WIDE WIDE fall time WIDE (H) rise to VCK rise/fall time WIDE (H) pulse width ∗5 HCKn means HCK1 and HCK2. (fHCKn = 1.5MHz) Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVckn tfVckn trEn tfEn tdEn twEn trWide tfWide tdhWide twhWide Min. — — 300 –30 — — –15 –15 — — 30 –30 — — — — 500 2900 — — –0.4 1.4 (VIH = 3.0V, VDD = 12V, Ta = 25°C) Typ. — — 333 0 — — 0 0 — — 32 –32 — — — — 600 3000 — — –0.5 1.5 Max. 30 30 363 30 30 30 15 15 100 100 34 –34 100 100 100 100 700 3100 100 100 –0.6 1.6 µs ns µs ns Unit –7– ACX306AK Horizontal Standard Timing 3.1µs HST HCK1 HCK2 FRP 0.6µs VCK EN 3.0µs WIDE 1.1µs 1.5µs 0.4µs –8– ACX306AK Item HST rise time HST fall time Symbol trHst HST 10% trHst Waveform 90% 90% 10% tfHst Conditions • HCKn∗5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tfHst ∗6 HST HST data setup time tdHst HST 50% 50% HCK1 50% 50% HST data hold time thHst tdHst thHst • HCKn∗5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns HCKn∗5 rise time trHckn ∗5 HCKn 90% 10% 90% 10% HCKn∗5 fall time HCK HCK1 fall to HCK2 rise time tfHckn trHckn tfHckn • HCKn∗5 duty cycle 50% to1Hck = 0ns to2Hck = 0ns tdHst = 333ns thHst = 0ns ∗6 to1Hck HCK1 50% 50% 50% 50% • tdHst = 333ns thHst = 0ns HCK1 rise to HCK2 fall time HCK2 to2Hck to2Hck to1Hck 90% WIDE 10% 10% tfWide 90% WIDE rise time WIDE fall time ∗7 WIDE WIDE rise to VCK rise/ fall time trWide tfWide trWide ∗6 tdhWide VCK 50% WIDE 50% twhWide tdhWide 50% WIDE pulse width ∗6 Definitions: twhWide The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement ∗7 WIDE represents every 1H pulse as shown in Horizontal Timing. –9– ACX306AK Vertical Standard Timing NTSC 4:3 (in case of EVEN field) VST VCK FRP HST EN WIDE – 10 – ACX306AK Item VST rise time VST fall time Symbol trVst VST 10% 10% tfVst Waveform 90% 90% Conditions • VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns tfVst ∗6 VST trVst VST VST data setup time tdVst 50% 50% VCK 50% 50% VST data hold time thVst tdVst thVst • VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns VCK rise time VCK VCK fall time trVck VCK 90% 10% 90% 10% tfVck trVck tfVck • VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns tdVst = 32µs thVst = –32µs • VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns EN rise time EN fall time trEn EN 90% 10% 10% 90% tfEn ∗6 VCK tfEn trEn EN EN fall to VCK rise/fall time tdEn 50% EN 50% tdEn twEn 50% EN pulse width twEn – 11 – ACX306AK Electrical Characteristics of Panel Block (Ta = 25°C, VDD = 12.0V, VIH = 3.0V, VREF = 1.5V) 1. Horizontal drivers Item HCKn input pin capacitance HST input pin capacitance Video signal input pin capacitance Psig input pin capacitance (4:3 display) Input pin current HCK1 HCK2 HST RGT REF HCKn: HCK1, HCK2 (1.5MHz) Symbol CHckn CHst Csig Cpsig I Hck1 I Hck2 I Hst I RGT I REF Min. — — — — –600 –600 –200 –150 –900 Typ. 55 30 120 5.2 –300 –300 –100 –50 –300 Max. 65 50 150 8.0 — — — — — Unit pF pF pF nF µA µA µA µA µA HCK1: actual driving HCK2: actual driving HST = GND RGT = GND REF = VIH/2 Conditions 2. Vertical drivers Item VCK input pin capacitance VST input pin capacitance Input pin current VCK VST EN DWN WIDE Symbol CVck CVst I Vck I Vst I En I DWN I WIDE Min. — — –150 –150 –150 –150 –150 Typ. 15 15 –50 –50 –50 –50 –50 Max. 20 20 — — — — — Unit pF pF µA µA µA µA µA VCK = GND VST = GND EN = GND DWN = GND WIDE = GND Conditions 3. Total power consumption of the panel Item Total power consumption of the panel (NTSC) (Ta = 25°C) (Ta = 60°C) Symbol PWR25 PWR60 Min. — — Typ. 43 — Max. 55 75 Unit mW mW 4. Pin input resistance Item Pin – VSS input resistance 1 Symbol Rin1 Min. 0.5 Typ. 1 Max. — Unit MΩ – 12 – ACX306AK Electro-optical Characteristics Item Contrast ratio Panel transmittance∗1 R X Y Chromaticity G X Y B X Y V90 V-T characteristics∗1 25°C 60°C V50 25°C 60°C V10 Half tone color reproduction range∗1 ON time Response time∗1 OFF time Flicker∗1 Image retention time∗1 25°C 60°C R–G B–G 0°C 25°C 0°C 25°C 60°C 60°C CR ≥ 10 θ = 0° 25°C 25°C 60°C Symbol CR25 CR60 T Rx Ry Gx Gy Bx By V90-25 V90-60 V50-25 V50-60 V10-25 V10-60 V50RG V50BG ton0 ton25 toff0 toff25 F YT1 θT θB θL θR Rf CTK 7 8 6 5 4 3 Measurement method 1 2 Min. 100 100 6.0 0.595 0.310 0.240 0.580 0.120 0.08 1.30 1.30 1.70 1.70 2.30 2.30 –0.115 0 — — — — — — 15 50 35 35 — — (Ta = 25°C, NTSC mode) Typ. 200 180 6.5 0.625 0.340 0.270 0.610 0.150 0.110 1.50 1.50 1.90 1.90 2.50 2.50 –0.080 0.03 70 17 120 30 –60 — 20 60 40 40 0.9 0.9 — 0.655 0.370 0.300 0.640 0.180 0.140 1.70 1.70 2.10 2.10 2.70 2.70 –0.045 0.05 90 25 180 75 –30 rank C dB s Degree (°) % % ms V V CIE standards % Max. — Unit — Viewing angle range 9 — Surface reflection ratio Cross talk∗1 10 11 1.5 1.5 ∗1 Conforms to the measurement results for the discrete panel. – 13 – ACX306AK Basic measurement conditions (1) Driving voltage VDD = 12.0V, VIH = 3.0V, VREF = 1.5V VVC = 6.0V, VCOM = 5.5V, Vpsig = 6.0 ± 2.5V (2) Measurement temperature 25°C unless otherwise specified. (3) Measurement point One point in the center of the screen unless otherwise specified. (4) Measurement systems Three types of measurement systems are used as shown below. (5) R, G and B input signal voltage Vsig Vsig = 6.0 ± VAC [V] (VAC: signal amplitude) • Measurement system I Surface A∗ Luminance Meter Backlight LCD panel E13585A Using the TOPCON BM-5A luminance meter. Using the Stanley E13585A inverter. DC6.0V • Measurement system II Optical fiber Light receptor lens Surface A∗ Light Detector Measurement Equipment Drive Cirucuit Measure using the discrete LCD panel. Light Source • Measurement system III Light Source Optical fiber Spectroscope Surface A∗ ∗ Surface A: See the Package Outline. 1. Contrast Ratio Contrast ratio (CR) is given by the following formula. CR = L (White)/L (Black) L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the panel at VAC = 4.0V. Both luminosities are measured by System I. – 14 – ACX306AK 2. Optical Transmittance of Panel Optical transmittance (T) is given by the following formula. T = L (White)/Luminance of Backlight × 100 [%] 3. Chromaticity Chromaticity of the panels is measured by System I. Raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. System I uses x and y of the CIE standards as the chromaticity here. Signal amplitudes (VAC) supplied to each input R input R Raster G B W 0.5 4.0 4.0 0.0 G input 4.0 0.5 4.0 0.0 B input 4.0 4.0 0.5 0.0 (Unit: V) 4. V-T Characteristics V-T characteristics, or the relationship between signal amplitude and the transmittance of the panel, are measured by System II by inputting the same signal amplitude VAC to each input pin. V90, V50, and V10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively. Transmittance [%] 90 50 10 V90 V50 V10 VAC – Signal amplitude [V] 5. Half Tone Color Reproduction Range The half tone color reproduction range of LCD panels is characterized by the differences between the V-T characteristics of R, G and B. The differences of these V-T characteristics are measured by System II. System II defines signal voltages of each R, G and B raster mode which correspond to 50% of transmittance, V50R, V50G and V50B, respectively. V50RG and V50BG, that is to say the differences between V50R and V50G and between V50B and V50G, are given by the following formulas respectively. V50RG = V50R – V50G V50BG = V50B – V50G 100 V50RG V50BG Transmittance [%] 50 R raster G raster B raster 0 V50R V50B V50G VAC – Signal amplitude [V] – 15 – ACX306AK 6. Response Time Response times ton and toff are measured by System II by applying the input signal voltages in the figure to the right to each input pin. These times are defined by the following formulas. ton = t1 – tON toff = t2 – tOFF t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the figure to the right. Input signal voltage (Waveform applied to measured pixels) 4.0V 6.0V 0.5V 0V Optical transmittance output waveform 100% 90% 10% 0% tON t1 ton tOFF t2 toff 7. Flicker Flicker (F) is given by the following formula. DC and AC components (NTSC: 30Hz, rms; PAL: 25Hz, rms) of the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in System II. F [dB] = 20 log {AC component/DC component} ∗ R, G, B input signal voltage for gray raster mode is given by Vsig = 6.0 ± V50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T curve. 8. Image Retention Time Image retention time is given by the following procedures. Apply the monoscope pattern∗ to the LCD panel for 1 minute and then change to a gray scale signal (Vsig = 6.0 ± VAC [V]; VAC = 3 to 4V). Judging by sight at the VAC that holds the maximum image retention, measure the time for the residual image to disappear. ∗ Monoscope pattern input conditions Vsig = 6.0 ± 4.0 or 6.0 ± 2.0 [V] (shown in the figure to the right) Vcom = 5.5V Black level 4.0V 2.0V 6.0V 2.0V 4.0V White level 0V Vsig waveform – 16 – ACX306AK 9. Definition of Viewing Angle Range Viewing angle range is measured by System Ι. The contrast ratio (CR) is measured at the angles defined in the figure to the right and the range where CR ≥ 10 is taken as the viewing angle range. Measure with surface A∗ facing upwards. ∗ Surface A: See the Package Outline. Normal (θ = 0°) θB θT Left θL θR Top Bottom Right Surface A 10. Surface Reflection Ratio Surface reflection ratio (Rf) is given by the following formula. Rf = Reflected optical luminance of the panel surface A∗/Reflected optical luminance of Al (wafer) × 100 [%] The incident and reflected angles of light are both 0°. Both luminosities are measured by System III. ∗ Surface A: See the Package Outline. 11. Cross Talk Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi (i = 1 to 4) around the black window (Vsig = 4.0V/1V). W1 W1' W2 W2' W4 W4' Cross talk value CTK = Wi' – Wi × 100 [%] Wi W3 W3' – 17 – ACX306AK Description of Panel Block Operation 1. Color Coding The color filters are coded in a delta arrangement. The shaded area is used for the dark border around the display. Gate SW Gate SW Gate SW Gate SW Gate SW Gate SW R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B R G B R G B Active area B R G R G B R G B R 240 242 R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R 2 490 494 2 – 18 – 1 1 ACX306AK 2. Description of LCD Panel Operations • A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to each of 240 line electrodes sequentially one line electrode at a time in a single horizontal scanning period. • The selected pulse is output when the enable pin goes to high level. PAL signal pulse elimination display is possible by using the enable pin and simultaneously controlling VCK. • A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuitry, applies selected pulses to each of 490 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines. • The scanning direction of the horizontal shift registers can be switched with the RGT pin. The scanning direction is left to right (right scan) for RGT pin at high level (2.6 to 5.5V), and right to left (left scan) for RGT pin at low level (0V). In addition, the scanning direction of the vertical shift registers can be switched with the DWN pin. The scanning direction is top to bottom for DWN pin at high level (2.6 to 5.5V), and bottom to top for DWN pin at low level (0V). (These scanning directions are from a front view.) • The vertical and horizontal drivers address one pixel, and then thin film transistors (TFTs; two TFTs for one pixel) turn on to apply a video signal to the pixel. The same procedures lead to the entire 240 × 490 pixels to display a picture in a single vertical scanning period. • Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned shifted by 1.5 dots against adjacent horizontal lines. The horizontal driver output pulse must be shifted by 1.5 dots for each horizontal line against the horizontal sync signal to apply a video signal to each pixel properly. • The video signal should be input with the polarity-inverted every horizontal cycle. • The relationships between the vertical shift register start pulse VST and the vertical display period, and between the horizontal shift register start pulse HST and the horizontal display period are shown below for top to bottom and left to right scan. (1) Vertical display period (DWN: high level) VD VST VCK 1 2 239 240 Vertical display period 240H (14.5ms) (2) Vertical display period (DWN: low level) VD VST VCK 1 2 239 240 Vertical display period 240H (14.5ms) (3) Horizontal display period (RGT: high level) BLK HST 165 HCK1 1 2 3 164 166 Horizontal display period (54.6µs) HCK2 – 19 – ACX306AK 3. RGB Simultaneous Sampling The horizontal driver samples R, G and B video signal simultaneously, which requires phase matching between the R, G and B signals to prevent the horizontal resolution from deteriorating. Thus phase matching by an external signal delay circuit is needed before applying the video signal to the LCD panel. Two methods are applied for the delaying procedure: Sample-and-hold and Delay circuit. These two block diagrams are as follows. The ACX306AK has a right/left inversion function. The following phase relationship diagram indicates the phase setting for right scan (RGT = high level). For left scan (RGT = low level), the phase setting should be inverted for the B and G signals. (1) Sample-and-hold (right scan) B S/H CKB R S/H CKR G S/H CKG S/H CKG S/H CKG AC Amp 20 GREEN AC Amp 21 RED AC Amp 22 BLUE (right scan) HCKn CKB CKR CKG (2) Delay element (right scan) B Delay Delay AC Amp 22 BLUE R Delay AC Amp 21 RED G AC Amp 20 GREEN – 20 – ACX306AK ACX306AK ACX306AK System Configuration +12.0V +3.0V +12.0V PSIG Y/color difference R/G/B RED GREEN BLUE COM HST HCK1 CXA3522R Serial data HCK2 VST VCK DWN EN RGT REF WIDE VSSG LCD Panel ACX306AK VDDG Cext/Rext Rext Cext ∗ See page 3 for the value setting. Zener diode RD4.3UM 1µF +12.0V Zener diode RD2.7UM 1µF – 21 – ACX306AK Notes on Handling (1) Static charge prevention Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install grounded conductive mats on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dirt a) Operate in a clean environment. b) When delivered, the panel surface (Polarizer) is not covered by a protective sheet. Take care of handling it so as not to damage the polarizer. c) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stains on the surface. d) Use ionized air to blow dust off the panel. (3) Others a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop the panel. c) Do not twist or bend the panel or panel frame. d) Keep the panel away from heat sources. e) Do not dampen the panel with water or other solvents. f) Avoid storage or use the panel at high temperatures or high humidity, as this may result in damage. – 22 – Package Outline Unit: mm 38 1.85 33.3 ±0.4 (Polarizer) 2.06 Note2 30.48(Effective area) 1 2 3 4 5 6 FPC Reinforcing board Polarizer Shield case(front) Shield case(rear) label (2.05) 33.8(Window) 2.15 34.3(Window) (1.85) 16.95 31.115(Active area) 16.85 32.7 ±0.4 (Polarizer) 24.4 ±0.4 (Polarizer) 3.42 3.12 22.86(Active area) 19 25 ±0.4 (Polarizer) 1.4 4 3 5 9.82 32.6 Center (reference) Center (reference) 16.12 (20) 25.4(Window) 10.18 26(Window) 3 6 (16.48) 10.53 ±0.5 10.94 ±0.5 12.5 ±0.05 1 2 3.25 ±0.5 (3.78) 21.5 ±0.5 7.81 ±0.5 28.9 ±0.5 φ 0.85 ±0.05 7 7.5 Rear View 0.3 1.03 Pin24 Pin1 6.6 ±0.5 34.9 ±0.5 3 ±0.3 4 ±0.5 Front view 1.4 ±0.1 LCD panel 1 4 ±0.1 BB 0.35 (0.5) ±0.03 0.5 ±0.1 P : 0.5±0.02×23=11.5±0.03 Sony Corporation ACX306AK A(3 : 1) Erectrode enlarged(back) 0.5 ±0.15 B B 12.5 ±0.05 Note1. Tolerance with no indication(±0.2) 2. SONY logotype 3. Design the guaranteed area of polarizer within the outer circumference of 0.7mm of the active area. 4. Mass:approximately 7g (3.48) – 23 –