CXA1622P

CXA1622M/P Stereo Power Amplifier/Monaural BTL Power Amplifier Description The CXA1622M/P is a bipolar IC developed as power amplifier for compact radio cassettes with built-in pre-amplifier and power amplifier electrical volume. Features • Use one channel in stereo mode · EIAJ output=110 mW (Typ.), VCC=3 (CXA1622M) · EIAJ output=450 mW (Typ.), VCC=6 (CXA1622P) • BTL mode · EIAJ output=320 mW (Typ.), VCC=3 (CXA1622M) · EIAJ output=360 mW (Typ.), VCC=3 CXA1622M 16 pin SOP (Plastic) CXA1622P 16 pin DIP (Plastic) V, RL=8 Ω V, RL=8 Ω Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC 8 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 410 (CXA1622M) mW 1200 (CXA1622P) mW Operating Conditions (Ta=25 °C) • Supply voltage • Stereo mode 1.8 V to 4.5 V (CXA1622M) 1.8 V to 7.0 V (CXA1622P) • Monaural BTL mode 1.8 V to 4.5 V (3 V recommended) V, RL=8 Ω V, RL=8 Ω (CXA1622P) • Built-in electrical volume • Built-in ripple filter (ripple rejection 34.5 dB typ.) • Selection between stereo power amplifier and monaural BTL power amplifier is possible by switching Pin 2. Applications Suitable for audio power amplifier for stereo and monaural radios and power amplifier for radio cassette and Walkman. { Power dissipation curve Free air PD-Power dissipation (mW) 1000 CXA1622P 500 CXA1622M –30 –20 –10 0 10 20 30 40 50 60 70 Ta-Ambient temperature (°C) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E92121B79-TE CXA1622M/P Pin Description Pin No. Symbol VCC 16 Equivalent circuit Pin voltage 3V 6V Description 1, 16 IN1 IN2 1 11k 0 7.5k GND 0 Input 3 NC — — VCC 4 4, 13 NF1 NF2 13 4.7k 100k 1.5 3 Power amplifier NF. Connected to time constant 4.7 µF. GND 5, 12 6, 11 GND1 GND2 P-GND1 P-GND2 VCC 0 0 0 0 Pre-amplifier GND Power amplifier GND 7, 10 OUT1 OUT2 7 10 1.5 100k 3 Power amplifier output GND VCC 8.5k 8 RIPPLE 8 73k 90k 73k 90k 2.72 5.43 Connected to time constant 10 µF for ripple filter. 9 VCC 3 6 VCC —2— CXA1622M/P Pin No. Symbol Equivalent circuit Pin voltage 3V 6V Description VCC 14 VOL 14 20k 80k GND 0 to 1.25 0 to 1.25 Control gain with change in voltage (0 to 1.25 V) to electrical volume control pin. VCC 24k 15 REG 15 1.25 4k 1.25 Regulator pin VCC REG 15k 2 SW 2 1.25 15k 1.25 Mode selection SW • BTL mode when open • Stereo mode when connected to GND Block Diagram, Pin Configuration, and Application Circuit 1) Stereo mode GND C3 10µ R1 50k REG VOL + 13 4 NF2 NC + C4 3.3µ + IN1 GND NF1 + C2 10µ IN1 16 15 REG 1 IN2 IN2 + C1 10µ 2 SW C5 3.3µ C7 0.1µ V1 3V C9 0.1µ C10 220µ + P GND1 OUT1 12 11 10 9 PRE+POWER1 VOL PRE+POWER2 5 GND 6 P GND2 7 OUT2 8 RIPPLE VCC + OUT1 C12 220µ C5 0.1µ + C8 10µ + OUT2 C11 220µ GND SP2 8 GND SP1 8 14 3 —3— CXA1622M/P 2) BTL mode C2 10µ R1 50k REG VOL + 13 4 NF2 NC + C3 3.3µ + 16 IN1 15 IN + REG VOL PRE+POWER2 C1 10µ 1 IN2 2 SW 3 5 GND C6 0.1µ C8 0.1µ C9 220µ + OUT+ P GND1 OUT1 GND NF1 VCC 9 12 11 10 PRE+POWER1 SP2 8 6 P GND2 7 OUT2 8 RIPPLE OUT– C5 0.1µ + C7 10µ GND C4 3.3µ V1 3V 14 ∗ The input signal enters the pre-amplifier with attenuation controlled with DC at Pin 14 and then it is amplified by the approximately 30 dB (fixed) power amplifier. ∗ The state of Pin 2 can be used to select between stereo mode and monaural BTL mode. The pre-power 1 and pre-power 2 output are positive phase output when Pin 2 is GND. Pre-power 2 is inverse output of pre-power 1 output when Pin 2 is open. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —4— Stereo mode BIAS SW conditions Input waveform and Output waveform and description of test method Min. Typ. Max. bias description Input point Test point { Unit S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 Upper : CXA1622M (VCC=3 V) Lower : CXA1622P (VCC=6 V) Test Typical conditions for each bias 1.0 1.0 28 27 28 27 –3 3.0 3.0 33.7 32.6 33.7 32.6 0 8.2 7.7 38 36 38 36 3 Function block No. Test item S1 S2 S3 1 Circuit current during no signal Circuit current I1 during no signal ON V4 V1=–40 dBm 1 kHz OFF OFF OFF ON OFF OFF ON OFF OFF OFF OFF OFF OFF OFF mA 2 Audio voltage gain Lch OFF ON V4 V5 V5 V1=–40 dBm 1 kHz ON ON OFF dB 3 Audio voltage gain Rch L and R channel balance V1=–40 dBm 1 kHz ON ON OFF V4 OFF ON dB 4 Channel balance dB 5 Attenuation Lch ON OFF Output level difference between max volume and half volume V1=–40 dBm 1 kHz 1.5 1.0 5.8 4.3 12 12 dB —5— OFF ON V5 ON ON OFF V4 OFF ON V5 ON OFF V4 OFF ON V5 OFF OFF ON OFF V4 OFF ON V5 ON OFF 6 Attenuation Rch OFF ON Output level difference between max volume and half volume V1=–20 dBm 1 kHz, RL=8 Ω Output level where THD=10 % V1=–20 dBm 1 kHz, RL=8 Ω Output level where THD=10 % V1=–20 dBm 1 kHz, RL=8 Ω Distortion factor when output is 50 mW V1=–20 dBm 1 kHz, RL=8 Ω Distortion factor when output is 50 mW Noise level during no signal at max volume Noise level during no signal at max volume V1=–40 dBm 1 kHz Rch output level when Lch is input V1=–40 dBm 1 kHz Lch output level when Rch is input 1.5 1.0 350 90 350 90 5.8 4.3 450 110 450 110 0.7 12 12 dB 7 EIAJ output Lch ON OFF mW 8 EIAJ output Rch OFF ON mW 9 Audio distortion factor Lch ON OFF 2.5 % 10 Audio distortion factor Rch OFF ON 0.7 2.5 % 11 Residual noise level Lch OFF OFF OFF –65 –60 dBm 12 Residual noise level Rch –65 –60 dBm 13 Crosstalk L → R ON ON –60 –56 dBm CXA1622M/P 14 Crosstalk R → L OFF ON –60 –56 dBm BTL mode VCC=3 V BIAS SW conditions Input waveform and Output waveform and description of test method Min. Typ. Max. bias description Input point Test point Upper : CXA1622M Lower : CXA1622P Test S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 Typical conditions for each bias Function block No. Test item Unit S1 S2 S3 1 Circuit current during no signal Circuit current I1 during no signal ON |V3| Output DC bias lag OFF ON ON OFF OFF OFF ON OFF ON ON OFF ON ON OFF 3 7 mA 2 Output DC bias lag V3 V1=–40 dBm 1 kHz ON V3 Output level difference between max volume and half volume ON V3 V1=–20 dBm 1 kHz, RL=8 Ω Output level where THD=10 % V1=–20 dBm 1 kHz, RL=8 Ω V1=–40 dBm 1 kHz 0 34 30 1.5 1.0 260 220 38 37 6.0 5.0 360 320 30 42 43 12 12 mV 3 Audio voltage gain ON dB 4 Attenuation dB 5 EIAJ output mW —6— V3 OFF OFF V3 6 Audio distortion factor Distortion factor when output is 50 mW Noise level during no signal at max volume –65 2.5 % 7 Residual noise level –62 dBm CXA1622M/P CXA1622M/P Electrical Characteristics Test Circuit C4 10µ R3 50k S8 R1 25k C3 10µ + R2 25k S7 C6 3.3µ S6 S5 + S9 S2 16 15 14 13 12 11 10 9 P GND1 OUT1 GND IN1 VOL REG NF1 VCC S11 R5 8 CXA1622M/P P GND2 OUT2 GND C1 10µ + RIPPLE Y3 Y SW IN2 1 2 NC 3 4 NF2 S3 5 6 7 8 S1 + + S18 V1 RC + C2 10µ + S4 C5 3.3µ C7 0.1µ + C9 10µ C12 220µ + I1 A GND Notes on Operation • Set print pattern to low impedance because Pins 6 and 11 are GND of power amplifier output stage. • The value of the phase correction capacitance attached to Pins 7 and 10 varies slightly according to the print pattern. • Provide a large land for DIP type Pin 5 because it also serves as heat dissipation pin. • Place the by-pass capacitor of VCC (Pin 9) as close to the pin as possible. —7— + + C8 0.1µ V2 3V C10 C11 0.1µ 220µ C13 220µ V R6 8 V4 S12 R4 8 V5 V S13 V6 V S14 CXA1622M/P Stereo output single mode ∗ Keep the by-pass capacitor close to the IC pins C7 0.1µ C5 3.3µ + 13 + IN1 C2 10µ + C12 220µ 16 15 14 12 11 10 9 GND NF1 CXA1622M/P P GND2 RIPPLE OUT2 GND NF2 IN2 SW + IN2 C1 10µ 1 2 NC 3 4 5 6 P GND1 7 OUT1 REG VOL VCC IN1 8 + + C4 3.3µ C5 0.1µ + C8 10µ GND Monaural output BTL mode ∗ Keep the by-pass capacitor close to the IC pins C5 0.1µ C4 3.3µ + V1 3V ∗ C8 C9 0.1µ 220µ + 16 REG VOL NF1 P GND1 OUT1 GND IN1 IN C1 10µ CXA1622M/P + VCC P GND2 1 2 3 4 5 6 7 + C3 3.3µ C5 0.1µ + RIPPLE OUT2 GND NF2 SW IN2 NC + C2 10µ R1 50k 15 14 13 12 11 10 9 8 C7 10µ GND —8— + C11 220µ + C3 10µ R1 50k V1 3V ∗ C9 C10 0.1µ 220µ R3 8 R2 8 R2 8 CXA1622M/P When using internal IC electrical volume in BTL mode C5 0.1µ C4 3.3µ + 13 4 16 15 14 12 11 10 9 GND NF1 P GND1 OUT1 REG VOL IN1 IN C1 10µ + VCC CXA1622M/P P GND2 RIPPLE OUT2 GND IN2 1 2 3 NF2 SW NC 5 6 7 8 + C3 3.3µ C5 0.1µ + C7 10µ GND When using IC as fixed gain amplifier in BTL mode Pin14 → GND (IC Gain MAX) C5 0.1µ C4 3.3µ + C8 C9 0.1µ 220µ + C2 10µ + V1 3V 16 15 14 13 12 11 10 9 REG VOL NF1 P GND1 GND OUT1 IN1 IN C1 10µ + + VCC CXA1622M/P P GND2 RIPPLE OUT2 1 2 3 4 GND NF2 SW IN2 NC 5 6 7 8 + C3 3.3µ C5 0.1µ + C7 10µ GND —9— + R2 8 s.p R2 8 s.p + C2 10µ R1 50k V1 3V C8 C9 0.1µ 220µ CXA1622M/P BTL, Stereo Application Circuit When using internal IC electrical volume 16 15 14 13 12 11 10 9 GND VOL NF1 P GND1 OUT1 REG IN1 VCC IN Lch + CXA1622M/P P GND2 RIPPLE OUT2 GND C1 10µ NF2 SW IN2 NC 1 2 3 4 5 6 7 8 + C3 3.3µ C5 0.1µ + C7 10µ LINKAGE VOL. 16 15 14 13 12 11 10 9 REG GND VOL NF1 P GND1 OUT1 IN1 IN Rch + CXA1622M/P P GND2 RIPPLE OUT2 C1 10µ GND NF2 SW IN2 NC VCC 1 2 3 4 5 6 7 8 + C3 3.3µ C5 0.1µ + C7 10µ GND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —10— + + + C2 10µ R1 50k C5 0.1µ C4 3.3µ V1 3V C8 C9 0.1µ 220µ + R2 8 s.p R2 8 s.p + + C2 10µ R1 50k C5 0.1µ C4 3.3µ C8 C9 0.1µ 220µ CXA1622M/P BTL, Stereo Application Circuit When using IC as fixed gain amplifier Pin14 → GND (IC Gain Max) C5 0.1µ C4 3.3µ C8 0.1µ + 14 13 C2 10µ + 16 15 C9 220µ + R2 8 s.p + R2 8 s.p GND 12 11 10 9 VOL NF1 P GND1 REG GND OUT1 OUT2 7 IN1 IN Lch C1 10µ + + CXA1622M/P P GND2 RIPPLE 8 1 2 3 4 GND NF2 SW IN2 NC 5 6 + C3 3.3µ C5 0.1µ + VCC C7 10µ V1 3V C8 C9 0.1µ 220µ 9 LINKAGE C2 10µ + 16 15 14 C4 3.3µ + 13 12 11 C5 0.1µ 10 GND VOL NF1 P GND1 OUT1 OUT2 7 REG IN1 IN Rch + + CXA1622M/P P GND2 RIPPLE 8 C1 10µ GND NF2 SW IN2 NC 1 2 3 4 5 6 + C3 3.3µ C5 0.1µ + VCC C7 10µ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —11— CXA1622M/P Output vs Distortion 1 CXA1622P stereo mode single-channel input 10 10 Output vs Distortion 2 CXA1622M stereo mode single-channel input VCC=1.8V VCC=3V VIN=–26dBm fIN=1kHz RL=8Ω IN=–20dBm IN=–26dBm 0 1000 10 100 VCC=1.8V VIN=–26dBm fIN=1kHz RL=8Ω VCC=4.5V IN=–26dBm IN=–20dBm 10 100 Distortion factor [%] 5 Distortion factor [%] VCC=3V 5 0 VCC=4.5V 1000 Output [mV] Output [mV] Output vs Distortion factor 3 CXA1622P BTL mode 10 10 Output vs Distortion 4 CXA1622M BTL mode VCC=1.8V VCC=3V VIN=–26dBm fIN=1kHz RL=8Ω Distortion factor [%] VCC=3V VIN=–26dBm fIN=1kHz RL=8Ω 5 Distortion factor [%] VCC=1.8V 5 IN=–20dBm IN=–26dBm 0 0 10 100 1000 10 100 1000 Output [mV] Output [mV] Stereo mode frequency characteristics VIN=–40dBm VOL MAX VCC=3V 0 0 BTL mode frequency characteristics VIN=–40dBm VOL MAX VCC=3V Output [dB] –10 Output [dB] –10 IN=–40dBm,1kHz is assumed as 0dB output C=220µF RL=8Ω –20 IN=–40dBm,1kHz is assumed as 0dB –20 10 100 1k 10k 100k 10 100 1k 10k 100k Input signal frequency [Hz] Input signal frequency [Hz] —12— CXA1622M/P Package Outline CXA1622M Unit : mm 16PIN SOP (PLASTIC) + 0.4 9.9 – 0.1 + 0.4 1.85 – 0.15 16 9 0.15 + 0.2 0.1 – 0.05 + 0.3 5.3 – 0.1 7.9 ± 0.4 0.45 ± 0.1 1.27 + 0.1 0.2 – 0.05 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PACKAGE MASS SOP-16P-L01 SOP016-P-0300 LEAD MATERIAL COPPER ALLOY 0.2g LEAD TREATMENT EPOXY RESIN SOLDER PLATING 16PIN DIP (PLASTIC) CXA1622P + 0.3 6.4 – 0.1 + 0.4 19.2 – 0.1 16 9 7.62 + 0.1 0.05 0.25 – 0° to 15° EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.0 g 1 2.54 8 + 0.4 3.7 – 0.1 0.5 MIN 0.5 ± 0.1 1.2 ± 0.15 3.0 MIN Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE DIP-16P-01 DIP016-P-0300 Similar to MO-001-AE LEAD TREATMENT LEAD MATERIAL PACKAGE MASS —13— 0.5 ± 0.2 1 8 6.9