CXA1784AS

CXA1784AS US Audio Multiplexing Decoder For the availability of this product, please contact the sales office. Description The CXA1784AS is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction and sound processor. Various kinds of filters are built in while adjustment, mode control and sound processor control are all executed through I2C BUS. Features • Audio multiplexing decoder, dbx noise reduction decoder and sound processor are all included in a single chip. Almost any sort of signal processing is possible through this IC. • All adjustments are possible through I2C BUS to allow for automatic adjustment. • Various built-in filter circuits greatly reduce external parts. • There are two systems for both inputs and outputs, and each mode control is possible. Standard I/O Level • Input level COMPIN (Pin 17) AUXIN-L/R (Pins 38 and 37) • Output level TVOUT-L/R (Pins 35 and 34) LSOUT-L/R (Pins 6 and 5) Pin Configuration (Top View) TVOUT-R SURRTC AUXIN-R VCAWGT BASSL1 VCATC VEOUT VCAIN VEWGT SAPOUT BASSR1 VETC SAPIN NOISETC BASSR2 AUXIN-L TVOUT-L 42 pin SDIP (Plastic) Absolute Maximum Ratings (Ta=25°C) 11 • Supply voltage VCC • Operating temperature Topr –20 to +75 • Storage temperature Tstg –65 to +150 • Allowable power dissipation PD 2.2 Range of Operating Supply Voltage 9±0.5 V °C °C W V Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Structure Bipolar silicon monolithic IC 245 mVrms 490 mVrms 490 mVrms 490 mVrms ITIME 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 VE 26 25 24 23 GND 20 NC 22 1 BASSL2 2 TRER 3 TREL 4 SURROUT 5 LSOUT-R 6 LSOUT-L 7 SDA 8 SCL 9 DGND 10 11 12 13 14 15 16 17 18 19 21 PLINT SUBOUT IREF STFIL MAININ COMPIN STIN SAD MAINOUT Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– SAPTC VGR VCC E95430A5Z-PK Block Diagram MAINOUT 14 AUXIN-R 37 SUBOUT 19 AUXIN-L 38 MAININ 13 PLINT 15 STFIL 16 STLPF 35 TVOUT-L SW1 MATRIX FLT SW2 LPF VCA 34 TVOUT-R "STLPF" 1/4 1/2 LFLT VCO "STEREO" WIDEBAND DeEm (+6dB) LPF NRSW/FOMO/ SAPC EXT1/EXT2/M1/M2 COMPIN 17 VCA LPF PREVOL 39 SURRTC SURROUND 42 BASSL1 PREVOL SURR STIND SAPVDET "SAPVCO" LOGIC VCC 21 INSW1 & INSW2 1 BASSL2 40 BASSR1 BASS BASS BASS –2– LPF DeEm "NOISE" "SAP" HPF RMSDET VE SPECTRAL LPF LPF "SAPLPF" AMP (+4dB) SW "PONRES" GND 23 BPF SAPVCO 41 BASSR2 VCA NOISETC 22 NOISE DET 3 TREB TREB TREBLE TREL 2 TRER SAPTC 18 SAPIND MATRIX RMSDET VOL-R STLPF STVCO SAPLPF SAPVCO SAPFDET VOL-R SURR-VOL VOL-L VOL-S ITIME 33 IREF I2 C BUS I/F VOL-L (L-R) 9 8 7 6 5 4 11 SDA STIN SAPIN SAPOUT 12 10 24 25 20 26 VE 27 28 29 30 31 32 SAD SCL SURROUT IREF VCAIN DGND LSOUT-L LSOUT-R VGR VETC VCATC VEOUT VEWGT VCAWGT CXA1784AS CXA1784AS Pin Description Pin No. Symbol Pin voltage Equivalent circuit VCC 3k (Ta = 25 °C, VCC = 9 V) Description BASS filter pin. (Left channel) (Connect a 15 nF capacitor between Pins 1 and 42.) The cutoff frequency is determined by the built-in resistor and the external capacitance. BASS filter pin. (Right channel) (Connect a 15 nF capacitor between Pins 41 and 40.) The cutoff frequency is determined by the built-in resistor and the external capacitance. 1 BASSL2 4.0 1 41 13.2k 10.7k 8.57k 6.89k 500 500 42 BASSL1 4.0 41 BASSR2 4.0 5.66k 4.44k 3.67k VCC 40 42 40 BASSR1 4.0 4V 15.3k VCC 3k 2 TRER 4.0 4.2k 3.42k 2.73k 2.2k 1.8k 1.42k 500 500 TREBLE filter pin. (Right channel) (Connect a 6.8 nF capacitor between this pin and GND.) 3 TREL 4.0 VCC 1.17k 4.88k 2 3 TREBLE filter pin. (Left channel) (Connect a 6.8 nF capacitor between this pin and GND.) VCC 4 SURROUT 4.0 VCC 500 (L - R) signal output pin. 5 LSOUT-R 4.0 4 5 6 500 LSOUT right channel output pin. 6 LSOUT-L 4.0 LSOUT left channel output pin. –3– CXA1784AS Pin No. Symbol Pin voltage Equivalent circuit VCC 7.5k ↓ 35µ 2.1V 4k Description 7 SDA — 7.5k ×2 4.5k ×5 3k Serial data I/O pin. VIH > 3.0 V VIL < 1.5 V 7 VCC 7.5k ↓ 35µ 2.1V 4k 8 SCL — 19.5k ×4 Serial clock input pin. VIH > 3.0 V VIL < 1.5 V 3k 8 9 DGND — VCC 9 Digital block GND. 2V 40k 80k 10 10 SAD — 10k Slave address control switch. The slave address is selected by changing the voltage applied to this pin. 3k 147 11 VGR 1.3V 11k 9.7k 19.4k ×4 VCC 11k 11k Band gap reference output pin. (Connect a 10 µF capacitor between this pin and GND.) 11 2.06k –4– CXA1784AS Pin No. Symbol Pin voltage VCC 40k Equivalent circuit Description 40k 30k 30k 15k ×2 30k VCC 12 IREF 1.3V 30p 1.8k 12 147 6.3k Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62 kΩ (±1%) resistor between this pin and GND.) 16k VCC 23k 23k ↓ 10µ VCC 13 MAININ 4.0V 147 13 47k 4V VCC 15k ×4 VCC 147 14 Input the (L + R) signal from MAINOUT (Pin 14). 14 MAINOUT 4.0V (L + R) signal output pin. ↓ 200µ 1k VCC 15k 15k 147 15 PLINT 6.3V 20k 20k 15 Pilot cancel circuit loop filter integrating pin. (Connect a 1 µF capacitor between this pin and GND.) ↓ 26µ 20k ↓ 50µ 10k –5– CXA1784AS Pin No. Symbol Pin voltage Equivalent circuit VCC 3k 3k Description 150k 16 STFIL 5.3V 75k 75k 4k 4k 147 16 Stereo block PLL loop filter integrating pin. 12k 1k 1k VCC 11k 11k 11k 27.66k 17 COMPIN 4.0V 500 500 4V 27.66k 34.86k 27.66k 34.86k 24.06k 17 147 VCC Audio multiplexing signal input pin. VCC 8k 10k 3k 1k VCC 4k ↓ 50µ 18 18 SAPTC 4.5V Set the time constant for the SAP carrier detection circuit. (Connect a 4.7 µF capacitor between this pin and GND.) Vcc 2k 2k 10P 4k 19 SUBOUT 4.0V 14.4k 2k 2k 500 19 500 147 (L - R) signal output pin. 2k 4k 1k –6– CXA1784AS Pin No. Symbol Pin voltage Equivalent circuit VCC 23k 23k Description 20 STIN 4.0V 11.7k 147 20 147 47k 20k 21 Vcc 8k 3.3k 4V Input the (L - R) signal from SUBOUT (Pin 19). 25 25 SAPIN 4.0V 47k 4V Input the (SAP) signal from SAPOUT (Pin 24). 21 VCC — Supply voltage pin. 10k 1k 2k 4k ×2 4V 3k Vcc 3k 22 NOISETC 3.0V Set the time constant for the noise detection circuit. (Connect a 4.7 µF capacitor and a 200 kΩ resistor between this pin and GND.) 22 23 23 GND — Vcc 5P Analog block GND. 500 24 SAPOUT 4.0V 500 7.4k 24 147 17k SAP FM detector output pin. 24k ↓ 10µ 4k ↓ 50µ 4V VCC 7.5k 26 VE 4.0V 147 26 Variable de-emphasis integrating pin. (Connect a 2700 pF capacitor and a 3.3 kΩ resistor in series between this pin and GND.) –7– CXA1784AS Pin No. Symbol Pin voltage Equivalent circuit Vcc Description 500 2.9V 4V 36k 27 VEWGT 4.0V 27 147 500 Weight the variable deemphasis control effective value detection circuit. (Connect a 0.047 µF capacitor and a 3 kΩ resistor in series between this pin and GND.) 8k 30k ↓ 8µ 4k ↓ 50µ Vcc 28 VETC 1.7V ×4 ×4 28 4k ↓ 50µ 20k ↓ 7.5µ Determine the restoration time constant of the variable de-emphasis control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 3.3 µF capacitor between this pin and GND.) Vcc 5P 500 29 VEOUT 4.0V 29 10k 500 Variable de-emphasis output pin. (Connect a 4.7 µF non-polar capacitor between Pins 29 and 30.) VCC 47k 47k 30 VCAIN 4.0V 20k VCC 30 VCA input pin. Input the variable deemphasis output signal from Pin 29 via a coupling capacitor. –8– CXA1784AS Pin No. Symbol Pin voltage Equivalent circuit VCC 40k 40k 3p Description 500 31 31 VCAWGT 4.0V 2.9V 36k 500 147 ↓ 50µ 4k ↓ 8µ 30k 8k Weight the VCA control effective value detection circuit. (Connect a 1 µF capacitor and a 3.9 kΩ resistor in series between this pin and GND.) VCC ×4 ×4 32 32 VCATC 1.7V ↓ 50µ 4k ↓ 7.5µ 20k Determine the restoration time constant of the VCA control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 10 µF capacitor between this pin and GND.) Set the reference current for the effective value detection timing current. The reference current is adjusted with the BUS DATA “SPECTRAL” based on the current which flows to this pin. The timing current determines the restoration time constant of the detection circuit and the variable de-emphasis characteristics. (Connect a 43 kΩ (±1%) resistor between this pin and GND.) VCC 40k 40k 30k 20k 40k 10k 2.6V 33 ITIME 1.3V 30p 1.8k 47k 25k ×4 33 147 VCC 3k 34 TVOUT-R TVOUT right channel output pin. 4.0V 500 34 35 500 35 TVOUT-L TVOUT left channel output pin. –9– CXA1784AS Pin No. 36 Symbol NC Pin voltage — Equivalent circuit 36 36 VCC Description — 37 AUXIN-R 4.0V 23k 147 37 27.6k 47k 38 Right channel external input pin. 38 AUXIN-L 4.0V 19.6k 20k 4V Left channel external input pin. VCC 23k 20k 40k 500 24k 500 39 SURRTC 4.0V 20k VCC 39 Set the central frequency of the SURROUND circuit phase shifter. The frequency is determined by the built-in resistor and the external capacitance. (Connect a 0.022 µF capacitor between this pin and GND.) – 10 – Electrical Characteristics INSW1 = 0, = 1 INSW2 = 0, = 1 = 245mVrms = 490mVrms = 49mVrms = 147mVrms (Ta = 25°C, Vcc = 9V) Measurement conditions Filter Min. 35 34/35 440 -1.2 -3.0 — 34/35 34/35 15kLPF 19 20 log ('12k'/'1k') 15kLPF 15kLPF 15kLPF fH BPF H COMPIN input level (100% modulation level) Main (L + R) (Pre-Emphasis : OFF) SUB (L – R) (dbx-TV :OFF) Pilot SAP Carrier fH = 15.734kHz Mode Input pin No signal MONO 17 17 17 17 15kLPF 15kLPF 20 log ('100%'/'0%') 17 17 17 17 17 17 17 17 34/35 20 log ('12k'/'1k') 34/35 20 log ('5k'/'1k') 34/35 MONO MONO MONO MONO MONO ST ST ST ST ST ST 44 490 0 -1.0 0.1 — 61 150 19 19 19 19 19 0dB=49mVrms Change PILOT (f ) Level H INSW1 = 1 INSW2 = 0 = 490mVrms = 980mVrms = 98mVrms = 294mVrms INSW1 = 0 INSW2 = 1 = 100mVrms = 200mVrms = 20mVrms = 60mVrms No. Item Symbol Input signal Output pin Typ. Max. 53 540 1.0 Unit mA mVrms 1 Current consumption Icc 2 Main output level Vmain 3 FCdeem dB 1.0 0.5 % 0.15 69 190 -3.0 — — 56 — -9.0 -0.5 0.1 0.2 64 -30 -6.0 0.5 — 230 1.0 1.0 % 2.0 — -22 -3.0 dB dB dB mVrms dB 4 Main de-emphasis frequency characteristic Main LPF frequency characteristic FCmain – 11 – PILOT (f ) 0dB 20 log ('100%'/'0%') 20 log ('out'/'in') ST 17 20 log (‘on level’/’off level’) 5 Main distortion THDm 6 Main overload distortion THDmmax 7 Main S/N SNmain 8 Sub output level Vsub 9 Sub LPF frequency characteristic FCsub 10 Sub distortion THDsub 11 Sub overload distortion THDsmax 12 Sub S/N SNsub Mono 1kHz 100% mod. Pre-em. on Mono 5kHz 30% mod. Pre-em. on Mono 12kHz 30% mod. Pre-em.on Mono 1kHz 100% mod. Pre-em. on Mono 1kHz 200% mod. Pre-em off Mono 1kHz, Pre-em on SUB (L-R), 1kHz, 100% mod., NR OFF SUB (L-R) 12kHz, 30% mod., NR OFF SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R), 1kHz, 200% mod., NR OFF SUB (L-R) 1kHz, NR OFF 13 Sub pilot leak PCsub 14 Stereo ON level THst CXA1784AS 15 Stereo ON/OFF hysteresis HYst BUS RETURN dB 2.0 4.0 8.0 No. 24 150 mVrms 34/35 370 -3.0 — — 46 -8.5 — -12.0 2.0 34/35 34/35 15kLPF 15kLPF 0dB=490mVrms 34/35 34/35 34/35 23 23 23 23 -0.5 55 -7.0 -75 -9.0 4.0 35 35 15kLPF 35 35 0 0.6 2.5 6.0 % 15kLPF 34/35 24 24 15kLPF 34/35 0dB=147mVrms 15kLPF 1.5 — dB -5.5 -54 -6.0 6.0 — — — — 0.5 dB dBm 0 2.5 24 15kLPF 24 490 610 dB 190 230 Item Mode Min. Input pin Input signal Output pin Max. Filter Unit Symbol Measurement conditions Typ. 16 SAP 17 Vsap1 SAP output level 17 SAP 17 Vsap2 18 SAP LPF frequency characteristic FCsap 19 SAP 17 SAP distortion THDsap1 20 SAP SAP SAP Change SAP SAP Carrier (5fH) Level 20 log(‘on level’/’off level’) 15kLPF 17 No signal 17 SAP 1kHz, 100% mod. NR OFF 17 THDsap2 21 SAP S/N SNsap SAP 1kHz 100% mod. NR OFF SAP 1kHz 100% mod. NR ON SAP 10kHz, 30% mod. 20 log ('10k'/'1k') NR OFF SAP 1kHz 100% mod. NR OFF SAP 1kHz 100% mod. NR ON 20 log SAP 1kHz, NR OFF ('100%'/'0%') 22 SAP soft mute Smute 23 dbx out noise level Ndbx 24 SAP ON level THsap – 12 – ST ST ST ST EXT INT EXT INT EXT 37/38 17 17 37/38 37/38 17 17 17 17 1kBPF 0dB=490mVrms EXT → INT 0dB=490mVrms INT → EXT 20 log (M1="0"/M1="1") 25 SAP ON/OFF hysteresis HYsap BUS RETURN 26 ST separation 1 L → R STLsep1 27 ST separation 1 R → L STRsep1 28 ST separation 2 L → R STLsep2 29 ST separation 2 R → L STRsep2 30 TVOUT output level Vtv CTtv1 31 TVOUT cross talk 34/35 — -75 -59 CTtv2 32 MUtv1 — 1kBPF 20 log (M1="0"/M1="1") -75 34/35 — -80 CXA1784AS 33 TVOUT muted amount -70 -70 MUtv2 ST-L 300Hz 30% mod. NR ON ST-R 300Hz 30% mod. NR ON ST-L 3kHz 30% mod. NR ON ST-R 3kHz 30% mod. NR ON Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms MONO 1kHz, 100%, Pre-em. on MONO 1kHz, 100%, Pre-em. on Sine wave 1kHz, 490mVrms No. — 34/35 mV % dB % 15kLPF 34/35 34/35 34/35 — 0.1 1.0 74 — 77 0.5 20 log ('490mVrms'/'No Item Mode Unit No signal -25 25 — 0.01 when there is no signal Symbol Filter Output pin 0 Max. INT EXT Mute (M1=0)/DC difference Input pin Min. Input signal Measurement conditions Typ. 34 EXT EXT signal') TVOUT DC offset 37/38 37/38 15kLPF 15kLPF 0dB=490mVrms 5/6 0dB=490mVrms dB 1kBPF 5/6 — -75 -59 -0.9 0 0.9 37/38 17 37/38 37/38 17 37/38 20 log (M2="0"/M2="1") Mute (M2=0)/DC difference when there is no signal OStv 35 TVOUT distortion THDtv 36 EXT INT EXT INT EXT EXT INT EXT — 37/38 37/38 signal') 20 lgo ('490mVrms'/'No TVOUT S/N SNtv 37 TVOUT overload distortion THDtvmax Vls1 38 LSOUT output level Vls2 CTls1 39 LSOUT cross talk CTls2 1kBPF 5/6 5/6 15kLPF 15kLPF 15kLPF 5/6 5/6 5/6 5/6 5/6 5/6 5/6 VOL-L="0", VOL-R="0" 0dB=490mVrms 0dB=490mVrms EXT → INT 0dB=490mVrms INT → EXT — -25 — 74 — 11 -13 11 -13 1kBPF VOL-SURR="0" 0dB=490mVrms 1kBPF 5/6 4 — — 40 No signal LSOUT muted amount MUls Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms/No signal Sine wave 1kHz, 2Vrms MONO 1kHz 100%, Pre-em. on Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms MONO 1kHz 100%, Pre-em. on Sine wave 1kHz, 490mVrms -80 0 0.01 77 0.1 12 -12 12 -12 -80 -80 -70 25 0.5 — 1.0 13 -11 13 – 13 – EXT EXT EXT EXT EXT EXT EXT EXT EXT 37/38 37/38 37/38 37/38 37/38 37/38 37/38 BASS="F" 0dB=245mVrms BASS="0" 0dB=245mVrms TREBLE="F" 0dB=245mVrms TREBLE="0" 0dB=245mVrms Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms Sine wave 1kHz, 2Vrms Sine wave 100Hz, 245mVrms Sine wave 100Hz, 245mVrms Sine wave 10kHz, 245mVrms Sine wave 10kHz, 245mVrms Sine wave 1kHz, 490mVrms Sine wave 1kHz, 490mVrms 41 LSOUT DC offset OSls mV % dB % 42 LSOUT distortion THDls 43 LSOUT S/N SNls 44 LSOUT overload distortion THDlsmax 45 BASS maximum value TBmax 46 BASS minimum value TBmin 47 TREBLE maximum value TTmax dB -11 -70 -70 48 TREBLE minimum value TTmin 49 Volume minimum value VOLmin CXA1784AS 50 SURROUT volume minimum value SVOLmin No. Mode Filter 6 3.0 4.6 dB 6 6.0 7.5 4.5 1.5 EXT EXT 38 38 Input signal Typ. Max. Item Output pin Min. Symbol Input pin Unit 51 Sr1 52 SURROUND frequency characteristic 1 SURROUND frequency characteristic 2 Sine wave 330Hz, 490mVrms Sine wave 10kHz, 490mVrms Sr2 Measurement conditions SURR="1" 0dB=490mVrms SURR="1" 0dB=490mVrms – 14 – CXA1784AS CXA1784AS I2C BUS block items (SDA, SCL) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Item High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 7) during 3 mA inflow Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation Symbol VIH VIL IIH IIL VOL IOL CI fSCL t BUF Min. 3.0 0 — — 0 3 — 0 4.7 4.0 4.7 4.0 4.7 0 250 — — 4.7 Typ. — — — — — — — — — — — — — — — — — — Max. 5.0 1.5 10 10 0.4 — 10 100 — — — — — — — 1 300 — Unit V µA V mA pF kHz t HD :STA LOW t t t t t SU µs HIGH :STA HD :DAT :DAT SU t t t SU R F :STO ns µs ns µs I2C BUS load conditions: Pull-up resistor 4 kΩ (Connect to +5 V) Load capacity 200 pF (Connect to GND) I2C BUS Control Signal SDA tBUF SCL tR tF tHD;STA P S tHD;STA tLOW tHD;DAT tHIGH tSU;STA tSU;DAT Sr tSU;STO P – 15 – BASSL2 C2 TRER 6.8n C4 TREL 6.8n C5 C6 SURROUT SURRTC 4.7µ C7 LSOUT-R SIGNAL GENERATOR 4.7µ C9 LSOUT-L 4.7µ 2 R1 SIGNAL GENERATOR SDA 220 R2 4.7µ I C BUS DATA SCL 220 DGND 10 Electrical Characteristics Measurement Circuit DGND C13 10µ R4 62k METAL ±1% C16 C20 0.47µ C21 2.2k 4.7µ R6 C18 1µ 0.22µ C23 4.7µ C25 V2 AC SAD 32 11 12 13 14 15 16 17 VGR 31 IREF 30 MAININ FILTERS 15kHz LPF fHBPF 1kHz BPF 29 MAINOUT 28 PLINT MEASURES 27 STFIL 26 COMPIN 18 25 SAPTC SIGNAL GENERATOR 4.7µ 24 19 SUBOUT GND 20 23 STIN C29 21 VCC 100µ – 16 – C1 42 1 2 3 4 5 6 7 8 9 BASSL1 15n 41 C3 15n BASSR2 40 39 38 C8 4.7µ 0.022µ V3 AC 4.7µ BASSR1 AUXIN-L 37 C10 V4 AUXIN-R 36 35 C11 4.7µ NC AC TVOUT-L 34 C12 R3 S2 S6 S1 S3 S7 S5 S4 43k METAL ±1% 10µ TVOUT-R 33 1µ C15 C22 ITIME VCATC C14 TANTALUM R5 VCAWGT BUFF 3.9k VCAIN C17 4.7µ VEOUT 3.3µ VETC VEWGT C19 TANTALUM 0.047µ R7 3k R8 3.3k 2700p VE C24 GND SAPIN C26 4.7µ SAPOUT C27 4.7µ GND 4.7µ NOISETC 22 C28 R9 200k VCC A 9V V1 GND CXA1784AS CXA1784AS I2C BUS Register Data Standard Setting Values Register ATT STVCO SAPVCO SAPLPF STLPF SPECTRAL WIDEBAND TEST-DA TEST1 PRE-VOL VOL-L VOL-R VOL-SURR TREBLE BASS SURR NRSW FOMO EXT1 EXT2 EXTFOMO M1 M2 INSW1 INSW2 SAPC Number Classifi- Standard of bits cation setting 4 6 4 4 6 6 6 1 1 4 6 6 6 4 4 1 1 1 1 1 1 1 1 1 1 1 A A A A A A A T T U U U U U U U U U U U U U U S S S 9 1F 8 8 1F 1F 1F 0 0 F 3F 3F 3F 8 8 0 — — 0 0 0 1 1 — — — Contents Setting value when electrical characteristics are measured Center point Adjustment point Normal mode F=0dB 3F=0dB 3F=0dB 3F=0dB 7 or 8=0dB 7 or 8=0dB Surround OFF According to the modecontrol table TV decoder output selection External forced MONO OFF Mute OFF Standard setting value Standard setting value Standard setting value Fixed by the set specifications Standard setting value Classification A: U: S: T: Adjustment User control Proper to set Test – 17 – CXA1784AS List of Adjustment Contents Adjustment item 1 MAIN VCA 2 ST VCO Adjustment data ATT STVCO Input pin ∗Input signal data Measurement Adjustment contents Test mode setting COMPIN 100Hz (Pin 17) None TVOUT-L output Adjust as close to 490 mVrms as possible possible Adjust to the center of the SAPVCO1 = 0, SAPVCO2 = 1 condition Adjust to the center of the STLPF = 1 condition Adjust to the center of the SAPLPF = 1 condition Minimize the output level Minimize the output level TEST1=1 TEST1=1 TEST-DA=1 TVOUT-R output Adjust as close to 62.936 kHz as frequency STA7 (SAPVCO1) STA8 (SAPVCO2) STA3 STA4 TVOUT-R output level TVOUT-R output level 245mVrms level None 5fH (78.67k) 147mVrms 3 SAP VCO SAPVCO COMPIN (Pin 17) 4 5 ST & dbx FILTER SAP FILTER Low frequency ST separation High frequency ST separation STLPF SAPLPF WIDEBAND SPECTRAL COMPIN 9.4kHz (Pin 17) (Pin 17) (Pin 17) (Pin 17) COMPIN 88kHz COMPIN ST-L 30% 300Hz 3kHz COMPIN ST-L 30% 600mVrms (STLPF) 110mVrms (SAPLPF) 6 ∗ This is the case when standard input level is 245mVrms. When this level is 100mVrms or 490mVrms, input signal during adjustment is varied according to the ratio of these level. – 18 – CXA1784AS Adjustment Method (Input signal level is the case when standard input signal level is 245mVrms) 1 ATT adjustment 1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2. Input a 100 Hz, 245 mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then, adjust the “ATT” data for ATT adjustment so that the TVOUT-L output goes to the standard value. 3. Adjustment range: ±30% Adjustment bits: 4 bits 2 Stereo VCO adjustment 1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 1”. 2. Monitor the TVOUT-R output (4fH free running) frequency in a no input state, and adjust “STVCO” adjustment data so that this frequency is as close to 4fH (62.936 kHz) as possible. 3. Adjustment range: ±20% Adjustment bits: 6 bits SAPVCO adjustment 1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2. Input a 5fH (SAP carrier , 78.67 kHz) , 147 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA7, STA8) condition, adjust “SAPVCO” adjustment data. 3. Adjustment range: ±20% Adjustment bits: 4 bits Align SAPVCO with the center of the STA7 = 0 and STA8 = 1 (adjustment OK) condition range. Adjustment point Control data "SAPVCO" 3 0 1 0 1 0 F Measurement data STA7 "SAPVCO1" STA8 "SAPVCO2" 4 Stereo block dbx filter adjustment 1. TEST BIT is set to “TEST1 = 1” and “TEST-DA = 0”. 2. Input a 9.4 kHz, 600 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA3) condition, adjust the “STLPF” adjustment data. 3. Adjustment range: ±20% Adjustment bits: 6 bits Align STLPF with the center of the STA3 = 1 (adjustment OK) condition range. Adjustment point Control data "STLPF" 0 1 0 3F Measurement data STA3 "STLPF" – 19 – CXA1784AS 5 SAP block filter adjustment 1. TEST BIT is set to “TEST1 = 1” and “TEST-DA = 0”. 2. Input a 88 kHz, 110 mVrms sine wave signal to COMPIN. While monitoring the STATUS FLAG (STA4) condition, vary and adjust the “SAPLPF” adjustment data. 3. Adjustment range: ±20% Adjustment bits: 4 bits Align SAPLPF with the center of the STA4 = 1 (adjustment OK) condition range. Adjustment point Control data "SAPLPF" 0 1 0 F Measurement data STA4 "SAPLPF" 6 Separation adjustment 1. TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2. Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300 Hz NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce TVOUTR output to the minimum. 3. Next, set the frequency only of the input signal to 3 kHz and adjust the “SPECTRAL” adjustment data to reduce TVOUT-R output to the minimum. 4. Then, the adjustments in 2 and 3 above are performed to optimize the separation. 5. “WIDEBAND” “SPECTRAL” Adjustment range: ±30% Adjustment range: ±15% Adjustment bits: 6 bits Adjustment bits: 6 bits – 20 – CXA1784AS Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 1. PEAK DEV kHz 50 AM-DSB-SC 50 25 25 L-R dbx-TV NR PILOT L+R 50-15kHz 15 SAP dbx-TV NR FM 10kHz 50-10kHz 2fH 3fH 4fH 5fH TELEMETRY FM 3kHz 3 6fH 6.5fH f 5 fH fH=15.734kHz Fig. 1. Base band spectrum PLL (VCO 8fH) STEREO LPF MVCA 2fHL0° fHL90° fHL0° PILOT DET I 2C BUS DECODER MODE CONTROL (MAIN OUT) (MAIN IN) (COMPIN) MAIN LPF DE.EM PILOT CANCEL SUB LPF L-R (DSB) DET SAP(FM) 17 14 L+R 4.7µ 13 WIDEBAND (SUBOUT) (ST IN) SUBVCA MATRIX 19 4.7µ L-R 20 NR SW (Lch) A dbx-TV BLOCK B TO (Rch) SW SAP BPF DET INJ. LOCK SAP LPF (SAP OUT) 24 (SAP IN) NOISE DET I 2C BUS DECODER 4.7µ 25 MODE CONTROL SAP DET I 2C BUS DECODER MODE CONTROL Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block) VARIABLE FIXED DEEMPHASIS DEEMPHASIS (VE OUT) 20 NR SW A (VCA IN) 30 VCA B 29 25 HPF LPF LPF RMS DET RMS DET 4.7µ TO MATRIX Fig 3. dbx-TV block – 21 – CXA1784AS (TVOUT-L)(TVOUT-R) 35 34 (LSOUT-L) SW1 (AUXIN-L) BASS TREBLE VOL-R VOL-L 6 38 SW2 PREVOL SURROUND (LSOUT-R) 37 (AUXIN-R) 5 (SURROUT) (Lch) (Rch) from MATRIX + VOL-S 4 Fig. 4. Sound processor block (1) L + R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 17) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L - R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2) L - R (SUB) The L - R signal follows the same course as L + R before the pilot signal is canceled. L - R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L - R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L - R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3) SAP SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 24 output is soft muted. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25 kHz after FM detection of SAP signal. (5) dbx-TV block Either the SAP signal or L - R signal input respectively from ST IN (Pin 20) or SAP IN (Pin 25) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. – 22 – CXA1784AS The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Matrix, SW1, SW2 The signals (L + R, L - R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and SAP signals according to the BUS data and whether there is ST/SAP discrimination. “SW1” and “SW2” switch the “MATRIX” output signal, external input signal (input to AUXIN-L, R (Pins 38 and 37)) and external forced MONO. Signals selected by “SW1” are output to TVOUT. Signals selected by “SW2” pass through the sound processor and are output to LSOUT. (7) Sound processor block The sound processor block contains “PREVOL”, “BASS/TREBLE” tone control functions, “SURROUND” (quasi-surround function) and “VOLUME”. BASS: ±12 dB (±1.7 dB/STEP at 100 Hz) TREBLE: ±12 dB (±1.7 dB/STEP at 10 kHz) VOLUME: 0 to -80 dB (-1.25 dB/STEP) “PREVOL” controls the input signal level of the sound processor block. When turning on the bass boost, treble boost or surround, attenuate the input signal to the sound processor block using “PREVOL” so that the signal is not dissipated inside the processor. PREVOL: 0 to -13.75 dB (-1.25 dB/STEP) (8) Surround At “SURROUND”, the L and R differential components are phase-shifted and these components are added to the left and right channels. When surround is OFF (SURR = 0) Inputs are output as is. Lout = Lin Rout = Rin { When surround is ON (SURR = 1) 1-jωRC Lout = Lin(Lin-Rin) 1+jωRC 1-jωRC Rout = Rin+ (Lin-Rin) 1+jωRC R = 24 kΩ (IC on-chip) C = 0.022 µF (Externally attached to Pin 39) { { (Lin, Lout) and (Rin, Rout) indicate the left- and right- channel I/O of the surround circuit. – 23 – CXA1784AS (9) Others “MVCA” is a VCA which adjusts the input signal level to the standard level of this IC. Standard input level can be selected by INSW1 or INSW2. “Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 12) and ITIME (Pin 33) with GND become the reference current. Standard input and output levels Input pin INSW1 0 1 1 0 — INSW2 0 1 0 1 — Input level 245mVrms∗1 490mVrms∗1 100mVrms∗1 490mVrms 490mVrms∗2 TVOUT output level LSOUT output level∗3 490mVrms∗2 COMPIN AUXIN 490mVrms 490mVrms ∗1 MONO, 25kHz Deviation, Pre-Em. off ∗2 MONO, 25kHz Deviation, Pre-Em. on ∗3 VOLUME MAX, PREVOL MAX – 24 – CXA1784AS Register Specifications Slave address SAD pin GND VCC SLAVE RECEIVER 80H 8AH SLAVE TRANSMITTER 81H 8BH Register table SUB ADDRESS MSB LSB BIT7 BIT6 BIT5 ∗∗∗∗0000 INSW2 INSW1 TEST-DA ∗∗∗∗0001 ∗ ∗∗∗∗0010 (SAPVCO (4) SAP VCO adj) ∗∗∗∗0011 ∗ ∗∗∗∗0100 ∗ ∗∗∗∗0101 ∗ ∗∗∗∗0110 EXTFOMO EXT1 EXT2 ∗∗∗∗0111 ∗ ∗∗∗∗1000 ∗ ∗∗∗∗1001 ∗ ∗∗∗∗1010 ∗ ∗∗∗∗1011 ∗ ∗∗∗∗1100 ∗ DATA BIT4 BIT3 BIT2 BIT1 BIT0 TEST1 ATT (4) INPUT LEVEL adj STVCO (6) STEREO VCO adj (SAPLPF (4) SAP FILTER adj) STLPF (6) ST FILTER adj SPECTRAL (6) WIDEBAND (6) M2 NRSW FOMO SAPC M1 SURR PR-VOL (4) Pre vol cont. VOL-L (6) Lch vol cont. VOL-R (6) Rch vol cont. VOL-SURR (6) Surr vol cont. TREBLE (4) BASS (4) ∗: Don't Care Status Registers When TEST1 = 0 STA1 BIT7 POWER ON RESET STA2 BIT6 STEREO STA3 BIT5 SAP STA4 BIT4 NOISE STA5 BIT3 — STA6 BIT2 — STA7 BIT1 SAP VCO1 STA8 BIT0 SAP VCO2 When TEST1 = 1 STA1 BIT7 POWER ON RESET STA2 BIT6 STEREO STA3 BIT5 STLPF STA4 BIT4 SAPLPF STA5 BIT3 — STA6 BIT2 — STA7 BIT1 — STA8 BIT0 — – 25 – CXA1784AS Description of Registers Control registers Register Number of bits ATT 4 STVCO 6 SAPVCO 4 SAPLPF 4 STLPF 6 SPECTRAL 6 WIDEBAND 6 TEST-DA TEST1 PRE-VOL VOL-L VOL-R VOL-SURR TREBLE BASS SURR NRSW FOMO EXT1 EXT2 EXTFOMO M1 M2 INSW1 INSW2 SAPC 1 1 4 6 6 6 4 4 1 1 1 1 1 1 1 1 1 1 1 Classification∗ A A A A A A A T T U U U U U U U U U U U U U U S S S Contents Input level adjustment STEREO VCO free running frequency adjustment SAP VCO free running frequency adjustment SAP filter adjustment STEREO and dbx filter adjustment Adjustment of stereo separation (3 kHz) Adjustment of stereo separation (300 Hz) Turn to DAC test mode and STVCO adjustment mode by means of TEST-DA = 1. Turn to test mode by means of TEST = 1. (Adjustment of STLPF and SAPLPF) Input signal level control of sound processor block LSOUT-L output signal level control LSOUT-R output signal level control SURROUT output signal level control LSOUT output treble control LSOUT output bass control Selection of quasi-surround function ON/OFF (0: OFF, 1: ON) Selection of the output signal (Stereo mode, SAP mode) Turn to forced MONO by means of FOMO = 1. (Left channel only is MONO during SAP output.) Selection of TV mode or external input mode for TVOUT output Selection of TV mode or external input mode for LSOUT output Forced MONO for external input (1: forced MONO ON) Selection of TVOUT mute ON/OFF (0: mute ON, 1: mute OFF) Selection of LSOUT mute ON/OFF (0: mute ON, 1: mute OFF) Select of standard input level. Select of standard input level. Selection of SAP mode or L + R mode according to the presence of SAP broadcasting ∗ Classification U: User control A: Adjustment S: Proper to set T: Test – 26 – CXA1784AS Status registers Register PONRES STEREO SAP NOISE STLPF SAPLPF SAPVCO1 SAPVCO2 Number of bits 1 1 1 1 1 1 1 1 Contents POWER ON RESET detection; 1: RESET Stereo discrimination of the COMPIN input signal; 1: Stereo SAP discrimination of the COMPIN input signal; 1: SAP Noise level discrimination of the SAP signal; 1: Noise Status of STEREO filter adjustment; 1: OK range Status of SAP filter adjustment; 1: OK range Status 1 of SAP VCO free running frequency adjustment;0: OK range Status 2 of SAP VCO free running frequency adjustment;1: OK range Description of Control Registers ATT (4): Adjust the signal level input to COMPIN (Pin 17) to the standard input level. Variable range of the input signal: standard input level -5.0 dB to +3.0 dB 0 = Level min. F = Level max. STVCO (6): Adjust STEREO VCO free running frequency (fo). Variable range: fo ±20% 0 = Free running frequency min. 3F= Free running frequency max. Adjust SAPVCO free running frequency (fo). Variable range: fo ±20% 0 = Free running frequency min. F = Free running frequency max. Adjust the filter fo of the SAP block. Variable range: fo ±20% 0 = Frequency min. F = Frequency max. Adjust the filter fo of the ST and dbx blocks. Variable range: fo ±20% 0 = Frequency min. 3F= Frequency max. SAPVCO (4): SAPLPF (4): STLPF (6): SPECTRAL (6): Perform high frequency (fs = 3 kHz) separation adjustment. 0 = Level max. 3F= Level min. WIDEBAND (6): Perform low frequency (fs = 300 Hz) separation adjustment. 0 = Level min. 3F= Level max. – 27 – CXA1784AS TEST1 (1): Set filter adjustment mode. 0 = Normal mode 1 = STLPF (STA3) and SAPLPF (STA4) adjustment mode In addition, the following outputs are present at Pins 35 and 34. TVOUT-L (Pin 35): SAP BPF OUT TVOUT-R (Pin 34): NR BPF OUT Set DAC output test mode and STVCO adjustment mode. 0 = Normal mode 1 = DAC output test mode and STVCO adjustment mode In addition, the following outputs are present at Pins 35 and 34. TVOUT-L (Pin 35): DA control DC level TVOUT-R (Pin 34): STEREO VCO oscillation frequency (4fH) Input signal level control of sound processor block When turning on the bass boost, treble boost or surround, attenuate the input signal to the sound processor block using “PREVOL” so that the signal is not dissipated inside the processor. 4 = Volume Min. (-13.75 dB) F = Volume Max. (0 dB) -1.25 dB/STEP LSOUT-L output signal level control 0 = Volume Min. (-80 dB) 3F= Volume Max. (0 dB) -1.25 dB/STEP LSOUT-R output signal level control 0 = Volume Min. (-80 dB) 3F= Volume Max. (0 dB) -1.25 dB/STEP TEST-DA (1): PRE-VOL (4): VOL-L (6): VOL-R (6): VOL-SURR (6): SURROUT output signal level control 0 = Volume Min. (-80 dB) 3F= Volume Max. (0 dB) -1.25 dB/STEP TREBLE (4): LSOUT output treble control 0 = Treble Min. 7 & 8 = Treble Center (0 dB) F = Treble Max. LSOUT output bass control 0 = Bass Min. 7 & 8 = Bass Center (0 dB) F = Bass Max. BASS (4): – 28 – CXA1784AS SURR (1): Surround function selection 0 = Surround OFF 1 = Surround ON Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L + R output is selected 1 = SAP output is selected Select standard input level of COMPIN(Pin 17) Standard input level INSW1 = 0 , INSW2 = 0 245mVrms =1, =1 NRSW (1): FOMO (1): SAPC (1): INSW1 (1) & INSW2 (1): } INSW1 = 1 , INSW2 = 0 INSW1 = 0 , INSW2 = 1 EXT1 (1): 490mVrms 100mVrms Select TV mode or external input mode for TVOUT output. 0 = TV mode 1 = External input mode Select TV mode or external input mode for LSOUT output. 0 = TV mode 1 = External input mode EXT2 (1): EXT-FOMO (1): Turn external input to forced MONO. 0 = Normal mode 1 = External input is forced MONO. Input the same signal to both AUXIN-L and AUXIN-R. M1 (1): Mute the TVOUT-L and TVOUT-R output. 0 = Mute ON 1 = Mute OFF Mute the LSOUT-L and LSOUT-R output. 0 = Mute ON 1 = Mute OFF M2 (1): – 29 – CXA1784AS Description of Mode Control Priority ranking: M1/M2 > EXT1/EXT2 > TEST-DA > TEST1 > (NRSW & FOMO & SAPC) Mode control SAPC=0 “Select dbx input and TV decoder output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) • During ST input: • During other input: NRSW left channel:L, right channel: R left channel:L + R, right channel: L + R SAPC=1 “Select dbx input and TV decoder output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) As on the left NRSW = 1 (SAP output) • When there is “SAP” during SAP discrimination - left channel: SAP, right channel: SAP • When there is “No SAP”, output is the same as when NRSW = 0. NRSW = 1 (SAP output) • Regardless of the presence of SAP discrimination, dbx input: “SAP” left channel: SAP, right channel: SAP However, when there is no SAP, SAPOUT output is soft muted (-7 dB) “Forced MONO” FOMO FOMO = 1 • During SAP output: left channel: L + R, right channel: SAP • During ST or MONO output: left channel: L + R, right channel: L + R Change the selection conditions for “MONO or ST output” and “SAP output”. SAPC = 0: Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination. “MUTE” M1 = 0: TVOUT output is muted. M2 = 0: LSOUT output is muted. “TV mode/external input mode selection” EXT1 = 0: Set TVOUT output to TV mode. EXT1 = 1: Set TVOUT output to external input mode. EXT2 = 0: Set LSOUT output to TV mode. EXT2 = 1: Set LSOUT output to external input mode. “TEST1” TEST1 = 1 Return adjustment data with STATUS REGISTER as an adjustment mode. In addition, outputs are as follows. left channel: SAP BPF OUT right channel: NR BPF OUT “TEST-DA” TEST-DA = 1 Used to adjust the D/A TEST and STVCO. left channel: D/A output right channel: STVCO oscillation frequency (4fH) – 30 – SAPC M1/M2 EXT1/EXT2 TEST1 TEST-DA CXA1784AS Decoder Output and Mode Control Table 1 (SAPC = 1) Input signal mode Mode detection ST SAP NOISE 0 0 0 0 0 0 0 0 0 ∗ 0 1 ∗ 0 1 ∗ 0 1 ∗ 1 0 ∗ 1 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 ∗ ∗ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 ∗ ∗ 0 0 1 1 ∗ ∗ 0 0 1 1 Mode control NRSW FOMO SAPC ∗ 0 1 1 0 1 1 1 1 ∗ 0 1 1 0 1 1 1 1 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 dbx input MUTE SAP SAP MUTE (SAP) (SAP) L-R MUTE L-R MUTE SAP SAP (SAP) (SAP) MUTE MUTE SAP SAP (SAP) (SAP) L-R MUTE SAP SAP (SAP) (SAP) Output Lch Rch L+R L+R SAP SAP L+R SAP L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R L R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) L+R L+R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) L R L+R L+R SAP SAP L+R SAP (SAP) (SAP) L+R (SAP) 1) MONO 1) STEREO MONO & SAP STEREO & SAP Note (SAP) : The SAPOUT output signal is soft muted (approximately -7 dB). The signal is soft muted when NOISE = 1. ∗ : Don’t care. 1): SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. – 31 – CXA1784AS Decoder Output and Mode Control Table 2 (SAPC = 0) Input signal mode Mode detection ST SAP NOISE ∗ 0 0 0 1 1 0 1 1 0 1 1 0 1 1 ∗ 1 0 ∗ 1 0 ∗ 1 0 ∗ 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Mode control NRSW FOMO SAPC ∗ ∗ 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 0 dbx input MUTE MUTE MUTE (SAP) (SAP) L-R MUTE L-R MUTE L-R MUTE (SAP) (SAP) MUTE MUTE SAP SAP MUTE MUTE (SAP) (SAP) L-R MUTE SAP SAP L-R MUTE (SAP) (SAP) Output Lch Rch L+R L+R L+R L+R L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R L R L+R L+R L R L+R L+R (SAP) (SAP) L+R (SAP) L+R L+R L+R L+R SAP SAP L+R SAP L+R L+R L+R L+R (SAP) (SAP) L+R (SAP) L R L+R L+R SAP SAP L+R SAP L R L+R L+R (SAP) (SAP) L+R (SAP) 1) MONO 1) STEREO MONO & SAP STEREO & SAP Note (SAP) : The SAPOUT output signal is soft muted (approximately -7 dB). The signal is soft muted when NOISE = 1. ∗ : Don’t care. 1): SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. – 32 – CXA1784AS Mode Control Table 3 EXT1 EXT2 0 1 1 0 0 1 1 ∗ 0 0 0 1 1 1 1 ∗ EXTFOMO ∗ 0 1 0 1 0 1 ∗ M1 1 1 1 1 1 1 1 M2 1 1 1 1 1 1 1 TV OUT-L TV mode L channel EXT mode L channel EXT mode L channel TV mode L channel TV mode L channel EXT mode L channel EXT mode L channel TV OUT-R TV mode R channel EXT mode R channel EXT mode L channel TV mode R channel TV mode R channel EXT mode R channel EXT mode L channel LS OUT-L TV mode L channel TV mode L channel TV mode L channel EXT mode L channel EXT mode L channel EXT mode L channel EXT mode L channel Selected according to 0 1 MUTE MUTE the EXT1, EXT2, LS OUT-R TV mode R channel TV mode R channel TV mode R channel EXT mode R channel EXT mode L channel EXT mode R channel EXT mode L channel Selected according to the EXT1, EXT2, EXTFOMO conditions EXTFOMO conditions Selected according to Selected according to ∗ ∗ ∗ 1 0 the EXT1, EXT2, the EXT1, EXT2, MUTE MUTE EXTFOMO conditions EXTFOMO conditions I2C BUS Signal There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal. • Accordingly there are 3 values outputs, H, L and HIZ. H L HIZ L • I2C transfer begins with Start Condition and ends with Stop Condition. Start Condition S SDA Stop Condition P SCL – 33 – CXA1784AS • I2C data Write (Write from I2C controller to the IC) L during Write SDA MSB HIZ MSB LSB HIZ SCL 1 S 2 3 4 5 6 7 8 9 1 8 9 Address MSB LSB HIZ HIZ ACK Sub Address ACK 1 8 9 1 8 9 DATA(n) ACK DATA(n+1) ACK DATA(n+2) HIZ HIZ 8 DATA 9 ACK 1 DATA 8 9 P ACK ∗ Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically. • I2C data Read (Read from the IC to I2C controller) H during Read SDA HIZ SCL 1 S Address ACK DATA ACK 6 7 8 9 1 7 8 9 P • Read timing IC output SDA MSB LSB SCL 9 1 2 3 4 5 6 7 8 9 Read timing ACK DATA ACK ∗ Data Read is performed during SCL rise. – 34 – CXA1784AS Input level vs. Distortion characteristics 1 (MONO) Input signal: MONO (Pre-emphasis on), 1 kHz 0 dB = 100% modulation level VCC = 9 V, 30 kHz using LPF Measurement point: TVOUT-L/R Input level vs. Distortion characteristics 2 (Stereo) Input signal: Stereo L = -R (dbx-TVNR ON), 1 kHz 0 dB = 100% modulation level VCC = 9 V, 30 kHz using LPF, ST mode Measurement point: TVOUT-L/R 1.0 10 Distortion (%) Distortion (%) 0.1 1.0 Standard level (100%) –10 0 Input level (dB) 10 Standard level (100%) –10 0 Input level (dB) 10 Input level vs. Distortion characteristics 3 (SAP) Input signal: SAP (dbx-TVNR ON) 1 kHz, 0 dB = 100% modulation level VCC = 9 V, 30 kHz using LPF, SAP mode Measurement point: TVOUT-L/R 10 Distortion (%) 1.0 Standard level (100%) –10 0 Input level (dB) 10 – 35 – CXA1784AS Stereo LPF frequency characteristics 10 5 Gain (dB) 0 –5 –10 0 20 40 60 80 100 Frequency (kHz) Main LPF and Sub LPF frequency characteristics 30 Gain (FC main and FC sub) (dB) 20 10 0 –10 –20 –30 –40 –50 1 2 5 7 10 20 50 70 100 Frequency (kHz) SAP frequency characteristics and group delay 100 20 5fH 10 Gain 90 80 60 0 50 40 –10 Group delay 3.8fH 20 40 60 80 30 20 –20 6.2fH 100 10 0 120 Frequency (kHz) – 36 – Group delay (µs) 70 Gain (dB) CXA1784AS BASS - TREBLE characteristics BASS. MAX +12 TREBLE. MAX +8 Boost amount (dB) +4 0 -4 -8 -12 BASS. MIN 2 0 100 1k Frequency (Hz) TREBLE. MIN 10 k 20 k Input: AUXIN (Pins 37 and 38) 245 mVrms Output: LSOUT (Pins 4, 5 and 6) Volume characteristics 0 -20 LSOUT output level (dB) -40 -60 -80 Input: AUXIN (Pins 37 and 38) 1 kHz,490mVrms Output: LSOUT (Pins 4, 5 and 6) -100 0 2 F Control data VOL-L, VOL-R, VOL-SURR F 1F 3 F – 37 – CXA1784AS Package Outline Unit: mm 42PIN SDIP (PLASTIC) 600mil + 0.1 – 0.05 22 42 15.24 ± 0.25 + 0.3 13.0 – 0.1 0.25 0° to 15° 21 0.5 ± 0.1 + 0.4 37.8 – 0.1 1 1.778 ± 0.25 0.9 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SDIP-42P-02 SDIP042-P-0600-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 4.4g – 38 – 3.0 MIN + 0.4 4.6 – 0.1 0.5 MIN