CXA1846AN

CXA1846AM/AN Electronic volume control For the availability of this product, please contact the sales office. Description The CXA1846AM/AN is an electrical volume control IC for use in car radios/stereos and radiocassette recorders featuring serial data control. It has improved over the CXA1846M/N by reducing the ‘pop’ noise during volume level-switchings. Features • Volume adjustment (0dB to –87dB, – ∞dB) • Balance • Serial data control (DATA, CLK, CE) • Single 8V power supply • Zero-cross detection circuit Structure Bipolar silicon monolithic IC CXA1846AM 20 pin SOP (Plastic) CXA1846AN 20 pin SSOP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC 13 V • Operating temperature Topr –40 to +85 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation 350 (75°C) mW PD SOP SSOP 220 (75°C) mW Recommended Supply Voltage Range Supply voltage VCC 6 to 12 V Block Diagram and Pin Configuration INAO1 VRIN1 VCT1 INN1 OUT1 INP1 GND VCT NC VCC 11 100k 20 19 18 17 16 15 14 13 12 100k VOLUME 8dB STEP VOLUME 1dB STEP VCTBUFF LATCH LATCH CONTROL ZCDET SHIFT REGISTER 50K VOLUME 8dB STEP VOLUME 1dB STEP 1 2 3 4 5 6 7 8 VCTBUFF 9 VCTBUFF 10 50K INAO2 VRIN2 DATA INN2 VCT2 INP2 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— OUT2 CLK INIT CE E97102B8Y CXA1846AM/AN Pin Description Pin No. Symbol I/O resistance voltage Equivalent circuit VCC Description 1 20 INP2 INP1 50kΩ VCT 129 1 20 Input operational amplifier positive phase input GND VCC 2 19 INN2 INN1 — VCT 129 2 19 Input operational amplifier reversed phase input GND VCC 3 18 VCT2 VCT1 — VCT 3 18 VCT buffer output GND VCC 4 17 INAO2 INAO1 — VCT 4 17 Input operational amplifier GND VCC 5 16 VRIN2 VRIN1 8.2kΩ VCT 5 16 Volume input GND —2— CXA1846AM/AN Pin No. Symbol I/O resistance voltage Equivalent circuit VCC Description 6 15 OUT2 OUT1 — VCT 6 Volume output GND VCC 7 CE ≅∞ — 129 7 Latch enable GND VCC 8 DATA ≅∞ — 129 8 Serial data input GND VCC 9 CLK ≅∞ — 129 9 Serial clock GND VCC 10 INIT — — 129 10 System reset GND 11 12 13 VCC VCT GND — — VCT — — + power supply Mid-point potential GND —3— CXA1846AM/AN Electrical Characteristics Item Circuit current Total harmonic distortion Output noise voltage Maximum output voltage Separation Maximum attenuation High Input voltage Low Input voltage range Maximum output current Symbol ICC THD Vn Vom CS ATTm Vsh Vsl Vin Imax (Unless otherwise specified VCC = 8V, Ta = 25°C) Measurement Condition No signal 1kHz, 5dBm Input shorted 1kHz 1kHz Data, INIT CLK, CE Input buffer amplifier output current Min. 5 — — 8 85 85 3 0 1 — Typ. Max. Unit 8 12 mA 0.003 0.01 % 5 7 µVrms — — dBm 90 — dB 90 — dB — 6 V — 1.5 V — VCC – 1 V — 1 mA RESET The IC is reset by reducing the voltage at the INIT pin to 1V or less when CLK is high. Reset can not be performed when CLK is low. The table below shows the status when the IC has been reset. MODE VRC1 VRF1 VRC2 VRF2 Setting –∞ –7dB –∞ –7dB —4— CXA1846AM/AN Data Allocation Fast bit D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 NOP MSB VRC1 VRF1 NOP VRC2 VRF2 LSB VRC1/VRC2 Setting 0 –8 –16 –24 –32 –40 –48 –56 –64 –72 –80 –∞ –∞ VRF1/VRF2 Setting 0 –1 –2 –3 –4 –5 –6 –7 D6/D14 1 1 1 1 0 0 0 0 D7/D15 1 1 0 0 1 1 0 0 D8/D16 1 0 1 0 1 0 1 0 —5— D2/D10 1 1 1 1 1 1 1 1 0 0 0 0 0 D3/D11 1 1 1 1 0 0 0 0 1 1 1 1 0 D4/D12 1 1 0 0 1 1 0 0 1 1 0 0 0 D5/D13 1 0 1 0 1 0 1 0 1 0 1 0 0 CXA1846AM/AN Data Timing CE DATA D1 D2 D3 D15 D16 CLK Min. 0.5µs Max. 1MHz Min. 0.5µs CE Min. 4µs —6— CXA1846AM/AN Test Circuit TP1 V4 50mV TP2 TP3 R8 C9 10k R6 10k 1µ V6 AC –60dBm GND GND 100p S4 B R4 C2 V2 10µ AC GND 20 19 18 1k R3 1k S3 C4 10µ S1 A C6 10µ C7 VCC S2 17 16 15 14 13 12 11 VCT1 INN1 INP1 VRIN1 OUT1 GND VCT NC INAO1 VCC V7 8V GND INAO2 VRIN2 OUT2 INP2 INN2 DATA VCT2 CLK C10 1n GND AC V1 10µ C1 1 2 S6 3 4 5 6 7 8 9 10 5V 0V CLK DATA CE 5V 0V 5V 0V S8 S5 1k 1k 1k INIT GND GND –60dBm V5 C8 A 1k 1k R2 R1 S7 10µ B 100p C5 R5 C3 10k CE 10k 1µ AC R7 50mV V3 TP4 TP5 —7— CXA1846AM/AN Application Circuit VCC OUT1 C7 10µ R4 GND C10 12 11 10k IN1 C2 10µ 20 19 R4 10k 18 17 C5 10µ 16 15 14 13 C8 10µ INP1 VRIN1 OUT1 NC INAO1 VCT1 INN1 INAO2 VRIN2 OUT2 INN2 DATA VCT2 INP2 GND CLK VCT 1 10µ IN2 C1 2 10k R1 3 4 10µ R4 5 6 7 8 9 10 INIT CE VCC 10k R3 10µ C11 0.01µ GND OUT2 C6 SERIAL CTL Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. —8— 47µ GND CXA1846AM/AN Total harmonic distortion 1.0 RL = 10kΩ VCC = 8V Volumue = 0dB Total harmonic distortion [%] 0.1 20kHz 100Hz 0.01 1kHz 0.001 –30 –20 –10 Output level [dBm] 0 2 4 6 8 10 —9— CXA1846AM/AN Package Outline Unit : mm CXA1846AM 20PIN SOP (PLASTIC) + 0.4 12.45 – 0.1 20 11 + 0.4 1.85 – 0.15 0.15 + 0.3 5.3 – 0.1 7.9 ± 0.4 + 0.2 0.1 – 0.05 1.27 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-20P-L01 SOP020-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.3g CXA1846AN ∗6.5 ± 0.1 20PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 0.1 20 11 A ∗4.4 ± 0.1 1 10 0.65 b 0.13 M + 0.05 0.15 – 0.02 (0.22) 0.1 ± 0.1 b=0.22 ± 0.03 0.5 ± 0.2 DETAIL B : SOLDER (0.15) DETAIL B : PALLADIUM NOTE: Dimension “∗” does not include mold protrusion. 0° to 10° PACKAGE STRUCTURE DETAIL A PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-20P-L01 SSOP020-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.1g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). —10— + 0.03 0.15 – 0.01 + 0.1 b=0.22 – 0.05 6.4 ± 0.2 0.5 ± 0.2 1 0.45 ± 0.1 10 6.9 + 0.1 0.2 – 0.05