CXA1898Q

CXA1898Q Recording/Playback Equalizer Amplifier Description The CXA1898Q is an IC developed for analog signal processing in tape recorders. Processing for both the recording and playback systems is achieved on one chip. Features • Recording equalizer Gp and Fp can be adjusted externally. • Recording mute function • AGC (Automatic Gain Control) • Comparator for AMS (Automatic Music Sensor) • Recording/playback equalizer amplifier with 1.7 times speed switching • 11-bit serial data interface Absolute Maximum Ratings • Supply voltage • Operating temperature • Storage temperature • Allowable power dissipation Operating Conditions Supply voltage 48 pin QFP (Plastic) Structure Bipolar silicon monolithic IC Applications All analog signal processing in the cassette decks of tape recorders and compact music centers (Applicable to Sankyo Seiki mfg. Co., Ltd. YK47R-KF202 R/P head or equivalent) VCC 12 V Topr –20 to +75 °C Tstg –65 to +150 °C PD 735 mW VCC 6.5 to 10.0 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94329B78 CXA1898Q Block Diagram and Pin Configuration (Top View) AGC IN2 REC IN2 AGC OUT2 REC OUT2 AGC TC D GND XRESET RFC VCC 36 35 VG GND 34 33 32 31 30 29 28 27 26 25 IREF 37 10k GND DATA AGC GAIN 19.5dB GND 24 CLK IREF PB OUT2 38 RECEQ 23 LATCH PB FB22 39 GND 210k PB FB12 40 GND PB INB2 41 GND GND PB INA2 42 70k 210k 40k D1 22 M2 D2 DECK A/B D10 SPEED D9 B EQ A EQ GND 21 M1 PBEQ CTL D3 GND 20 PL2 SHIFT REGISTERS LATCHES D4 GND 19 PL1 AGC GND GND 70k 70k AGC OFF D8 PB INA1 43 GND GND PB INB1 44 GND PB FB11 45 210k GND PB FB21 46 210k 40k 70k D5 GND 18 BPB RECEQ CTL D6 GND 17 BPA SPEED B EQ D7 GND 16 PB MUTE MUTE AGC GAIN 19.5dB D9 GND 15 SPEED RECEQ PB OUT1 47 D8 D10 D9 D11 GND 14 R MUTE2 AMS GAIN 48 AMS GND 1 2 3 4 5 6 10k D11 GND 13 R MUTE1 7 8 9 10 11 12 GND AGC OUT1 REC OUT1 AGC IN1 REC IN1 AMS FIL GP CAL FP CAL AMS GND –2– RMUTE1 I AMS OUT A EQ B EQ CXA1898Q Pin Description Pin No. Symbol DC voltage I/O I/O resistance VCC Equivalent circuit Description VCC 6 31 AGC IN1 AGC IN2 147 3k 47k ×4 4.0V I 50kΩ 6 31 AGC signal input. Input resistance changes between 47kΩ and 3kΩ GND VGS VCC VCC 147 23k 7 30 REC IN1 REC IN2 4.0V I 50kΩ 7 30 50k 1.8k VGS VGS GND GND Recording equalizer input. VCC ×2 VCC 8 29 AGC OUT1 AGC OUT2 147 4.0V O 147Ω 8 29 ×4 500 500 18.8k 47.8k VGS AGC output pin. AGC is applied at –11dBm or more. 5.3k GND GND GND VGS VCC VCC ×3 500 40k ×2 500 5p 9 28 REC OUT1 REC OUT2 4.0V O 147Ω 9 28 147 × 10 Recording equalizer output. GND GND –3– CXA1898Q Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit VCC VCC Description 147 10 A EQ — I — 10 A deck equalizer switch. Low: 120µs EQ High: 70µs EQ GND GND VCC VCC 11 B EQ 2.5V (when open) 147 50k 5k I 53kΩ 11 5k B deck equalizer switch. Low: Normal Tape, 120µs EQ High: CrO2 Tape, 70µs EQ Medium: Metal Tape, 70µs EQ GND GND VCC 50µA 20k ×2 20k ×2 VCC 12 RMUTE1 I — I — 12 147 2.7V GND GND Recording mute ON/OFF switch. Low: Mute OFF High: Mute ON ∗ Fader function is realized by the external time constant circuit. Connects Pin 13 (RMUTE1). Output for recording mute ON/OFF switch control signal. Outputs D11 from Pin 25 (DATA). Output for recording/ playback equalizer speed switch control signal. Outputs D9 from Pin 25 (DATA). Low: Normal Speed High: High Speed (1.7 times) Output pin for playback mute ON/OFF switch control signal. Outputs D7 from Pin 25 (DATA). Connects a resistor to VDD for Pins 13 to 16. 13 14 R MUTE1 R MUTE2 VDD VCC 15 SPEED 5.0V (when reset) (when Pin 25 (DATA) is set to high) ×4 O — 5k 13 14 15 ×4 20k 16 GND GND 5k 16 PB MUTE –4– CXA1898Q Pin No. 17 18 19 20 21 22 Symbol BPA BPB PL1 PL2 M1 M2 DC voltage I/O I/O resistance VDD Equivalent circuit Description Outputs D6 from Pin 25 (DATA). Outputs D5 from Pin 25 (DATA). VCC 5.0V (when reset) (when Pin 25 (DATA) is set to high) ×4 O — 10k 17 18 19 ×4 Outputs D4 from Pin 25 (DATA). Outputs D3 from Pin 25 (DATA). 20k 20 GND 21 22 GND Outputs D2 from Pin 25 (DATA). Outputs D1 from Pin 25 (DATA). Serial data interface latch input. Serial data interface reset input. Low: Reset. At this time serial data outputs (Pins 13 to 22) are all open (high). 23 LATCH 25µA 2k 23 VCC 100µA — 26 XRESET I — 26 ×4 GND 5p 10.5k 24k GND VCC 24 CLK 24 25µA 4k 100µA Serial data interface clock input. — 25 DATA I — 25 ×4 GND 10.5k 24k Serial data interface serial data input. GND VCC ×2 ×2 200 500 ×2 500 5k 100k GND 32 147 VCC 32 AGC TC 0.0V — — ×4 200 Connects a resistor and capacitor for determining AGC attack/recovery time constants. GND –5– CXA1898Q Pin No. Symbol DC voltage I/O I/O resistance VCC Equivalent circuit VCC 30k ×2 500 To each 500 VSG ×4 30k GND GND Description ×2 34 VG 4.0V — 60kΩ 147 34 45k Signal reference voltage. Connects a capacitor for ripple rejection. 35 VCC 8.0V — — 35 VCC Power supply. VCC VCC ×3 ×3 36 RFC 8.0V — — 36 147 × 250 Connects a resistor and capacitor for obtaining stable voltage with power supply ripple rejected. To each RFS GND VCC VCC ×3 5p 500 38 47 PB OUT2 PB OUT1 38 2.8V O 147Ω 47 147 ×6 500 5k × 2 ×2 Playback equalizer output. GND GND –6– CXA1898Q Pin No. Symbol DC voltage I/O I/O resistance VCC Equivalent circuit RFS 2k ×4 2k ×4 Description 39 46 PB FB22 PB FB21 147 2.8V — — 39 46 7k ×3 ×3 Connects a capacitor for determining playback equalizer time constants, such as 120µs and 70µs. GND GND GND VCC VCC 10k VCC 40 45 PB FB12 PB FB11 RFS VCC 1.4V — 105kΩ 10k Playback equalizer negative feedback. 1k 41 42 43 147 70k ×6 ×6 1k ×2 210k 5p 40 147 210k 45 41 42 43 44 PB INB2 PB INA2 PB INA1 PB INB1 44 0.0V I 70kΩ GND GND GND Playback equalizer input. VCC VCC 10µ 48 AMS GAIN 3.5V — — 48 147 100k Connects a resistor for determining AMS signal detection level and a capacitor for determining HPF cut-off frequency. GND GND Note) The resistance of open collector outputs (Pins 2 and 13 to 22) can be also connected to VCC. –7– CXA1898Q Electrical Characteristics (Ta = 25°C, VCC = 8.0V, VDD = 5.0V, refer to Electrical Characteristics Measurement Circuit) Item Operating voltage Current consumption AGC ON output level AGC ON channel balance AGC ON distortion AGC OFF output level AMS No signal detection threshold level 120µs–NS frequency response 120µs–NS frequency response 70µs–NS frequency response 120µs–HS frequency response 70µs–HS frequency response Signal handling Total harmonic distortion S/N ratio Output offset voltage VCC NORM–NS, VCC = 8V, No signal Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = –25dBm Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = –15dBm Pin 32 external R300kΩ/ /C47µF f = 1kHz, Vin = 0dBm Pin 32 external R300kΩ/ /C 47µF f = 1kHz, Vin = –25dBm Pin 48 external R9.1kΩ, C0.015µF Pin 1 external R100kΩ/ /C0.1µF f = 5kHz, 0dB = –21dBm (at PBEQ reference output level) f = 315Hz, Vin = –70dBm Reference for frequency response f = 2.7kHz, Vin = –58.5dBm at 120µs–NS, 315Hz f = 4.5kHz, Vin = –53.8dBm at 120µs–NS, 315Hz f = 5.3kHz, Vin = –52.5dBm at 120µs–NS, 315Hz f = 9.1kHz, Vin = –47.8dBm at 120µs–NS, 315Hz 120µs–NS, RL = 2.7kΩ f = 1kHz, THD + N = 1% 120µs–NS, RL = 2.7kΩ f = 1kHz, Vin = –56.4dBm 120µs–NS, Rg = 2.2kΩ "A" weighting filter 120µs–NS, Rg = 70kΩ Measurement conditions Min. 6.5 13.5 –13.0 –2.0 — –7.5 Typ. 8.0 18.0 –11.0 0.0 0.3 –5.5 Max. 10.0 22.5 –9.0 2.0 1.5 –3.5 Unit V mA dBm dB % dBm AGC –11.5 –8.2 — dB –23.0 –0.1 –0.1 1.8 2.1 –10.0 — 55.0 2.4 –21.0 1.3 1.7 3.0 3.6 –6.0 0.3 62.0 2.7 –19.0 2.9 2.9 dBm Playback equalizer amplifier block dB 4.8 5.1 — 0.7 — 3.2 dBm % dB V –8– CXA1898Q Item Reference input level Reference output level Channel balance NORM–NS frequency response NORM–NS frequency response NORM–NS frequency response CrO2–NS frequency response CrO2–NS frequency response Recording equalizer amplifier block CrO2–NS frequency response METAL–NS frequency response METAL–NS frequency response METAL–NS frequency response NORM–HS frequency response NORM–HS frequency response NORM–HS frequency response CrO2–HS frequency response CrO2–HS frequency response CrO2–HS frequency response METAL–HS frequency response METAL–HS frequency response METAL–HS frequency response Measurement conditions NORM–NS, 315Hz, input level at which reference output can be obtained NORM–NS, 315Hz NORM-NS, 315Hz, Output difference 1ch–2ch for –27.9dBm input f = 3kHz at NORM–NS, 315Hz, reference output –20dB f = 8kHz at NORM–NS, 315Hz, reference output –20dB f = 12kHz at NORM–NS, 315Hz, reference output –20dB f = 3kHz at NORM–NS, 315Hz, reference output –20dB f = 8kHz at NORM–NS, 315Hz, reference output –20dB f = 12kHz at NORM–NS, 315Hz, reference output –20dB f = 3kHz at NORM–NS, 315Hz, reference output –20dB f = 8kHz at NORM–NS, 315Hz, reference output –20dB f = 12kHz at NORM–NS, 315Hz, reference output –20dB f = 5kHz at NORM–NS, 315Hz, reference output -20dB f = 15kHz at NORM–NS, 315Hz, reference output –20dB f = 20kHz at NORM–NS, 315Hz, reference output –20dB f = 5kHz at NORM–NS, 315Hz, reference output –20dB f = 15kHz at NORM–NS, 315Hz, reference output –20dB f = 20kHz at NORM–NS, 315Hz, reference output –20dB f = 5kHz at NORM–NS, 315Hz, reference output –20dB f = 15kHz at NORM–NS, 315Hz, reference output –20dB f = 20kHz at NORM–NS, 315Hz, reference output –20dB Min. –29.4 — –1.5 –1.3 3.7 10.4 1.8 6.7 13.2 3.3 5.9 11.3 –0.7 8.3 13.5 3.6 12.0 17.0 4.9 10.5 14.7 Typ. –27.9 –10.0 0.0 –0.2 5.7 13.4 3.0 8.4 15.8 4.5 7.4 13.7 0.2 10.5 16.7 4.9 14.2 20.0 6.1 12.4 17.4 Max. –26.4 — 1.5 1.1 7.3 16.4 4.2 9.7 18.2 5.7 8.9 15.8 1.7 12.3 19.5 6.0 16.0 22.5 7.3 14.0 19.7 Unit dBm dB –9– CXA1898Q Item Recording equalizer amplifier block Signal handling Total harmonic distortion S/N ratio Output offset voltage Mute characteristics 1 Mute characteristics 2 Measurement conditions NORM–NS, RL2.7kΩ f = 1kHz, THD = 1% NORM–NS, RL2.7kΩ f = 1kHz, 0dB NORM–NS, Rg = 5.1kΩ "A" weighting filter NORM–NS NORM–NS, f = 1kHz 8dB, Pin 12 = 3.5V NORM–NS, f = 1kHz 8dB, Pin 12 = 2.0V A-EQ (Pin 10) A-EQ (Pin 10) B-EQ (Pin 11) B-EQ (Pin 11) B-EQ (Pin 11) RMUTE1-I (Pin 12) RMUTE1-I (Pin 12) Min. 8.0 — 57.0 3.6 — –8.3 0.0 2.5 0.0 2.2 4.2 0.0 3.5 Typ. 8.8 0.2 60.6 4.0 –100 –7.0 — — — — — — — Max. — 0.5 — 4.4 –80 Unit dB % dB V dB –4.3 0.5 VCC 0.5 2.8 VCC 0.5 VCC V Control voltage low level 1 Control voltage high level 1 Control voltage low level 2 Control voltage medium level 1 Control voltage high level 2 Control voltage low level 3 Control voltage high level 3 Note) NORM–NS : NORMAL TAPE–NORMAL SPEED NORM–HS : NORMAL TAPE–HIGH SPEED CrO2–NS : CrO2 TAPE–NORMAL SPEED CrO2–HS : CrO2 TAPE–HIGH SPEED METAL–NS : METAL TAPE–NORMAL SPEED METAL–HS : METAL TAPE–HIGH SPEED 120µs–NS : EQ = 120µs–NORMAL SPEED 120µs–HS : EQ = 120µs–HIGH SPEED 70µs–NS : EQ = 70µs–NORMAL SPEED 70µs–HS : EQ = 70µs–HIGH SPEED – 10 – CXA1898Q Item Low level input voltage High level input voltage Low level output voltage High level output offleak current 11-bit serial data interface block Measurement conditions VIL (LATCH/CLK/DATA/XRESET) (Pins 23, 24, 25, 26) VIH (LATCH/CLK/DATA/XRESET) (Pins 23, 24, 25, 26) VOL, IOL = 2mA (max) (Pins 13, 14, 15, 16, 17, 18, 19, 20, 21, 22) IOZ Leak current which flows to the output pin when Ioz output is open; applied voltage is 10V. Min. 0.0 3.5 0.0 Typ. — — — Max. 1.5 VDD 0.5 Unit V — 500 — — — — — — — — — — — — — — — — — — 1.0 — 1.0 1.0 1.0 1.0 µA kHz Maximum clock frequency (1) fCK Minimum clock pulse width Minimum reset pulse width Minimum data setup time Minimum data hold time Minimum data pulse width Minimum latch setup time Minimum latch hold time Minimum clock hold time (2) tWC (3) tWR (4) tSDK (DATA → CLK) (5) tHCD (CLK → DATA) (6) tWD (7) tSLD (LATCH → DATA) (8) tHCL (CLK → LATCH) (9) tHLC (LATCH → CLK) µs 2.0 1.0 1.0 1.0 Note) • VDD is CPU supply voltage 5.0V. • The maximum value for VDD is Pin 35 (VCC) voltage. • For high level output off leak current, VCC is 10.0V. – 11 – CXA1898Q Timing Chart for 11-bit Serial Data Interface tWC 3.5V CLK 1.5V tSDK 3.5V DATA 1.5V tSLD D1 D2 tHCD tWD tWC LATCH 1.5V 3.5V CLK tHCL tHLC DATA D10 D11 3.5V LATCH 1.5V XRESET 1.5V tWR – 12 – XRESET S17B S21A S13A S13B S15 S21B 100 10k 10k 100 S17A 47k 8.0V AC INPUT 0.1µ 10µ 10µ 10µ 0.1µ 300k 47µ 5.1k S19 S4A 0.47µ 0.47µ 4.7µ 2.2µ 1k S4B ATT –29dB 36 34 25 DATA CLK 24 VG GND D GND 33 29 27 32 30 28 26 31 RFC VCC S6B AGC TC IREF 35 S6A ATT 37 12k S3B S12A 2.7k 2.2µ 39 TL072 40 PB FB12 47µ 377k S7A 0.1µ 2.2k S8 0.47µ 377k S7B 0.1µ 2.2k S9 0.47µ CXA1898Q 43 PB INA1 0.47µ BPB 18 377k S7C 0.1µ 2.2k S10 377k S7D 2.2k S11 0.47µ PB FB11 44 PB INB1 0.1µ 45 47µ 46 PB FB21 100 100k 0.018µ 42 PB INA2 PL1 19 41 PB INB2 PL2 20 100 600 0.018µ S1B PB FB22 M2 22 38 PB OUT2 5.1k 10k –40dB 2.7k S12C ATT S7E S2A S2B 0.1µ 390k 100 10k DATA Electrical Characteristics Measurement Circuit AGC IN2 REC IN2 AGC OUT2 –17dB S3A REC OUT2 XRESET CLK LATCH 23 LATCH ATT –9dB 10k 2k M1 21 2k 10k 2k 10k 2k 10k 2k BPA 17 10k 2k PB MUTE 16 10k 2k SPEED 15 10k 2k 10k S38 S1A ATT S37 –6dB GND AMS FIL AMS OUT AMS GND FP CAL GP CAL AGC IN1 REC IN1 AGC OUT1 REC OUT1 A EQ B EQ 1 2 3 4 5 0.47µ 6 0.47µ 7 4.7µ 8 2.2µ 9 RMUTE1 I 10k 0.1µ 10k 27k 27k 10k 5.1k 2.7k S27 S23 100k 0.1µ 100k 5.1k S20 S24 S25 S26 S505 REC MUTE 1kHz Band Pass Filter (20dB) A EQ 0.1µ B EQ 10k S12D S7F 0.1µ 120µs 70µs S28A S18A 47k 390k 100 100 100 10k 10k 10k 0.5V S14A S16 S14B S18B S22A S22B S39 NORM CrO2 METAL 4.2V 2.0V 2.5V 3.5V 5.0V GND DC OUTPUT OFF ON S28B 0.1µ – 13 – GND S12B 2.7k 2.2µ AMS GAIN 48 0.015µ 9.1k 47 PB OUT1 S36 S35 S34 S33 S501 BUF S32 S31 S502 30dB AMP R MUTE2 14 10k 2k R MUTE1 13 10k 2k 10 11 12 S30 AC OUTPUT S503 "A" Weighting Filter S29 S504 Audio (22.2Hz-22.2kHz) Filter CXA1898Q CXA1898Q Application Circuit GND VCC GND GND GND GND 0.1µ 10µ 1k 100µ 47µ 2.2meg 47µ 0.47µ 2.7k 10k GND VDD GND 2.2µ 100k 2.2µ 4.7µ AGC IN2 REC IN2 AGC OUT2 REC OUT2 AGC TC D GND XRESET RFC VCC 36 12k GND 35 VG GND 34 33 32 31 30 29 28 27 26 37 GND 10k IREF GND DATA 25 24 CLK GND 47k GND 10k 2.2µ 38 RECEQ PB OUT2 AGC GAIN 19.5dB IREF 23 LATCH VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC VDD or VCC PB FB22 820p GND 150p 180p GND 12mH GND PB INB2 41 10k 0.018µ 47µ 100 PB FB12 40 39 GND 210k 210k 40k 47k D1 22 M2 D2 DECK A/B D10 SPEED D9 B EQ A EQ GND 21 M1 47k PBEQ CTL GND GND 70k D3 GND 20 PL2 47k REC SHIFT REGISTERS PB LATCHES R/P-HEAD DECK-B PB INA2 GND 42 DECK-A PB-HEAD D4 GND 19 PL1 47k BIas OSC AGC GND PB INA1 43 GND GND PB INB1 GND 44 GND 70k 70k AGC OFF D8 REC PB D5 GND 18 BPB 47k 70k RECEQ CTL GND GND 180p GND 150p 820p 12mH 10k 0.018µ PB FB21 47µ 100 PB FB11 D6 GND 17 BPA 47k 47k 45 210k GND 46 210k 40k SPEED B EQ D7 GND 16 PB MUTE MUTE AGC GAIN 19.5dB D9 GND 15 SPEED 47k RECEQ 10k GND 2.2µ PB OUT1 47 D8 D10 D9 D11 GND 14 R MUTE2 47k 10k GND 0.1µ 1k AMS GAIN 48 AMS GND 1 2 3 4 5 6 D11 GND 13 R MUTE1 47k 47k 7 8 9 10 11 12 GND AGC OUT1 REC OUT1 AGC IN1 REC IN1 AMS FIL GP CAL FP CAL AMS GND 100k 100k 0.1µ 4.7µ 0.1µ 2.2µ 27k 27k 0.47µ 10k 2.7k 0.1µ RMUTE1 I 10k VDD or VCC AMS OUT GND GND GND GND A EQ B EQ GND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 14 – CXA1898Q 1. System control mode Playback and recording equalizer (1) Playback equalizer (120µs/70µs) A-EQ (Pin 10) L DECK-AB (serial data D10 (Pin 25)) L H 120µs (A DECK) H 70µs (A DECK) L B-EQ (Pin 11) M/H According to A EQ control 120µs (B DECK) 70µs (B DECK) According to B EQ control (2) Recording equalizer (Normal, CrO2, Metal) B-EQ (Pin 11) REC MODE L Normal (Type I) M CrO2 (Type II) H Metal (Type IV) (3) Recording mute (Pin 12) Rec Mute Control voltage Mute OFF GND ≤ VCL ≤ 0.5V –7dB attenuation 2.0V Mute ON 3.5V ≤ VCH ≤ VCC Muting is achieved by varying the recording equalizer amplifier gain just like an electronic volume, according to the DC voltage applied to the REC MUTE pin. (4) FP CAL (Pin 4) The standard resistor setting is 27kΩ, but when resistance value is larger, fo (Hz) is low, and when resistance value is smaller, fo (Hz) is high. (5) Gp Cal (Pin 5) The standard resistor setting is 27kΩ, but when resistance value is larger, gain is larger, and when resistance value is smaller, gain is smaller. – 15 – CXA1898Q 2. 11-bit serial data interface CLk (Pin 24) DATA (Pin 25) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 LATCH (Pin 23) XRESET (Pin 26) • The DATA signal is taken in at the rising edge of the CLK signal. • The DATA signal is taken in to the internal shift register when the LATCH signal is low. (Outputs (Pins 13 to 22) hold the previous value while the LATCH signal is low.) • The internal shift register data is latched and output in parallel at the rising edge of the LATCH signal. (Internal shift register data is loaded while the LATCH signal is high.) • The CLK signal of 11th bit should fall after the LATCH signal rises. • Reset is done when the XRESET pin is low. (asynchronous method) Outputs (Pins 13 to 22) are all high (open) during reset. DATA (Pin 25) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 M2 M1 PL2 PL1 BPB BPA PB-MUTE AGC-OFF SPEED DECK-AB REC-MUTE Output Control signal Output pin Pin 22 Pin 21 Pin 20 Pin 19 Pin 18 Pin 17 Pin 16 — Pin 15 — Pin 14/Pin 13 Input set at low L L L L L L L AGC function stops Low, normal speed A DECK selected Low mute OFF Input set at high H (OPEN) H (OPEN) H (OPEN) H (OPEN) H (OPEN) H (OPEN) H (OPEN) AGC function operates High (open) 1.7 B DECK selected High (open) mute ON – 16 – CXA1898Q • Make sure that RFC is 5.5V or more and XRESET is 1.5V or less, and 1µs or more when resetting by applying CR time constant to XRESET (Pin 26) and turning power ON. 5.5V or more RFC (Pin 36) XRESET (Pin 26) 1.5V or less 1µs or more • When resetting with CPU or other when power is turned ON 5.5V or more RFC (Pin 36) 5.0V XRESET (Pin 26) 0V 1µs or more • Examples of AGC control during timer recording (1) Resets when power is turned ON (AGC function operates). (2) AGC is turned OFF after AGC inputs (Pins 6 and 31) rise. (External capacitor charge of AGC TC is discharged.) (3) AGC is turned ON and timer recording begins. – 17 – CXA1898Q LATCH CLK DATA XRESET DGND 5V SW GND 100µ/25V GND C21 15 L R19 B0 1 10 A0 L 11 B1 H 2 12 A1 13 A2 4 L R18 H 100 B1 VDD C19 0.1µ A1 2 19 Y1 3 4 14 B2 L 15 A3 B4 H 8 14 16 VDD 1 C18 0.1µ B3 16 1 A>BOUT 74HC85 A>BIN A=BIN A