CXA1946CR

CXA1946CR Electronic Volume For the availability of this product, please contact the sales office. Description The CXA1946CR is a serial control electronic volume IC designed for use in audio systems. Features • Loudness • Volume control (0dB to –87dB in 1dB step, –∞dB) • Balance • Tone control (15 steps, 2 bands, –16dB to +16dB) • Fader (2dB-step to –20dB, –25dB, –35dB, –45dB, –60dB, –∞dB) • Input selector (4 channels) • Gain can be set for each input channel (common for channels 3 and 4) • Serial data control (DATA, CLK, CE) • Single 8V power supply • Zero-cross detection circuit (with timer) • Power-off mute • Volume control and tone control input/output pins are separate. Absolute Maximum Ratings • Supply voltage • Operating temperature • Storage temperature • Allowable power dissipation Operating Conditions Supply voltage 48 pin LQFP (Plastic) VCC Topr Tstg PD LQFP 13 –40 to +85 –65 to +150 180 V °C °C mW (Ta = 85°C) VCC 6 to 12 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97516A7Y CXA1946CR Block Diagram and Pin Configuration GAIN134 LDLC1 TCLC11 LDHC1 TCLC12 TCHC1 VOUT1 INAO1 VRIN1 36 35 34 33 32 31 30 29 28 27 26 TCO1 TIN1 25 GAIN12 37 LOUD 8dB STEP VOLUME 1dB STEP VOLUME FADER FDIN1 24 FNTO1 GAIN11 38 TONE 23 REO1 IN14 39 VCTBUFF VCTBUFF 22 CE IN13 40 INPUT SW VCTBUFF 21 CLK IN12 41 20 DGND LATCH LATCH CONTROL 100k ZCDET 19 GND IN11 42 IN21 43 SHIFT REGISTER 100k 18 VCC INPUT SW IN22 44 17 VCT IN23 45 VCTBUFF VCTBUFF 16 DATA IN24 46 VCTBUFF VOLUME 8dB STEP VOLUME 1dB STEP 15 TIMER GAIN21 47 LOUD GAIN22 48 TONE FADER 14 REO2 13 FNTO2 1 2 3 4 5 6 7 8 9 10 11 12 VOUT2 TCHC2 TCLC22 GAIN234 LDHC2 VRIN2 TCLC21 LDLC2 INAO2 –2– FDIN2 TIN2 TCO2 CXA1946CR Pin Description Pin No. Symbol I/O resistance Pin voltage Equivalent circuit Description VCC 1 36 GAIN234 GAIN134 ~∞ – VCT 1 36 Sets gain for IN3 and IN4. GND VCC 2 35 LDLC2 LDLC1 6.18kΩ VCT 2 35 Sets loudness low cut-off frequency. GND VCC 3 34 LDHC2 LDHC1 8.92kΩ VCT 3 34 Sets loudness high cut-off frequency. GND VCC 4 33 INAO2 INAO1 — VCT 4 33 Input selector output GND –3– CXA1946CR Pin No. Symbol I/O resistance Pin voltage Equivalent circuit Description VCC 5 5 32 VRIN2 VRIN1 9.5kΩ VCT 32 Volume input GND VCC 6 31 VOUT2 VOUT1 — VCT 6 31 Volume output GND VCC 7 30 TIN2 TIN1 19kΩ VCT 7 30 Tone input GND VCC 8 29 TCHC2 TCHC1 5kΩ VCT 8 29 Sets tone high frequency. GND –4– CXA1946CR Pin No. Symbol I/O resistance Pin voltage Equivalent circuit Description VCC 9 28 TCLC21 TCLC11 8kΩ VCT 9 28 Sets tone low frequency. GND VCC 10 27 TCLC22 TCLC12 8kΩ VCT 10 27 Sets tone low frequency. GND VCC 11 26 TCO2 TCO1 — VCT 11 26 Tone control output GND VCC 12 25 FDIN2 FDIN1 24kΩ VCT 12 25 Fader input GND –5– CXA1946CR Pin No. Symbol I/O resistance Pin voltage Equivalent circuit Description VCC 13 24 FNTO2 FNTO1 — VCT 13 24 Front output GND VCC 14 23 REO2 REO1 — VCT 14 23 Rear output GND VCC 15 TIMER — — 15 Sets timer. GND VCC 16 DATA ~∞ – — 16 Serial data input GND –6– CXA1946CR Pin No. 17 18 19 20 Symbol VCT VCC GND DGND I/O resistance Pin voltage — VCT VCC GND — Equivalent circuit Description Center electric potential + power supply GND Digital GND VCC 21 CLK ~∞ – — 21 Serial clock input GND VCC 22 CE ~∞ – — 22 Latch enable input GND VCC 37 48 GAIN12 GAIN22 ~∞ – VCT 37 48 Sets gain for IN2. GND –7– CXA1946CR Pin No. Symbol I/O resistance Pin voltage Equivalent circuit Description VCC 38 47 GAIN11 GAIN21 ~∞ – 38 47 Sets gain for IN1. GND 39 40 41 42 43 44 45 46 IN14 IN13 IN12 IN11 IN21 IN22 IN23 IN24 VCC 50kΩ VCT 39 43 40 44 41 45 42 46 GND Signal input –8– CXA1946CR Data Format (a) Data allocation FAST BIT D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 LAST BIT D32 NOP ISW LOUD MSB VRC1 VRF1 VRC2 VRF2 TONE BASS TONE TREBLE FADER FADER SELECT LSB –9– CXA1946CR (b) Setting table • NOP Setting value — • ISW Setting value IN14/IN24 IN13/IN23 IN12/IN22 IN11/IN21 • LOUD Setting value ON OFF • VRC1/VRC2 Setting value 0 –8 –16 –24 –32 –40 –48 –56 –64 –72 –80 –∞ –∞ • VRF1/VRF2 Setting value 0 –1 –2 –3 –4 –5 –6 –7 D10/D17 1 1 1 1 0 0 0 0 D11/D18 1 1 0 0 1 1 0 0 D12/D19 1 0 1 0 1 0 1 0 D6/D13 1 1 1 1 1 1 1 1 0 0 0 0 0 D7/D14 1 1 1 1 0 0 0 0 1 1 1 1 0 D8/D15 1 1 0 0 1 1 0 0 1 1 0 0 0 D9/D16 1 0 1 0 1 0 1 0 1 0 1 0 0 D5 1 0 D3 1 1 0 0 D4 1 0 1 0 D1 0 D2 0 – 10 – CXA1946CR • TONE BASS/TREBLE Setting value 14 12 10 8 6 4 2 0 • BOOST/CUT Setting value BOOST CUT • FADER Setting value –∞ –60 –45 –35 –25 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 • FADER SELECT Setting value Attenuation of front signal Attenuation of rear signal D32 1 0 D28 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D29 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D30 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D31 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D23/D27 1 0 D20/D24 1 1 1 1 0 0 0 0 D21/D25 1 1 0 0 1 1 0 0 D22/D26 1 0 1 0 1 0 1 0 • RESET Reset is performed automatically when power is first supplied to the IC; there is no reset pin. The following table shows the respective statuses of various settings after a reset has been performed. However, from the time when power is first supplied until the first data transfer, keep CE high by pulling it up to Vcc, etc. MODE INPUT VRC1 VRF1 VRC2 VRF2 LOUD TONE BASS TONE TREBLE FADER Setting value 1 –∞ –7dB –∞ –7dB OFF 0dB 0dB 0dB, REAR – 11 – CXA1946CR Electrical Characteristics Item Current consumption Total harmonic distortion Output noise voltage Maximum output voltage Separation Volume maximum attenuation Loudness Bass max. boost gain Bass max. cut gain Treble max. boost gain Treble max. cut gain Input voltage Input voltage range Low High Low High Symbol ICC THD Vn Vom CS ATTm Glb Glh Gbb Gbc Gtb Gtc Vsl Vsh Vin DATA, CLK, CE (Unless otherwise specified, Vcc = 8V, Ta = 25°C) Measurement conditions No signal 1kHz, 5dBm output input shorted, A weight 1kHz 1kHz 1kHz 100Hz, VRC = –16dB 10kHz, VRC = –16dB Min. — — — 8 72 85 7 5 14 14 14 14 0 3 1 Typ. 20 Max. 25 Unit mA % µVrms dBm dB dB dB dB dB dB dB dB V V V 0.005 0.01 7 — 90 90 8 6 16 16 16 16 — — — 10 — — — 9 7 18 18 18 18 1.5 6 VCC–1 IN11 to 14, IN21 to 24, VRIN1, VRIN2, TIN1, TIN2, FDIN1, FDIN2 – 12 – CXA1946CR Electrical Characteristics Measurement Circuit 0.0027µ 10µ V6 AC B A S3 31 30 B 10µ 0.39µ 10µ A 0.047µ 0.0022µ V7 AC B S5-1 25 OFF ON S1 1k 1k V5 AC OP AMP VCT-50mV 10k 10k 10k 36 35 A S2 33 32 1k 220p 34 29 28 27 26 LDLC1 LDHC1 INAO1 VRIN1 VOUT1 TIN1 TCHC1 TCLC11 TCO1 GAIN134 TCLC12 FDIN1 FNTO1 24 10k REO1 23 10k CE 22 1k CLK 21 1k DGND 20 GND 19 VCC 18 VCT 17 DATA 16 1k TIMER 15 S4 REO2 14 10k FNTO2 13 A B OF S6 F ON 37 GAIN12 38 GAIN11 B S14 A 39 IN14 B S1310k 40 IN13 A B S1210k 41 IN12 A B S1110k A 42 IN11 B S2110k A 43 IN21 B S2210k A 44 IN22 B S2310k A 45 IN23 B S2410k A 46 IN24 10k 47 GAIN21 V3 V2 V14 AC V13 AC V12 AC V11 AC V21 AC V22 AC V23 AC V24 AC VCC 3 to 6V VEE 3 to 6V V1 0.01µ 10k GAIN234 TCLC21 TCLC22 TCHC2 LDHC2 VOUT2 48 GAIN22 LDLC2 INAO2 VRIN2 FDIN2 1 2 3 4 5 6 7 8 9 TCO2 TIN2 10k 10 11 A 12 S5-2 0.0022µ 0.047µ 10k 10k 10k 0.0027µ 0.39µ B V8 AC 10µ 10µ 10µ – 13 – CXA1946CR Application Circuit 1 0.047µ 0.0022µ 10µ 0.0027µ 10µ 32 31 30 29 28 27 0.39µ 10µ 26 25 36 35 34 33 TCHC1 TCLC11 GAIN134 TCLC12 INAO1 LDLC1 TCO1 LDHC1 VRIN1 VOUT1 37 GAIN12 38 GAIN11 39 IN14 40 IN13 41 IN12 42 IN11 43 IN21 44 IN22 45 IN23 46 IN24 47 GAIN21 FDIN1 TIN1 FNTO1 24 REO1 23 CE 22 CLK 21 DGND 20 GND 19 33µ VCC 18 VCT 17 10µ DATA 16 TIMER 15 0.01µ REO2 14 GAIN234 TCLC22 LDHC2 VOUT2 LDLC2 TCHC2 VRIN2 INAO2 1 2 3 4 10µ 0.0022µ 5 6 7 8 9 10 11 10µ 12 0.047µ 0.0027µ 10µ 0.39µ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 14 – FDIN2 TIN2 TCO2 48 GAIN22 TCLC21 FNTO2 13 CXA1946CR Application Circuit 2 0.047µ 0.0027µ 0.0022µ 10µ 0.39µ 10µ 27 10µ 26 25 36 35 34 33 32 31 30 29 28 GAIN134 INAO1 LDLC1 TCO1 LDHC1 VRIN1 VOUT1 TCHC1 TCLC11 37 GAIN12 38 GAIN11 39 IN14 40 IN13 41 IN12 42 IN11 43 IN21 44 IN22 45 IN23 46 IN24 47 GAIN21 TCLC12 FDIN1 FNTO1 24 REO1 23 CE 22 CLK 21 DGND 20 GND 19 33µ VCC 18 VCT 17 10µ DATA 16 TIMER 15 0.01µ REO2 14 FNTO2 GAIN234 TIN1 TCLC21 LDHC2 VOUT2 LDLC2 TCHC2 INAO2 VRIN2 1 2 3 4 10µ 5 6 7 8 9 TCO2 10 11 12 0.047µ 0.0027µ 0.0022µ 10µ 0.39µ 10µ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 15 – FDIN2 48 GAIN22 TCLC22 13 TIN2 CXA1946CR Tone control characteristics 20 16 +16dB 12 8 Response [dB] 4 0 0dB –4 –8 –12 –16 –20 10 –16dB 100 1k Frequency [Hz] 10k 100k Loudness characteristics 0 VRC = 0dB –5 VRC = –8dB Response [dB] –10 VRC = –16dB –15 VRC = –24dB –20 –25 10 100 1k Frequency [Hz] 10k 100k – 16 – CXA1946CR Description of Operation The CXA1946CR is a serial control electronic volume IC designed for use in audio systems. The internal circuit of the IC consists of the following blocks: 1. 2. 3. 4. 5. 6. 7. 8. 9. Input selector Volume Loudness Tone control Fader VCT buffer Serial data I/O Zero-cross detector (with timer) Power-off mute The operation of each block and notes on their use are described below. Note that when the circuits for channels 1 and 2 are identical, the suffix “X” is added to pin names and device names in order to distinguish between the two channels. 1. Input selector There are two channels (stereo), each with four systems of input pins; the input selector selects one of those input systems. The gain between the input pins and the output pin of the input selector can be set independently for each input system, except the gain for inputs 3 and 4 is common. Determine the gain for each system through the settings of the feedback circuit constants as shown in Figs. 1 and 2. When each input gain is set to × 1, short INAOX and GAIN × 1,GAIN × 2,GAIN × 34. The input impedance is 50kΩ (typ.) for each input. The output impedance for INAO1 and INAO2 is low impedance (roughly 0Ω). The gain is not affected by the load impedance. VCT GAINX2 GAINX1 GAINX34 INAOX INX4 50k INX3 50k INX2 50k INX1 50k Fig. 1. Input Selector (1) – 17 – CXA1946CR VCT GAINX2 GAINX1 GAINX34 INAOX INX4 50k INX3 50k INX2 50k INX1 50k Fig. 2. Input Selector (2) 2. Volume The volume circuit consists of two sections, an 8dB/step section and a 1dB/step section, as shown in Fig. 3. This circuit also serves as a balance control because the volume for channel 1 and channel 2 can be set independently. To mute the output signal, send –∞dB data. The input impedance is 9.5kΩ (typ.) for VRIN1 and VRIN2. The output impedance for VOUT1 and VOUT2 is low impedance (roughly 0Ω). The volume step width and gain are not affected by the load impedance. 3. Loudness The configuration of the loudness circuit is shown in Fig. 3. CLDHCX and CLDLCX are connected externally, and the loudness frequency characteristics are determined by these constants. The relationships between CLDHCX/CLDLCX and the frequency characteristics are as follows: 1/fL = 2πCLDLCXR1 1/fH = 2πCLDHCXR2 The loudness characteristics are not affected by the load impedance of VOUT1 and VOUT2. Loudness is turned on and off by serial data bit D5. VRINX (input impedance 9.5kΩ) 20k CLDHCX 0.0022µ R2 8.92k LDHCX 25.7k CLDLCX 0.047µ LDLCX 20k 4.98k OFF ON LOUD R1 6.18k Total 40k fH fL Loudness frequency characteristics VOUTX Loudness Volume Fig. 3. Volume and Loudness – 18 – CXA1946CR 4. Tone control The configuration of the tone control circuit is shown in Fig. 4. CTCLCX2 and CTCHCX are connected externally, and the tone control frequency characteristics can be changed by changing these constants. The relationships between CTCLCX2/CTCHCX and the frequency characteristics are as follows: 1/fL = 2πCTCLCX2 (R3//R4) 1/fH = 2πCTCHCXR5 The maximum bass boost and cut can be made smaller than in the Application Circuit by connecting an external resistance to the TCLCX1 pin in series, or else connecting an external resistance to CTCLCX2 in parallel. (See Fig. 5.) Furthermore, the maximum treble boost and cut can be made smaller than in the Application Circuit by connecting an external resistance to CTCHCX in series. (See Fig. 6.) However, when these methods are used, variations in the absolute value of the CXA1946C internal resistance (±20% max.) and in the external resistance will cause variations in the tone control characteristics. Set these constants after studying all considerations carefully. Note that when the method illustrated in the Application Circuit is used, variations in the internal resistance of the CXA1946C have no effect on the tone control characteristics. The input impedance is 19kΩ (typ.) for TIN1 and TIN2. The output impedance for TCO1 and TCO2 is low impedance (roughly 0Ω). The tone step width and gain are not affected by the load impedance. CTCLCX2 0.39µ TCLCX1 12k TCOX TINX input impedance 19kΩ R4 8k BASS ON OFF R3 8k ON 14.1k BOOST 14.1k CUT 14.1k 12k TCLCX2 OFF 10k 10k 10k fL fH 10k Tone control frequency characteristics TCHCX CTCHCX 0.0027µ ON OFF R5 5k TREBLE ON CUT OFF 14.1k BOOST Fig. 4. Tone Control – 19 – CXA1946CR CTCLCX2 RexA TCLCX1 R4 8k R3 8k TCLCX2 CTCLCX2 RexB TCLCX1 R4 8k R3 8k TCLCX2 TINX (A) (B) Fig. 5. Method for Reducing Bass Boost/Cut 10k 10k 10k 10k R3 5k TCHCX RexC CTCHCX Fig. 6. Method for Reducing Treble Boost/Cut 5. Fader The configuration of the fader circuit is shown in Fig. 7. The fader operates by specifying the amount of attenuation for either the front or rear output signal and by specifying which output signal (front or rear) is to be attenuated. The input impedance is 24kΩ (typ.) for FDIN1 and FDIN2. The output impedance for FNTO1, FNTO2, REO1, and REO2 is low impedance (roughly 0Ω). The gain and fader step width are not affected by the load impedance. FDINX (input impedance 24kΩ) Center FNTOX ATT Center REOX ATT Fig. 7. Fader – 20 – CXA1946CR 6. VCT buffer The internal circuit for the VCT pin is shown in Fig. 8. This circuit generates the electric potential for the center between Vcc and GND (Vcc/2). The IC internal operation reference potential is equal to the output potential of VCT buffer. The impedance for the VCT pin (Pin 17) is high since it is connected to a bypass capacitor. Add an external buffer when using the electric potential of the VCT pin as the external reference potential for the CXA1946. VCC 100k VCT 10µ 100k Fig. 8. VCT Buffer 7. Serial data I/O The serial data has a 32-bit structure as indicated in the specifications. Data input is conducted using three inputs: DATA, CLK, and CE. DATA is shifted in the CXA1946C internal shift register at the rising edge of CLK. The data in the shift register is latched at the falling edge of CE. Refer to this specification for details on the timing. The CXA1946C does not have a reset (initialize) pin. The internal shift register and latch are reset automatically when power is first supplied to the IC. To execute a reset at other times, send the data (statuses after reset ) shown in the item "RESET" of this specification to the CXA1946C. 8. Zero-cross detector (with timer) Using the zero-cross detector, the internal latch data is overwritten the first time the input signal becomes roughly 0 after serial data is sent (after CE goes low). This operation reduces noise when overwriting data. Although there are usually no problems when a normal audio signal is input, in rare cases there may be nothing except a large-amplitude input signal of the high band, causing the slew rate to become abnormally high; the zero-cross detection signal is not output in such a case because the zero-cross detector response speed is too slow. Another rare situation would be that the zero-cross detection signal is output very infrequently because the input signal frequency is extremely low. In these types of instances, it is conceivable that the internal latch data will not be overwritten after data is sent, or that it will take much time until the data is overwritten. Therefore, to an external observer it will appear that the data is not being overwritten regardless of the fact that data is being sent. As a countermeasure, the IC is designed to permit the internal latch data to be forcibly overwritten if the zero-cross detection signal is not output within a certain waiting period after the data is sent (after CE goes low). This function is called the “timer.” If the zero-cross detection signal is output within a certain waiting period, the internal latch data is overwritten in synchronization with the zero-cross of the input signal. The waiting period mentioned above can be changed according to the value of the external capacitor connected to the TIMER pin. When the value of the capacitor is 0.01µF, the waiting period is approximately 500µs. 9. Power-off mute When Vcc goes below 5V, the output stage bias of the fader output pins FNTO1, FNTO2, REO1, and REO2 is turned off and the pins go to high impedance. This operation prevents popping noises caused by the output pin potential deviating from Vcc/2 when the power is turned off. – 21 – CXA1946CR Connections and Characteristics of Each Block In the Application Circuit, the signal path goes from the input selector to the volume (+loudness) to the tone control to the fader. The sequence of the blocks in the signal path can be changed because the I/O pins for each block are independent of each other. For example, it is possible to switch the sequence of the volume circuit and the tone control so that the signal path goes from the input selector to the tone control to the volume (+loudness) to the fader. When this connection method is used, the noise voltage in the fader output can be reduced in actual use because the noise and signal up to the tone control are attenuated by the volume. However, because the maximum output amplitude of the tone control circuit is limited by the supply voltage, care should be given to the setting of the input signal level. Although blocks in the Application Circuit are linked either by coupling capacitors or by direct connection, it is also possible to insert external circuits between blocks. In this case, the gain will change according to the input impedance of the following block and the impedance of the external circuit. In addition, the input impedance of each block can vary by ±20% due to the characteristics of the IC. Consequently, the overall gain also varies. Give careful consideration to the effects of this variation when setting the constants. The step widths (control characteristics) of the volume, tone control, and fader are not affected. Timing Chart CE DATA D1 D2 D30 D31 D32 Invalid CLK t1 t1 ≥ 0.5µs t2 ≥ 0.5µs tck ≥ 1.0µs tsu ≥ 0.5µs th ≥ 0.5µs tck tsu th t2 tL tL ≥ tT + 0.5µs (tT is the maximum value for the timer operation time) CE tce tce ≥ 4.0µs Timer Waiting Period Setting Chart (Vcc = 6 to 12V, operating temperature = –35°C to 85°C) TIMER pin capacitance C C = 100pF C = 0.001µF C = 0.01µF C = 0.1µF C = 1µF C = 10µF Waiting peroid Min. 3µs 30µs 300µs 3ms 30ms 300ms Typ. 5µs 50µs 500µs 5ms 50ms 500ms Max. 9µs 90µs 900µs 9ms 90ms 900ms – 22 – CXA1946CR Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 36 37 7.0 ± 0.1 25 24 (8.0) A 48 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 0.1 ± 0.1 + 0.2 1.5 – 0.1 12 13 (0.22) + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 ∗QFP048-P-0707-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY 0.2g – 23 – 0.5 ± 0.2