CXA1982Q

CXA1982Q RF Signal Processing Servo Amplifier for CD players For the availability of this product, please contact the sales office. Description The CXA1982Q is a bipolar IC with built-in RF signal processing and various servo ICs. A CD player servo can be configured by using this IC, DSP and driver. Features • Low operating voltage (VCC – VEE = 2.8 to 4.0V) • Low power consumption (36mW, VCC = 3.0V) • Supports pickup of either current output, voltage output • Supports tracking system balance adjustment externally • Single power supply and positive/negative dual power supplies Applications • RF I-V amplifier, RF amplifier • Focus and tracking error amplifier • APC circuit • Mirror detection circuit • Defect detection and prevention circuits • Focus servo control • Tracking servo control • Sled servo control Structure Bipolar silicon monolithic IC 48 pin QFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 12 V • Supply voltage VCC • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 833 mW Recommended Operating Condition Operating supply voltage VCC – VEE 2.8 to 4.0 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97215-PS CXA1982Q Block Diagram PHD1 RF_M PHD2 RF_O RF_I 36 35 34 33 32 31 30 29 28 27 CC1 PD LD CP 26 25 APC LEVEL S I IL 24 SENS FOK CB CC2 TTL 23 C.OUT RF IV AMP1 MIRR FOK DFCT TTL RF IV AMP2 FE_BIAS 37 TTL •I IL DATA REGISTER •INPUT SHIFT REGISTER •ADRESS.DECODER 20 XLT 22 XRST 21 DATA I IL F 38 FE AMP F IV AMP I IL •OUTPUT DECODER 19 CLK E 39 E IV AMP EI 40 TE AMP FZC COMP FS1 to 4 TG1 to 2 TM1 to 7 PS1 to 4 18 Vcc •TRACKING PHASE COMPENSATION VEE 41 TEO 42 TG1 TM5 TM4 TZC COMP NC 43 TEI 44 ATSC 45 TZC 46 TDFCT 47 DFCT VC 48 FS4 •WINDOW COMP. ATSC FS2 DFCT TM1 •FCS PHASE COMPENSATION FS1 TM7 TM3 TM6 •I SET 17 ISET 16 SL_O 15 SL_M TM2 14 SL_P 13 TA_O 1 2 3 4 5 6 7 8 9 10 11 •F SET TG2 12 FEO FDFCT TG2 FEI FLB FE_M FSET FGD SRCH • • • • The switch state in Block Diagram is for initial resetting. Switch turns to ° side for 1 and to • side for 0 in Serial Data Truth Table. DFCT switch turns to ° side when defect signal generates for DEFECT = E in Serial Data Truth Table. TG1 switch turns to ° side and TG2 switch is left open when TG1 and TG2 (address 1 : D3) is 1. –2– TA_M FE_O TGU CXA1982Q Pin Description Pin No. Symbol I/O Equivalent circuit Description 25p 147 1 174k 51k 300µ 10k 9k 1 FEO O Focus error amplifier output. Connected internally to the FZC comparator input. 2 FEI I 2 147 100k 147 Focus error input. 3 FDFCT I 3 Capacitor connection pin for defect time constant. 68k 147 4 FGD I 4 130k 20µ Ground this pin through a capacitor when decreasing the focus servo high-frequency gain. 5 FLB I 40k 5 External time constant setting pin for increasing the focus servo lowfrequency. 6 FE_O O 6 Focus drive output. 13 TA_O O 13 16 Tracking drive output. 16 SL_O O 250µ Sled drive output. 147 90k 7 FE_M I 7 50k Focus amplifier inverted input. –3– CXA1982Q Pin No. Symbol I/O Equivalent circuit Description 147 8 SRCH I 8 50k 11µ External time constant setting pin for generating focus servo waveform. 110k 9 TGU I 20k 9 82k External time constant setting pin for switching tracking high-frequency gain. 10 TG2 I 10 470k 2µ External time constant setting pin for switching tracking high-frequency gain. 147k 11 FSET I 11 15k 15k High cut-off frequency setting pin for focus and tracking phase compensation amplifier. 100k 12 TA_M I 147 12 11µ Tracking amplifier inverted input. 14 SL_P I 147 14 Sled amplifier non-inverted input. 147 15 SL_M I 15 22µ Sled amplifier inverted input. –4– CXA1982Q Pin No. Symbol I/O Equivalent circuit Description 147 17 ISET I 17 Setting pin for Focus search, Track jump, and Sled kick current. 19 20 21 22 CLK XLT DATA XRST I 15µ Serial data transfer clock input from CPU. (no pull-up resistance) Latch input from CPU. (no pull-up resistance) Serial data input from CPU. (no pull-up resistance) Reset input; resets at Low. (no pull-up resistance) I I I 19 20 21 22 147 1k 23 C. OUT O 20k 147 23 24 Track number count signal output. 24 SENS O 100k Outputs FZC, DFCT, TZC, gain, balance, and others according to the command from CPU. 20k 25 FOK O 147 25 40k Focus OK comparator output. 100k 26 CC2 I 147 28 147 27 Input for the DEFECT bottom hold output with capacitance coupled. 27 CC1 O DEFECT bottom hold output. 147 26 28 CB I Connection pin for DEFECT bottom hold capacitor. –5– CXA1982Q Pin No. Symbol I/O Equivalent circuit Description 147 29 29 CP I Connection pin for MIRR hold capacitor. MIRR comparator non-inverted input. 30 RF_I I 147 30 Input for the RF summing amplifier output with capacitance coupled. RF sunning amplifier output. Eye-pattern check point. 147 31 147 32 31 RF_O O 32 RF_M I RF summing amplifier inverted input. The RF amplifier gain is determined by the resistance connected between this pin and RFO pin. 10k 1k 33 LD O 33 APC amplifier output. 130k 17µ 34 PD I 100k 34 APC amplifier input. 10k 35 36 PHD1 PHD2 I I 147 35 36 100µ 11.6k RF I-V amplifier inverted input. Connect these pins to the photo diode A + C and B + D pins. –6– CXA1982Q Pin No. Symbol I/O Equivalent circuit Description 32k 164k 37 FE_BIAS I 37 25p 8µ Bias adjustment of focus error amplifier. 12p 260k 38 39 F E I I 147 38 39 10µ 513 F I-V and E I-V amplifier inverted input. Connect these pins to photo diodes F and E. 6.8k 260k 40 EI — 40 20.3k I-V amplifier E balance adjustment. 147 42 TEO O 42 Tracking error amplifier output. E-F signal is output. 300µ 43 NC — –7– CXA1982Q Pin No. Symbol I/O Equivalent circuit Description 44 TEI I 44 147 100k Tracking error input. 147 47 TDFCT I 47 Capacitor connection pin for defect time constant. 1k 10k 100k 45 ATSC I 45 100k 1k Window comparator input for ATSC detection. 10k 46 TZC I 46 75k Tracking zero-cross comparator input. 48 VC O 50 48 120 (VCC + VEE)/2 DC voltage output. 120 VC –8– Electrical Characteristics SW conditions SD Measurement conditions Min. Typ. 12 –12 0 28.1 1.2 — –120 V1 = 1kHz I/O ratio V1 = 1kHz I/O ratio 27.0 27.0 –3.0 V1 = 100mVDC V1 = 100mVDC 42 V1 = 1kHz O O V1 = 1kHz EI: 39kΩ V1 = 1VDC O O O O O O O O 48 33 V1 = 1VDC EI: 39kΩ V2 = 120mV V2 = 145mV V2 = 170mV 0.8mA sink 1.0 — –25 7.3 7.2 1.2 — –900 –400 350 –200 –100 1.3 –0.9 0 30.0 30.0 0 1.3 –1.3 0 10.3 10.2 1.45 –1.33 18 –8 50 31.1 — –0.3 120 33.0 33.0 3.0 — –1.0 25 13.3 13.2 — –1.0 –300 900 1500 500 100 8 –18 –50 1kHz input ratio V1 = 100mVDC V1 = –100mVDC 1 25.1 Max. mA mA mV dB V V mV dB dB dB V V mV dB dB V V mV mV mV mV mV 4 6 10 RST 18 41 31 11 12 13 16 14 15 7 5 8 9 17 18 Measurement pin (VCC = 1.5V, VEE = –1.5V, Ta = 25°C) Ratings Unit Item 1 2 3 T1 Current consumption 1 T2 Current consumption 2 T3 Offset T4 Voltage gain O O RF amplifier T5 Max. output voltage-High O T6 Max. output voltage-Low O T7 Offset T8 Voltage gain 1 O T9 Voltage gain 1 O TE amplifier APC VC –9– T11 FE amplifier T10 Voltage gain difference Max. output voltage-High O T12 Max. output voltage-Low O T13 Offset T14 Voltage gain F0 O T15 Voltage gain E0 T16 Max. output voltage-High O T17 Max. output voltage-Low T18 Output voltage 1 T19 Output voltage 2 T20 Output voltage 3 T21 Output voltage 4 T22 Center amplifier output offset CXA1982Q SW conditions 4 6 7 10 11 Max. 24 53 –35 1.0 — –640 360 24 Pin 1 threshold 13 T31+ T14 O O O O 2C 28 O O O O 25 25 25 38 24 25 10 O Output gain difference between SD = 20 and SD = 25. V1 = –0.5VDC V1 = +0.5VDC –640 360 –25 7 –20 –400 1.0 1.3 –1.3 –500 500 –15 15 0 –356 –1.0 –360 640 –7 25 20 –330 185 12.25 22.9 1.3 –1.3 –500 500 225 14.6 24.9 — –1.0 –360 640 265 17.6 26.9 –39 dB dB dB V V mV mV mV dB dB dB V V mV mV mV mV mV mV O 08 6 T23+ T8 (or T9) O O O V1 = 200mVDC V1 = –200mVDC O 02 03 00 O 25 08 O 08 00 Output gain difference between SD = 00 and SD = 08. 49 51 21.0 18 12 13 14 15 16 Min. 5 9 8 17 18 SD ment pin Measurement conditions Typ. Measure- Ratings Unit Item 1 2 3 T23 DC voltage gain T24 FCS total gain T25 Feed through T26 Max. output voltage-High FCS servo T27 Max. output voltage-Low T28 Search voltage (–) T29 Search voltage (+) T30 FZC threshold O T31 DC voltage gain T32 TRK total gain T36 TRK servo FOK – 10 – T33 Feed through T34 Max. output voltage-High T35 Max. output voltage-Low Jump output voltage (–) T37 Jump output voltage (+) T38 ATSC threshold (–) T39 ATSC threshold (+) T40 TZC threshold T41 FOK threshold CXA1982Q SW conditions 4 6 11 Max. dB –34 1.0 1.3 –1.3 –750 450 23 Measures at C. OUT pin. Measures at C. OUT pin. Measures at C. OUT pin. 10 24 Measures at SENS pin. Measures at SENS pin. Measures at SENS pin. Measures at SENS pin. 1.8 2.5 0.5 1.8 1 30 0.3 –600 600 –1.0 –450 750 dB V V mV mV kHz Vp-p Vp-p kHz kHz Vp-p Vp-p O O O V1 = +0.4VDC V1 = –0.4VDC 23 22 O O O O O O 14 O 25 20 Output gain difference between SD = 20 and SD = 25. 25 50 16 12 13 14 15 16 7 17 18 5 8 9 10 SD ment pin Measurement conditions Min. Typ. Measure- Ratings Unit Item 1 2 3 T42 DC open gain T43 Feed through T45 Sled servo T44 Max. output voltage-High Max. output voltage-Low T46 Kick voltage (–) T47 Kick voltage (+) T48 Max. operating frequency T50 MIRR T49 Min. input operating voltage Max. input operating voltage T51 Min. operating frequency O O T52 Max. operating frequency O O DEFECT – 11 – T53 Min. input operating voltage O O T54 Max. input operating voltage O O CXA1982Q CXA1982Q Electrical Characteristics Measurement Circuit VEE Vcc V2 S17 S16 10k 3000p 1000p S2 S1 10k 36 35 10k 22k 34 33 32 31 S15 30 29 28 27 26 25 PD2 RF_I CB RF_M RF_O CC1 PD CP 37 S3 S4 10k 390k FOK CC2 PD1 LD 10k 24 10k Vcc 10k XRST DATA XLT CLK 3300p FE_BIAS SENS Vcc 38 F 39 E 390k 39kΩ S5 VEE 40 EI 41 VEE 42 TEO 43 NC V1 AC DC S6 44 TEI S7 45 ATSC S8 46 TZC 47 TDFCT C. OUT 23 XRST 22 DATA 21 XLT 20 CLK 19 Vcc 18 ISET 17 A S18 A Vcc 240k VEE 60k S14 SL_O 16 SL_M 15 13k 5.1k 10k SL_P 14 FDFCT SRCH FE_M FGD TGU FEO FEI FLB TG2 200k S13 48 VC FSET TA_M FE_O V 0.1µ S9 TA_O 13 1 2 3 4 5 6 100k 7 8 9 10 S12 11 12 0.1µ 10k S10 47k S11 – 12 – 10k 200k 0.015µ 510k 100k CXA1982Q Application Circuit (Dual ±1.5V power supplies) Vcc Vcc 1k 1µ/6.3V A C B D VEE 500 10µH 10 100µ/6.3V 1µ/6.3V 100 0.033µ 22k 0.01µ 0.033µ PD RF O RF M CC1 FOK PD1 CC2 RF I CP Vcc 47k F E 6.8k 22k 40 EI 41 VEE 100k VEE 36 35 34 33 32 31 0.01µ 30 29 28 27 26 PD2 CB LD MICROCOMPUTER 25 24 DSP DSP MICROCOMPUTER DSP DSP DSP Vcc Vcc 18 120k ISET 17 VEE SENS C. OUT 23 XRST 22 DATA 21 XLT 20 CLK 19 SL O 16 SL M 15 SL P 14 37 VEE FE_BIAS 38 F 39 E 42 TEO 43 NC 44 TEI 0.022µ 8.2k 100k 46 TZC 47 TDFCT FDFCT SRCH 0.1µ FE M TA M FE O FGD TGU FEO 10µ FLB TG2 FEI 48 VC FSET TA O 13 22µ 15k 100k 2200p 0.1µ 680k 0.1µ 22k 4.7µ 82k Driver DSP DSP MICROCOMPUTER DSP DSP DSP Driver 1 2 3 4 5 6 7 8 9 10 11 12 0.1µ 0.033µ Vcc Application Circuit (Single +3V power supply) Vcc Vcc 1k 1µ/6.3V A C B D Vcc 47k F E 6.8k 22k 40 EI 41 VEE 100k 42 TEO 43 NC 44 TEI CLK 19 Vcc 18 120k ISET 17 Vcc DATA 21 XLT 20 37 36 35 34 33 32 31 30 10µH 10 100µ/6.3V 1µ/6.3V Driver 0.01µ 22k 0.01µ 0.033µ 100 500 0.033µ 29 28 27 26 RF O RF M FOK PD CC1 CC2 PD1 PD2 LD RF I CP CB MICROCOMPUTER 25 24 FE_BIAS SENS 38 F 39 E C. OUT 23 XRST 22 0.022µ 8.2k 100k 46 TZC 47 TDFCT SL M 15 SL P 14 FDFCT SRCH 0.1µ FE M TA M FE O FEO FGD TGU 10µ Vcc 10µ TG2 FLB FEI 48 VC FSET TA O 13 22µ 15k 100k 2200p 0.1µ 0.1µ 680k 0.1µ 22k 4.7µ 82k 1 2 3 4 5 6 7 8 9 10 11 12 0.015µ BPF 45 ATSC SL O 16 0.015µ 100k 510k 3.3µ 0.033µ Vcc Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 13 – Driver 0.015µ 100k 510k Driver 0.015µ 3.3µ BPF 45 ATSC Driver CXA1982Q Description of Functions RF Amplifier The photo diode currents input to the input pins (PD1 and PD2) are each I-V converted via a 58kΩ equivalent resistor by the PD I-V amplifiers. these signals are added by the RF summing amplifier, and the photo diode (A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check can be performed at this pin. 1k 3.3µ 22k RF_M A 58k C PD1 iPD1 → B PD2 iPD2 → 36 PD2 IV AMP VC VB 10k 35 PD1 IV AMP VC 58k VC VA 10k FOK DEFECT RF SUMMING AMP 32 RF_O 31 D The low frequency component of the RFO output voltage is VRFO = 2.2 × (VA + VB) = 127.6kΩ × (iPD1 + iPD2). Focus Error Amplifier The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and output current-voltage converted voltage of the photo diode (A + C – B – D). 25p 174k VB VA 32k 1 FEO 32k 25p 87k 164k FE_BIAS 37 VEE 47k VCC FE AMP – (B + D) – (A + C) VC The FEO output voltage (low frequency) is VFEO = 5.4 × (VA – VB) = (iPD2 – iPD1) × 315kΩ. Be aware that the rotation of the focus bias volume has reversed for the usual CD RF IC. – 14 – CXA1982Q Tracking Error Amplifier The photo diode currents input to E and F pins are each current-voltage converted by the E I-V and F I-V amplifiers. 1k 3.3µ RF1 260k 12p F 38 VF 30k TE AMP 96k 42 30k TEO VC 26k RF3 96k VC VC F I-V AMP RE1 260k 12p 13k E RF2 VC → iF 6.8k 20.3k 40 EI VC → iE 39 VE VC E I-V AMP R1 Tracking system balance adjustment is performed by varying the resistance externally attached to EI pin. This external resistance sets combined feed back resistance of the T-configured E I-V AMP. F I-V AMP feedback resistance = RF1 + RF2 + E I-V AMP feedback resistance = RE1 + RE2 + RF1 × RF2 = 403kΩ RF3 RE1 × RE2 (Rx = R1//RE3) Rx Gain adjustment is performed by adjusting external variable resistor of TEO pin. – 15 – RE3 RE2 CXA1982Q Center Voltage Generation Circuit (Single voltage application; Connect to GND when it’s positive/negative dual power supplies.) Maximum current is approximately ±3mA. Output impedance is approximately 50Ω. Vcc 30k VC VC 48 50 APC Circuit When driving a constant current, the optical output by the laser diode possesses large negative temperature characteristics. Therefore, the current must be controlled with the monitor photo diode to ensure the output remains constant. Vcc 130k 60k 30k VEE 100k 34 PD 100µ /6.3V 2k 1k 33 LD 10µH 33k 15k 80k 8k 1SS149 27k 1.25V 4k 1µ/6.3V LD PD GND VEE – 16 – CXA1982Q Focus Servo FE 9k 51k FEO 10k 22k 2200p 3 0.47µ 1 2 FEI 100k FDFCT FGD 4 680k 40k 0.1µ ISET 120k 17 50k FS2 FLB 5 0.1µ FSET 11 510k 0.01µ SRCH 8 4.7µ FS1 11µ 22µ 50k FE_M 7 100k DFCT FS4 68k Focus 100k phase Compensation FE_O 6 FZC FOCUS COIL The above figure shows a block diagram of the focus servo. Ordinarily the FE signal is input to the focus phase compensation circuit through a 68kΩ resistance; however, when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal 100kΩ resistance and the capacitance connected to Pin 3. When this DFCT prevention circuit is not used, leave Pin 3 open. The defect switch operation can be enabled and disabled with command. The capacitor connected between Pin 5 and GND is a time constant to raise the low frequency in the normal playback state. The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510Ω is connected to Pin 11. The focus search height is approximately ±1.1Vp-p when using the constants indicated in the above figure. This height is inversely proportional to the resistance connected between Pin 17 and VEE. However, changing this resistance also changes the height of the track jump and sled kick as well. The FZC comparator inverted input is set to 15% of VCC and VC (Pin 48); (VCC – VC) × 15%. ∗ 510kΩ resistance is recommended for Pin 11. – 17 – CXA1982Q Tracking Sled Servo TE 42 TEO 43 NC SL_O 16 TEI 44 100k TDFCT 47 100k 680k 66p TM6 22µA DFCT TM1 680k TG1 SL_M 15 SLED MOTOR M 0.015µ 3.3µ 22µ 15k 0.47µ TM5 ATSC 45 1k 1k ATSC TM2 22µA 14 SL_P 0.047µ 470k 330k 47p 0.022µ 46 TZC TZC 9 TGU TG2 TG2 470k 100k TM4 11µA TM3 11µA 90k 82k TA_M 12 100k 20k 0.033µ 10 Tracking Phase Compensation 10k TA_O TM7 TRACKING COIL 13 FSET 11 510k 0.01µ The above figure shows a block diagram of the tracking and sled servo. The capacitor connected between Pins 9 and 10 is a time constant to decrease the high-frequency gain when TG2 is OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510kΩ resistance connected to Pin 11. In the CXA1782, TG1 and TG2 are inter-linked switches. To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be more specific, Track jump peak voltage = TM3 (or TM4) current × feedback resistance value The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15; Sled kick peak voltage = TM5 ( or TM6) current × feedback resistance The values of the current for each switch are determined by the resistance connected between Pin 17 and VEE. When this resistance is 120kΩ: TM3 ( or TM4) = ±11µA, and TM5 (or TM6) = ±22µA. As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the internal resistance (100kΩ) and the capacitance connected to Pin 47. – 18 – 120k 8.2k CXA1982Q Focus OK Circuit RF DEFECT RF_O C5 0.01µ RF_I 31 ×1 VCC 20k 54k VG 15k 92k 0.625V 25 FOK 30 FOCUS OK AMP FOCUS OK COMPARATOR The focus OK circuit creates the timing window okaying the focus servo from the focus search state. The HPF output is obtained at Pin 30 from Pin 31 (RF signal), and the LPF output (opposite phase) of the focus OK amplifier output is also obtained. The focus OK output reverses when VRFI – VRFO ≈ –0.37V. Note that, C5 determines the time constant of the HPF for the mirror circuit and the LPF of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01µF selected, the fc is equal to 1kHz, and block error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented. DEFECT Circuit After inversion, RF O signal is bottom held by means of the long and short time constants. The long timeconstant bottom hold keeps the mirror level prior to the defect. The short time-constant bottom hold responds to a disc mirror defect in excess of 0.1msec, and this is differentiated and level-shifted through the AC coupling circuit. The long and short time-constant signals are compared to generate at mirror defect detection signal. 0.033µ CC1 RF FOK RF_O 31 a ×2 CC2 26 27 b c d e 24 SENS DEFECT AMP DEFECT SW 28 CB 0.01µ DEFECT BOTTOM HOLD DEFECT COMPARATOR a RFO b DEFECT AMP c BOTTOM HOLD (1) solid line CC1 H DEFECT L d BOTTOM HOLD (2) dotted line CC2 e – 19 – CXA1982Q Mirror Circuit The mirror circuit performs peak and bottom hold after the RFI signal has been amplified. The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation. FOK DEFECT RF_O 31 RF MIRROR HOLD AMP 0.033µ 29 30 RF_I ×1.4 G MIRROR AMP PEAK & BOTTOM HOLD H ×1 CP J K I 20k MIRROR COMPARATOR LOGIC RF_O 0V G (RF_I) 0V H (PEAK HOLD) 0V I (BOTTOM HOLD) J K (MIRROR HOLD) 0V MIRR H L The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time constant must be sufficiently large compared with the traverse signal. In the CXA1982Q, this mirror output is used only during braking operations, and no external output pin is attached. Accordingly, when connecting DSP such as the CXD2500 with MIRR input pin, input the C. OUT output to the MIRR input of the DSP. – 20 – CXA1982Q Commands The input data to operate this IC is configured as 8-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F. Commands for the CXA1982Q can be broadly divided into four groups ranging in value from $0X to $2X. 1. $0X (“FZC” at SENS pin (Pin 24)) These commands are related to focus servo control. The bit configuration is as shown below. D7 0 D6 0 D5 0 D4 0 D3 FS4 D2 DEFECT D1 FS2 D0 FS1 Four focus-servo related switches exist: FS1, FS2, FS4, and DEFECT corresponding to D0 to D3, respectively. $00 $02 When FS1 = 0, Pin 8 is charged to (22µA – 11µA) × 50kΩ = 0.55V. If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 6 becomes 0V. From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output to Pin 6. This voltage level is obtained by equation 1 below. (22µA – 11µA) × 50kΩ × $03 resistance between Pins 6 and 7 50kΩ .... Equation 1 From the state described above, FS1 becomes 1, and a current source of +22µA is split off. Then, a CR charge/discharge circuit is formed, and the voltage at Pin 8 decreases with the time as shown in Fig. 1 below. 0V Fig. 1. Voltage at Pin 8 when FS1 gose from 0 → 1 This time constant is obtained with the 50kΩ resistance and an external capacitor. By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2) 0V $ 00 02 03 02 03 02 00 Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 6) $04 When the fact that the RF signal is missing is detected and the scratches on the disc are detected with DEFECT = 0, DFCT (FS3) is turned ON. – 21 – CXA1982Q 1-1. FS4 This switch is provided between the focus error input (Pin 2) and the focus phase compensation, and is in charge of turning the focus servo ON and OFF. $00 → $08 Focus OFF ← Focus ON 1-2. Procedure of focus activation For description, suppose that the polarity is as described below. a) The lens is searching the disc from far to near; b) The output voltage (Pin 6) is changing from negative to positive; and c) The focus S-curve is varying as shown below. A t Fig. 3. S-curve The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and the turning the focus servo switch ON are performed during the focus S-curve transits the point A indicated in Fig. 3. To prevent misoperation, this signal is ANDed with the focus OK signal. In this IC, FZC (Focus Zero Cross) signal is output from the SENS pin (Pin 24) as the point A transit signal. In addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case). Following the line of the above description, focusing can be well obtained by observing the following timing chart. (20ms) (200ms) $02 ($00) $03 $08 Drive voltage ∗ The broken lines in the figure Focus error indicate the voltage assuming the signal is not in focus. SENS pin (FZC) The instant the signal is brought into focus. Focus OK Fig. 4. Focus ON timing chart – 22 – CXA1982Q Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be minimized. To do this, the software sequence shown in B is better than the sequence shown in A. FZC ↓ ? YES NO Transfer $08 F. OK ? YES Transfer $08 F. OK ? NO YES FZC ↓ ? YES NO NO Latch Latch (A) (B) Fig. 5. Poor and good software command sequences 1-3. SENS pin (Pin 24) The output of the SENS pin differs depending on the input data as shown below. $0X: FZC $1X: DEFECT $2X: TZC $3X: PROHIBITED $4X to 7X: HIGH-Z 2. $1X (“DEFECT” at SENS pin (Pin 24)) These commands deal with switching TG1/TG2, brake circuit ON/OFF, and the sled kick output. The bit configuration is as follows Sled kick height Relative D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 value (PS1) (PS0) 0 0 0 1 TG1, TG2 Break Sled kick ±1 0 0 circuit height ±2 0 1 ON/OFF ON/OFF ±3 1 0 ±4 1 1 TG1, TG2 The purpose of these switches is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked switches. The brake circuit (TM7) is to prevent the occurrence of such frequently occurring phenomena as extremely degraded actuator settling due to the servo motor exceeding the linear range causing what should be a 100-track jump to fall back down to a 10-track jump after a 100 or 10-track jump has been performed. To do this, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope and the tracking error is 180˚out-of-phase to cut the unneeded portion of the tracking error and apply braking. – 23 – CXA1982Q [∗A] RF_I 30 Tracking error (TZC) 46 Envelope Detection [∗B] Waveform Shaping D2 (MIRR) [∗C] [∗F] (Latch) [∗G] BRK TM7 Low: open High: make DQ CK [∗D] Waveform Shaping [∗E] Edge Detection CXA1982Q Fig. 6. TMI movement during braking operation From inner to outer track [∗A] [∗B] [∗C] [∗D] From outer to inner track (“MIRR”) (“TZC”) [∗E] [∗F] [∗G] [∗H] Braking is applied from here. 0V Fig. 7. Internal waveform 3. $2X (“TZC” at SENS pin (Pin 24)) These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse and fast forward pulse during access operations. D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 Tracking control 00: OFF 01: Servo ON 10: F-JUMP 11: R-JUMP ↓ TM1, TM3, TM4 Sled control 00: OFF 01: Servo ON 10: F-FAST FORWARD 11: R-FAST FORWARD ↓ TM2, TM5, TM6 – 24 – CXA1982Q CPU Serial Interface Timing Chart DATA D0 tWCK CLK 1/fck tD XLT tWL tCD D1 D2 tWCK D3 tSU D4 th D5 D6 D7 D0 (VCC = 3.0V) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width Data transfer interval Symbol fck fwck 500 500 500 500 1000 1000 Min. Type. Max. 1 Unit MHz ns ns ns ns ns ns tsu th tD tWL tCD System Control ADRESS Item D7 D6 D5 D4 0 0 0 D3 D2 DATA D1 D0 SENS output Focus Control FS4 FS1 DEFECT (FS3) FS2 0 Focus Search Disable = 1 Search ON = 1, OFF = 0 Enable = 0 ON = 1, OFF = 0 Up = 1, Down = 0 TG1, TG2 Brake Sled ON = 1, OFF = 0 ON = 1, OFF = 0 Kick + 2 0 Tracking Mode ∗1 Sled Mode ∗2 1 1 Prohibited Sled Kick + 1 FZC DEFECT TZC — Tracking Control 0 Tracking Mode 0 Select 0 0 0 0 0 1 1 ∗1 TRACKING MODE D3 OFF ON FWD JUMP REV JUMP 0 0 1 1 D2 0 1 0 1 ∗2 SLED MODE D1 OFF ON FWD MOVE REV MOVE 0 0 1 1 D0 0 1 0 1 – 25 – CXA1982Q Serial Data Truth Table Serial Data FOCUS CONTROL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F Hex FS4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Functions FS = 4321 DEFECT FS2 E E E E D D D D E E E E D D D D 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DEFECT E: enable D: disable TRACKING MODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Hex $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F TM = 6 5 4 3 2 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 – 26 – CXA1982Q Initial State (resetting state) ADDRESS Item Focus Control Tracking Control Tracking Mode Select DATA HEXADECIMAL 0 0 0 1 0 $00 $10 $20 $37 $38 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 The above data means the following operation modes. Focus Control Tracking Control Tracking Mode Focus off, Defect enable, Focus Search off, Focus Search down TG1 – TG2 off, Brake off, Sled Kick + 2 off, Sled Kick + 1 off Tracking off, Sled off – 27 – CXA1982Q Notes on Operation 1. FSET pin The FSET pin determines the fc for the focus and tracking high-frequency phase compensation. 2. ISET pin ISET current = 1.27V/R = Focus search current = Tracking jump current 1 = Sled kick current ($1X: PS1 = PS0 = 0) × 2 Use the setting resistance within the range of 120kΩ to 240kΩ. If the resistance value is out of this range, the oscillation may be occurred in the ISET block. 3. FE (focus error)/TE (tracking error) gain changing method 1) High gain: Resistance between FE pins (pins 6 and 7) 100kΩ → Large Resistance between TE pins (pins 12 and 13) 100kΩ → Large 2) Low gain: A signal, whose resistance is divided between Pins 1 and 2, is input to FE. The external variable resistor of TEO pin is used for TE. The anti-shock circuit always operates in the CXA1982Q so that TG1 and TG2 (address 1 : D3) should be set to 1 for tracking adjustment to prevent this effect. When the anti-shock function is not used, Pin 45 (ATSC) should be fixed to VC. 4. Input voltage at Pins 19 to 22 of the microcomputer interface should be as follows: VIH VCC × 90% or more VIL VCC × 10% or less 5. Focus OK circuit 1) Refer to the “Description of Operation” for the time constant setting of the focus OK amplifier LPF and the mirror amplifier HPF. 2) The equivalent circuit of the output pin (FOK) is as shown below. VCC 20k FOK 40k 100k VCC VEE VEE 25 RL The FOK and comparator output are as follows: Output voltage High: VFOKH ≈ near VCC Output voltage Low: VFOKL ≈ Vsat (NPN) – 28 – CXA1982Q 6. Sled amplifier The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB. Sled/Tracking internal phase compensation and reference design material Item FCS 1.2kHz gain 1.2kHz phase 1.2kHz gain TRK 1.2kHz phase 2.7kHz gain 2.7kHz phase 08 08 25 25 25→13 25→13 13 CTGU = 0.1µF SD Measurement pin 6 Conditions CFLB = 0.1µF CFGD = 0.1µF Typ. 21.5 63 13 –125 26.5 –130 Unit dB deg dB deg dB deg – 29 – CXA1982Q Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.4 12.0 – 0.1 + 0.1 0.15 – 0.05 36 25 0.15 37 24 48 13 + 0.2 0.1 – 0.1 1 + 0.15 0.3 – 0.1 12 0.8 ± 0.12 M + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 ∗QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g – 30 – 0.9 ± 0.2 13.5