CXA1998AQ

CXA1998AQ Recording/Playback Equalizer Amplifier For the availability of this product, please contact the sales office. Description The CXA1998AQ is an IC developed for analog signal processing in tape recorders. Processing for both the recording and playback systems is achieved on one chip. Features • 11-bit serial data interface • Recording/playback mute function • Recording equalizer Gp and Fp can be adjusted externally. • AGC (Automatic Gain Control) • Comparator for AMS (Automatic Music Sensor) • Recording/playback equalizer amplifier with 1.7 times speed switching Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VCC, VDD 12 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 645 mW Operating Conditions Supply voltage 48 pin QFP (Plastic) Structure Bipolar silicon monolithic IC Applications All analog signal processing in the cassette decks of tape recorders and compact music centers Applicable Head Applicable to MITSUMI ELECTRIC Co., Ltd. Playback head: BP-7442-CP-6973 Recording/playback head: BC-9242-CB-9267 VCC VDD 6.5 to 10.0 4.5 to 5.5 V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96802A78 CXA1998AQ Block Diagram and Pin Configuration (Top View) AGC OUT2 REC OUT2 AGC IN2 XRESET REC IN2 DGND GND DATA RFC Vcc 36 RFS 35 VG 34 33 32 31 30 29 28 27 26 25 24 LATCH VDD 23 VDD D1 GND D2 GND 10k 2.8V 40k AGC GAIN 19.5dB IREF 37 GND GND PB OUT2 38 IREF RECEQ CLK 210k PB FB22 39 PB FB12 40 22 M2 PBEQ CTL 21 M1 210k AGC OFF A EQ DECK A/B GND SHIFT REGISTERS GND D3 PB INB2 41 B EQ 20 PL2 LATCHES AGC GND D4 GND D5 GND D6 GND D9 RECEQ CTL PB INA2 42 PB INA1 43 19 PL1 SPEED 18 BPB GND PB INB1 44 17 BPA 16 SPEED 210k PB FB11 45 PB FB21 46 210k D8 MUTE 40k AGC GAIN 19.5dB D10 GND RECEQ D7 PB OUT1 47 2.8V GND AMS VDD GND 20k D9 D11 D11 GND 15 RMUTE 20k 20k GND 20k 14 RMUTEI VDD 1 2 3 4 5 6 7 8 9 GND GND FP CAL 48 10k 13 PBMUTE 10 11 12 REC IN1 AGC OUT1 REC OUT1 AMS GAIN AMS GND AGC IN1 AMS TC A EQ GP CAL B EQ –2– AMS OUT AGC TC CXA1998AQ Pin Description Pin No. Symbol DC voltage I/O I/O resistance (Ta = 25°C, VCC = 8V, VDD = 5V, no signal, RESET ON) Equivalent circuit Description Vcc Vcc 1 GP CAL 1.2V — — 1 ×2 30k 147 GND GND Connects a resistor for determining the high-band peak gain of recording equalizer. Reference setting resistance is 27kΩ. VCC VCC 147 2 A EQ — I — 2 Deck A equalizer switch. Low: 120µs EQ High: 70µs EQ GND GND VCC VCC 3 B EQ 2.5V (OPEN) 147 50k 5k I 53kΩ 3 5k Deck B equalizer switch. Low: NORMAL TAPE, 120µs EQ Medium: Cro2 TAPE, 70µs EQ High: METAL TAPE, 70µs EQ GND GND VCC ×2 ×2 200 500 ×2 500 5k 100k GND VCC 4 AGC TC 0.0V — — 4 147 ×4 200 Connects a resistor and capacitor for determining AGC attack/recovery time constants. GND –3– CXA1998AQ Pin No. Symbol DC voltage I/O I/O resistance VCC Equivalent circuit Description AGC signal input. Input resistance changes between 50kΩ and 100kΩ. AGC functions when the signal of –30dBm or more is input to AGC for AGC ON. (External 47µF//300kΩ for Pin 4) VCC 5 32 AGC IN1 AGC IN2 147 10k 4.0V I 50kΩ 5 32 40k ×4 VGS GND VCC VCC 147 23186 6 31 REC IN1 REC IN2 4.0V I 50kΩ 6 31 50k 1759 VGS VGS GND GND Recording equalizer input. VCC VCC ×2 147 7 30 AGC OUT1 AGC OUT2 7 4.0V O 147Ω 500 500 18752 30 ×4 107423 VGS AGC output. GND GND 9945 VGS VCC VCC ×3 500 40k ×2 500 5p 8 29 REC OUT1 REC OUT2 4.0V O 147Ω 8 29 147 × 10 Recording equalizer output. GND GND –4– CXA1998AQ Pin No. Symbol DC voltage I/O I/O resistance VCC Equivalent circuit Description VCC 10µ 9 AMS GAIN 3.5V — — 9 147 100k Connects a resistor for determining AMS signal detection level and a capacitor for determining HPF cutoff frequency. GND GND 10 AMS GND 0.0V — — 10 GND AMS block ground. Vcc Vcc Vcc 11 147 11 AMS TC 8.0V — — 1k Connects time constant for AMS detection. GND GND Vcc Vcc Vcc 12 AMS OUT 8.0V O — 12 10k AMS output. No signal detection: High Signal detection: Low GND GND –5– CXA1998AQ Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit VDD ×4 20k 20k VDD Description Connects a capacitor for setting time constant for playback mute ON/OFF switching. Connects a capacitor for setting time constant for recording mute ON/OFF switching. Output for recording mute ON/OFF switch control signal. Outputs D11 from Pin 26 (DATA). Output for recording/playback equalizer speed switch control signal. Outputs D9 from Pin 26 (DATA). Low: Normal Speed High: High Speed (1.7 times) Outputs D6 from Pin 26 (DATA). Outputs D5 from Pin 26 (DATA). 13 PBMUTE 5.0V — — 13 14 147 GND 14 RMUTE1 GND GND 15 RMUTE VDD VDD ×4 5k 5.0V 16 SPEED O — 15 16 ×4 GND GND 5k 20k 17 18 19 20 21 22 BPA BPB VDD VDD ×4 PL1 5.0V PL2 M1 M2 O — 17 18 19 20 21 22 GND ×4 GND 10k Outputs D4 from Pin 26 (DATA). Outputs D3 from Pin 26 (DATA). Outputs D2 from Pin 26 (DATA). Outputs D1 from Pin 26 (DATA). VDD 20k 23 VDD 5.0V — — 23 Power supply of serial data interface block. –6– CXA1998AQ Pin No. 24 Symbol DC voltage I/O I/O resistance Equivalent circuit Description Serial data interface latch input. Serial data interface reset input. Low: Reset. At this time serial data outputs (Pins 15 to 22) are all open (high). LATCH 25µA 2k 24 VDD 30k — 27 XRESET I — 27 ×4 GND 5p 10.5k 30k GND VDD 25 CLK 4k 25 26 ×4 GND 25µA 30k Serial data interface clock input. — I — 30k 10.5k 26 DATA GND Serial data interface serial data input. 28 DGND 0.0V — — 28 GND Serial data interface block ground. 33 GND 0.0V — — 33 GND VCC 30k ×2 500 500 45k 30k GND GND ×4 VCC Ground. To each VGS ×2 34 VG 4.0V — 60kΩ 147 34 Signal reference voltage. Connects a capacitor for ripple rejection. 35 VCC 8.0V — — 35 VCC Power supply. –7– CXA1998AQ Pin No. Symbol DC voltage I/O I/O resistance VCC Equivalent circuit VCC ×3 ×3 36 147 × 250 Description 36 RFC 8.0V — — Connects a resistor and capacitor for obtaining stable voltage with power supply ripple rejected. To each RFS GND Vcc Vcc 37 IREF ×2 Connects a resistor (12kΩ) for determining equalizer gains. Connects a resistor for determining the highband peak frequency of recording equalizer. Reference setting resistance is 27kΩ. 1.2V 48 FP CAL — — 37 GND GND 5p 48 147 Vcc ×3 500 Vcc 38 47 PB OUT2 PB OUT1 2.8V O 147Ω 38 47 147 500 ×6 15p GND Playback equalizer output. GND VCC 2k ×4 RFS 2k ×4 39 46 PB FB22 PB FB21 147 2.8V — — 39 46 7k ×3 ×3 Connects a capacitor for determining playback equalizer time constants, such as 120µs and 70µs. GND GND GND –8– CXA1998AQ Pin No. Symbol DC voltage I/O I/O resistance Equivalent circuit Description VCC VCC 5k 10k VCC RFS VCC 40 45 PB FB12 PB FB11 1.4V — 105kΩ Playback equalizer negative feedback. 1k 41 42 147 70k 43 44 ×6 30p ×6 210k 1k ×2 210k 10p 147 40 45 41 42 43 44 PB INB2 PB INA2 PB INA1 PB INB1 0.0V I 70kΩ Playback equalizer input. GND GND GND Note) • AMS GND (Pin 10), DGND (Pin 28) and GND (Pin 33) are each independent in the IC and are not connected. Be sure tp ground each of the ground pins listed above. • The resistance of open collector outputs (Pins 15 to 22) can be connected Vcc. –9– CXA1998AQ Electrical Characteristics (Ta = 25°C, VCC = 8.0V, VDD = 5.0V, refer to Electrical Characteristics Measurement Circuit) Item Operating voltage Current consumption AGC ON output level AGC AGC ON channel balance AGC ON distortion AGC OFF output level AMS No signal detection threshold level 120µs – NS frequency response 120µs – NS frequency response Playback equalizer amplifier block 70µs – NS frequency response 120µs – HS frequency response 70µs – HS frequency response Signal handling Total harmonic distortion S/N ratio Output offset voltage Playback mute characteristics VCC VDD Sum of VCC and VDD pin currents NORM – NS, no signal Pin 4 external R300kΩ//C47µF f = 1kHz, Vin = –25dBm Pin 4 external R300kΩ//C47µF f = 1kHz, Vin = –25dBm Pin 4 external R300kΩ//C47µF f = 1kHz, Vin = 0dBm Pin 4 external R300kΩ//C 47µF f = 1kHz, Vin = –25dBm Pin 9 external R9.1kΩ, C0.015µF Pin 11 external R100kΩ//C0.1µF f = 5kHz, 0dB = –21dBm (at PBEQ reference output level) f = 315Hz, Vin = –70dBm Reference for frequency response f = 2.7kHz, Vin = –58.5dBm at 120µs – NS, 315Hz f = 4.5kHz, Vin = –53.8dBm at 120µs – NS, 315Hz f = 5.3kHz, Vin = –52.5dBm at 120µs – NS, 315Hz f = 9.1kHz, Vin = –47.8dBm at 120µs – NS, 315Hz 120µs – NS, RL = 2.7kΩ f = 1kHz, THD + N = 1% 120µs – NS, RL = 2.7kΩ f = 1kHz, Vin = –56.4dBm 120µs – NS, Rg = 470Ω “A” weighting filter 120µs – NS, Rg = 470Ω, playback mute OFF 120µs – NS, f = 1kHz, Vin = –51.4dBm Measurement conditions Min. 6.5 4.5 13.5 –13.0 –2.0 — –7.5 Typ. 8.0 5.0 19.7 –11.0 0.0 0.3 –5.5 Max. 10.0 5.5 25.0 –9.0 2.0 1.5 –3.5 Unit V V mA dBm dB % dBm –11.5 –8.2 — dB –23.0 –0.1 –0.1 1.8 2.1 –10.0 — 55.0 2.4 — –21.0 1.3 1.7 3.0 3.6 –6.0 0.3 62.0 2.7 –100 –19.0 2.9 2.9 dBm dB 4.8 5.1 — 0.7 — 3.2 –80 dBm % dB V dB – 10 – CXA1998AQ Item Reference input level Reference output level Channel balance NORM – NS frequency response NORM – NS frequency response NORM – NS frequency response CrO2 – NS frequency response CrO2 – NS frequency response Recording equalizer amplifier block CrO2 – NS frequency response METAL – NS frequency response METAL – NS frequency response METAL – NS frequency response NORM – HS frequency response NORM – HS frequency response NORM – HS frequency response CrO2 – HS frequency response CrO2 – HS frequency response CrO2 – HS frequency response METAL – HS frequency response METAL – HS frequency response METAL – HS frequency response Measurement conditions NORM – NS, 315Hz, input level at which reference output can be obtained NORM – NS, 315Hz NORM – NS, 315Hz, output level difference 1ch-2ch for –26.7dBm input f = 3kHz at NORM – NS, 315Hz, reference output –20dB f = 8kHz at NORM – NS, 315Hz, reference output –20dB f = 12kHz at NORM – NS, 315Hz, reference output –20dB f = 3kHz at NORM – NS, 315Hz, reference output –20dB f = 8kHz at NORM – NS, 315Hz, reference output –20dB f = 12kHz at NORM – NS, 315Hz, reference output –20dB f = 3kHz at NORM – NS, 315Hz, reference output –20dB f = 8kHz at NORM – NS, 315Hz, reference output –20dB f = 12kHz at NORM – NS, 315Hz, reference output –20dB f = 5kHz at NORM – NS, 315Hz, reference output –20dB f = 15kHz at NORM – NS, 315Hz, reference output –20dB f = 20kHz at NORM – NS, 315Hz, reference output –20dB f = 5kHz at NORM – NS, 315Hz, reference output –20dB f = 15kHz at NORM – NS, 315Hz, reference output –20dB f = 20kHz at NORM – NS, 315Hz, reference output –20dB f = 5kHz at NORM – NS, 315Hz, reference output –20dB f = 15kHz at NORM – NS, 315Hz, reference output –20dB f = 20kHz at NORM – NS, 315Hz, reference output –20dB Min. –28.2 — –1.5 –1.8 3.4 8.7 3.7 9.9 14.8 4.7 8.7 12.9 –1.6 7.6 11.9 5.2 14.1 16.7 6.8 13.7 16.9 Typ. –26.7 –10.0 0.0 –0.6 5.2 11.7 4.9 11.4 17.6 5.9 10.2 15.2 0.2 9.7 14.9 6.4 16.2 19.7 8.0 15.5 19.4 Max. –25.2 — 1.5 0.6 7.0 14.7 6.1 12.9 20.4 7.1 11.7 17.5 2.2 11.8 17.4 7.6 18.3 22.7 9.2 17.3 21.9 Unit dBm dB – 11 – CXA1998AQ Item Recording equalizer amplifier block Measurement conditions NORM – NS, RL = 2.7kΩ f = 1kHz, THD + N = 1% NORM – NS, RL = 2.7kΩ f = 1kHz, 0dB NORM – NS, Rg = 5.1kΩ “A” weighting filter NORM – NS NORM – NS, f = 1kHz 8dB A-EQ (Pin 2) A-EQ (Pin 2) B-EQ (Pin 3) B-EQ (Pin 3) B-EQ (Pin 3) Min. 8.0 — 57.0 3.6 — 0.0 2.5 0.0 2.2 4.2 Typ. 8.8 0.2 60.6 4.0 –100 — — — — — Max. — 0.5 — 4.4 –80 0.5 VCC 0.5 2.8 VCC Unit dB % dB V dB Signal handling Total harmonic distortion S/N ratio Output offset voltage Recording mute characteristics Control voltage low level 1 Control voltage high level 1 Control voltage low level 2 Control voltage medium level 1 Control voltage high level 2 V Note) NORM – NS: NORMAL TAPE – NORMAL SPEED NORM – HS: NORMAL TAPE – HIGH SPEED CrO2 – NS: CrO2 TAPE – NORMAL SPEED CrO2 – HS: CrO2 TAPE – HIGH SPEED METAL – NS: METAL TAPE – NORMAL SPEED METAL – HS: METAL TAPE – HIGH SPEED 120µs – NS: EQ = 120µs – NORMAL SPEED 120µs – HS: EQ = 120µs – HIGH SPEED 70µs – NS: EQ = 70µs – NORMAL SPEED 70µs – HS: EQ = 70µs – HIGH SPEED – 12 – CXA1998AQ Item Low level input voltage High level input voltage Low level output voltage High level output off leak current VIL Measurement conditions (LATCH/CLK/DATA/XRESET) (Pins 24, 25, 26, 27) Min. 0.0 3.5 0.0 Typ. — — — Max. 1.5 VDD 0.5 Unit VIH (LATCH/CLK/DATA/XRESET) (Pins 24, 25, 26, 27) VOL, IOL = 2mA (max) (Pins 15, 16, 17, 18, 19, 20, 21, 22) IOZ Leak current which flows to the output pin when IOZ output is open; applied voltage is 10V. (Pins 15 to 22) (1) fCK (2) tWC (3) tWR (4) tSDK (DATA → CLK) (5) tHCD (CLK → DATA) (6) tWD (7) tSLD (LATCH → DATA) (8) tHCL (CLK → LATCH) (9) tHLC (LATCH → CLK) V — — 1.0 µA 11-bit serial data interface block Maximum clock frequency Minimum clock pulse width Minimum reset pulse width Minimum data setup time Minimum data hold time Minimum data pulse width Minimum latch setup time Minimum latch hold time Minimum clock hold time 500 — — — — — — — — — — — — — — — — — — 1.0 1.0 1.0 1.0 kHz µs 2.0 1.0 1.0 1.0 Note) • VDD is CPU supply voltage of 5.0V. • VCC is 10.0V for high level output off-leak current. • The threshold levels of low level input voltage and high level input voltage depend on VDD. Input level detection is done by comparison with VDD/2. (Refer to “Equivalent circuit” of Pin Description.) – 13 – CXA1998AQ Timing Chart for 11-bit Serial Data Interface (VDD = 5.0V) tWC 3.5V CLK 1.5V tSDK 3.5V DATA 1.5V tSLD D1 D2 tHCD tWD tWC LATCH 1.5V 3.5V CLK tHCL tHLC DATA D10 D11 3.5V LATCH 1.5V XRESET 1.5V tWR – 14 – S11A S11B S16 100 R41 R52 10k S21A R64 10k R72 47k R81 R76 390k 100 S21B 100 S27A R84 8V S25A C17 C18 C24 0.1µ R79 10k 47µ/25V C15 R69 5.1k 4.7k R5B C26 C28 C22 C30 0.47µ/50V 0.47µ/50V 4.7µ/25V 2.2µ/25V 1k S15 S55 CHARGE2 36 34 29 DGND DATA CLK LATCH 24 25 VG GND 33 30 28 27 26 31 RFC Vcc 35 32 12k S12A R39 C12 5V 5V AGC OUT2 REC OUT2 37 IREF AGC IN2 REC IN2 XRESET R45 R61 10k CHARGE1 S23 R75 5.1k R86 2.7k R54 47µ/25V 47µ/25V S12D R89 10k S27B Electrical Characteristics Measurement Circuit DATA CLK XRESET LATCH S1A S1B AC INPUT ATT 2.7k 2.2µ/25V 38 PB OUT2 VDD 23 –40dB 39 PB FB22 S58A 2.2k M2 22 R103 R114 10k S36A R102 S58B 2.2k R113 10k S35A S36B C14 R37 4.7k 47µ/25V C4 470 C9 4.7µ/25V 1µ C3 470 C8 4.7µ/25V 1µ C2 470 C7 4.7µ/25V 1µ C1 470 C6 4.7µ/25V S9 1µ C5 R43 S14 100 C13 0.018µ R36 47µ/25V S8 R47 S7 R48 S6 R49 100 S13 R50 C10 R44 ATT 0.018µ S2A S2B 40 PB FB12 M1 21 S35B –29dB R35 S3A S3B 82k 41 PB INB2 PL2 20 S58C R101 2.2k R112 10k S34A S34B ATT R34 –17dB 42 PB INA2 82k PL1 19 S58D R100 2.2k R111 10k S33A S33B S4A S4B R33 ATT R30 600 R536 30dB AMP R42 100k A EQ B EQ AGC TC GP CAL AGC IN1 REC IN1 AGC OUT1 REC OUT1 AMS GAIN AMS GND AMS TC AMS OUT 10k C21 C25 C27 4.7µ/25V C29 2.2µ/25V R90 0.47µ/50V A EQ C16 0.1µ R59 B EQ 10k C19 0.1µ R63 0.47µ/25V 9.1k R92 C32 0.1µ R93 R56 27k S17 5.1k S18 S19 S20 S24 C20 5.1k 10k R85 47µ/25V R74 R78 2.7k R66 300k R68 C31 S25B 120µs 70µs NORM CrO2 METAL C23 0.1µ S12C 0.015µ 100k 100k 100 10k R83 100 R88 10k R94 10k S37 S22A R71 47k R73 390k S10A R40 S10B R51 CXA1998AQ 0.5V 2.5V 4.2V S22B R80 100 S26A S26B S28 – 15 – 43 PB INA1 44 PB INB1 45 PB FB11 4.7k 82k BPB 18 S58E R99 2.2k R98 R110 10k S32A S32B –9dB R32 S5A S5B 82k BPA 17 S58F S31B 2.2k R109 10k S31A + ATT TL072 – –6dB SPEED 16 S58G R97 2.2k R108 10k S30A S30B 46 PB FB21 RMUTE 15 S58H R96 2.2k R107 S29B S57A S12B R38 C11 S501 BUF 2.7k 2.2µ/25V 47 PB OUT1 RMUTEI 14 S56A C34 10k S29A R106 10k S53 GND S502 PBMUTE 13 S56B 0.1µ R105 C33 0.1µ S57B 10k S54 48 27k FP CAL AC OUTPUT S503 "A" Weighting Filter S504 Audio (22.2Hz – 22.2kHz) Filter 1 2 3 4 5 6 7 8 9 10 11 12 S505 1kHz Band Pass Filter (20dB) GND DC OUTPUT CXA1998AQ Application Circuit GND VCC GND GND GND 0.1µ GND 100µ 0.47µ 47µ 47µ 2.2µ 2.7k 4.7µ GND VDD GND GND GND 100k 10k AGC OUT2 AGC IN2 REC OUT2 DGND GND RFC DATA 820p 1k XRESET REC IN2 10k 36 GND RFS 35 VG 34 33 32 31 30 29 28 27 26 CLK Vcc GND 100k 2.2µ 25 LATCH 24 VDD 23 M2 D1 GND D2 22 M1 21 PL2 20 PL1 19 BPB 18 BPA 17 SPEED 16 RMUTE 15 RMUTEI 47k 14 0.1µ 20k 20k PBMUTE 13 22µ 12 GND GND 47k VDD 47k VDD 47k VDD 47k VDD 47k VDD 47k VDD 47k VDD VDD VDD 100k VDD 12mH 10k 150p 12k GND IREF 180p 2.8V GND 10k 2.2µ PB FB22 38 IREF 0.018µ 210k GND 47µ 100 AGC OFF A EQ DECK A/B 40 PBEQ CTL GND PB FB12 GND 210k 39 40k RECEQ PB OUT2 AGC GAIN 19.5dB 37 GND 100k VDD GND LATCHES R/P-HEAD DECK-B DECK-A PB-HEAD PB INA2 42 PB INA1 43 GND PB INB1 AGC REC PB B EQ 41 SHIFT REGISTERS PB INB2 GND D3 GND D4 GND D5 GND D6 GND D9 RECEQ CTL Bias OSC REC PB GND PB FB11 0.018µ 210k GND GND 47µ 100 45 PB FB21 46 PB OUT1 210k 44 SPEED 40k AGC GAIN 19.5dB RECEQ D7 GND 47 12mH 180p 2.8V 10k GND 2.2µ FP CAL 48 27k GND AMS VDD 20k 20k GND VDD GND 150p AGC OUT1 1 2 3 4 5 6 7 8 9 GND 10 11 AGC TC A EQ AGC IN1 0.47µ REC IN1 10k REC OUT1 2.2µ AMS GAIN AMS TC B EQ GND 10k 27k 3.3meg AMS GND AMS OUT 100k 0.1µ VCC GP CAL 820p 10k 2.2k 0.1µ 2.7k 4.7µ GND VCC GND 0.1µ GND GND VCC Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 16 – 100k 47µ GND D8 D10 D9 GND D11 MUTE D11 GND CXA1998AQ 1. System control mode Playback and recording equalizer (1) Playback equalizer (120µs/70µs) A-EQ (Pin 2) L DECK-AB (serial data D10 (Pin 25)) L H 120µs (DECK A) H 70µs (DECK A) L B-EQ (Pin 3) M/H According to A-EQ control 120µs (DECK B) 70µs (DECK B) According to B-EQ control (2) Playback mute (Pin 13) ON/OFF control is performed by 11-bit serial data interface D7 (Pin 26). A capacitor for setting the switching time constant is connected. Time constant = 20kΩ × C (3) Recording equalizer (Normal, CrO2, Metal) B-EQ (Pin 3) REC MODE L NORMAL (TYPE I) M CrO2 (TYPE II) H METAL (TYPE IV) (4) Recording mute (Pin 14) ON/OFF control is performed by 11-bit serial data interface D11 (Pin 26). A fader function is achieved using a time constant circuit formed with the external capacitor and incorporated 20kΩ resistor. (5) FP CAL (Pin 48) The standard resistor setting is 27kΩ, but when resistance value is larger, fo (Hz) is lower, and when resistance value is smaller, fo (Hz) is higher. (fo: high-band peak frequency) (6) GP CAL (Pin 1) The standard resistor setting is 27kΩ, but when resistance value is larger, high-band peak gain is larger, and when resistance value is smaller, high-band peak gain is smaller. – 17 – CXA1998AQ 2. 11-bit serial data interface CLK (Pin 25) DATA (Pin 26) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 LATCH (Pin 24) XRESET (Pin 27) • The DATA signal is taken in at the rising edge of the CLK signal. • The DATA signal is taken into the internal shift register when the LATCH signal is low. (Outputs (Pins 15 to 22) hold the previous value while the LATCH signal is low.) • The internal shift register data is latched and output in parallel at the rising edge of the LATCH signal. (Internal shift register data is loaded while the LATCH signal is high.) • The CLK signal of the 11th bit should fall after the LATCH signal rises. • Reset is done when the XRESET pin is low. (asynchronous method) Outputs (Pins 15 to 22) are all high (open) during reset. DATA (Pin 26) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Output Control signal M2 M1 PL2 PL1 BPB BPA PB MUTE AGC OFF SPEED DECK AB REC MUTE Output pin Pin 22 Pin 21 Pin 20 Pin 19 Pin 18 Pin 17 — — Pin 16 — Pin 15 Input set at low Low Low Low Low Low Low Low mute OFF AGC function stops Low, normal speed DECK A selected Low mute OFF Input set at high High (OPEN) High (OPEN) High (OPEN) High (OPEN) High (OPEN) High (OPEN) High mute ON AGC function operates High (open) 1.7 DECK B selected High (open) mute ON – 18 – CXA1998AQ • Make sure that VDD is 4.0V or more and XRESET is 1.5V or less, and 1µs or more when resetting by applying CR time constant to XRESET (Pin 27) and turning power ON. 4.0V or more VDD (Pin 23) XRESET (Pin 27) 1.5V or less 1µs or more A • XRESET (Pin 27) input level detection is done by comparison with VDD/2. The level should be VDD/2 > XRESET during the interval A. • For resetting with CPU when power is turned ON 4.0V or more VDD (Pin 23) 5.0V XRESET (Pin 27) 0V 1µs or more • Examples of AGC control during timer recording (1) Resets when power is turned ON (AGC function operates). (2) AGC is turned OFF after AGC inputs (Pins 5 and 32) rise. (External capacitor charge of AGC TC is discharged.) (3) AGC is turned ON and timer recording begins. – 19 – CXA1998AQ LATCH CLK DATA XRESET DGND 5V SW GND 100µ/25V GND C21 L R19 B0 9 VSS 8 1 10 A0 A < BOUT L 11 B1 A = BOUT 7 D7 LH L 10 6 15 QH H 100 VSS 9 14 Y3 VSS Y3 7 A3 6 74HC08 (2) B3 Y4 A4 B4 14 VDD C19 0.1µ B2 A2 Y1 B1 A1 5 Y2 8 7 Y2 9 6 10 B2 5 74HC00 11 A2 4 12 Y1 7 3 13 B1 2 A1 1 VSS A3 B3 Y4 A4 B4 VDD C20 0.1µ SERIAL XQH IN H 10 8 11 A 2 12 A1 A > BOUT 74HC85 13 A2 A > BIN 5 D6 LH D5 4 H 9 6 7 8 D2 4 LH L R18 3 H 100 19 4 14 B2 L 15 A3 2 H 8 16 VDD 1 C18 0.1µ B3 1 D4 H A = BIN A < BIN 3 11 13 D3 12 14 13 15 CLK2 2 CLK1 14 16 VDD S/XL C17 0.1µ Circuit Diagram for 11-bit Serial Data Transfer Evaluation Tool 5 9 R17 XA2 9 10 Y3 VSS B2 8 7 XQ2 7 8 R16 Q2 9 6 10 74HC74 (2) XPR2 5 11 CLK2 4 D2 3 XR2 2 VDD 1 C14 0.1µ XR1 D1 CLK1 XPR1 Q1 4 XQ1 6 XPR2 CLK2 12 D2 13 XR2 14 VDD C13 0.1µ Q2 VSS XQ2 VSS XQ1 Q1 74HC74 (4) XPR1 CLK1 D1 XR1 R/C2 7 11 A3 9 6 10 B3 5 12 11 Y4 4 12 A4 3 13 B4 2 14 VDD 1 C12 0.1µ R12 10k R11 10k C9 0.1µ C8 0.1µ Y2 B2 74HC08 (1) A2 Y1 B1 A1 XRES2 6 74HC123 12 11 5 R15 220 XQ2 13 Q1 4 14 C15 1000P C1 3 15 2 R14 220 R/C1 16 VDD 1 R13 2.2k C11 0.1µ C2 Q2 XQ1 XRES1 B1 XA1 LH LH L C16 4.7µ A 6 D14 5 H 74HC165 (1) D9 10 12 D13 4 LH D10 11 13 D12 3 H D11 12 14 13 15 CLK2 2 1 CLK1 14 16 VDD S/XL C10 0.1µ 16 Q1 2 9 R10 17 10 XQ2 8 Q2 9 10 VSS XQ1 XQ2 8 7 Q2 6 9 3 18 10 VSS XQ1 Y4 8 7 100 A4 6 9 10 Y3 6 VSS R9 220 CLOCK 7 11 RESET 74HC4040 12 VSS Q2 Q3 XLOAD 8 7 R8 220 6 VSS 9 10 ENA 1 ENA P 500kHz XPR2 R6 10k Q1 74HC74 (1) START 5 R5 10k XPR2 Q1 74HC74 (3) Y5 A3 Q9 8 5 Q4 1 11 RESET 5 OFF ON 12 ON 11 CLK2 XPR1 4 OFF 5 R4 220 74HC04 11 11 CLK2 12 XPR1 A5 4 12 Y2 4 DD 250kHz EXCLK 13 Q8 14 Q7 4 R7 220 R2 220 12 Q9 74HC161 DC 13 Q8 RESET D2 R3 10k 13 XR2 14 VDD C5 0.1µ CLK1 D1 XR1 D2 3 13 XR2 2 14 VDD 1 C4 0.1µ CLK1 D1 XR1 Y6 3 13 A6 2 14 VDD 1 C3 0.1µ A2 Y1 A1 Q10 3 C7 15P 15 Q11 2 16 VDD 1 4.4MHz R1 1M C6 15P C2 0.1µ Q5 Q6 Q12 3 DB 14 Q10 2 DA 15 Q11 CLOCK 1 16 VDD XRESET C 0.1µ EXCLK DGND 1 2 3 4 5 6 7 8 1 2 H D E 3 LH C F 4 LH B G 5 LH L D15 D8 – 20 – 7 13 100 68k VSS QH 8 VSS 9 SERIAL XQH IN 10 8 11 9 6 7 8 1 2 H D E 3 LH C F 4 LH B 74HC165 (2) D1 10 12 G 5 L Timing Chart for 11-bit Serial Data Transfer Evaluation Tool (1) CLK (2) CLK (3) START PULSE (4) (5) (6) = (4) (7) S/L (8) CLK GATE CONT. CLOCK STOP (9) – 21 – Dummy D1 D2 D3 D4 D5 D6 D7 D8 (10) H when A = B COUNT RESET 2µs (11) HC123 (12) (13) (14) RESET/CLOCK STOP and COUNT RESET (15) DATA HC165 D9 D10 D11 (16) CLK (17) = (8) (18) (19) LATCH CXA1998AQ The numbers (1) to (19) correspond to those of test pins for the 11-bit serial data transfer evaluation tool circuit. CXA1998AQ 3. AMS (1) AMS output logic Detection status AMS OUT (Pin 12) Signal detection Low No signal detection High AMS OUT (Pin 12) is an open collector output pin. When a 3.9 kΩ resistor is connected to VCC = 8V: Low: approximately 0.5V (IOL = 2mA (max.)) High: 8V Fig. 1 shows the AMS block diagram. PB OUT1 Inside IC 20k SA LPF HPF DET 100k AMS OUT 11 AMS TC AMS GND 20k 25kHz AMS GAIN 9 12 10 PB OUT2 R1 C1 R2 GND VCC VCC C2 R3 VCC GND Fig. 1. AMS Block Diagram Fig. 2 shows the frequency response of the signal output from HPF. fC G GAIN (dB) 10 1kHz f (Hz) 25kHz 100kHz Fig. 2. Frequency Response – 22 – CXA1998AQ (2) AMS level setting The AMS level is set by adjusting HPF gain and cut-off frequency with the external resistor and capacitor at Pin 9. G and fc in Fig. 2 are obtained from the following formula. G = 20log (1 + 100k/R1) [dB] (1) fc = 1 / (2 · π · C1 · R1) [Hz] Full-wave rectifier is applied for the signal at DET. Signal detection time is set by the time constant of Pin 11 external resistor and capacitor. DET signal detection level: = –7.5dBm (typ.) = playback equalizer reference output level + AMS level + HPF gain (2) Playback equalizer reference output level of –21dBm is 0dB. Ex.) To set AMS level at –25dB, determine and set the constant for Pin 9 external resistor. (Calculate assuming PBOUT1 = PBOUT2) First, get the required HPF gain from formula (2). –7.5dBm = –21dBm + (–25dB) + HPFgain, so HPF gain = 38.5dB. Next, get Pin 9 external resistance from formula (1). 38.5dB = 20log (1 + 100k / R1), so R1 ≈ 1.2kΩ, and external resistance is 1.2kΩ. – 23 – CXA1998AQ Example of Representative Characteristics Quiescent current consumption vs. Supply voltage 25 24 23 22 21 20 19 18 17 16 15 6 7 8 9 10 11 ICC is the sum of the VCC and VDD currents. VDD = 5.0V Quiescent current consumption [mA] VCC – Supply voltage [V] VCC = 8V Playback equalizer frequency response 65 60 55 10µF PB IN PB FB1 PB FB2 PB OUT 100 0.018µ 47µ GAIN [dB] 50 45 40 35 30 25 20 50 100 200 500 1k 2k 5k 10k 20k 120µs – NS 120µs – HS 70µs – NS 70µs – HS 50k Frequency [Hz] – 24 – 470 M 2.2µ CXA1998AQ Recording equalizer frequency response 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 20 VCC = 8V 0dB = NORM – NS, 315Hz, –30dBm (TAPE) (SPEED) NORM – NS CrO2 – NS METAL– NS Output response [dB] 50 100 200 500 1k 2k 5k 10k 20k 50k Frequency [Hz] Recording equalizer frequency response 28 26 VCC = 8V 0dB = NORM – NS, 315Hz, –30dBm 24 (TAPE) (SPEED) 22 NORM – NS CrO2 – NS 20 METAL– NS 18 16 14 12 10 8 6 4 2 0 20 50 100 200 500 1k 2k 5k 10k 20k 50k Output response [dB] Frequency [Hz] – 25 – CXA1998AQ VCC = 8V 120µs – NS AMS OUT 8V 0dB = –21dBm, 315Hz (playback equalizer reference output level) AMS input level (playback equalizer output level) [dB] AMS quiescent detection level frequency response 30 25 20 15 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 A : 0.015µ 9.1k B : 0.1µ 1k AMS GAIN A 9 11 AMS TC 12 AMS OUT 100k to 8V A: Pin 9 R9.1k C0.015µ B: Pin 9 R1k C0.1µ B 20 50 100 200 500 1k 2k 5k 10k 20k 50k Frequency [Hz] AGC output characteristics 10 AGC TC VCC = 8V 1kHz 5 4 AGC OFF Output level [dBm] 0 300k 47µ –5 –10 AGC ON –15 –35 –30 –25 –20 –15 –10 –5 Input level [dBm] – 26 – 0.1µ 100k CXA1998AQ Recording equalizer total harmonic distortion VCC = 8V NORM – NS RL = 2.7kΩ 1kHz 0dB = –10dBm 2.0 T.H.D + Noise [%] 1.0 0.5 0.2 0.1 –15 –10 –5 0 5 10 Output level [dBm] Playback equalizer total harmonic distortion VCC = 8V 120µs – NS RL = 2.7kΩ 1kHz 2.0 T.H.D + Noise [%] 1.0 0.5 0.2 0.1 –30 –25 –20 –15 –10 –5 Output level [dBm] – 27 – CXA1998AQ Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.4 12.0 – 0.1 + 0.1 0.15 – 0.05 36 25 0.15 37 24 48 13 + 0.2 0.1 – 0.1 1 + 0.15 0.3 – 0.1 12 0.8 ± 0.12 M + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 ∗QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 28 – 0.9 ± 0.2 13.5