CXA2027

CXA2027Q Analog signal processor IC For the availability of this product, please contact the sales office. Description The CXA2027Q is an analog signal processor for CCD linear image sensor output signal. This device is suitable for 3 lines of full-color CCD linear image sensor (ILX516K/ILX518K/ILX520K: 3648 pixels × 3 lines/5363 pixels × 3 lines/7078 pixels × 3 lines). This device has a built-in sample-and-hold, clamp, multiplex, gain control amplifier circuits and can be connected directly with external AD converters. (Sony’s CXD2311AR, CXD1175AM or CXA1977R are recommended as AD converters.) Features • Sample-and-hold circuit • Pixel-clamp and line-clamp circuit • Multiplex circuit • ADC driver circuit • Gain control amplifier circuit • Offset control circuit • Clock frequency: 1.5 to 6MHz (after multiplex) Applications Color image scanner Structure Bipolar silicon monolithic IC 48 pin QFP (Plastic) Absolute Maximum Ratings –0.3 to 7 V • Supply voltage VCC • Input voltage VI –0.3 to VCC + 0.3 V • Output voltage VO –0.3 to VCC + 0.3 V • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 640 mW Operating Conditions (Typ. in parentheses) • Supply voltage VCC 4.75 to 5.25 (5.0) V • Digital input voltage High VIH 3.5 to VCC (VCC) V • Digital input voltage Low VIL 0 to 0.8 (0) V • Operating temperature Topr 0 to +70 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95210A78 CXA2027Q Block Diagram and Pin Configuration MPX2 G-IN BUF MPX1 R-IN TD3 TD1 CLP TD2 TD5 26 36 B-IN 37 35 34 33 32 31 30 29 28 27 25 24 TD4 23 LCLP LPR 38 GCA LPG LPB D4-0 VCCA D4-1 39 40 41 42 43 S/H S/H GCA TD6 22 GC 21 VCCP 20 SIGOUT 19 GND 18 VRT 17 VRB 16 CLPC 15 LD4 14 LD3 13 LD2 12 SH S/H GCA DC shift Driver VREF D4-2 44 D4-3 45 D4-4 46 D/A GCA LOG D/A LATCH LOG D/A LATCH LOG D/A LATCH VCCD 47 D5-0 48 D/A D/A 1 2 3 4 5 6 7 8 9 10 11 D5-1 D6-1 D6-4 D5-4 D6-2 D5-2 D6-0 D6-3 D6-5 D5-3 –2– LD0 LD1 CXA2027Q Pin Description Pin Symbol (I/O) No. Typical pin voltage Equivalent circuit DC AC 5-bit data input pin 1 for G channel pixel clamp voltage adjustment (LSB) 5-bit data input pin 2 for G channel pixel clamp voltage adjustment 5-bit data input pin 3 for G channel pixel clamp voltage adjustment 5-bit data input pin 4 for G channel pixel clamp voltage adjustment 5-bit data input pin 5 for G channel pixel clamp voltage adjustment (MSB) 5-bit data input pin 1 for B channel pixel clamp voltage adjustment (LSB) 5-bit data input pin 2 for B channel pixel clamp voltage adjustment 5-bit data input pin 3 for B channel pixel clamp voltage adjustment 5-bit data input pin 4 for B channel pixel clamp voltage adjustment 5-bit data input pin 5 for B channel pixel clamp voltage adjustment (MSB) 6-bit data input pin 1 for SIGOUT output line clamp voltage adjustment (LSB) 6-bit data input pin 2 for SIGOUT output line clamp voltage adjustment 1.8V Description 48 D5-0 (I) 1 D5-1 (I) 2 D5-2 (I) 3 D5-3 (I) VCCD VCCD 4 D5-4 (I) Lo: 0 to 0.8V Hi: 3.5 to 5V 48 129 1.5k 1.8V 41 D4-0 (I) 100µ 43 D4-1 (I) 44 D4-2 (I) 45 D4-3 (I) 46 D4-4 (I) 5 D6-0 (I) 6 D6-1 (I) VCCD VCCD 7 D6-2 (I) Lo: 0 to 0.8V Hi: 3.5 to 5V 5 129 1k 6-bit data input pin 3 for SIGOUT output line clamp voltage adjustment 6-bit data input pin 4 for SIGOUT output line clamp voltage adjustment 6-bit data input pin 5 for SIGOUT output line clamp voltage adjustment 6-bit data input pin 6 for SIGOUT output line clamp voltage adjustment (MSB) 8 D6-3 (I) 100µ 9 D6-4 (I) 10 D6-5 (I) –3– CXA2027Q Pin Symbol (I/O) No. 11 LD0 (I) Typical pin voltage Equivalent circuit DC AC 5-bit data input pin 1 for pre-stage GCA gain adjustment (LSB) VCCD VCCD Description 12 LD1 (I) Lo: 0 to 0.8V Hi: 3.5 to 5V 20k 11 129 1.5k 5-bit data input pin 2 for pre-stage GCA gain adjustment 5-bit data input pin 3 for pre-stage GCA gain adjustment 5-bit data input pin 4 for pre-stage GCA gain adjustment 5-bit data input pin 5 for pre-stage GCA gain adjustment (MSB) 13 LD2 (I) 14 LD3 (I) 15 LD4 (I) VCCA VCCA 1.5k 16 CLPC Approx. 3.1V 16 129 Additional capacitance pin for line clamp. Add 0.47µF between this pin and GND. 6.7µ VCCA 6k 17 VCCA 2.0V 3k 2k VCCA VCCA 100µ 100µ 17 VRB (O) 2.0V Output pin for AD converter reference voltage VRB 100µ 1k 75µ VCCA VCCA 187.5 VCCA 2k 18 VRT (O) 4.0V 18 750 Output pin for AD converter reference voltage VRT 4k 100µ 19 GND 0V –4– GND pin CXA2027Q Pin Symbol (I/O) No. Typical pin voltage Equivalent circuit DC AC VCCA VCCA 21 100µ 1k 20 2mA Description 20 SIGOUT (O) 2.0V +MAX1.8V (2.0 to 3.8V) Signal output pin (to AD converter) 21 VCCP 5V VCCA VCCA 20k VCCA 100µ Power supply pin (for signal output system) 22 GC (I) 0 to 5V 129 22 4k 30k 1.5k Voltage input pin for poststage GCA gain adjustment (Can be open; in that case outputs 3V) Lo: 0 to 0.8V Hi: 3.5 to 5V 23 LCLP (I) VCCA VCCA 100µ Lo: clamp OFF Hi: clamp ON 1.5V 23 129 2k Line clamp pulse input pin (Apply high level during the optical black period of CCD output) 24 25 26 27 28 29 TD4 (O) 1.7 to 3.6V TD6 (O) 2.0 to 3.6V TD5 (O) TD1 (O) TD2 (O) TD3 (O) Lo: 0 to 0.8V Hi: 3.5 to 5V 1.7 to 3.6V 24 VCCA VCCA DA4 analog output test pin DA6 analog output test pin DA5 analog output test pin (Use with open) 129 126µ DA1 analog output test pin DA2 analog output test pin DA3 analog output test pin VCCA VCCA 250µ 30 CLP (I) 129 Lo: clamp OFF Hi: clamp ON 1.5V 1k 30 Pixel clamp pulse input pin (Apply high level during the precharge period of CCD output) VCCA VCCA 1.5k 31 MPX1 (I) Lo: 0 to 0.8V Hi: 3.5 to 5V 1.2V 31 129 100µ MPX channel switching pulse input pin 1 (See high/low table under Pin 32 in following section.) –5– CXA2027Q Pin Symbol (I/O) No. Typical pin voltage Equivalent circuit DC AC VCCA VCCA 130µ Description MPX channel switching pulse input pin 2. Pin 31 MPX1 L L H H Pin 32 MPX2 L H L H Pin 20 SIGOUT R channel G channel B channel B channel 32 MPX2 (I) Lo: 0 to 0.8V Hi: 3.5 to 5V 5k 2.4V 32 129 1.5k VCCA Lo: 0 to 0.8V Hi: 3.5 to 5V 1.5V 33 129 33 SH (I) 1m Lo: sample mode Hi: hold mode 1m 1.5V 1.5V 1m Sample-and-hold pulse input pin. (Apply low level during the effective signal period (refer to Note 1) of CCD output) VCCA VCCA 260µ 34 BUF (O) 2.4V +MAX1.8V (2.4 to 4.2V) 34 2k Output test pin after MPX (use with open) 35 R-IN (I) CCD effective signal level MAX1.5Vp-p (Note 1) VCCA VCCA 100µ 3.7V CCD signal R channel input pin CCD signal G channel input pin CCD signal B channel input pin 36 G-IN (I) 35 129 1µ 37 B-IN (I) –6– CXA2027Q Pin Symbol (I/O) No. Typical pin voltage Equivalent circuit DC AC Voltage input pin for setting R channel pre-stage GCA gain adjustment latch circuit to data input mode (high) or hold mode (low). Voltage input pin for setting G channel pre-stage GCA gain adjustment latch circuit to data input mode (high) or hold mode (low). Voltage input pin for setting B channel pre-stage GCA gain adjustment latch circuit to data input mode (high) or hold mode (low). 5V 5V Power supply pin (for analog, general system) Power supply pin (for DA converter system) Description 38 LPR (I) VCCD VCCD 39 Lo: 0 to 0.8V data hold LPG (I) Hi: 3.5 to 5V data input 1.5k 38 129 28k 40 LPB (I) 42 47 VCCA VCCD Note 1: Effective signal levels are defined as follows for CCD output signals. Reset level CCD output signal Precharge level Effective signal level Fig. 1 –7– CXA2027Q Description of Data Input Pin Polarity Pin name (Pin No.) CLP(30) Function Pixel clamp Input level High Low High Low MPX1 Low MPX1/MPX2 (31/32) Channel switching for R,G,B Low High High LPR/LPG/LPB (38/39/40) LD0 to LD4 (11/12/13/14/15) D4-0 to D4-4 (41/43/44/45/46) D5-0 to D5-4 (48/1/2/3/4) D6-0 to D6-5 (5/6/7/8/9/10) LCLP(23) Channel switching for pre-stage GCA gain data input Pre-stage GCA gain data B-IN clamp voltage adjustment G-IN clamp voltage adjustment Output DC voltage adjustment Line clamp High Low 11111 00000 11111 00000 11111 00000 111111 000000 High Low MPX2 Low High Low High Characteristics Clamp ON Clamp OFF Hold mode Sample mode Output R-ch G-ch B-ch B-ch Data input Data hold Maximum gain Minimum gain Maximum clamp voltage Minimum clamp voltage Maximum clamp voltage Minimum clamp voltage Maximum DC output voltage Minimum DC output voltage Clamp ON Clamp OFF LPR: for R-ch LPG: for G-ch LPB: for B-ch LD0: LSB LD4: MSB D4-0: LSB D4-4: MSB D5-0: LSB D5-4: MSB D6-0: LSB D6-5: MSB Others SH(33) Sample-and-hold –8– CXA2027Q Electrical Characteristics (See Electrical Characteristics Measurement Circuit.) No. Item Current consumption (1) Symbol Measurement conditions Pre and Post-stage GCA gain = maximum SW11 to 15 = b, SW16 = a, SW22-1 = b, SW22-2 = b, SW23 = a, SW31 to 32 = a, SW35-1 = a Pre and Post-stage GCA gain = minimum SW11 to 15 = a, SW16 = a, SW22-1 = b, SW22-2 = a, SW23 = a, SW31 to 32 = a, SW35-1 = a Min. (VCC = 5V, Ta = 25°C) Typ. Max. Unit 1 Icc1 44 60 78 mA 2 Current consumption (2) Digital input voltage High Digital input voltage Low VRB DC voltage VRT DC voltage Icc2 54 73 94 mA 3 4 5 6 7 Vih Vil Vrb Vrt VRB-VRT equivalent impedance 300Ω VRB-VRT equivalent impedance 300Ω VRB-VRT equivalent impedance 300Ω Minimum pre-stage GCA gain. Input (0.4V) and output (V20) ratio. SW11 to 15 = a, SW16 = a, SW22-1 = a, SW23 = a, SW35-1 = b, SW35-2 = a, SW31, 32 = (a, a) or (a, b) or (b, b) Maximum pre-stage GCA gain. Input (0.4V) and output (V20) ratio. SW11 to 15 = b, SW16 = a, SW22-1 = a, SW23 = a, SW35-1 = b, SW35-2 = a, SW31, 32 = (a, a) or (a, b) or (b, b) Minimum post-stage GCA gain. Input (0.4V) and output (V20) ratio. SW11 to 15 = a, SW16 = a, SW22-1 = b, SW22-2 = a, SW23 = a, SW35-1 = b, SW35-2 = a, SW31 to 32 = a Maximum post-stage GCA gain. Input (0.4V) and output (V20) ratio. SW11 to 15 = a, SW16 = a, SW22-1 = b, SW22-2 = b, SW23 = a, SW35-1 = b, SW35-2 = a, SW31 to 32 = a Difference between output value 1/2 level for input level Vx and output level for input level 1/2 Vx. Vx = 1.5V (SG35-2). See Note 2. SW11 to 15 = a, SW16 = b, SW22-1 = a, SW23 = b, SW31, 32 = (a, a) or (a, b) or (b, b), SW35-1 = b, SW35-2 = b Difference between output value 1/2 level for input level Vx and output level for input level 1/2 Vx. Vx = 0.3V (SG35-2). See Note 2. SW11 to 15 = a, SW16 = b, SW22-1 = a, SW23 = b, SW31, 32 = (a, a) or (a, b) or (b, b), SW35-1 = b, SW35-2 = b –9– 3.5 0 1.96 3.94 1.95 2.00 3.99 1.98 5 0.8 2.04 4.06 2.05 V V V V V VRT-VRB voltage Vtb 8 Pre-stage GCA gain min. Gfn –1.67 –0.25 +1.11 dB 9 Pre-stage GCA gain max. Gfx 11.77 13.92 16.03 dB 10 Post-stage GCA gain min. Grn –8.33 –6.92 –5.61 dB 11 Post-stage GCA gain max. Grx 3.55 5.24 7.12 dB 12 Output signal linearity 1 Lin1 –5 +5 % 13 Output signal linearity 2 Lin2 –5 +5 % CXA2027Q Electrical Characteristics Measurement Circuit SW polarity a b f = 1MHz 3.12VDC + 0.4Vp-p SG35-2 63.6µs 3.32V SG35-1 3.32V Vx 11.5µs 36 37 38 SW35-2 63.6µs 7µs SW35-1 SW32 SW31 5V 0V 30 29 28 27 26 25 24 23 GCA SW23 SW22-2 22 SW22-1 21 Driver 20 19 18 17 LOG LOG D/A LATCH LOG D/A LATCH 16 15 14 13 SW13 8 9 10 11 12 0.47µ SW16 1µ 1µ V18 35 34 33 32 31 SG23 39 40 47µ 41 5V 42 43 0.01µ S/H GCA S/H GCA DC shift 0.01µ V20 VREF S/H 44 45 46 47 48 0.01µ D/A GCA 300 V17 3.1V D/A LATCH SW15 SW14 D/A D/A SW11 Note 2: No. 12, 13 Input SG35-2 4µs Line clamp pulse SG23 SW12 1 2 3 4 5 6 7 Vx Output V20 V20 (Vx) Defined as: 1 V20 ( 2 Vx) V20 (Vx) × 1 2 –1 × 100 [%]. No. 12 Vx = 1.5V No. 13 Vx = 0.3V – 10 – CXA2027Q Pulse Timing [Pulse Timing 1 (pixel units)] CLP pulse and SH pulse Input the SH pulse at the end of the effective signal so as not to be affected by signal fluctuation caused by the clamp. SH pulse and MPX pulse (MPX1, MPX2) Input the SH pulse in sync with the reference channel. MPX1 pulse and MPX2 pulse Delay the timing of MPX2 when G changes to B. (Table 1, t3) Reset level CCD signal (R-IN/ G-IN/ B-IN) t4 Precharge level Effective signal level t1 CLP t2 SH 50% 50% tr = tf = 5ns MPX1 t3 MPX2 50% 50% SIGOUT t5 Data taken in at AD converter Output channel B R G B R Min. t1 t2 t3 t4 t5 Table 1 – 11 – 100ns 40ns 5ns 5ns Typ. Max. 50ns 20ns 60ns [Pulse Timing 2 (line units)] CCD signal (R-IN/ G-IN/ B-IN) Optical black Dummy signal 1-line output period LCLP t6 – 12 – Typ. Max. The LCLP pulse is recommended to be applied during the optical black period. CXA2027Q Min. t6 10µs Table 2 CXA2027Q [Pulse Timing 3 (latch data input)] Latch gate (LPR/LPG/LPB) t8 Input data (LD0 to LD4) t7 t9 t10 (input data decision time) Min. t7 t8 t9 t10 50ns 50ns 50ns 800ns Table 3 Typ. Max. – 13 – CXA2027Q Notes on Operation 1. Pre-stage GCA The gain characteristics is as given in page 16. As a guideline, the calculation formula is 0.5 × 1.05n [times] (n = 0 to 31: n is D/A converter input in decimal). 2. Post-stage GCA The gain characteristics is as given in page 16. When the GC pin is open, gain becomes approximately double. 3. Line clamp When the LCLP pulse (line clamp pulse) is made high during the optical black period of CCD output, output (Pin 20) is clamped approximately to VRB (= 2.0V) voltage. 4. Pixel clamp The pixel clamp function (at Pins 35, 36 and 37) requires large charging and discharging current through the capacitor, therefore, keep the ground area below the emitter follower as wide as possible. The distance between the input capacitor and input pin should also be as short as possible. 5. DC offset adjustment between channels There is a slight difference between clamp voltages (black level voltage) of different channels due to component scatterings within the IC. Correct the B and G channel DC levels relative to R channel using D4-0 to D4-4 and D5-0 to D5-4. The adjustment step for the input pins (Pins 36 and 37) is approximately 5mV/LSB. The standard settings are D4-0 to D4-3 = “L”, D4-4 = “H”, and D5-0 to D5-3 = “L”, D5-4 = “H”. 6. Output DC voltage adjustment Output (Pin 20) clamp voltage varies slightly due to variations within the IC. Adjust output clamp voltage using D6-0 to D6-5. The adjustment step is approximately 1mV/LSB. The standard settings are D6-0, D6-1 = “H”, D6-2 to D6-5 = “L”. 7. Pulse input signals Sharp edges at input pulse signals may affect output. If there is a problem, insert a damping resistor (around 100 to 200Ω) to smooth the pulse’s edges. – 14 – Application Circuit Pulse input Pulse input 5V Digital data input SH D5-1 MPX2 D5-0 D4-1 (N.C.) D5-4 D4-2 D4-3 (N.C.) CLP D5-2 D5-3 D4-4 D4-0 MPX1 GC LCLP 47µF VCCA 42 0.1µF TD4 30 33 24 26 31 32 VCCD 47 VCCP 21 × 0.5 to 2.27 GND 19 SH1 GCA1 48 1 23 22 23 DA4 (5bit) 4 DA5 (5bit) 41 43 44 45 46 100Ω SW (cont) 12V VOUT-R R-IN 2.2kΩ 35 1000pF 100Ω SH2 GCA DC shift GCA2 12V × 0.5 to 2.27 Driver TD5 × 1 to 3 SIGOUT 20 CLPC 16 VIN VOUT-G G-IN 2.2kΩ 36 1000pF 100Ω SH3 GCA3 LOG LOG LOG × 0.5 to 2.27 CCD Linear Image Sensor VOUT-B B-IN 37 2.2kΩ 1000pF REF VOLTAGE DA3 (5bit) LATCH3 DA6 (6bit) 18 17 VRT VRT VRB VRB 1µF 1µF DA1 (5bit) LATCH1 LATCH2 DA2 (5bit) TD1 TD2 TD3 BUF 38 39 11 12 13 14 15 40 27 28 29 34 5 6 7 8 9 10 25 LD0 LD2 LD3 LPR LPG LD1 LD4 LPB D6-1 D6-3 D6-2 (N.C.) (N.C.) D6-4 D6-5 (N.C.) CXA2027Q Digital data pulse input (N.C.) D6-0 Digital data input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. (N.C.) TD6 A/D Converter 0.47µF – 15 – 12V CXA2027Q Example of Representative Characteristics (VCC = 5V, Ta = 25°C) Pre-stage GCA gain characteristics data (unit) 9 8 f = 1MHz 7 6 5 4 3 Post-stage GCA gain characteristics data (unit) 12 11 f = 1MHz 10 9 8 7 Gain [dB] 1 0 –1 –2 –3 –4 –5 –6 –7 0 5 10 15 20 25 30 LD0 to LD4 input data (expressed as decimal system) Gain [dB] 2 6 5 4 3 2 1 0 –1 –2 0 1 2 3 GC pin input voltage [V] 4 5 G, B channels clamp voltage adjustment range 80 2060 SIGOUT clamp voltage adjustment range 60 2050 Difference from R channel clamp voltage [mV] 40 2040 20 SIGOUT voltage [mV] 2030 0 2020 –20 2010 –40 –60 2000 VRB –80 0 5 10 15 20 25 30 1990 D4-0 to D4-4 or D5-0 to D5-4 input data (expressed as decimal system) 0 10 20 30 40 50 60 D6-0 to D6-5 input data (expressed as decimal system) – 16 – CXA2027Q Example of Temperature and Supply Voltage Fluctuation Characteristics Total gain temperature characteristics fluctuation 0.3 5V 5.25V 4.75V 0.25 LD0 to LD4 = 0, GC = open 0.1 0.2 0.15 Total gain supply voltage fluctuation DA1, 2, 3 = all 0/GC = VCC DA1, 2, 3 = all 0/GC = open DA1, 2, 3 = all 0/GC = GND DA1, 2, 3 = all 1/GC = VCC DA1, 2, 3 = all 1/GC = open DA1, 2, 3 = all 1/GC = GND Ta = 25°C f = 1MHz Gain fluctuation [dB] 0.15 Gain fluctuation [dB] 30 50 0.05 0.1 0.05 0 0 –0.05 0 10 20 40 60 70 –0.05 4.75 5 Vcc [V] 5.25 Temperature [°C] VRT, VRB temperature characteristics voltage fluctuation 2.5 VRT VRB VRT – VRB VCC = 5V Clamp voltage temperature characteristics fluctuation 2 SIGOUT SIGOUT – VRB 1.5 VCC = 5V 2 1.5 1 SIGOUT fluctuation voltage [mV] 0 10 20 30 40 50 60 70 1 Fluctuation voltage [mV] 0.5 0.5 0 0 –0.5 –0.5 –1 –1 –1.5 –1.5 0 10 20 30 40 50 60 70 Temperature [°C] Temperature [°C] – 17 – CXA2027Q Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.4 12.0 – 0.1 + 0.1 0.15 – 0.05 36 25 0.15 37 24 48 13 + 0.2 0.1 – 0.1 1 + 0.15 0.3 – 0.1 12 0.8 ± 0.12 M + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 ∗QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 18 – 0.9 ± 0.2 13.5