CXA2040Q

CXA2040Q I2C Bus-Compatible Video Switch For the availability of this product, please contact the sales office. Description The CXA2040Q is an I2C bus-compatible 5-input, 3-output video switch for TVs. Features • Serial data control via I2C bus • 5 composite video input systems • 2 Y/C (S terminal) input systems • 3 composite video output systems • 1 Y/C (S terminal) output system • Input can be selected independently for each output system. • SYNC_ID function for CV1 system input • Built-in 6dB amplifier for CVOUT2 system output • Built-in Y/C MIX circuit • Slave address can be changed (90H/92H). • High impedance maintained by I2C bus line (SDA, SCL) even when power is OFF. Applications TVs Pin Configuration (Top View) SYNCTC SDA CV1 32 pin QFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VCC 12 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1.0 W (when mounted on a 50mm × 50mm board) Operating Conditions Supply voltage Structure Bipolar silicon monolithic IC ADR CVOUT1 SCL VCC 9.0 ± 0.5 V NC 24 23 22 21 20 19 18 NC 17 CV2 25 VCC 26 CV3 27 NC 28 CV4 29 GND 30 CV5 31 BIAS 32 16 NC 15 CVOUT2 14 NC 13 CVOUT3 12 NC 11 YOUT 10 NC 9 COUT 1 2 3 4 5 6 7 8 C1 S1 S2 C2 Y1 Y2 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. NC –1– NC E95Z44-ST CXA2040Q Block Diagram GND VCC SCL ADR SDA 19 S1 30 26 20 21 4 I2C BUS DECODER SYNCTC 22 SYNC DETECT CV1 CV2 CV1 23 CV1 CV3 CV4 CV5 CV6 SW1 17 CVOUT1 CV2 25 CV2 CV7 MUTE CV3 27 CV3 CV1 CV2 CV3 CV4 6dB SW2 15 CVOUT2 CV4 29 CV4 CV5 CV6 CV7 MUTE CV5 31 CV5 CV1 CV2 Y1 1 CV6 CV3 CV4 CV5 CV6 C1 3 CV7 MUTE SW3 13 CVOUT3 Y2 5 CV7 Y1 Y2 MUTE SW4 11 YOUT C2 7 C1 C2 MUTE BIAS 32 BIAS MUTE SW5 9 COUT ∗ Numbers inside circles indicate the IC pin numbers. –2– S2 6 CXA2040Q Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description VCC 1 20k 147 ×2 28k 1 5 3 7 Y1 Y2 C1 C2 5 4.5V 3 7 Y/C separation signal inputs. Biased to approximately 4.5V. Input the input signals through capacitors. Connect protective resistor of 220Ω between these pins and the capacitors. Y1 and Y2 pins: Luminance signals input. C1 and C2 pins: Chrominance signals input. VCC 4 6 S1 S2 50k 4 6 50k 100k ×4 Applying a DC voltage to S1 and S2 pins allows these voltages to be applied to the microcomputer as the I2C bus status register data. S1, S2 = 0 to 2V OPEN = 0, SEL = 1 S1, S2 = 4.75 to 7.25V OPEN = 0, SEL = 0 S1, S2 = 9.5 to 12V OPEN = 1, SEL = 0 VCC 200 1.2k 11 9 YOUT COUT ×5 4.5V ×2 ×2 11 9 ×6 Y/C signal outputs. YOUT pin: Luminance signal output. COUT pin: Chrominance signal output. VCC 200 1.2k 17 15 13 CVOUT1 CVOUT2 CVOUT3 4.5V 17 15 13 ×5 ×6 ×2 ×2 Composite video signal outputs. CVOUT1, CVOUT2: 0dB output with respect to the input signal. CVOUT2: +6dB output with respect to the input signal. –3– CXA2040Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC 19 19 ADR 72k 28k Selects the slave address for the I2C bus. 90H at 1.0V or less 92H at 3.5V or more 90H when open VCC 4k 20 SCL — 20 ×4 I2C bus signal input. Connect protective resistor of 220Ω between this pin and the SCL line. VCC 4k 21 21 SDA — ×6 I2C bus signal input. Connect protective resistor of 220Ω between this pin and the SDA line. VCC 1.2k 147 147 22 SYNCTC 22 Sync tip clamp time constant for Sync Separation. Connect 68kΩ resistor between this pin and VCC. Connect 10µF capacitor between this pin and GND. 1.2k –4– CXA2040Q Pin No. Symbol Pin voltage Equivalent circuit Description VCC 20k 23 CV1 4.5V 147 23 28k Composite video signal input. Biased to approximately 4.5V. Input the input signal through capacitor. Connect protective resistor of 220Ω between this pin and the capacitor. The composite video signal input to CV1 is also taken into the "SYNC DETECT circuit" of which SYNC is existed or not. VCC 20k 147 28k 25 27 29 31 CV2 CV3 CV4 CV5 25 4.5V 27 29 31 Composite video signal input. Biased to approximately 4.5V. Input the input signals through capacitors. Connect protective resistor of 220Ω between these pins and the capacitors. 26 30 VCC GND 9.0V∗1 0.0V∗1 VCC 1.2k Power supply. Apply 9.0V. GND. 32 BIAS 4.5V 32 20k 22.5k 4.5V bias. Attach a decoupling capacitor between this pin and GND. This pin cannot be used as an external power supply. 2 8 10 12 14 16 18 24 28 NC NC (not connected). Connect to GND. If these NC pins are not connected to GND, the cross talk and other desired values indicated in the Electrical Characteristics cannot be obtained. ∗1 Applied externally. –5– Electrical Characteristics See Electrical Characteristics Measurement Circuit 2 for Cross talk and MUTE. See Electrical Characteristics Measurement Circuit 1 for all other items. Measurement conditions 26 32 Measure the pin voltage. 4.25 4.50 Measure the pin inflow current. 18.0 27.7 39.0 4.75 Measurement pins Measurement contents Min. Typ. Max. Unit mA V (Ta = 25°C, VCC = 9V) No. Item Symbol 1 Current consumption ICC VCC = 9V, no signal 2 Pin voltage VBIAS VCC = 9V, no signal 3 13, 17 20Log VCV11 0.3Vp-p CV system gain 1 –0.40 GCV11 CV1 In, CV2 In, CV3 In, CV4 In or CV5 In 100kHz, 0.3Vp-p CW VCV11 0.00 0.40 dB Select each input with I2C bus control and obtain the I/O gain. –6– 15 20Log VCV21 0.3Vp-p 13, 17 4 CV system gain 2 GCV21 CV1 In, CV2 In, CV3 In, CV4 In or CV5 In 100kHz, 0.3Vp-p CW VCV21 5.75 6.25 6.75 dB Select each input with I2C bus control and obtain the I/O gain. Y1 and C1 (CV6) In or Y2 and C2 (CV7) In 100kHz, 0.15Vp-p CW VCVM11 5 CV system (Y/C MIX) gain 1 GCVM11 0.10 0.60 dB Select each input with I2C bus control and obtain the I/O gain. VCVM11 20Log –0.40 0.3Vp-p ∗ Since the sum of 0.15Vp-p and 0.15Vp-p is input to each switch, calculations are performed with 0.3Vp-p. CXA2040Q No. Measurement conditions Measurement pins Measurement contents Min. Item Symbol Typ. Max. Unit Y1 and C1 (CV6) In or Y2 and C2 (CV7) In 100kHz, 0.15Vp-p CW VCVM21 6 VCVM21 20Log 0.3Vp-p ∗ Since the sum of 0.15Vp-p and 0.15Vp-p is input to each switch, calculations are performed with 0.3Vp-p. CV system (Y/C MIX) gain 2 15 5.75 6.40 GCVM21 7.05 dB Select each input with I2C bus control and obtain the I/O gain. Y1 In or Y2 In 100kHz, 0.3Vp-p CW VY11 7 20Log VY11 0.3Vp-p Y system gain 11 GY11 –0.40 0.00 0.40 dB Select each input with I2C bus control and obtain the I/O gain. –7– 9 20Log VC11 0.3Vp-p 13, 17 20Log VCV12 VCV11 C1 In or C2 In 100kHz, 0.3Vp-p CW VC11 8 C system gain GC11 –0.40 0.00 0.40 dB Select each input with I2C bus control and obtain the I/O gain. CV1 In, CV2 In, CV3 In, CV4 In or CV5 In 10MHz, 0.3Vp-p CW VCV12 9 CV system frequency response 1 ∆GCV12 –0.85 ∗ VCV11 and VCV12 should be the same I/O. –0.15 0.55 dB Select each input with I2C bus control and obtain the I/O gain. Then obtain the difference from the I/O gain measured by Test 3. CXA2040Q No. Measurement conditions VCV22 Item Symbol Measurement pins Measurement contents Min. Typ. Max. Unit CV1 In, CV2 In, CV3 In, CV4 In or CV5 In 10MHz, 0.3Vp-p CW 15 20Log VCV22 VCV21 ∗ VCV21 and VCV22 should be the same I/O. VCVM12 10 CV system frequency response 2 –0.85 –0.15 0.55 ∆GCV22 Select each input with I2C bus control and obtain the I/O gain. Then obtain the difference from the I/O gain measured by Test 4. dB Y1 and C1 (CV6) In or Y2 and C2 (CV7) In 10MHz, 0.15Vp-p CW 13, 17 20Log VCVM12 VCVM11 ∗ VCVM11 and VCVM12 should be the same I/O. VCVM22 11 CV system (Y/C MIX) frequency response 1 ∆GCVM12 Select each input with I2C bus control and obtain the I/O gain. Then obtain the difference from the I/O gain measured by Test 5. –1.75 –0.25 1.25 dB –8– 15 20Log VCVM22 VCVM21 11 20Log VY12 VY11 Y1 and C1 (CV6) In or Y2 and C2 (CV7) In 10MHz, 0.15Vp-p CW 12 CV system (Y/C MIX) frequency response 2 ∆GCVM22 Select each input with I2C bus control and obtain the I/O gain. Then obtain the difference from the I/O gain measured by Test 6. –1.75 –0.25 1.25 dB ∗ VCVM21 and VCVM22 should be the same input. VY12 Y1 In or Y2 In 10MHz, 0.3Vp-p CW 13 Y system frequency response ∆GY12 Select each input with I2C bus control and obtain the I/O gain. Then obtain the difference from the I/O gain measured by Test 7. –0.70 ∗ VY11 and VY12 should be the same input. 0.00 0.70 dB CXA2040Q No. Measurement conditions VCV13 Item 2.2 Vp-p Symbol Measurement pins Measurement contents Min. Typ. Max. Unit 14 The input waveform amplitude value when Pins 13, 15 or 17 output waveform distortion factor = 1%. Y1 or Y2 input waveform VCVMY CV system input dynamic range 23, 25, 27, 29, 31 VCV13 CV1 In, CV2 In, CV3 In, CV4 In or CV5 In f = 100kHz CW The value for the PAL composite signal should correspond to an amplitude of approximately 1Vp-p + 3dB. Select each input with I2C bus control and then increase the input waveform amplitude. Y1 (CV6) In or Y2 (CV7) In f = 100kHz CW 1, 5 2.2 Vp-p VCVMY33 Select each input with I2C bus control and then increase the input waveform amplitude. C1 or C2 input waveform 15 CV system (Y/C MIX) input dynamic range VCVMC The value for the PAL Y signal The input waveform amplitude value when Pins 13, 15 or 17 output should correspond to an amplitude of approximately 1Vp-p + 3dB. waveform distortion factor = 1%. C1 (CV6) In or C2 (CV7) In f = 100kHz CW 3, 7 0.95 Vp-p –9– 1, 5 3, 7 VCVMC33 Select each input with I2C bus control and then increase the input waveform amplitude. The value for the PAL C signal The input waveform amplitude value when Pins 13, 15 or 17 output should correspond to an amplitude of approximately 0.66Vp-p + 3dB. waveform distortion factor = 1%. VY13 Y1 In or Y2 In f = 100kHz CW 2.2 The input waveform amplitude value when Pin 11 output waveform distortion factor = 1%. VC13 Vp-p The value for the PAL Y signal should correspond to an amplitude of approximately 1Vp-p + 3dB. 2.2 The input waveform amplitude value when Pin 9 output waveform distortion factor = 1%. Vp-p CXA2040Q 16 Y system input dynamic range VY13 Select each input with I2C bus control and then increase the input waveform amplitude. C1 In or C2 In f = 100 kHz CW 17 C system input dynamic range VC13 Select each input with I2C bus control and then increase the input waveform amplitude. The value for the C signal should correspond to an amplitude of approximately 2.2Vp-p. No. Measurement conditions Read the output waveform value. VX Item Symbol Measurement pins Measurement contents Min. Typ. Max. Unit 18 Cross talk GCRS 9, 11, 13, 15, 17 20Log VX 1Vp-p Select the input with I2C bus control and ground that input pin via a capacitor. Input a 4.43MHz, 1Vp-p CW to one input pin system among the remaining 8 input pins (7 input pins for Y/C MIX). Then ground the remaining 7 input pins (6 input pins for Y/C MIX) via capacitors. –55 Read the output waveform value. VX dB 19 MUTE CV system 1, Y system, C system 9, 11, 13, 17 20Log VX 1Vp-p GM1 Set this pin to MUTE status with I2C bus control and input a 4.43MHz, 1Vp-p CW to one input pin system. Then ground the remaining 8 input pins via capacitors. –50 dB – 10 – 15 VX 20Log 1Vp-p Read the output waveform value. VX 20 MUTE (CV system 2) GM2 Set this pin to MUTE status with I2C bus control and input a 4.43MHz, 1Vp-p CW to one input pin system. Then ground the remaining 8 input pins via capacitors. –45 dB CXA2040Q No. Measurement conditions 100 63.56µs 100mV 4.70µs Item mV Symbol Measurement pins Measurement contents Min. Typ. Max. Unit CV1 In: Sig-1 21 SYNC discrimination 11 21 (SDA) SYNCD11 Input Sig-1 to CV1 and check that bit 5 "SYNCSEP" of the I2C bus status register is "1" when the Sig-1 sync level is 100mV or more. The Sig-1 sync level should correspond to approximately –9dB when the 1Vp-p NTSC composite signal sync level (286mV) is set as 0dB. 30 mV CV1 In: Sig-2 63.56µs 30mV 4.70µs 22 SYNC discrimination 21 21 (SDA) SYNCD21 Input Sig-2 to CV1 and check that bit 5 "SYNCSEP" of the I2C bus status register is "0" when the Sig-2 sync level is 30mV or less. The Sig-2 sync level should correspond to approximately –19dB when the 1Vp-p NTSC composite signal sync level (286mV) is set as 0dB. 91 % – 11 – 63.56µs 286mV 5.72µs Duty = 91% CV1 In: Sig-3 23 SYNC discrimination 12 21 (SDA) SYNCD12 Input Sig-3 to CV1 and check that bit 5 "SYNCSEP" of the I2C bus status register is "1" when the Sig-3 duty is 91% or more (the sync width is 5.72µs or less). Sync is determined to exist when the sync level is 100mV or more and a rectangular wave with a duty of 91% or more is input to CV1. 84 % CV1 In: Sig-4 63.56µs 286mV Duty = 84% 10.17µs 24 SYNC discrimination 22 SYNCD22 21 (SDA) Input Sig-4 to CV1 and check that bit 5 "SYNCSEP" of the I2C bus status register is "0" when the Sig-4 duty is 84% or less (the sync width is 10.17µs or more). Sync is determined not to exist when a rectangular wave with a duty of 84% or less is input to CV1 even when the sync level is 100mV or more. CXA2040Q No. Unit V 21 1.0 3.5 The slave address goes to 92H at high level and 90H at low level. Item Measurement conditions Measurement pins Measurement contents Min. Typ. Max. Symbol 25 ADR threshold voltage VADRVTH Vary the Pin 19 VADR. – 12 – CXA2040Q CXA2040Q Electrical Characteristics Measurement Circuit 1 68k CV1 I2C bus I/O 0.1µ 22 21 20 19 10k VADR 10µ 2.2µ 24 23 18 17 SYNCTC CVOUT1 ADR SDA CV1 SCL NC NC 25 CV2 CV2 VCC 9V 27 CV3 CV3 2.2µ 28 NC 29 CV4 CV4 2.2µ 30 GND 31 CV5 CV5 2.2µ 32 BIAS 2.2µ 26 VCC NC 16 CVOUT2 15 10µ NC 14 CVOUT3 13 10µ NC 12 YOUT 11 10µ NC 10 COUT 9 10k 10k 10k NC S1 S2 C1 0.01µ Y1 Y2 1 2 3 Vs1 4 5 Vs2 2.2µ Y2 6 C2 7 2.2µ Y1 2.2µ C1 2.2µ C2 ∗1 Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, all are GND. ∗2 Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, the supply voltages are as follows. VCC = 9V, VS1 = 0V, VS2 = 0V VADR = 0V when operated with a slave address of 90H. VADR = 9V (VCC) when operated with a slave address of 92H. – 13 – NC 33µ 0.47µ 10k 8 CXA2040Q Electrical Characteristics Measurement Circuit 2 (Cross talk, MUTE) 68k CV1 0.1µ 2.2µ 24 23 22 I2C bus I/O VADR 21 20 19 18 17 SYNCTC SCL NC NC CVOUT1 2.2µ C2 ADR SDA CV1 25 CV2 CV2 VCC 9V 27 CV3 CV3 2.2µ 28 NC 29 CV4 CV4 2.2µ 30 GND 31 CV5 CV5 2.2µ 32 BIAS 33µ 2.2µ 26 VCC NC 16 CVOUT2 15 NC 14 CVOUT3 13 NC 12 YOUT 11 NC 10 COUT 9 NC 0.01µ S1 1 2 3 4 5 S2 6 7 2.2µ Y1 2.2µ C1 2.2µ Y2 ∗1 Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, all are GND. ∗2 Unless otherwise specified in the Measurement conditions column of Electrical Characteristics, the supply voltages are as follows. VCC = 9V VADR = 0V when operated with a slave address of 90H. VADR = 9V (VCC) when operated with a slave address of 92H. – 14 – NC 8 C1 Y1 Y2 C2 CXA2040Q I2C Bus Control Map 1) Control Register The CXA2040Q control system is comprised of 4 bytes of control registers which control the various outputs. The inputs which are to be output are selected by writing the respective input data into the control register. S Slave address A DATA1 A DATA2 A DATA3 A DATA4 A P S: START CONDITION A: ACKNOWLEDGE P: STOP CONDITION • Slave address R/W bit This bit is set to "0" when data is to be written into the control registers. Value set by the address pin DATA1 DATA2 DATA3 DATA4 Controls the video output 1. Controls the video output 2. Controls the video output 3. Controls the S terminal output. 1 0 0 1 0 0 X 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 X X video select X X X Each register is set to "0" upon POWER ON. • Video switch control map bit5 bit4 bit3 Selected input signal 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MUTE CV1/YC1 CV2/YC2 CV3 CV4 CV5 CV6 CV7 Other conditions: MUTE – 15 – CXA2040Q 2) Status Register S Slave address A DATA NA P S: START CONDITION P: STOP CONDITION A: ACKNOWLEDGE • Slave address R/W bit This bit is set to "1" when data is to be read into the status registers. Value set by the address pin DATA bit7 PON RES bit6 X bit5 SYNC SEP bit4 X bit3 S1 OPEN bit2 bit1 bit0 S2 SEL 1 0 0 1 0 0 X 1 S1 S2 SEL OPEN (1) PONRES Returns "1" when the CXA2040Q is POWER ON RESET. Becomes "0" after reading once. (2) SYNCSEP "1" returns if sync exists, "0" if sync does not exist. (3) OPEN/SEL for S1 and S2 is determined by comparing the DC voltages for S1 and S2 pins with two threshold levels. DC voltages for S1 and S2 pins S1, S2 OPEN S1, S2 SEL 2V or less 4.75 to 7.25V 9.5 to 12V 0 0 1 1 0 0 3) POWER ON RESET The CXA2040Q incorporates a POWER ON RESET function which sets each control register to "0" upon POWER ON. (Which goes to MUTE status.) The POWER ON RESET VTH has hysteresis. The POWER ON VCC and released VCC are as shown below. Also, the PONRES bit of the status register is read to determine whether the IC is reset upon POWER ON. POWER ON RESET RELEASE POWER ON RESET Vcc 4.7V 5.9V – 16 – CXA2040Q Description of Operation 1) Composite Video System I/Os There are three systems of composite outputs. Each output switch can select the eight systems of CV1 to CV5 composite video inputs, CV6 and CV7 Y/C MIX (composite video) inputs and MUTE. All composite video inputs are input from the input pins to each switch by DC coupling. CV6 is the composite video signal obtained by inputting Y1 and C1 to an adder and adding Y1 and C1. CV7 is the composite video signal obtained by inputting Y2 and C2 to an adder and adding Y2 and C2. The CV6 and CV7 composite video signals are input from the input pins to each switch by DC coupling. When MUTE is selected, the internal bias DC output (approximately VCC/2 [V]) is input to each switch. Only one type of input is selected by the I2C bus control register. The CVOUT1 and CVOUT3 switches output the signal selected by the I2C bus at a gain of 0 [dB] with respect to the input signal. The switch output stages are push-pull circuits which output at low impedance. The CVOUT2 switch outputs the signal selected by the I2C bus amplified to +6 [dB] with respect to the input signal. The switch output stage is a push-pull circuit which outputs at low impedance. The switches are DC coupled from input to output. 2) Y System I/Os The YOUT switch can select the three systems of Y1, Y2 and MUTE. Y1 and Y2 are input from the input pins to the switch by DC coupling. When MUTE is selected, the internal bias DC output (approximately VCC/2 [V]) is input to the switch. Only one type of input is selected by the I2C bus control register. The YOUT switch outputs the signal selected by the I2C bus at a gain of 0 [dB] with respect to the input signal. The switch output stage is a push-pull circuit which outputs at low impedance. The switch is DC coupled from input to output. 3) C System I/Os The COUT switch can select the three systems of C1, C2 and MUTE. C1 and C2 are input from the input pins to the switch by DC coupling. When MUTE is selected, the internal bias DC output (approximately VCC/2 [V]) is input to the switch. Only one type of input is selected by the I2C bus control register. The COUT switch outputs the signal selected by the I2C bus at a gain of 0 [dB] with respect to the input signal. The switch output stage is a push-pull circuit which outputs at low impedance. The switch is DC coupled from input to output. – 17 – CXA2040Q 4) Sync Discrimination Vcc 0.1µ 22 IC Input signal 23 2.2µ CV1 Sync tip clamp and comparator Duty discrimination I2C SYNCTC Fig. 1. Sync discrimination circuit block diagram Fig. 1 shows the block diagram for the sync discrimination circuit. The signal input from Pin 23 (CV1) is sync tip clamped by the external element attached to Pin 22. This signal is compared with a threshold voltage which is larger than the sync tip level. If the signal is smaller than the threshold level, it does not proceed to the following stage. At this time, the IC determines that sync does not exist. If the signal is larger than the threshold level, it proceeds to the duty discrimination block. If the duty is greater than 91%, the duty discrimination block determines that sync exists and sends the data to the I2C. If the duty is less than 84%, sync is determined not to exist and the data is sent to the I2C. The duty discrimination block also has a time constant. After sync is determined to exist, the sync status is held for approximately 14H (NTSC signal) even if the IC goes to a status where sync does not exist such as no signal, etc. If there is no signal or sync does not exist for longer than 14H, the status switches from sync exists to sync does not exist. 68k – 18 – CXA2040Q Application Circuit VCC I2C BUS 68k 0.1µ 2.2µ 75 24 23 22 21 20 19 18 17 220 220 220 10µ VADR Composite video signal 0dB output 1 SYNCTC NC Composite video signal inputs 75 Vcc 9V 2.2µ 0.01µ 220 33µ CVOUT1 ADR SDA CV1 SCL NC 25 CV2 26 VCC 27 CV3 NC 16 Composite video signal +6dB output 2 CVOUT2 15 10µ NC 14 CVOUT3 13 CXA2040Q 10µ NC 12 YOUT 11 10µ NC 10 COUT 9 2.2µ 75 220 28 NC 29 CV4 Composite video signal 0dB output 3 2.2µ 75 220 30 GND 31 CV5 Luminance signal output 2.2µ 75 220 32 BIAS 33µ Chrominance signal output NC S1 S2 0.01µ Y2 1 220 2 3 220 4 Vs1 5 220 6 Vs2 C2 7 220 2.2µ 75 2.2µ 75 2.2µ 75 2.2µ 75 Chrominance signal input 1 ∗1 Input pins of Pins 1, 3, 5, 7, 23, 25, 27, 29 and 31 are biased to approximately 4.2 to 4.7V. Therefore, care should be taken for the capacitance polarity. ∗2 Output pins of Pins 9, 11, 13, 15 and 17 are biased to approximately 3.8 to 4.8V. Therefore, care should be taken for the capacitance polarity. ∗3 Set VADR to 0V (GND) when the IC slave address is 90H, or to 9V (VCC) when the IC slave address is 92H. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Luminance signal input 1 – 19 – Chrominance signal input 2 Luminance signal input 2 NC Y1 C1 0.47µ 8 CXA2040Q Notes on Operation • Connect the power supply side of the by-pass capacitor between the power supply and GND as close to the pin as possible. • Take care not to allow interference signals to enter Pin 32 (BIAS). If interference signals enter Pin 32, the signal S/N, cross talk and MUTE will deteriorate. Therefore, connect the by-pass capacitor, etc. as close to the pins as possible. • For dual surface boards, using one side as a solid earth is best. • Pins 2, 8, 10, 12, 14, 16, 18, 24 and 28 are NC (not connected) pins. Connect these NC pins to GND. If these NC pins are not connected to GND, the cross talk and other desired values indicated in the Electrical Characteristics cannot be obtained. • Input pins of Pins 1, 3, 5, 7, 23, 25, 27, 29 and 31 are biased to approximately 4.2 to 4.7V. Therefore, care should be taken for the capacitance polarity. • Output pins of Pins 9, 11, 13, 15 and 17 are biased to approximately 3.8 to 4.8V. Therefore, care should be taken for the capacitance polarity. – 20 – CXA2040Q Curve Data CV1 to 5 inputs — CVOUT1, 3 frequency response 2 0 –2 –4 –6 –8 0.1 1 Frequency [MHz] 10 8 6 4 2 0 –2 0.1 CV1 to 5 inputs — CVOUT2 frequency response Video I/O gain [dB] Video I/O gain [dB] 1 Frequency [MHz] 10 Y/C MIX input — CVOUT1, 3 frequency response 2 0 –2 –4 –6 –8 0.1 1 Frequency [MHz] 10 8 6 4 2 0 –2 0.1 Y/C MIX input — CVOUT2 frequency response Video I/O gain [dB] Video I/O gain [dB] 1 Frequency [MHz] 10 Y input — YOUT frequency response 2 0 –2 –4 –6 –8 0.1 1 Frequency [MHz] 10 2 0 –2 –4 –6 –8 0.1 C input — COUT frequency response Video I/O gain [dB] Video I/O gain [dB] 1 Frequency [MHz] 10 – 21 – CXA2040Q Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 + 0.3 7.0 – 0.1 24 17 + 0.35 1.5 – 0.15 0.1 25 16 32 9 + 0.2 0.1 – 0.1 1 0.8 + 0.15 0.3 – 0.1 8 + 0.1 0.127 – 0.05 0° to 10° ± 0.12 M PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 ∗QFP032-P-0707-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g – 22 – 0.50 (8.0)