CXA2064M

CXA2064M US Audio Multiplexing Decoder Description The CXA2064M is an IC designed as a decoder for the Zenith TV Multi-channel System. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction. Features • Adjustment free of VCO and filter. • Audio multiplexing decoder and dbx noise reduction decoder are all included in a single chip. Almost any sort of signal processing is possible through this IC. • Various built-in filter circuits greatly reduce external parts. • This IC is near pin to pin compatible with the CXA2020M. Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Structure Bipolar silicon monolithic IC 30 pin SOP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VCC 11 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1000 mW • STID, SAPID drive current IO 2 (max.) mA Range of Operating Supply Voltage 9 ± 0.5 V ∗ This device is available only to the licensees of the dbx-TV noise reduction system. Standard I/O Level • Input level COMPIN (Pin 7) • Output level TVOUT-L/R (Pins 23 and 22) Pin Configuration (Top View) 100mVrms (MONO 100Hz 100% mod.) 490mVrms (MONO 100Hz 100% mod.) TVOUT-R VCAWGT VEWGT TVOUT-L SAPOUT SAPIN 30 29 28 27 26 25 24 23 22 21 20 19 18 M1 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 COMPIN IREF NOISETC PCINT1 SAPTC SAPID STIN PLINT GND Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– MAINOUT VCC SUBOUT PCINT2 STID VGR MAININ VEOUT VCATC VCAIN VE MUTE FOMO VETC E98513-PS Block Diagram PLINT SUBOUT MAINOUT MAININ 14 13 10 2 16 15 PCINT1 LFLT MATRIX PCINT2 VCO 1/4 1/2 23 TVOUT-L 22 TVOUT-R FLT LPF COMPIN DeEm +6dB STIND LPF 7 LPF – VCC 4 GND 6 SAPVCO DeEm LPF VE VCA M1 VGR IREF STID STIN VE MUTE FOMO SAPIN VETC SAPID VCAIN SAPOUT VEWGT VEOUT VCAWGT VCATC –2– NOISE DET HPF SAPIND AMP (+4dB) LPF LPF MODE_DISPLAY SW 11 17 18 19 28 27 1 BPF NOISETC 3 RMSDET SAPTC 8 RMSDET IREF DETECTION 9 5 12 30 29 26 25 24 20 21 CXA2064M CXA2064M Pin Description Pin No. Symbol Pin voltage Equivalent circuit VCC (Ta = 25°C, VCC = 9V) Description 1 STIN 4.0V 23k 23k Input the (L-R) signal from SUBOUT (Pin 2). 11.7k 147 1 147 27 18k 4V 20k 4V 18k 27 SAPIN 4.0V Input the (SAP) signal from SAPOUT (Pin 28). Vcc 580 2 SUBOUT 4.0V 2 147 580 (L–R) signal output pin. 12k 4k Vcc 8k 3.3k 10k 1k 2k 4k 4V 3k Vcc 3k 3 NOISETC 3.0V ×2 Set the time constant for the noise detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) 200k 3 4 VCC — 4 Supply voltage pin. –3– CXA2064M Pin No. Symbol Pin voltage VCC 40k Eqivalent circuit Description 40k 30k 34k 15k ×2 30k VCC 5 IREF 1.3V 30p 1.8k 5 147 6.3k Set the filter and VCO reference current. (Connect a 68kΩ (±1%) resistor between this pin and GND.) 16k 6 GND — 6 Analog block GND. VCC 24k 24k 147 7 7 COMPIN 4.0V 50k 4V 24k Audio multiplexing signal input pin. VCC 8k 10k 3k 1k VCC 4k ↓ 50µ 8 8 SAPTC 4.5V Set the time constant for the SAP carrier detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) –4– CXA2064M Pin No. Symbol Pin voltage Eqivalent circuit Description 3k 147 9 VGR 1.3V 11k 9.7k 19.4k ×4 2.06k VCC 11k 9 11k Band gap reference output pin. (Connect a 10µF capacitor between this pin and GND.) VCC 20k 20k 147 10 PLINT 5.1V 20k 20k 10 Pilot cancel circuit loop filter integrating pin. (Connect a 1µF capacitor between this pin and GND.) ↓ 26µ 20k ↓ 50µ 10k 11 11 STID — 68k 12 Stereo detection pin. Open collector output. Drive current is 2mA (Max.). SAP detection pin. Open collector output. Drive current is 2mA (Max.). 12 SAPID — 15k 10.5k –5– CXA2064M Pin No. Symbol Pin voltage Eqivalent circuit Description VCC 147 13 13 PCINT2 4.0V 2k 10k 10k ×2 4k Stereo block PLL loop filter integrating pin. VCC 147 14 14 PCINT1 4.0V 30k 22k VCC 15k ×4 VCC 15 MAINOUT 4.0V 147 15 (L + R) signal output pin. ↓ 200µ 1k VCC 10k VCC 16 MAININ 4.0V 147 16 47k 4V Input the (L + R) signal from MAINOUT (Pin 15). 17 17 FOMO — 19 70k Mode control switch pin. This pin has 3 ranges for input voltage. Sets forced monoral mode and also control ST.ID. Mode control switch pin. When this pin is set to H level, TVOUT output is muted. 10.5k 50k 19 MUTE — –6– CXA2064M Pin No. Symbol Pin voltage Eqivalent circuit Description VCC 4V 24k 25k 18 M1 — 40k 10.5k 18 Mode control switch pin. This pin has 3 ranges for input voltage. Stereo, BOTH, SAP selection are available. VCC 40k 40k 3p 580 20 VCAWGT 4.0V 20 2.9V 36k 580 147 Weight the VCA control effective value detection circuit. (Connect a 1µF capacitor and a 3.9kΩ resistor in series between this pin and GND.) ↓ 50µ 4k↓ 8µ 30k 8k VCC ×4 21 ×4 21 VCATC 1.7V ↓ 50µ 4k ↓ 7.5µ 20k Determine the restoration time constant of the VCA control effective value detection circuit. (the specified restoration time constant can be obtained by connecting a 10µF capacitor between this pin and GND.) VCC 3k 22 TVOUT-R 4.0V 580 22 23 580 TVOUT right channel output pin. 23 TVOUT-L 4.0V TVOUT left channel output pin. –7– CXA2064M Pin No. Symbol Pin voltage Eqivalent circuit VCC Description 47k 20k 47k 24 VCAIN 4.0V VCC 24 VCA input pin. Input the variable de-emphasis output signal from Pin 25 via a coupling capacitor. Vcc 5P 580 25 VEOUT 4.0V 25 580 10k Variable de-emphasis output pin. (Connect a 4.7µF non-polar capacitor between Pins 25 and 24.) Vcc 26 VETC 1.7V ×4 ×4 26 4k ↓ 50µ 20k ↓ 7.5µ Determine the restoration time constant of the variable de-rmphasis control effective value detection circuit. (the specified restoration time constant can be obtained by connecting a 3.3µF capacitor between this pin and GND.) Vcc 5P 580 28 SAPOUT 4.0V 580 10k 28 147 SAP FM detector output pin. 24k ↓ 10µ 4k ↓ 50µ –8– CXA2064M Pin No. Symbol Pin voltage Eqivalent circuit Vcc Description 580 2.9V 4V 36k 29 VEWGT 4.0V 29 147 580 Weight the variable de-emphasis control effective value detection circuit. (Connect a 0.047µF capacitor and a 3kΩ resistor in series between this pin and GND.) 8k 30k ↓ 8µ 4k ↓ 50µ VCC 7.5k 30 VE 4.0V 147 30 Variable de-emphasis integrating pin. (Connect a 2700pF capacitor and a 3.3kΩ resistor in series between this pin and GND.) –9– Electrical Characteristics COMPIN input level (100% modulation level) Main (L + R) (Pre-Emphasis: OFF) = 100mVrms SUB (L – R) (dbx-TV: OFF) = 200mVrms Pilot= 20mVrms SAP Carrier= 60mVrms fH = 15.734kHz Signal — MONO 7 7 7 7 7 7 7 7 7 7 7 7 7 SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 1kHz, 200% mod., NR OFF SUB (L-R) 1kHz, NR OFF SUB (L-R) 1kHz, 100% mod., NR ON, SAP Carrier (5fH) PILOT (fH) 0dB SUB (L-R) 12kHz, 30% mod., NR OFF SUB (L-R) 1kHz, 100% mod., NR OFF Mono 1kHz, Pre-em. ON Mono 1kHz 200% mod. Pre-em. ON Mono 1kHz 100% mod. Pre-em. ON Mono 12kHz 30% mod. 20 log ('12k'/'1k') Pre-em. ON Mono 5kHz 30% mod. Pre-em. ON Mono 1kHz 100% mod. Pre-em. ON No signal (Ta = 25°C, VCC = 9V) Measurement conditions Filter 15 22/23 20 log ('5k'/'1k') 22/23 22/23 15kLPF 15kLPF 20 log ('100%'/'0%') 15kLPF 22/23 22/23 22/23 2 20 log ('12k'/'1k') 15kLPF 15kLPF 20 log ('100%'/'0%') 20 log ('M1 = L'/ 'M1 = H') 0dB = 20mVrms 15kLPF 1kBPF fH BPF 2 2 2 2 23 2 440 –1.2 –3.0 — — 61 225 –3.0 — — 56 60 — 23 490 0 –1.0 0.1 0.15 69 275 –0.5 0.1 0.2 64 70 –27 Output pin Min. Typ. Max. 31 540 1.0 1.0 0.5 0.5 — 325 1.0 1.0 2.0 — — –16 Unit mA mVrms dB dB % % dB mVrms dB % % dB dB dB No. Item Mode Input pin Input signal 1 Current consumption Icc 2 MONO MONO MONO MONO MONO ST ST ST ST ST SAP ST Main output level Vmain 3 Main de-emphasis frequency characteristic FCdeem 4 Main LPF frequency characteristic FCmain – 10 – 5 Main distortion THDm 6 Main overload distortion THDmmax 7 Main S/N SNmain 8 Sub output level Vsub 9 Sub LPF frequency characteristic FCsub 10 Sub distortion THDsub 11 Sub overload distortion THDsmax 12 Sub S/N SNsub 13 ST → SAP Crosstalk CTst CXA2064M 14 Sub pilot leak PCsub No. 0dB = 20mVrms 11 –6.0 –3.0 10.0 210 2.5 6.0 55 60 –12.0 12 12 15kLPF 15kLPF 15kLPF 15kLPF 22/23 22/23 22/23 22/23 2.0 23 23 23 23 70 –9.0 4.0 35 35 35 35 — — –6.5 6.0 — — — — dB mVrms dB % 2.5 dB 46 dB dB dB dB dB dB dB 6.0 170 0 11 28 28 15kLPF 28 28 23 — 20 log ('100%'/'0%') 15kLPF 1kBPF –3.0 130 2.0 –9.0 dB 20 log (‘on level'/'off level') Item Signal Mode Input pin Input signal Measurement conditions Filter Output pin Min. Typ. Max. Unit 15 ST 7 Change PILOT (fH) Level Stereo ON level THst 16 SAP SAP SAP SAP ST 0dB = 60mVrms 20 log (‘on level’/’off level’) 7 SAP 1kHz 100% mod. 20 log ('M1 = H'/ NR ON, Pilot (fH) 'M1 = L') 7 SAP 1kHz, NR OFF 7 SAP 1kHz 100% mod. NR OFF 7 SAP 10kHz 30% mod. 20 log NR OFF ('10k'/'1k') 7 SAP 1kHz 100% mod. NR OFF Stereo ON/OFF hysteresis HYst 17 SAP output level Vsap 18 SAP LPF frequency characteristic FCsap 19 SAP distortion THDsap 20 SAP S/N SNsap 21 SAP → ST Cross talk CTsap 22 SAP 7 Change SAP Carrier (5fH) Level ST-L 300Hz 30% mod. 20 log NR ON ('Lch'/'Rch') ST-R 300Hz 30% mod. 20 log NR ON ('Rch'/'Lch') ST-L 3kHz 30% mod. NR ON ST-R 3kHz 30% mod. NR ON 20 log ('Lch'/'Rch') 20 log ('Rch'/'Lch') SAP ON level THsap – 11 – ST ST ST ST 7 7 7 7 23 SAP ON/OFF hysteresis HYsap 24 ST separation 1 L → R STLsep1 25 ST separation 1 R → L STRsep1 26 ST separation 2 L → R STLsep2 27 ST separation 2 R → L STRsep2 CXA2064M Electrical Characteristics Measurement Circuit BUFF FILTERS 15kHz LPF fH BPF 1kHz BPF V3 2.5V R7 3.9k C10 1µ S3 19 18 20 S2 17 S1 16 V2 5V MEASURES S9 S8 S7 S6 S5 S4 R9 3.3k C16 4.7µ C15 3.3µ TANTALUM 27 25 24 22 21 26 23 C14 4.7µ C13 4.7µ C12 4.7µ C11 10µ TANTALUM R8 5k C18 2700P C17 0.047µ 30 29 28 VE VETC MUTE M1 SAPIN VCAIN VCATC FOMO VEWGT SAPOUT VEOUT TVOUT-L NOISETC SAPTC TVOUT-R VCAWGT IREF PLINT SUBOUT COMPIN SAPID VCC VGR GND STID STIN 1 4 7 C3 4.7µ C4 4.7µ C5 10µ 8 C2 4.7µ VCC V1 9V R2 68k METAL ±1% 2 3 5 6 9 10 C6 1µ 11 R3 10k 12 R4 10k 13 R5 1MEG C7 5600p PCINT2 14 PCINT1 15 C1 4.7µ MAINOUT C9 4.7µ R6 C8 100k 0.012µ R1 10k C19 4.7µ GND SG ATT GND MAININ – 12 – CXA2064M CXA2064M Adjustment Method 1. Input level adjustment 1) Connect components as shown in Fig. 1. 2) Set the US MPX encoder output to MONO 100Hz 100% modulation. 3) Adjust the "ATT" so that COMPIN (Pin 7) level goes to 100mVrms (±0.5dB). 2.Separation adjustment 1) Mode control pin are set to FOMO (Pin 17): L, M1 (Pin 18): L, MUTE (Pin 19): L. 2) Set the US MPX encoder ouput to Stereo Lch-only 300Hz 30% modulation, NR-ON. Then, adjust the variable resistor of SUBOUT (Pin 2) to reduce the TVOUT-R output to the minimum. 3) Next, set the frequency only of the input signal to 3kHz and adjust the variable resistor of VEWGT (Pin 29) to reduce the TVOUT-R output to the minimum. 4) The adjustments in 2 and 3 above are performed to optimize the separation. US MPX encoder ATT 4.7µ COMPIN (Pin 7) CXA2064M Fig. 1. Adjustment setup ∗ Adjust this IC through Tuner and IF when this IC is mounted on the set. – 13 – CXA2064M Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 2. PEAK DEV kHz 50 AM-DSB-SC 50 25 25 L-R dbx-TV NR PILOT 15 SAP dbx-TV NR FM 10kHz 50 – 10kHz 2fH 3fH 4fH 5fH TELEMETRY FM 3kHz 3 6fH 6.5fH f L+R 5 50 – 15kHz fH fH = 15.734kHz Fig. 2. Base band spectrum PLL (VCO 8fH) 2fHL0° fHL90° fHL0° ST.ID MODE CONTROL PILOT DET (COMPIN) STEREO LPF MAIN LPF DE.EM PILOT CANCEL (MAIN OUT) (MAIN IN) 7 15 L+R SUB LPF (SUBOUT) 4.7µ 16 L-R (DSB) DET MATRIX (STIN) 2 10k 4.7µ (TVOUT-L) 23 NR SW 1 SAP BPF SAP(FM) DET INJ. LOCK A SAP LPF (SAP OUT) (SAP IN) dbx-TV BLOCK B (TVOUT-R) 22 28 4.7µ NOISE DET 27 MODE CONTROL SAP DET SAP.ID MODE CONTROL Fig. 3. Overall block diagram (See Fig. 4 for the dbx-TV block) (ST IN) 1 (SAP IN) 27 HPF LPF LPF RMS DET RMS DET NR SW A FIXED DEEMPHASIS VARIABLE DEEMPHASIS (VE OUT) 25 4.7µ (VCA IN) 24 VCA B to MATRIX Fig 4. dbx-TV block – 14 – CXA2064M (1) L + R (MAIN) When the audio multiplexing signal is inputted to COMPIN (Pin 7), the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L – R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2) L – R (SUB) The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW circuit. (3) SAP SAP is an FM signal using 5fH as a carrier as shown in the Fig. 2. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25kHz after FM detection of SAP signal. (5) dbx-TV block Either the L – R signal or SAP signal input respectively from STIN (Pin 1) or SAPIN (Pin 27) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Matrix The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and SAP signals according to the mode control and whether there is ST / SAP discrimination. (7) Others “Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 5) with GND become the reference current. – 15 – CXA2064M Decoder Output and Mode Control Table Input signal mode ST H MONO H H L L H L STEREO L H L L H H H MONO & SAP H H H L L H L STEREO & SAP L H L L H ID SAP H H H H H H H H H H H H L L L L L L L L L L L L L L M1 L M H L L L M M M H H H L M H H H L L L M M M H H H Pin FOMO ∗ ∗ ∗ L M H L M H L M H ∗ ∗ L M H L M H L M H L M H dbx input MUTE MUTE MUTE L–R MUTE MUTE MUTE MUTE MUTE L–R MUTE MUTE MUTE SAP SAP SAP SAP L–R MUTE MUTE SAP SAP SAP SAP SAP SAP Output Lch L+R L+R L+R L L+R L+R L+R L+R L+R L L+R L+R L+R L+R SAP L+R L+R L L+R L+R L+R L+R L+R SAP L+R L+R Rch L+R L+R L+R R L+R L+R L+R L+R L+R R L+R L+R L+R SAP SAP SAP SAP R L+R L+R SAP SAP SAP SAP SAP SAP ∗: Don’t care Regarding ST, SAP, ID L shows that drive current runs through load register and pin voltage is low. H shows that drive current doesn't run through load resistor and pin voltage is high. – 16 – CXA2064M Limits of Control Voltage H M1 M L H FOMO M L MUTE H L SAP BOTH 4.5V to VCC 2 to 3V (or OPEN) STEREO 0 to 0.5V STID-H STID-L STID-L ON OFF 8.5V to VCC 3 to 7V 0 to 0.5V (or OPEN) 3V to VCC 0 to 0.5V (or OPEN) – 17 – Application Circuit TVOUT-L TVOUT-R C14 4.7µ C13 4.7µ C10 1µ 20 19 18 17 24 23 22 21 C12 4.7µ R7 3.9k MODE CONTROL SW R9 3.3k C15 3.3µ TANTALUM 27 25 26 C11 10µ TANTALUM R8 5k C18 2700P C17 0.047µ C16 4.7µ 30 29 28 16 VE VETC MUTE M1 SAPIN VCAIN VCATC FOMO VEWGT SAPOUT VEOUT TVOUT-L NOISETC SAPTC TVOUT-R VCAWGT IREF PLINT SUBOUT COMPIN SAPID VCC VGR GND STID STIN 1 4 7 C3 4.7µ C4 4.7µ C5 10µ R10 10k 8 10 VCC V1 9V R2 68k METAL ±1% 2 3 5 6 9 11 C6 1µ R3 10k 12 R4 10k V2 3 to VCC 13 R5 1MEG C7 5600p PCINT2 14 PCINT1 15 C1 4.7µ R1 10k C2 4.7µ MAINOUT C9 4.7µ R6 C8 SAPID 100k 0.012µ GND COMP IN STID CXA2064M Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. MAININ – 18 – CXA2064M Input level vs. Distortion characteristics 1 (MONO) Input signal: MONO (Pre-emphasis on), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF Measurement point: TVOUT-L/R Input level vs. Distortion characteristics 2 (Stereo) Input signal: Stereo L = –R (dbx-TVNR ON), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, ST mode Measurement point: TVOUT-L/R 1.0 10 Distortion [%] Distortion [%] 0.1 1.0 Standard level (100%) –10 0 Input level [dB] –10 10 Standard level (100%) 0 Input level [dB] 10 Input level vs. Distortion characteristics 3 (SAP) Input signal: SAP (dbx-TVNR ON) 1kHz, 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, SAP mode Measurement point: TVOUT-L/R 10 Distortion [%] 1.0 Standard level (100%) –10 0 Input level [dB] 10 – 19 – CXA2064M Stereo LPF frequency characteristics 10 Main LPF and Sub LPF frequency characteristics 30 5 Gain (FC main and FC sub) [dB] 20 10 0 –10 –20 –30 –40 –50 Gain [dB] 0 –5 –10 0 20 40 60 80 100 1 2 5 7 10 20 50 70 100 Frequency [kHz] Frequency [kHz] SAP frequency characteristics and group delay 100 20 5fH 10 Gain 90 80 Gain [dB] 60 0 50 40 –10 Group delay 3.8fH 20 40 60 80 30 20 –20 6.2fH 100 10 0 120 Frequency [kHz] – 20 – Group delay [µs] 70 CXA2064M Package Outline Unit: mm 30PIN SOP(PLASTIC) + 0.4 2.3 – 0.15 0.1 16 + 0.4 18.8 – 0.1 30 10.3 ± 0.4 + 0.3 7.6 – 0.1 + 0.2 0.1 – 0.05 (9.3) 15 1 0.45 ± 0.1 1.27 0.2 M + 0.1 0.2 – 0.05 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-30P-L03 SOP030-P-0375 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.7g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 21 – 0.5 ± 0.2 A