CXA2089Q

CXA2089Q/S S2-Compatible 5-Input 2-Output Audio/Video Switch Description The CXA2089Q/S is a 5-input, 2-output audio/video switch featuring I2C bus compatibility for TVs. This IC has input pins that are compatible with S2 protocol. Features • 3 inputs that are compatible with S2 protocol • Serial control with I2C bus • 5 inputs, 2 outputs • The desired inputs can be selected independently for each of the 2 outputs • Wide band video amplifier (20MHz, –3dB) • Y/C MIX circuit • Slave address can be changed (90H/92H) • Audio muting from external pin • High impedance maintained by I2C bus lines (SDA, SCL) even when power is OFF • Wide audio dynamic range (3Vrms typ.) Applications Audio/video switch featuring I2C bus compatibility for TVs Structure Bipolar silicon monolithic IC CXA2089Q 48 pin QFP (Plastic) CXA2089S 48 pin SDIP (Plastic) Absolute Maximum Ratings • Supply voltage VCC • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation PD Operating Conditions Supply voltage 12 –20 to +75 –65 to +150 1500 V °C °C mW 9 ± 0.5 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97431B7Z-PS CXA2089Q/S Block Diagram CXA2089Q TV 47 V1 1 V2 8 V3 15 V4 23 42 TRAP1 6dB 6dB 40 VOUT1 36 YIN1 43 YOUT1 6dB 45 COUT1 38 CIN1 Y1 3 6dB 33 VOUT2 Y2 10 Y3 17 6dB 31 YOUT2 C1 5 6dB 29 COUT2 44 GND C2 12 C3 19 BIAS S2-1 6 37 BIAS 34 VCC 28 DC OUT Logic 26 SCL 27 SDA 25 ADR 35 MUTE 6dB 39 LOUT1 0dB 6dB 41 ROUT1 0dB RTV 48 RV1 4 RV2 11 RV3 18 RV4 24 6dB 32 ROUT2 6dB 30 LOUT2 S2-2 13 S2-3 20 S-1 7 S-2 14 S-3 21 LTV 46 LV1 LV2 2 9 LV3 16 LV4 22 Audio system is attenuated by 6dB for 6kΩ resistor input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to –6dB). –2– CXA2089Q/S CXA2089S TV 5 V1 7 6dB 46 VOUT1 42 YIN1 6dB 1 YOUT1 V2 14 V3 21 V4 29 48 TRAP1 6dB 3 COUT1 44 CIN1 Y1 9 6dB 39 VOUT2 Y2 16 Y3 23 6dB 37 YOUT2 C1 11 C2 18 C3 25 6dB 35 COUT2 2 GND BIAS S2-1 12 S2-2 19 S2-3 26 S-1 13 S-2 20 S-3 27 6dB Logic 43 BIAS 40 VCC 34 DC OUT 32 SCL 33 SDA 31 ADR 41 MUTE LTV LV1 4 8 45 LOUT1 0dB 6dB 47 ROUT1 0dB LV2 15 LV3 22 LV4 28 RTV 6 RV1 10 RV2 17 RV3 24 RV4 30 6dB 36 LOUT2 6dB 38 ROUT2 Audio system is attenuated by 6dB for 6kΩ resistor input, and a total gain is 0dB (LOUT1 and ROUT1 can be changed to –6dB). –3– CXA2089Q/S Pin Configuration MUTE LOUT2 YIN1 SDA 36 35 34 33 32 31 30 29 28 27 26 25 BIAS 37 CIN1 38 LOUT1 39 VOUT1 40 ROUT1 41 TRAP1 42 YOUT1 43 GND 44 COUT1 45 LTV 46 TV 47 RTV 48 VCC SCL ADR 24 RV4 23 V4 22 LV4 21 S-3 20 S2-3 19 C3 18 RV3 17 Y3 16 LV3 15 V3 14 S-2 13 S2-2 CXA2089Q 1 2 3 4 5 6 COUT2 8 7 9 10 11 12 S-1 V1 DC OUT ROUT2 VOUT2 YOUT2 S2-1 RV1 CXA2089S ROUT1 ROUT2 VOUT1 VOUT2 YOUT2 LOUT1 TRAP1 MUTE LOUT2 COUT2 CIN1 DC OUT BIAS YIN1 RV2 C1 LV1 LV2 Y1 V2 C2 Y2 ADR RV4 VCC LV4 S-3 S2-3 Y3 SDA SCL 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TV V4 RV1 LTV COUT1 LV2 GND LV1 YOUT1 S2-2 LV3 Y2 Y1 S-1 S-2 V1 V2 V3 S2-1 RTV –4– RV2 RV3 C1 C2 C3 CXA2089Q/S Pin Description Pin No. Symbol Pin voltage Equivalent circuit Pin numbers in brackets are for the CXA2089S. Description VCC 47 (5) 1 (7) 8 (14) 15 (21) 23 (29) TV V1 V2 V3 V4 47 15 150 3µA 4.0V 1 23 8 Video signal inputs. Input composite video signals. VCC 3 (9) 10 (16) 17 (23) 36 (42) Y1 Y2 Y3 YIN1 3 150 3µA 4.0V 10 17 36 Y/C separation signal inputs. Input luminance signals. The YIN1 pin inputs the signal obtained by Y/C separating the VOUT1 pin output. VCC 5 (11) 12 (18) 19 (25) 38 (44) C1 C2 C3 CIN1 20k 5 4.5V 150 27k 12 19 38 Y/C separation signal inputs. Input chrominance signals. The CIN1 pin inputs the signal obtained by Y/C separating the VOUT1 pin output. 46 (4) 2 (8) 9 (15) 16 (22) 22 (28) 48 (6) 4 (10) 11 (17) 18 (24) 24 (30) LTV LV1 LV2 LV3 LV4 RTV RV1 RV2 RV3 RV4 46 48 2 4 VCC 33k 27k 4.5V 9 11 16 18 22 24 15k Audio signal inputs. VCC 250 VCC 40 (46) VOUT1 33 (39) VOUT2 3.9V 40 33 30k 27k 23.5k Video signal outputs. Output composite video signals. –5– CXA2089Q/S Pin No. Symbol Pin voltage Equivalent circuit VCC VCC VCC Description 43 (1) YOUT1 3.3V 43 31 VCC Video signal outputs. Output luminance signals. 31 (37) YOUT2 3.5V VCC VCC VCC VCC 45 (3) COUT1 29 (35) COUT2 4.5V 45 29 Video signal outputs. Output chrominance signals. VCC VCC 56 20k 20k 39 (45) 30 (36) 41 (47) 32 (38) LOUT1 LOUT2 ROUT1 ROUT2 39 4.5V 30 41 32 Audio signal outputs. Zo = 50Ω (within DC ± 2mA) VCC VCC VCC 6 (12) S2-1 13 (19) S2-2 20 (26) S2-3 — 6 13 20 147 100k Detects the S2-compatible DC superimposed onto the C signal. 4:3 video signal at 1.3V or less 4:3 letter-box signal at 1.3V or more to 2.5V or less 16:9 picture squeezed signal at 2.5V or more These pins are pulled down to GND by a 100kΩ resistor, so the 4:3 video signals are selected when open. Composite video/S selector. The detection results are written to the status register. S signal at 3.5V or less Composite video signal at 3.5V or more These pins are pulled up to 5V by a 100kΩ resistor, so the composite video signals are selected when open. Selects the slave address for the I2C bus. 90H at 1.5V or less 92H at 2.5V or more 90H when open 5V VCC 50k 50k VCC 7 (13) S-1 14 (20) S-2 21 (27) S-3 VCC 100k — 7 14 21 10k VCC 147 25 28k 72k 25 (31) ADR — –6– CXA2089Q/S Pin No. Symbol Pin voltage Equivalent circuit VCC Description 26 (32) SCL — 4k 26 10k I2C bus signal input VILmax = 1.5V VIHmin = 3.0V VCC 27 (33) SDA — 27 4k I2C bus signal input VILmax = 1.5V VIHmin = 3.0V VOLmax = 0.4V VCC 4k 28 28k 1k 28 (34) DC OUT — Q1 Outputs the S2-compatible DC superimposed onto the COUT2 output. The DC is superimposed by connecting this pin to the COUT2 output via a capacitor. Control is performed by the I2C bus. When 0V is output, Q1 is ON and the impedance is 5kΩ. S2 protocol output DC impedance of 10 ± 3kΩ is realized by attaching external resistance of 4.7kΩ. DC OUT (bus) Output DC 0 4.5V 1 0V 2 1.9V 3 4.5V VCC 100 42 (48) TRAP1 3.8V 42 1k Connects trap circuit for subcarrier. VCC 147 35 28k 72k 35 (41) MUTE — Audio signal output mute. Mute OFF at 1.5V or less Mute ON at 2.5V or more Mute OFF when open VCC VCC VCC 147 37 (43) BIAS 4.5V 37 20k 20k Internal reference bias (Vcc/2). Connects to GND via a capacitor. –7– CXA2089Q/S Electrical Characteristics Item Current consumption Symbol ICC Conditions No signal, no load Min. 30 (Ta = 25°C, VCC = 9V) Typ. 45 Max. 62 Unit mA Video system (Measurement circuit; Fig. 1) Gain Frequency response characteristics Frequency response characteristics (Y/C mix) Input dynamic range Cross talk GVv FBWv1 f = 100kHz, 0.3Vp-p input f = 100kHz, input frequency where output amplitude is –3dB with 0.3Vp-p output serving as 0dB f = 100kHz, maximum with distortion < 1.0% f = 4.43MHz, 1Vp-p input 5.9 15 6.4 20 6.9 — dB MHz FBWv2 10 15 — MHz Ddv Vctv 1.4 — — — — –50 Vp-p dB Audio system (Measurement circuits; Fig. 2 to Fig. 5) Gain Frequency response characteristics Total harmonic distortion Input dynamic range Cross talk Ripple rejection ratio Output DC offset Residual noise GVA f = 1kHz, 1Vp-p input, 5.7kΩ resistor inserted to input f = 1kHz, input frequency where output amplitude is –3dB with 1Vp-p output serving as 0dB f=1kHz, 2.2Vp-p input, where 400Hz HPF + 80kHz LPF are inserted f=1kHz, maximum with distortion < 0.3% f=1kHz, 1Vp-p input f=100Hz, 0.3Vp-p applied to Vcc Offset voltage between input and output When 400Hz HPF+ 30kHz LPF are inserted f=1kHz, 1Vrms input When 400Hz HPF + 30kHz LPF are inserted –1 0 1 dB FBWA 50 — — kHz THD DdA VctA VctA Voff VNA — 2.8 — — –30 0 0.03 3.0 –90 –55 — 20 0.05 — –80 –40 30 30 % Vrms dB dB mV µVrms S/N ratio S/N –100 –90 dB –8– CXA2089Q/S Logic system Item High level input voltage Low level input voltage Symbol VIH VIL With SDA 3mA current supplied VIH = 4.5V VIL = 0.4V Conditions Min. 3.0 0 0 0 0 0 4.7 4.0 4.7 4.0 4.7 150 0 — — 4.7 Typ. — — — — — — — — — — — — — — — — Max. 5.0 1.5 0.4 10 10 100 — — — — — — — 1 300 — Unit V V V µA µA kHz µs µs µs µs µs ns ns µs ns µs Low level output voltage VOL High level input current Low level input current Maximum clock frequency Minimum waiting time for data change Minimum waiting time for data transfer start Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation IIH IIL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO –9– Electrical Characteristics Measurement Circuit Measurement point 75 1k 0.47µ 22µ 36 34 29 33 30 25 31 28 27 26 35 32 10µ 10µ 10k 10µ 10k 10µ 10k 10µ µ-com 10k 10k VCC SDA SCL MUTE ROUT2 COUT2 75 75 600 38 CIN1 V4 23 1µ 39 LOUT1 LV4 22 S-3 21 S2-3 20 0.1µ 42 TRAP1 C3 19 1µ 43 YOUT1 RV3 18 0.47µ 44 10µ 45 1µ 46 0.47µ 47 1µ 48 RTV S2-2 13 TV S-2 14 LTV V3 15 COUT1 LV3 16 0.47µ 75 GND Y3 17 1µ 600 75 600 10µ 75 10µ 40 VOUT1 10µ 41 ROUT1 10µ 0.1µ 0.47µ 10k 10k 10k 10k 10k 600 75 600 V1 Y1 C1 DC OUT BIAS RV4 VOUT2 YOUT2 LOUT2 37 24 YIN1 LV1 RV1 S2-1 V2 Y2 1 2 3 0.47µ 1µ 1µ 75 600 75 600 75 75 0.1µ 7 4 0.47µ 5 6 S-1 LV2 8 0.47µ 1µ 9 RV2 10 0.47µ 11 1µ 75 600 600 12 0.1µ C2 ADR 10µ 1µ 600 – 10 – 75 Input signal Signal is input from one of the following pins: 1, 3, 5, 8, 10, 12, 15, 17, 19, 23 and 47. Output signal is measured from one of the following pins: 29, 31, 33, 40, 43 and 45. CXA2089Q/S Fig. 1-a. Video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit (CXA2089Q) Measurement point µ-COM +9V 10k 10k 10µ 0.47µ 22µ 40 39 36 34 33 29 31 27 30 28 38 32 37 35 43 42 41 1k 10µ 10µ 10µ 10µ 10µ 1µ 0.47µ 1µ 26 0.1µ 25 10k 10k 10k 75 75 10k 10k 10k 600 75 600 75 10µ 10µ 10µ 0.1µ 48 47 46 45 44 V4 VCC SDA SCL ADR RV4 LV4 S-3 TRAP CIN1 BIAS YIN1 MUTE LOUT1 VOUT1 VOUT2 YOUT2 LOUT2 ROUT1 ROUT2 COUT2 DC-OUT S2-3 LV3 22 23 COUT1 RTV Y1 S2-1 LV2 C2 YOUT1 LTV V1 RV1 S-1 Y2 S2-2 V3 – 11 – LV1 C1 6 7 0.47µ 1µ 600 75 75 75 75 600 600 0.47µ 1µ 0.1µ 0.47µ 1µ 8 11 15 9 10 12 14 16 17 13 GND TV V2 RV2 1 0.47µ 1µ 600 75 2 3 4 5 18 19 0.1µ S-2 20 21 Y3 0.47µ 1µ 600 24 0.47µ 1µ 10µ 10µ 1µ 0.47µ 1µ 600 75 600 10k 75 75 75 RV3 600 10k Signal is input from one of the following pins: 5, 7, 9, 11, 14, 16, 18, 21, 23, 25 and 29. Output signal is measured from one of the following pins: 1, 3, 35, 37, 39 and 46. Input signal CXA2089Q/S Fig. 1-b. Video system (gain, frequency response characteristics, input dynamic range, cross talk) measurement circuit (CXA2089S) C3 Measurement point 75 1k 0.47µ 22µ 36 34 29 33 30 25 31 28 27 26 35 32 10µ 10µ 10µ 10k 10µ 10k 10µ µ-com 10k 10k 10k VCC SDA SCL MUTE ROUT2 VOUT2 YOUT2 LOUT2 DC OUT BIAS 0.47µ 75 V4 23 5.7k 1µ 600 LV4 22 S-3 21 S2-3 20 0.1µ 75 C3 19 5.7k 1µ 600 RV3 18 0.47µ 75 Y3 17 5.7k 1µ 600 LV3 16 0.47µ 75 V3 15 S-2 14 S2-2 13 75 38 CIN1 10k 39 LOUT1 10k 40 VOUT1 10k 41 ROUT1 42 TRAP1 10k 43 YOUT1 44 GND COUT1 10k 45 1µ 5.7k 46 LTV 75 47 TV RTV 1µ 5.7k 48 0.47µ 10µ 10µ 10µ 10µ 10µ 0.1µ 600 600 LV1 RV1 S2-1 V2 COUT2 37 RV4 24 YIN1 V1 Y1 C1 S-1 LV2 RV2 1 2 3 0.47µ 5.7k 1µ 75 600 600 75 0.1µ 5.7k 0.47µ 1µ 75 4 5 6 7 0.47µ 75 8 5.7k 1µ 9 Y2 10 11 0.47µ 5.7k 1µ 75 600 75 600 12 0.1µ Input signal Signal is input from one of the following pins: 2, 4, 9, 11, 16, 18, 22, 24, 46 and 48. Output signal is measured from one of the following pins: 30, 32, 39 and 41. CXA2089Q/S Fig. 2-a. Audio system (gain, frequency response characteristics, total harmonic distortion, input dynamic range, cross talk) measurement circuit (CXA2089Q) C2 ADR 10µ 600 5.7k 1µ – 12 – Measurement point µ-COM +9V 600 10k 75 10k 1µ 5.7k 22µ 41 34 29 40 39 36 33 31 27 26 30 28 38 32 37 35 10µ 10µ 10µ 10µ 10µ 5.7k 0.47µ 25 0.1µ 75 10k 10k 10k 1µ 75 600 10k 10k 10k 75 10µ 43 42 10µ 10µ 0.1µ 10µ 0.47µ 1k 48 47 46 45 44 V4 VCC SDA SCL ADR RV4 LV4 S-3 TRAP CIN1 BIAS YIN1 MUTE LOUT1 VOUT1 VOUT2 YOUT2 LOUT2 ROUT1 ROUT2 COUT2 DC-OUT S2-3 23 COUT1 RTV Y1 S2-1 LV2 C2 V3 YOUT1 LTV V1 RV1 S-1 Y2 S2-2 LV3 GND TV LV1 C1 – 13 – 6 7 8 11 15 9 10 12 14 16 17 13 18 0.47µ 5.7k 0.47µ 5.7k 0.1µ 1µ 75 75 75 75 1µ 1µ 1µ 75 1µ 75 600 600 600 600 600 V2 RV2 1 2 3 4 5 19 S-2 20 21 22 Y3 24 0.47µ 5.7k 0.47µ 5.7k 1µ 75 75 600 600 1µ 10µ 10µ 5.7k 0.47µ 5.7k 0.47µ 5.7k 0.47µ 5.7k 0.1µ 10k 10k 1µ 75 600 Signal is input from one of the following pins: 4, 6, 8, 10, 15, 17, 22, 24, 28 and 30. Output signal is measured from one of the following pins: 36, 38, 45 and 47. Input signal CXA2089Q/S Fig. 2-b. Audio system (gain, frequency response characteristics, total harmonic distortion, input dynamic range, cross talk) measurement circuit (CXA2089S) RV3 C3 Measurement point Input signal 75 1k 0.47µ 36 34 29 33 30 25 31 28 27 26 35 32 10µ 10µ 10µ 10k 10µ 10k 10µ µ-com 10k 10k 10k VCC SDA SCL MUTE ROUT2 VOUT2 YOUT2 LOUT2 DC OUT BIAS RV4 0.47µ 75 600 V4 23 1µ LV4 22 S-3 21 S2-3 20 0.1µ 75 1µ 600 0.47µ 75 Y3 17 1µ 600 LV3 16 0.47µ 75 V3 15 S-2 14 S2-2 13 C3 19 RV3 18 CIN1 LOUT1 75 38 10k 39 10k 40 VOUT1 10k 41 ROUT1 42 10k 43 YOUT1 44 10k 45 600 46 LTV 75 47 600 48 RTV 1µ TV 0.47µ 1µ COUT1 10µ GND 10µ TRAP1 10µ 10µ 10µ 0.1µ COUT2 37 24 YIN1 LV1 RV1 S2-1 V2 Y2 V1 Y1 C1 1 2 3 0.47µ 0.47µ 75 600 75 600 75 1µ 1µ 0.1µ 4 5 6 S-1 LV2 7 0.47µ 75 8 1µ 600 9 RV2 10 0.47µ 1µ 75 600 11 12 0.1µ 75 A f=100Hz, 0.3Vp-p signal is applied to Vcc and the output signals from Pins 30, 32, 39 and 41 are measured. CXA2089Q/S Fig. 3-a. Audio system (ripple rejection ratio) measurement circuit (CXA2089Q) C2 ADR 10µ 600 1µ – 14 – Measurement point µ-COM +9V 10k 10k 10k 600 75 10k 10µ 0.47µ 43 42 41 34 33 36 31 40 39 30 38 32 37 35 29 1k 10µ 10µ 10µ 10µ 10µ 1µ 0.47µ 1µ 28 27 26 25 10k 0.1µ 600 75 Input signal 10k 75 75 10k 10k 10µ 44 10µ 10µ 0.1µ 48 47 46 45 V4 VCC SDA SCL ADR RV4 LV4 S-3 TRAP CIN1 BIAS YIN1 MUTE LOUT1 VOUT1 VOUT2 YOUT2 LOUT2 ROUT1 ROUT2 COUT2 DC-OUT S2-3 V3 S2-2 LV3 19 COUT1 RTV Y1 S2-1 LV2 YOUT1 LTV V1 RV1 S-1 Y2 C2 GND TV LV1 C1 1 5 7 0.47µ 1µ 0.47µ 1µ 0.1µ 8 11 10 12 14 0.47µ 1µ 9 2 3 4 6 13 V2 RV2 15 16 17 0.47µ 1µ 18 S-2 20 0.1µ 21 22 0.47µ 1µ 23 Y3 600 75 600 75 75 600 75 24 0.47µ 1µ 10µ 10µ 1µ 0.47µ 1µ 10k 10k 600 75 600 75 600 75 600 75 75 RV3 600 A f=100Hz, 0.3Vp-p signal is applied to Vcc and the output signals from Pins 36, 38, 45 and 47 are measured. CXA2089Q/S Fig. 3-b. Audio system (ripple rejection ratio) measurement circuit (CXA2089S) C3 – 15 – Measurement point 75 10k 10µ µ-com 10µ 22µ 36 34 29 33 30 25 31 28 27 26 35 32 10µ 10µ 1k 0.47µ 10k 10k 10k 10µ 10k VCC SDA SCL MUTE VOUT2 YOUT2 LOUT2 ROUT2 75 38 CIN1 V4 23 1µ 600 39 LOUT1 LV4 22 S-3 21 S2-3 20 0.1µ 42 TRAP1 C3 19 1µ 600 43 YOUT1 RV3 18 0.47µ 44 10µ 45 1µ 46 LTV 47 1µ 48 RTV S2-2 13 TV V3 15 S-2 14 COUT1 LV3 16 0.47µ 75 GND Y3 17 1µ 600 75 10µ 75 10µ 40 VOUT1 10µ 41 ROUT1 10µ 0.1µ 0.47µ 75 10k 10k 10k 10k 10k 600 75 0.47µ 600 DC OUT BIAS RV4 COUT2 37 24 YIN1 LV1 RV1 S2-1 V2 Y2 V1 Y1 C1 1 2 3 0.47µ 0.47µ 75 600 600 1µ 75 1µ 75 0.1µ 7 4 5 6 S-1 LV2 8 9 RV2 10 0.47µ 11 12 0.1µ 0.47µ 75 1µ 75 600 1µ 75 600 Measurement point CXA2089Q/S Fig. 4-a. Audio system (output DC offset voltage) measurement circuit (CXA2089Q) C2 ADR 10µ 600 1µ – 16 – Measurement point µ-COM +9V 10k 75 75 0.47µ 1k 22µ 40 39 36 34 33 29 31 27 30 28 38 32 37 35 26 10µ 10µ 10µ 10µ 10µ 1µ 1µ 41 0.1µ 25 10k 600 10k 10k 10k 600 75 10k 10k 10k 75 0.1µ 10µ 43 42 10µ 10µ 10µ 0.47µ 48 47 46 45 44 V4 VCC SDA SCL ADR RV4 LV4 S-3 TRAP CIN1 BIAS YIN1 MUTE LOUT1 VOUT1 VOUT2 YOUT2 LOUT2 ROUT1 ROUT2 COUT2 DC-OUT S2-3 LV3 22 23 COUT1 RTV Y1 S2-1 LV2 C2 YOUT1 LTV V1 RV1 S-1 Y2 S2-2 V3 – 17 – LV1 C1 6 7 1µ 0.47µ 600 75 600 75 600 75 75 600 0.47µ 0.47µ 0.47µ 75 600 75 1µ 1µ 0.1µ 1µ 1µ 8 11 15 9 10 12 14 16 17 13 GND TV V2 RV2 1 2 3 4 5 18 19 0.1µ S-2 20 21 0.47µ Y3 1µ 75 600 75 24 0.47µ 1µ 10µ 10µ 1µ 0.47µ 10k 10k 600 75 RV3 600 Measurement point CXA2089Q/S Fig. 4-b. Audio system (output DC offset voltage) measurement circuit (CXA2089S) C3 Measurement point 75 10k 1k 0.47µ 22µ 36 34 29 33 25 31 30 28 27 26 35 32 10µ 10µ 10µ 10k 10µ 10k 10µ µ-com 10k 10k 4.5V VCC SDA SCL MUTE ROUT2 VOUT2 YOUT2 LOUT2 DC OUT BIAS RV4 0.47µ 75 600 V4 23 1µ LV4 22 S-3 21 S2-3 20 0.1µ 75 1µ 600 RV3 18 0.47µ 75 Y3 17 1µ 600 LV3 16 0.47µ 75 V3 15 S-2 14 S2-2 13 C3 19 CIN1 LOUT1 VOUT1 75 38 10k 39 10k 40 10k 41 ROUT1 42 10k 43 YOUT1 44 10k 45 600 46 LTV 75 47 600 48 RTV 1µ TV 0.47µ 1µ COUT1 10µ GND 10µ TRAP1 10µ 10µ 10µ 0.1µ COUT2 37 24 YIN1 V1 Y1 C1 S-1 LV2 RV2 LV1 RV1 S2-1 1 2 3 0.47µ 0.47µ 75 600 75 600 1µ 1µ 75 4 5 6 V2 7 0.47µ 8 1µ 9 Y2 10 0.47µ 1µ 11 12 0.1µ C2 ADR 10µ 600 1µ – 18 – 75 600 75 600 75 0.1µ CXA2089Q/S Fig. 5-a. Audio system (residual noise) measurement circuit (CXA2089Q) Measurement point µ-COM +9V 10k 75 0.1µ 10µ 0.47µ 22µ 40 39 36 34 33 31 30 38 32 37 35 29 44 42 41 43 1k 10µ 10µ 10µ 10µ 10µ 1µ 0.47µ 1µ 28 27 26 0.1µ 25 75 75 10k 10k 10k 10k 600 600 75 10k 10k 10k 10µ 10µ 10µ 48 47 46 45 V4 VCC SDA SCL ADR RV4 LV4 S-3 TRAP CIN1 BIAS YIN1 MUTE LOUT1 VOUT1 VOUT2 YOUT2 LOUT2 ROUT1 ROUT2 COUT2 DC-OUT S2-3 V3 S2-2 LV3 19 COUT1 RTV Y1 S2-1 LV2 YOUT1 LTV V1 RV1 S-1 Y2 C2 GND TV LV1 C1 1 5 7 1µ 0.47µ 75 600 75 600 75 600 75 0.47µ 0.47µ 75 1µ 1µ 0.1µ 8 11 10 12 14 9 2 3 4 6 13 V2 RV2 15 1µ 16 17 1µ 0.47µ 600 75 18 S-2 20 0.1µ 21 0.47µ 22 1µ 23 Y3 600 75 75 600 75 24 0.47µ 1µ 10µ 10µ 1µ 0.47µ 10k 10k 600 RV3 600 CXA2089Q/S Fig. 5-B. Audio system (residual noise) measurement circuit (CXA2089S) C3 – 19 – CXA2089Q/S I2C BUS Control Signal 34 SDA tBUF 33 SCL tLOW tHD;STA P S tR tHD;DAT S P tHIGH tF tSU;DAT tSU;STA tSU;STO Fig. 6. I2C BUS Control Signal Timing Chart Description of Operation The CXA2089Q/S is a TV I2C bus-compatible AV switch IC. The video system and the stereo audio system both have 5 inputs and 2 outputs each. 3 of the 5 video system inputs support S2 and S protocols. The desired inputs can be independently assigned to each output (in the audio system, the left and right channels are processed as one unit) by I2C bus control. However, the same input is assigned to both the video and audio system output 2. I2C BUS Registers 1) I2C BUS The I2C bus (inter-IC bus) is an inter-IC bus system developed by Philips. Two lines (SDA – serial data, SCL – serial clock) provide control over start, stop, data transfer, synchronization, and collision avoidance. The IC outputs are either open collector or open drain, forming a bus line in the wired OR format. SDA A A MSB LSB MSB LSB SCL S 1 2 3 4 5 6 7 8 9 1 2 9 S: Start condition; SDA is set "Low" when SCL is "High" P: Stop condition; SDA is set "High" when SCL is "High" A: Acknowledge; signal sent from the slave P Data is transmitted by MSB-first. One data unit consists of 8 bits, to which the acknowledge signal, which indicates that the data has been accepted by the slave, is attached at the end. Normally, the slave∗1 IC receives data at the rising edge of SCL and the master∗2 IC changes data at the falling edge of SCL. ∗1 Slave: An IC that is placed under the control of the master. In a normal system, all devices excluding the central microcomputer are slaves. ∗2 Master: A central microcomputer or other controlling IC. – 20 – CXA2089Q/S 2) Control Registers The CXA2089Q/S control is exercised by writing 2-byte data into the two 8-bit control registers which control the output selector circuits for the 2 outputs. S Slave address A DATA1 A DATA2 AP S: Start condition A: Acknowledge P: Stop condition Control register structure (DATA1 and DATA2) • All registers are set to "0" during IC power on. • "∗" indicates undefined. b7 Slave add. DATA1 DATA2 1 A-GAIN ∗ b6 0 S/COMP1 S/COMP2 b5 0 b4 1 V-IN1 AV-IN2 b3 0 b2 0 b1 ADR A-IN1 DC OUT ∗ b0 R/W R/W (1): Read/write mode 0: Control data write 1: Status register read ADR (1): This bit sets the slave address set by the address pin. 0: 90H 1: 92H A-GAIN (1): LOUT1/ROUT1 output gain selector 0: 0dB output 1: –6dB output S/COMP1 and S/COMP2 (1 each): S terminal input/composite signal input selectors By setting S/COMP1 to "0", when composite signal input is selected, YOUT1/COUT1 output the inputs from YIN1/CIN1. 0: Composite signal inputs (TV, V1 to V4 inputs) 1: S terminal inputs (Y1/C1 to Y3/C3 inputs) V-IN1 (3 each): This bit selects the input signals output to each video output. 0: Mute 1: Selects the TV input 2: Selects the V1 and Y1/C1 inputs 3: Selects the V2 and Y2/C2 inputs 4: Selects the V3 and Y3/C3 inputs 5: Selects the V4 inputs 6: Mute 7: Mute – 21 – CXA2089Q/S A-IN1 (3 each): This bit selects the input signals output to each audio output. 0: Mute 1: Selects the LTV/RTV inputs 2: Selects the LV1/RV1 inputs 3: Selects the LV2/RV2 inputs 4: Selects the LV3/RV3 inputs 5: Selects the LV4/RV4 inputs 6: Mute 7: Mute AV-IN2 (3): This bit selects the input signals output to output 2 (VOUT2, YOUT2/COUT2, LOUT2/ROUT2). Note) Both the video output and the audio output are selected at the same time only for AV-IN2. 0: Mute 1: Selects the TV and LTV/RTV inputs 2: Selects the V1, Y1/C1 and LV1/RV1 inputs 3: Selects the V2, Y2/C2 and LV2/RV2 inputs 4: Selects the V3, Y3/C3 and LV3/RV3 inputs 5: Selects the V4 and LV4/RV4 inputs 6: Mute 7: Mute DC OUT (2): This bit sets the DC voltage output from DC OUT. 0: 4.5V 1: 0V 2: 1.9V 3: 4.5V 3) Status Registers • When reading two bytes S Slave address A DATA1 A DATA2 NA P • When reading one byte S Slave address A DATA1 NA P S: Start condition A: Acknowledge NA: No acknowledge P: Stop condition When communication is to be terminated in the status register reading mode, the no-acknowledge signal is needed to assure that the master does not issue the acknowledge signal to the slave. It is possible to read only DATA1 of the status register by sending the no-acknowledge signal after DATA1. – 22 – CXA2089Q/S Status register structure (DATA1 and DATA2) "∗" indicates undefined. b7 Slave add. DATA1 DATA2 1 S1SEL S1SEL b6 0 S2SEL S2SEL b5 0 S3SEL S3SEL b4 1 ∗ ∗ b3 0 S-C1 S-C3 b2 0 b1 ADR S-C2 ∗ b0 1 S1SEL to S3SEL (1 each): S-1 to S-3 pin status 0: S-1 to S-3 pins are not grounded. 1: S-1 to S-3 pins are grounded. S1SEL to S3SEL are actually determined by comparing the S-1 to S-3 pin DC voltages with 3.5V. S-1 to S-3 pin DC voltage 3.5V or more 3.5V or less S1SEL to S3SEL 0 1 S-C1, S-C2, S-C3 (2 each): S2-1, S2-2 and S2-3 pin status 0: 4:3 video signal 1: 4:3 letter-box signal 2: 16:9 video squeezed signal 3: No signal S-C1 to S-C3 are actually determined by comparing the S2-1 to S2-3 pin DC voltages with two threshold. However, when the S-1 to S-3 pins are open, the outputs are fixed to "3". S2-1 to S2-3 pin DC voltage 1.3V or less 1.3V or more to 2.5V or less 2.5V or more S-1 to S-3 OPEN S-C1 to S-C3 0 1 2 3 4) Power-on Reset The CXA2089Q/S has an internal power-on reset function that sets each control register to "0" during IC power ON. The power-on reset VTH has hysteresis. Power-on reset released Power-on reset VCC 4.5V 5.6V – 23 – Application Circuit (CXA2089Q) µ-com VIDEO 2 output 75 0.1µ 0.47µ 22µ 36 34 29 33 30 25 31 28 27 26 35 32 4.7k 220 220 1k 10µ 10µ 10µ 10µ • Depending on the output bias of the comb filters, pay attention to the polarities of the capacitors since the bias at Pins 36 and 38 is approximately 3.1V and 4.5V, respectively. • Connect Pin 25 to Vcc when setting the slave address of the IC to 92H. • The audio output can be muted by setting Pin 35 to 3.5V or more. • The TRAP (Pin 42) are of 3.58MHz subcarrier. • Pay attention to the polarities of the capacitors since each output of video system and audio system has optional bias, respectively. 1.2k 1µ 24 0.47µ V4 23 1.2k 1µ 75 VIDEO 4 input VCC SDA SCL ADR RV4 LV4 22 S-3 21 1µ S2-3 20 0.1µ 75 C3 19 1.2k 1µ RV3 18 0.47µ Y3 17 1.2k 1µ LV3 16 0.47µ V3 15 S-2 14 S2-2 13 470k 75 470k 75 VIDEO 3 input 12 0.1µ 75 1µ MUTE ROUT2 VOUT2 YOUT2 LOUT2 COUT2 0.1µ 38 CIN1 39 LOUT1 40 VOUT1 41 ROUT1 42 TRAP1 43 YOUT1 44 GND 45 COUT1 46 LTV 47 TV 48 RTV COMB FILTER 10µ 10µ VIDEO 1 output 10p 620 LV1 V1 Y1 C1 S-1 LV2 RV2 V2 8 9 10 RV1 1 2 3 0.47µ 1.2k 1µ 75 470k 75 1µ 0.1µ 7 4 0.47µ 1.2k 1µ 470k 75 5 S2-1 6 Y2 11 0.47µ 1.2k 0.47µ 1.2k 1µ 1µ 75 470k 75 470k CXA2089Q/S VIDEO 1 input VIDEO 2 input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. C2 – 24 – 180µ 10µ 1µ 1.2k 75 0.47µ TV input 1µ 1.2k DC OUT 37 BIAS YIN1 10µ Application Circuit (CXA2089S) µ-COM Video2 output +9V COMB FILTER 75 4.7k 1µ 0.1µ 220 1.2k 28 27 26 25 1k 22µ 41 34 29 40 39 36 33 31 30 38 32 37 35 10µ 10µ 10µ 10µ 75 0.1µ 1µ Video4 input Video1 output 10p 180µ 10µ 0.47µ 43 42 10µ 10µ 620 0.1µ 1µ 75 220 1.2k 0.47µ 48 47 46 45 44 V4 VCC SDA SCL ADR RV4 LV4 S-3 TRAP CIN1 BIAS YIN1 MUTE LOUT1 VOUT1 VOUT2 YOUT2 LOUT2 ROUT1 ROUT2 COUT2 DC-OUT S2-3 V3 LV3 21 22 23 COUT1 RTV Y1 S2-1 LV2 C2 YOUT1 LTV V1 RV1 S-1 Y2 S2-2 GND TV LV1 C1 1 7 0.47µ 1.2k 0.1µ 75 1µ 75 1µ 470k 1µ 470k 75 1µ 1µ 470k 8 11 15 9 10 12 14 16 2 3 4 5 6 13 V2 RV2 17 18 19 0.1µ 20 S-2 Y3 75 75 1µ 75 1µ 24 0.47µ 1.2k 0.47µ 1.2k 10µ 75 75 10µ 1.2k 0.47µ 1.2k 0.47µ 1.2k 0.47µ 1.2k 0.47µ 1.2k 75 1µ 470k RV3 1µ 470k 470k Video3 input 1µ TV input Video1 input Video2 input • Depending on the output bias of the comb filters, pay attention to the polarities of the capacitors since the bias at Pins 42 and 44 is approximately 3.1V and 4.5V, respectively. • Connect Pin 31 to Vcc when setting the slave address of the IC to 92H. • The audio output can be muted by setting Pin 41 to 3.5V or more. • The TRAP (Pin 48) are of 3.58MHz subcarrier. • Pay attention to the polarities of the capacitors since each output of video system and audio system has optional bias, respectively. CXA2089Q/S Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. C3 – 25 – CXA2089Q/S Example of Representative Characteristics Video system frequency response characteristics 8 TV, V1 to V4 → VOUT1, VOUT2 Y1 to Y3 → YOUT1, YOUT2 C1 to C3 → COUT1, COUT2 Audio system frequency response characteristics 2 L/RTV, L/R1 to L/R4 → LOUT1 (0dB) L/RTV, L/R1 to L/R4 → LOUT2 0 Video system input/output gain [dB] 6 4 Y1/C1 to Y3/C3 → VOUT1, VOUT2 Audio system input/output gain [dB] –2 2 –4 L/RTV, L/R1 to L/R4 → LOUT1 (–6dB) –6 0 –2 100k –8 1M 10M Frequency [Hz] 100M 1k 10k 100k 1M Frequency [Hz] Audio system distortion vs. Input amplitude 10 f = 1kHz 400Hz HPF, 80kHz LPF 1 Total harmonic distortion [%] 0.1 LOUT1 output (0dB gain) LOUT2 output 0.01 0.002 0 1 2 Input amplitude [Vrms] 3 4 – 26 – CXA2089Q/S Package Outline CXA2089Q Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.4 12.0 – 0.1 + 0.1 0.15 – 0.05 36 25 0.15 37 24 48 13 + 0.2 0.1 – 0.1 1 + 0.15 0.3 – 0.1 12 0.8 ± 0.12 M + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 ∗QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 27 – 0.9 ± 0.2 13.5 CXA2089Q/S CXA2089S 48PIN SDIP (PLASTIC) + 0.1 5 0.0 0.25 – + 0.4 43.2 – 0.1 48 25 15.24 + 0.3 13.0 – 0.1 0° to 15° 1 1.778 24 0.5 ± 0.1 0.9 ± 0.15 Two kinds of package surface: 1.All mat surface type. 2.Center part is mirror surface. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 5.1g SONY CODE EIAJ CODE JEDEC CODE SDIP-48P-02 SDIP048-P-0600 – 28 – 3.0 MIN LEAD TREATMENT LEAD MATERIAL PACKAGE MASS + 0.4 4.6 – 0.1 0.5 MIN