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CXA2093

CXA2093

  • 厂商:

    SONY(索尼)

  • 封装:

  • 描述:

    CXA2093 - Sharpness for Display - Sony Corporation

  • 数据手册
  • 价格&库存
CXA2093 数据手册
CXA2093S Sharpness for Display Description The CXA2093S is a bipolar IC which performs contour accentuation for display RGB signals. Features • Sharpness time constant selection (50ns/100ns) • Built-in sync separator for sync on green • Differential output pins • Built-in wide-band amplifier (200MHz/–3dB@0.7Vp-p) Applications Display Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C, GND = 0V) • Supply voltage VCC 7 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1.13 W Operating Conditions Supply voltage 22 pin SDIP (Plastic) VCC 5 ± 0.25 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97680A26-PS CXA2093S Block Diagram CLAMP 13 VILMAX = 0.8V VIHMIN = 2.8V Y = 0.6G + 0.3R + 0.1B Y operation 1st-order differential (50ns) 1st-order differential (100ns) RIN 1 f0/GAIN 12 GAIN Min. GAIN Max. 0.5V to 2.0V ; 50ns 3.0V to 4.5V ; 100ns Switching identification Limiter Limiter level = 30% Time constant selection 21 ROUT GCA 15 DIFOUT GIN 3 CLAMP 19 GOUT BIN 5 17 BOUT SYNCIN 7 SyncSep 14 SYNCOUT Pin Configuration RIN GND 1 2 22 GND 21 ROUT 20 GND 19 GOUT 18 VCC 17 BOUT 16 VCC 15 DIFOUT 14 SYNCOUT 13 CLAMP 12 F0_GAIN GIN 3 GND BIN VCC SYNCIN GND NC 4 5 6 7 8 9 GND 10 NC 11 –2– CXA2093S Pin Description Pin No. Symbol Pin voltage Equivalent circuit Description VCC VCC VCC VCC 250 VCC VCC VCC 1 3 5 RIN GIN BIN 1 3 5 500 150 RGB input pins. Input these pins through capacitor. 2, 4 8, 10 20, 22 GND GND pins. VCC VCC VCC VCC 7 SYNCIN 7 150 Sync input pin for sync on green. Input this pin through capacitor. 100µA VCC VCC VCC 30k 12 F0_GAIN 12 143 30k Sharpness time constant selection and gain control pin. VCC VCC 50k Clamp pulse input pin. 13 CLAMP 13 30k 20k ILMAX; 0.8V IHMIN; 2.8V –3– CXA2093S Pin No. Symbol Pin voltage VCC Equivalent circuit VCC VCC VCC Description 14 SYNCOUT 14 150 Sync output pin. 0 to 4.3V positive polarity pulse is output in synchronizing with sync. VCC VCC 1p VCC 15 DIFOUT 15 625 Differential signal output pin. 2mA 6, 16 18, 20 VCC 5V (applied) Power supply pins. VCC VCC 1p VCC 19 21 23 BOUT GOUT ROUT 19 21 23 625 RGB signal output pins. 6mA –4– CXA2093S Electrical Characteristics No. Item Power consumption I/O gain R I/O gain G I/O gain B Symbol MeasureInput signals ment pins 6 16 18 21 19 17 17 19 21 19 Measurement contents (Ta = 25°C, VCC = 5V) Min. Typ. Max. Unit 1 ICC Vcc pin inflow current 45 69 95 mA 2 3 4 VGR VGG VGB Input video signal to Pins 1, 3 and –0.5 5, input clamp pulse to Pin 13, and measure the output amplitude of Pins 1, 3, 5: Sig-1 –0.5 each output pin. Then calculate Pin 13: Sig-2 the I/O gain. output amplitude –0.5 VGR = 20 log 0.7 Input video signal to Pins 1, 3 and 5, input Pins 1, 3, 5: Sig-3 clamp pulse to Pin 13, and measure the Pin 13: Sig-2 output amplitude of each output pin. Pins 1, 3, 5: CW Pin 13: 5 V Pin 12: 0.5 V Input 30MHz and 0.1Vp-p sine wave to Pins 1, 3 and 5, and measure the output amplitude of Pin 19. Input 30MHz and 0.1Vp-p sine wave to Pins 1, 3 and 5, and measure the output amplitude of Pin 19. Then calculate the I/O gain. VGR = 20 log output amplitude 0.1 60 0.9 0.5 0.5 0.5 1.5 1.5 1.5 dB dB dB 5 Input dynamic Drng range Sharpness gain 1 1.05 1.2 Vp-p 6 VSG1 60 110 150 mVp-p 7 Sharpness gain 2 VSG2 19 Pins 1, 3, 5: CW Pin 13: 5 V Pin 12: 2.5 V 5.0 7.0 9.0 dB 8 Sharpness gain 3 VSG3 19 Pins 1, 3, 5: CW Pin 13: 5 V Pin 12: 3.0 V Input 30MHz and 0.1Vp-p sine wave to Pins 1, 3 and 5, and measure the output amplitude of Pin 19. Input 30MHz and 0.1Vp-p sine wave to Pins 1, 3 and 5, and measure the output amplitude of Pin 19. Then calculate the I/O gain. VGR = 20 log output amplitude 0.1 110 150 mVp-p 9 Sharpness gain 4 VSG4 19 Pins 1, 3, 5: CW Pin 13: 5 V Pin 12: 4.5 V 5.0 7.0 9.0 dB 10 DIFOUT output level VDF 15 Pin 1: CW Pin 13: 5 V Pin 12: 4.5 V Input 30MHz and 0.3Vp-p sine wave to Pin 1, and measure the output amplitude of Pin 15. 290 375 455 mVp-p 11 12 13 14 SYNCSEP VSHi output high level SYNCSEP VSLo output low level SYNCSEP SDtr output delay 1 SYNCSEP SDtf output delay 1 Input video signal to Pin 7, and 3.9 measure the high level of Pin 14. Input video signal to Pin 7, and measure the low level of Pin 14. Vth = 50% SDtr Vth = 50% SDtf 4.2 0.18 19 51 4.5 0.26 40 70 V V ns ns 0.1 0 30 14 Pin 7: Sig-4 –5– CXA2093S Signals Used for Measurement 25µs Sig-1 20µs 0.7Vp-p 4µs 2.7V Sig-2 0.9V 200ns 25µs Sig-3 20µs 1.0Vp-p 25µs 0.7Vp-p Sig-4 0.3Vp-p 2µs 1µs 2µs –6– CXA2093S Electrical Characteristics Measurement Circuit 1 0.1µ 2 3 0.1µ 4 5 0.1µ 6 7 0.1µ 8 9 10 RIN GND GIN GND BIN VCC SYNCIN GND NC GND GND 22 ROUT 21 GND 20 GOUT 19 0.01µ 47µ VCC 18 BOUT 17 VCC 16 DIFOUT 15 SYNCOUT 14 CLAMP 13 F0_GAIN 12 0V to 5V Differential waveform output Sync pulse output BOUT GOUT 9V ROUT 11 NC –7– CXA2093S Application Circuit R input 0.1µ 1 2 RIN GND GIN GND BIN VCC SYNCIN GND NC GND GND 22 ROUT 21 GND 20 GOUT 19 VCC 18 BOUT 17 VCC 16 DIFOUT 15 SYNCOUT 14 CLAMP 13 F0_GAIN 12 0.01µ Differential output Sync output Clamp pulse input 0.01µ B output G output R output G input 0.1µ 3 4 B input 0.1µ 5V 47µ Sync on green input 0.01µ 0.1µ 5 6 7 8 9 10 11 NC Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –8– CXA2093S Description of Operation 1. Video signal system RGB signals input to Pins 1, 3 and 5 is synchronous clamped by the clamp pulse input from Pin 13. This RGB signals are mixed in the ratio of 0.6G + 0.3R + 0.1B, and Y signal is generated. The high frequency component is pulled out from a Y signal through a differential circuit, and the amplitude is varied according to the gain control circuit. The selecting of gain control and differential circuit time constant is performed by the DC voltage input from Pin 12. Gain controlled signal is output from Pin 15 after amplitude limited from a limiter circuit. At the same time, its signal is added to RGB signals input to Pins 1, 3 and 5, and then is output from Pins 17, 19 and 21. Sharpness Min. F0_GAIN = 0.5V/3.0V No sharpness component Portion that are not output from limiter 100% Sharpness Max. F0_GAIN = 2.0V/4.5V 100% (0.7Vp-p) Limiter level Approx. 0.2V 50ns 100ns 10% Time constant F0_GAIN = 0.5V to 2.0V; 50ns F0_GAIN = 3.0V to 4.5V; 100ns 2. Synchronous system The sync on green signal input to Pin 7 is synchronous separated by the sync separation circuit after diode clamped, and is output from Pin 14 as a positive polarity pulse. The input signal is not sync on green signal, video portion is sliced and then is output as a positive polarity pulse. –9– CXA2093S Example of Representative Characteristics F0_GAIN control characteristics 7 6 GOUT output gain [dB] 5 4 3 2 1 0 0 1 2 3 F0_GAIN applied voltage [V] 4 5 Frequency characteristics 2 0 Output gain [dB] –2 –4 –6 –8 1 10 Input frequency [MHz] 100 300 – 10 – CXA2093S Package Outline Unit: mm 22PIN SDIP (PLASTIC) + 0.1 0.05 0.25 – 12 + 0.4 19.2 – 0.1 22 + 0.3 6.4 – 0.1 1 1.778 11 0.5 ± 0.1 + 0.15 0.9 – 0.1 + 0.15 3.25 – 0.2 0.51 MIN + 0.4 3.9 – 0.1 7.62 0˚ to 15˚ Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-22P-01 SDIP022-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.95g 22PIN SDIP (PLASTIC) + 0.1 0.05 0.25 – 12 + 0.4 19.2 – 0.1 22 + 0.3 6.4 – 0.1 1 1.778 11 0.5 ± 0.1 + 0.15 0.9 – 0.1 + 0.15 3.25 – 0.2 0.51 MIN + 0.4 3.9 – 0.1 7.62 0˚ to 15˚ Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-22P-01 SDIP022-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.95g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18µm – 11 – Sony Corporation
CXA2093 价格&库存

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