CXA2108AQ

CXA2108AQ Constant-Current Driver for Full Color LED Display Description The CXA2108AQ is a 1,024-gradation LED driver which is ideal for full color LED displays. This IC has 24 outputs and a maximum output current of 70mA. Time division allows driving of either two or six LEDs per output by connecting an external FET or other switch. The luminance (PWM) and drive current for each LED are set using the internal RAM. The LED type is common anode. 80 pin QFP (Plastic) Features • 24 outputs: 10-bit (1,024-gradation) PWM current outputs • Maximum output current: 70mA • LED type: Common anode • 4-bit brightness function capable of switching the basic PWM pulse width in 16 steps • Time division allows driving of up to six LEDs with a single output, making it possible to configure a high definition display with few driver ICs. • Coarse Adj. (2 bits) and Fine Adj. (8 bits) output current adjustment for each LED makes it possible to drive R, G and B using the same output from the same IC. In addition, the characteristics variance of each LED can also be corrected. • All luminance (PWM) data and drive current data are set by writing to the internal RAM. • PWM emitting can be performed up to 15 times per frame to realize a screen with little flicker. • Two built-in PWM data RAM make it possible to set the next luminance data even during PWM operation. • Abnormal internal temperature detection circuit • Single 5V power supply • Current output with protection diode (diode cathode voltage: VPD can be supplied independently of the 5V power supply.) • Surface mounting package (80-pin QFP) Applications LED display panels Structure Bi-CMOS silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C) • Supply voltage • • • • • • • AVCC, DVCC VPD Digital input voltage VI_D Digital output current Io_D Driver output voltage V_DVR Driver output current I_DVR Operating temperature∗1 Topr Storage temperature Tstg Allowable power dissipation∗1 (Ta = 65°C or less) PD AVCC, DVCC VPD Vcmp Ta Tc –0.3 to +6.0 –0.3 to +10.5 –0.3 to DVCC + 0.3 –5.0 to +5.0 0 to VPD + 0.3 –1 to +80 –40 to +80 –65 to +150 1.5 4.75 to 5.25 AVCC to 10 1.0 to VPD + 0.3 (I_DVR = 0 to 70mA) –20 to +65 –20 to +110 V V V mA V mA °C °C W V V V °C °C Recommended Operating Range • Supply voltage • Driver output compliance voltage • Operating temperature (ambient temperature)∗1 • Operating temperature (case temperature)∗1 ∗1 When mounted on a printed circuit board Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99160-PS Block Diagram DLDI Data Read Counter XUPR XR 9 R_CLK 4 BRT Counter out R_ADR 10 PWMout 24 XG XB IOUT0 PWM Counter DLDO CLK MODE RDY PWM data RAM (A) (6word × 24ch × 10bit) 10 × 24 10 DATA Data Comparator PWM data 10bit × 24 Shift Reg. & Latch 8bit DAC with 2bit coarse Adj. (× 24) × 24 XTAO A0 to 9 D0 to 9 XR/W XRD XWR REXT –2– 10 DATA Drive Current data 10 × 24 Band Gap Ref. 10 10bit × 24 Shift Reg. & Latch PWM data RAM (B) (6word × 24ch × 10bit) IOUT23 24 Drive Current data RAM (6word × 24ch × 10bit) 10 CXA2108AQ Rext CXA2108AQ Pin Configuration (Top View) IOUT17 IOUT16 IOUT15 IOUT14 IOUT13 IOUT12 IOUT10 IOUT11 IOUT9 IOUT8 IOUT7 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 IOUT18 1 IOUT19 2 IOUT20 3 IOUT21 4 IGND 5 IOUT22 6 IOUT23 7 AVCC 8 AGND 9 VPD 10 MODE 11 DGND 12 RDY 13 DLDO 14 WALL 15 XUPR 16 TEST_O 17 XB 18 XR 19 XG 20 CLK 21 DGND 22 DVCC 23 D0 24 IOUT6 64 IOUT5 63 IOUT4 62 IOUT3 61 IOUT2 60 IGND 59 IOUT1 58 IOUT0 57 AVCC 56 AGND 55 REXT 54 NC 53 NC 52 XTAO 51 XRST 50 XR/W 49 XRD 48 XWR 47 XCS 46 DLDI 45 A9 44 A8 43 DVCC 42 DGND 41 A7 A6 IGND IGND IGND 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D1 D2 D3 D4 D5 D6 D7 D8 D9 A0 A1 A2 A3 A4 A5 –3– IGND CXA2108AQ Pin Description Pin No. 9, 56 8, 57 Symbol AGND AVCC I/O voltage level Reference Equivalent circuit Description Analog GND. Analog power supply. Digital GND. Digital power supply. GND for driver output. Open. This pin is not connected with the internal circuits. — GND — 5V (Typ.) — GND 12, 22, 42 DGND 23, 43 DVCC 5, 60, 66, 70, IGND 75, 79 53, 54 NC — 5V (Typ.) — GND — 21 CLK I CMOS Clock input. Driver operation is synchronized with this clock. Reset input. The IC is initialized by inputting low level. However, the memory is not initialized. Input high level during normal operation. Output mode switching. Upper/Lower mode for low level input. Upper/Lower/RGB mode for high level input. (See the Description of Operation.) Address input. These pins are used to input the internal RAM (luminance data, brightness data and drive current data RAM) address. RAM selection. The luminance data RAM is selected when this pin is low, and the drive current data RAM when high. DVCC 51 XRST I CMOS DVCC 21 51 11 11 MODE I CMOS 34 35 36 37 38 39 40 41 44 45 34 to 41, A0 to 8 44 I CMOS DGND 45 A9 I CMOS DGND 24 to 33 D0 to 9 I/O CMOS DVCC 24 25 26 27 28 29 30 31 32 33 Data I/O. These pins are used to input and output data to and from the internal RAM (luminance data, brightness data and drive current data RAM). See Table 1. Read/Write Switching Condition Correspondence Table for the data I/O switching conditions. DGND –4– CXA2108AQ Pin No. Symbol I/O voltage level Reference Equivalent circuit Description Internal RAM chip select. Internal RAM access is enabled by inputting low level. (See Table 1. Read/Write Switching Condition Correspondence Table.) Internal RAM read/write select. Write mode is selected for high level, and read mode for low level. See Table 1. Read/Write Switching Condition Correspondence Table for the actual read/write switching signal input conditions. Write clock input. This pin is used to input the clock for writing the luminance, brightness and drive current data. It is not synchronized with CLK. Read clock input. This pin is used to input the clock for externally reading the luminance, brightness and drive current data. It is not synchronized with CLK. Trigger signal input for luminance data RAM (A)/(B) switching and PWM output start. (See the Timing Charts.) Voltage supply terminal for cathode of positive protection diode which connected to drivers (IOUTO to IOUT23) and REXT (55pin). Normally,connect to LED DC supply. However ,when the LED DC supply voltage exceeds 10V,VPD must be set 10V or less. 47 XCS I CMOS 50 XR/W I CMOS DVCC 46 47 48 48 XWR I CMOS 49 50 DGND 49 XRD I CMOS 46 DLDI I CMOS 10 VPD — 5V (Typ.) –5– CXA2108AQ Pin No. Symbol I/O voltage level Reference Equivalent circuit Description READY signal output. This indicates the drive current data RAM access enabled period. Access is enabled while high level is output. (See the Timing Charts.) DLDI signal output. This outputs the DLDI signal synchronized with CLK. Write ALL signal output. One pulse (= high level signal with a width of 1 clock) is output synchronized with the rising edge of the next CLK after the final address∗1 of the currently selected mode is input. Note that both the final address must be input and the XCS and XWR input levels must be low at the rising edge of this CLK. (See the Timing Charts for details.) ∗1 02Fh (Upper/Lower mode) 08Fh (Upper/Lower/RGB mode) Upper signal output. This is used as the LED switching signal. (See the Timing Charts and Application Circuits for details.) Test signal output. This pin is unrelated to the functions of this IC. Do not connect anything; leave this pin open. Blue signal output. This is used as the LED switching signal. (See the Timing Charts and Application Circuits for details.) Red signal output. This is used as the LED switching signal. (See the Timing Charts and Application Circuits for details.) Green signal output. This is used as the LED switching signal. (See the Timing Charts and Application Circuits for details.) Thermal Alarm Out signal output. This pin normally outputs high level, but it outputs low level when the internal temperature rises to an abnormally high level. 13 RDY O CMOS 14 DLDO O CMOS 15 WALL O CMOS DVCC 13 14 15 16 17 18 19 20 52 16 XUPR O CMOS DGND 17 TEST_O O CMOS 18 XB O CMOS 19 XR O CMOS 20 XG O CMOS 52 XTAO O CMOS –6– CXA2108AQ Pin No. Symbol I/O voltage level Reference Equivalent circuit Description VPD 55 REXT O 55 Drive current setting. Connect a resistor between this pin and GND. The drive current is proportional to the current flowing to this resistor. (See Table 2. Drive Current Setting and Power Consumption.) AGND 1 to 4, 6, 7, 58, 59, 61 to 65, IOUT0 67 to 69, to 23 71 to 74, 76 to 78, 80 VPD 1 6 2 3 4 7 58 59 O 61 62 63 64 65 67 68 69 71 72 73 74 76 77 78 80 IGND Drivers. These pins drive the LED. XCS [I] XR/W [I] L A9 [I] L H L H L H L H Luminance Write Disable Disable Enable Disable Disable Disable Disable Disable Read Enable Disable Disable Disable Disable Disable Disable Disable Drive current Write Disable Disable Disable Enable Disable Disable Disable Disable Read Disable Enable Disable Disable Disable Disable Disable Disable D0 to 9 [I/O] Output Output Input Input Hi-Z Hi-Z Hi-Z Hi-Z L H L H H Table 1. Read/Write Switching Condition Correspondence Table –7– CXA2108AQ Rext [kΩ] 2.0 2.0 2.0 2.0 2.5 2.5 2.5 2.5 3.0 3.0 3.0 3.0 3.5 3.5 3.5 3.5 4.0 4.0 4.0 4.0 D9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Io (FFh) [mA] 21.7 43.3 65.0 86.7 ∗1 17.3 34.7 52.0 69.3 14.4 28.9 43.3 57.8 12.4 24.8 37.1 49.5 10.8 21.7 32.5 43.3 Istb [mA] 22.3 38.1 53.8 69.6 18.4 31.1 43.7 56.3 15.9 26.4 36.9 47.4 14.0 23.1 32.1 41.1 12.7 20.6 28.4 36.3 Pstb [W] 0.111 0.190 0.269 0.348 0.092 0.155 0.218 0.281 0.079 0.132 0.184 0.237 0.070 0.115 0.160 0.205 0.063 0.103 0.142 0.182 Po (max) [W] 1.39 1.31 1.23 1.15 1.41 1.34 1.28 1.22 1.42 1.37 1.32 1.26 1.43 1.38 1.34 1.29 1.44 1.40 1.36 1.32 ∗1 Absolute maximum rating exceeded. Table 2. Drive Current Setting and Power Consumption (when D0 to D7 = FFh) Rext : External resistor that sets the DAC reference current (Iref) D9, D8 : Data that sets the maximum drive current (Io (FFh)) Iref : DAC reference current Iref [mA] = 1.3 [V]/Rext [kΩ]/24 Io (FFh) : Maximum drive current that can be set by D0 to D7 Io (FFh) [mA] = Iref × (2 × D9 + D8 + 1) × 800 Istb : Standby current (Internal current consumption excluding the driver block) Istb [mA] = 3.06 + 24 × Iref × (16/3 + 24.25 × (2 × D9 + D8 + 1)) Pstb : Standby power (Internal power consumption excluding the driver block, Vcc = 5 V) Pstb [W] = 5 [V] × Istb [mA]/1000 Po (max) : Maximum power that can be consumed by the driver block Po (max) [W] = 1.5 [W] – Pstb [W] Note) Istb, Pstb and Po (max) are the values when D0 to D7 = 11111111 (FFh). In addition, these values assume the case where all channels are set to the same drive current. –8– CXA2108AQ Electrical Characteristics Item Driver block PWM reference clock frequency REXT pin voltage REXT pin voltage Supply voltage dependency Standby supply current PWM output resolution Drive current setting resolution Coarse Adj. Fine Adj. DC characteristics DLE Differential linearity error Output current IOUT Output compliance voltage Vcmp Logic block Digital input current (I, I/O) (H) (L) IIH IIL Symbol fCLK VREXT ∆VREXT ICC (AVCC, DVCC = +5V, VPD = +10V, AGND, DGND, IGND = 0V) Conditions Min. Typ. Max. 15 Rext = 2kΩ VREXT (@AVCC = 5.25V) – VREXT (@AVCC = 4.75V) Rext = 2kΩ, D8 = D9 = 0 Note) Excluding the driver block 1235 0 20 10 2 8 Io (FFh) = 60mA (D0 [LSB] to D7 [MSB] = FFh) Io = 0 to 70mA 1 ±0.8 1300 1365 20 30 Unit MHz mV mV mA bit bit bit LSB 70 mA VPD + 0.3 V VIN = 5V VIN = 0V –5 –5 0.7DVCC –0.3 5 5 DVCC + 0.3 0.3DVCC µA µA V V V Digital input voltage (I, I/O) VIH (H) (L) VIL Digital output voltage (O) (H) VOH (L) VOL Digital output voltage (I/O) (H) VOZH (L) VOZL RAM write mode Write cycle Write pulse width Setup time Hold time RAM read mode Read cycle Read pulse width Setup time Hold time Output delay time TWR TCWR TSWR THWR TRD TCRD TSRD THRD TPDD DVCC = 5V, IOH = –2mA DVCC = 5V, IOL = 4mA DVCC = 5V, IOH = –2mA DVCC = 5V, IOL = 4mA 4 0.4 3.7 0.4 133.3 55 10 10 133.3 55 10 10 V V V ns ns ns ns ns ns ns ns Output load 50pF or less 100 ns –9– CXA2108AQ Timing Charts (RAM) (1) Write mode (XR/W = H) TWR TCWR XWR TSWR THWR A0 to 9 D0 to 9 Note) The address is not latched internally, so do not change the address while XWR is low. (1) Read mode (XR/W = L) TRD TCRD XRD TSRD THRD A0 to 9 TPDD D0 to 9 Note) The address is not latched internally, so do not change the address while XRD is low. – 10 – CXA2108AQ Electrical Characteristics Measurement Circuit DC Characteristics Measurement Circuit 5V 10V Logic Tester 10 10 AGND DGND IGND XRST MODE XR/W XRD XWR DLDI A0 to 9 D0 to 9 XCS CLK AVCC DVCC VPD IOUT0 to 23 A 1V CXA2108AQ 5V 0V 15MHz REXT 2kΩ – 11 – CXA2108AQ Description of Operation 1. Description The CXA2108AQ is an LED driver for full color LED displays. The RGB luminance which becomes the video data is controlled by pulse width modulation (PWM), and the luminance variance of each LED is corrected by the drive current. The basic PWM clock width can be set in 16 steps from 1× to 16× by the brightness data, making it possible to adjust the brightness of the entire screen. There are 24 driver outputs, and time division allows driving of either two or six LEDs per output by adding an external FET or other switch. The luminance (pulse width), drive current and brightness are set by writing data to the internal memory according to the memory map. The luminance and drive current can be set independently for each LED. 2. Relationship between the luminance data (PWM data: Dv), brightness data (Db) and the LED emitting duty The CXA2108AQ adjusts the LED luminance which becomes the video data by changing the LED emitting time duty through PWM of the luminance data. The luminance consists of luminance data and brightness data. The luminance data (Dv) has an accuracy of 10 bits (= 1,024 steps: 0 to 1,023) and can be set independently for each LED. The brightness data (Db) controls the basic PWM clock width with 4 bits (= 16 steps: 1× to 16×), and is common data for all outputs. The brightness data is normally used when adjusting the brightness of the entire screen. Labeling the LED emitting cycle as Ts and the CLK cycle as TCLK , this relationship is given by the following formula. Ts = 1,024 × 16 × TCLK The LED emitting time Tv within this Ts time is: Tv = Dv × Db × TCLK Therefore, the emitting duty is: Tv/Ts × 100 = (Dv × Db)/(1,024 × 16) × 100 [%] The drive current waveform and the relationship between the luminance data, brightness data and the emitting duty are shown below. Current Tv = Dv × Db × TCLK IOUT 0 Drive current TS = 1,024 × 16 × TCLK TS Time Fig. 1. Drive Current Waveform – 12 – CXA2108AQ Luminance data (Dv) D9 to 0 Brightness (D3 to 0) = 0000 D9 D0 Emitting duty [%] Nv 0000000000 0000000001 0000000010 : 1000000000 : 1111111111 0 1 2 : 512 : 1023 0 0.006 0.012 : 3.125 : 6.244 Nv∗1 and emitting duty Brightness (D3 to 0) = 0111 Nv 0 8 16 : 4096 : 8184 Emitting duty [%] 0 0.049 0.098 : 25.00 : 49.95 Brightness (D3 to 0) = 1111 Nv 0 16 32 : 8192 : 16368 Emitting duty [%] 0 0.098 0.195 : 50.00 : 99.90 : ∗1 Nv = Tv/TCLK = Dv × Db Table 3. Relationship Between Luminance Data, Brightness Data and Emitting Duty 3. Drive current data (Dd) Even when driving LEDs of the same color with the same current value, individual differences in characteristics result in an uneven emitting intensity. In addition, the required current value also differs according to the emitting color (RGB). That is to say, the necessary current differs for each LED. This drive current IOUT corresponds to the amplitude of the IOUT output PWM waveform as shown in Fig. 1. The CXA2108AQ can set this current independently for each LED using Coarse Adj. (2 bits: D8, D9) and Fine Adj. (8 bits: D0 to D7). The maximum values of the drive current (Io (FFh): IOUT @ D0 to D7 = FFh) are varied in 4 levels by Coarse Adj. (2 bits: D8, D9). The minimum drive current (Io (00h): IOUT @ D0 to D7 = 00h) is approximately 0mA,regardless of the Coarse Adj. range. The range from the minimum to the maximum drive current can be set at an accuracy of 8 bits (D0 to D7 = 256 steps). Note that this drive current is generated using the Iref described in 6. as the reference. The relationship between the Fine Adj. (8 bits: D0 to D7) data and the drive current, and the drive current data (D0 to D9) to drive current correspondence table are shown below. Drive current Io (FFh) (Maximum drive current) •• (256 steps) •• 1 LSB = Io (FFh)/255 Io (00h) ≈ 0 (Minimum drive current) 01h 00h FEh FFh Fine Adj. (8 bits: D0 to D7) data Fig. 2. Relationship Between Fine Adj. (8 bits: D0 to D7) Data and Drive Current Drive current D9 0 D8 D9 00 D8 D9 11 D8 D9 01 D8 1 Drive current data (Dd) D7 to 0 D7 D0 00000000 (00h) : 10000000 (80h) : 11111111 (FFh) 0 0 0 Minimum drive current Io (00h) 0 : : : : 400 × Iref 800 × Iref 1200 × Iref 1600 × Iref : : : : 800 × Iref 1600 × Iref 2400 × Iref 3200 × Iref Maximum drive current Io (FFh) Table 4. Drive Current Data (D0 to D9) to Drive Current Correspondence Table – 13 – : CXA2108AQ 4. Operating modes (Upper/Lower, Upper/Lower/RGB) The CXA2108AQ has the following two operation modes which are set by the MODE pin. 4-1. Upper/Lower mode (MODE = low) In this mode, two LEDs are driven by time division for each IOUT output. First, PWM waveform output starts triggered by the DLDI input signal. In this mode, two kinds of luminance data are output by time division for each output. Labeling these data as U and L, the driver outputs the data in the order of U → L → U → L → U → and so on. The XUPR pin output voltage switches in sync with the LED emitting cycle Ts in the order of L → H → L → and so on, so this can be used as the FET or other switch signal for switching the LED. (See Fig. 6. Timing Chart 2-1 and Fig. 11. Application Circuit (1) for details.) New PWM data is output when the next DLDI signal is input. 4-2. Upper/Lower/RGB mode (MODE = high) In this mode, six LEDs can be driven by time division for each IOUT output. PWM waveform output starts triggered by the DLDI input signal. In this mode, six kinds of luminance data are output by time division for each output. Labeling these data as UB, UR, UG, LB, LR and LG, the driver switches the output in the order of UB → UR → UG → LB → LR → LG → UB → and so on. Like Upper/Lower mode, the XUPR and also the XB, XR and XG output voltages switch in sync with Ts, so these can be used as the FET or other switch signals for switching the LEDs. The output voltages at this time are: XUPR = low for U∗, XUPR = high for L∗, XB = low (XR = XG = high) for ∗B, XR = low (XB = XG = high) for ∗R, and XG = low (XB = XR = high) for ∗G. (See Fig. 7. Timing Chart 2-2 and Fig. 12. Application Circuit (2) for details.) New PWM data is output when the next DLDI signal is input. 5. Luminance data memory and DLDI signal The CXA2108AQ uses two sets of 6-word × 24-channel × 10-bit RAM (RAM (A), RAM (B)) as luminance data memories, and switches these memories. While the data in one memory is being loaded internally and PWM output is being performed, the next luminance data can be written to the other memory from an external source. Memory switching is performed by inputting a trigger signal to the DLDI pin. The read/write enabled memory alternates from A → B → A → and so on, and the memory used for PWM output alternates from B → A → B → and so on each time the signal is input to DLDI. The DLDI signal switches the memory, and at the same time functions as the PWM output start trigger pulse. See the Timing Charts for details. 6. Reference current (Iref) The drive current is generated using the current flowing to an external resistor as the reference. This resistor Rext is connected between the REXT pin and GND. The REXT pin voltage is designed to be unaffected by supply voltage, temperature or other fluctuations, and is always a constant voltage (approximately 1.3V). Therefore, a constant current can be realized by using a resistor that does not have temperature characteristics. The current obtained by dividing this current value by the number of IOUT outputs (24) is defined as Iref. Iref = (1.3/Rext)/24 The maximum drive current value can be changed by varying the resistance value. See Table 2. Drive Current Setting and Power Consumption for details. – 14 – CXA2108AQ 7. Data setting The above mentioned luminance data Dv, brightness data Db and drive current data Dd are set using address input pins A0 to A9 and data I/O pins D0 to D9. See the Timing Charts for the memory read/write enabled period, and Table 1. Read/Write Switching Condition Correspondence Table for the pin setting conditions. The address, data, XWR and XRD setup, hold and other timings should be as stated in the Electrical Characteristics. See Tables 5. and 6. LED Driver Memory Map with respect to the memory address of each IOUT output pin (IOUT0 to IOUT23). The relationship between the data and the memory address is as follows. A9 to A0 MSB A9 LSB A0      
,      
 ,   • • Can't use Can't use 0100101000 0100100XXX 0100011111 • • Brightness Data Don't use Brightness Data 0010010000 0010001111 • • LG 0001111000 0001110111 • • LR Don't use a + 23 0001100000 0001011111 • • LB 0001001000 0001000111 • • IOUT23 IOUT22 IOUT21 • • UG 0000110000 0000101111 • • UR L 0000011000 0000010111 • • UB U a IOUT4 IOUT3 IOUT2 IOUT1 IOUT0 0000000000 MODE Note) X: Don't care Upper/Lower/RGB Upper/Lower Fig. 3. Relationship Between Memory Address and Data (Luminance Data Dv, Brightness Data Db) – 15 – CXA2108AQ A9 to A0 MSB A9 LSB A0   , 
, 

,,          
  ,    • • Can't use 1010010000 1010001111 • • LG 1001111000 1001110111 • • LR Can't use 1001100000 1001011111 • • a + 23 LB 1001001000 1001000111 • • IOUT23 IOUT22 IOUT21 • • UG 1000110000 1000101111 • • UR L 1000011000 1000010111 • • UB U a IOUT4 IOUT3 IOUT2 IOUT1 IOUT0 1000000000 MODE Upper/Lower/RGB Upper/Lower Fig. 4. Relationship Between Memory Address and Data (Drive Current Data Dd) – 16 – Luminance Data A9 to A3 LOWER L UPPER U 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 000 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 001 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 010 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 011 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 A2 to A0 100 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 101 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 110 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 111 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 Drive Current Data LOWER L – 17 – A2 to A0 = Don't care UPPER U 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 000 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 001 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 010 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 011 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 A2 to A0 100 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 101 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 110 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 111 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 Brightness data: A9 to A3 = 0100100b (24h) CXA2108AQ Table 5. LED Driver Memory Map (Upper/Lower mode) Luminance Data A9 to A3 UPPER R UR UG LB LR LOWER G B R G LG B UB 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 000 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 001 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 010 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 011 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 A2 to A0 100 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 101 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 110 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 111 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 – 18 – UPPER R UR UG Drive Current Data LOWER G B LB B UB R LR G LG 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 000 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 IOUT0 IOUT8 IOUT16 001 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 IOUT1 IOUT9 IOUT17 010 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 IOUT2 IOUT10 IOUT18 011 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 IOUT3 IOUT11 IOUT19 A2 to A0 100 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 IOUT4 IOUT12 IOUT20 101 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 IOUT5 IOUT13 IOUT21 110 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 IOUT6 IOUT14 IOUT22 111 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 IOUT7 IOUT15 IOUT23 CXA2108AQ Brightness data: A9 to A3 = 0100100b (24h) A2 to A0 = Don't care Table 6. LED Driver Memory Map (Upper/Lower/RGB mode) Case 1: Upper/Lower mode DLDI IOUT output data U ••• ••• U RAM (A) RAM (B) R/W Enable R/W Disable R/W Disable (Accessing Internally) L L U L U L U L U U L U L U L U L U L U U L U L U L U RAM (A) RAM (A) R/W Enable RAM (B) R/W Enable (Accessing Internally) R/W Disable R/W Enable Partial enlargement diagram (Fig. 6. Timing Chart 2-1) Case 2: Upper/Lower/RGB mode – 19 – ••• DLDI IOUT output data RAM (A) R/W Disable (Accessing Internally) UB UR UG LB LR LG UB UR UG LB LR UB UR UG LB LR LG UB UR UG LB LR RAM (B) R/W Enable ••• UB UR UG LB LR LG UB RAM (A) R/W Disable RAM (A) R/W Enable RAM (B) R/W Enable R/W Disable (Accessing Internally) R/W Enable Partial enlargement diagram (Fig. 7. Timing Chart 2-2) CXA2108AQ Note) U, L and other symbols correspond to Tables 5. and 6. LED Driver Memory Map. Fig. 5. Timing Chart 1. Relationship between PWM waveform output and luminance RAM (A)/(B) with respect to DLDI input pulse 1 clk DLDI DLDO RDY IOUT 1024 × 16 clk = 1 Cycle XUPR – 20 – L Emitting end U L U L U Note) U, L and other symbols correspond to Tables 5. LED Driver Memory Map. U Emitting start Partial enlargement diagram (Fig. 8. Timing Chart 3-1) Fig. 6. Timing Chart 2-1. DLDI input to IOUT output (Upper/Lower mode) CXA2108AQ 1 clk DLDI DLDO RDY IOUT 1024 × 16 clk = 1 Cycle XUPR XB – 21 – UR Emitting end UG LB LR XR XG LG UB UB Emitting start Partial enlargement diagram (Fig. 9. Timing Chart 3-2) Note) UB , LG and other symbols correspond to Tables 6. LED Driver Memory Map. Fig. 7. Timing Chart 2-2. DLDI input to IOUT output (Upper/Lower/RGB mode) CXA2108AQ CLK DLDI DLDO 48 clk 9 clk 48 clk RDY XUPR 8 clk Nv clk IOUT – 22 – Emitting start Emitting end D D E E Emitting start 1024 × 16 clk = 1 Cycle Luminance data RAM (A) Luminance data RAM (B) Driver current RAM E D E D E E = R/W Enable D = R/W Disable ∗ NV = Dv × Db (Dv: Luminance data, Db: Brightness data) Fig. 8. Timing Chart 3-1. DLDI input to IOUT output (1 cycle) example (Upper/Lower mode) CXA2108AQ CLK DLDI DLDO 9 clk 48 clk RDY 48 clk XUPR 8 clk XB XR – 23 – Nv clk Emitting start Emitting end D E E XG IOUT Emitting start 1024 × 16 clk = 1 Cycle Luminance data RAM (A) Luminance data RAM (B) Driver current RAM E D E D D E E = R/W Enable D = R/W Disable ∗ NV = Dv × Db (Dv: Luminance data, Db: Brightness data) Fig. 9. Timing Chart 3-2. DLDI input to IOUT output (1 cycle) example (Upper/Lower/RGB mode) CXA2108AQ 1 clk = 15MHz (Max) CLK 1 clk = 7.5MHz (Max) XRST XWR XR/W A0 to 9 200 201 202 22F 120 000 001 002 02F D0 to 9 Dd0 Dd1 Dd2 Dd2F Db Dv0 Dv1 Dv2 Dv2F DLDI DLDO – 24 – 48 clk Drive current data write Luminance data write Brightness data write E D E D WALL RDY 128 clk 9 clk XUPR 8 clk IOUT Nv clk IC initialization Emitting start Emitting end Luminance data RAM (A) Luminance data RAM (B) Driver current RAM D D D E E E = R/W Enable D = R/W Disable ∗ NV = Dv × Db (Dv: Luminance data, Db: Brightness data) ∗ Dd: Drive current data 


              


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   CXA2108AQ Fig. 10. Timing Chart 4. XRST input to IOUT output example (Upper/Lower mode) Application Circuit UPPER/LOWER mode IGND IOUT12 IOUT11 IOUT10 IOUT9 IOUT8 IOUT7 IOUT17 IOUT16 IOUT15 IOUT14 IOUT13 IOUT6 IGND IGND IGND VG = 5.5V VR = 4.0V VB = 5.5V 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 IOUT18 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 from IOUT0 DGND Bus CLK Address Bus Data: D0 to D9 From Data Bus Address: A0 to A9 From Address Bus Data Bus 5V 0V 5V 0V 5V 0V DVCC XR/W XRD XWR Bus CLK (7.5MHz) REXT AGND 2kΩ AGND IOUT1 IOUT0 AVCC IGND IOUT2 IOUT3 IOUT4 2 3 4 5 IGND IOUT22 6 7 8 AGND 10 MODE 11 12 13 14 from IOUT3 15 XUPR 16 17 18 from IOUT2 19 20 15MHz CLK 21 22 DGND 23 24 from IOUT1 DVCC DGND DGND VPD 9 IOUT23 AVCC from IOUT23 • • • • • • • • • IOUT5 IOUT19 IOUT20 from XUPR IOUT21 G G – 25 – Read/write control signal B B G Green R Red 7.5MHz B Bule VG, VR, VB: LED DC supply Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXA2108AQ Fig. 11. Application Circuit (1) UPPER/LOWER/RGB mode IGND IOUT12 IOUT11 IOUT10 IOUT9 IOUT8 IOUT7 IOUT17 IOUT16 IOUT15 IOUT14 IOUT13 IOUT6 IGND IGND IGND VG = 5.5V VR = 4.0V VB = 5.5V from XB IOUT18 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DGND DVCC XR/W XRD XWR REXT AGND 2kΩ AGND IOUT1 IOUT0 AVCC IGND IOUT2 IOUT3 IOUT4 2 3 4 5 IGND IOUT22 6 7 8 VPD 10 MODE 11 12 DGND 13 14 15 XUPR 16 17 XB 18 19 20 21 22 DGND 23 24 XR XG 15MHz CLK from IOUT0 DVCC 9 IOUT23 AVCC from XUPR from IOUT23 • • • • • • • • • 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 IOUT5 IOUT19 from XR IOUT20 IOUT21 from XG B AGND DVCC R G B R – 26 – from IOUT1 Data: D0 to D9 From Data Bus G Read/write control signal B R Bus CLK (7.5MHz) G B R G B R G Bus CLK 5V 0V Address Bus Address: A0 to A9 From Address Bus Data Bus 5V 0V 5V 0V Bule 7.5MHz Red Green VG, VR, VB: LED DC supply CXA2108AQ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Fig. 12. Application Circuit (2) CXA2108AQ Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 64 41 + 0.1 0.15 – 0.05 0.15 65 40 + 0.4 14.0 – 0.1 17.9 ± 0.4 A 80 25 + 0.2 0.1 – 0.05 0.8 0.2 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.6g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L01 QFP080-P-1420 – 27 – 0.8 ± 0.2 1 24 16.3