CXA2134Q

CXA2134Q US Audio Multiplexing Decoder Description The CXA2134Q is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C bus. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction and sound processor. Various kinds of filters are built in this IC. Adjustment, mode control and sound processor control are all executed through I2C bus. Features • Alignment-free VCO and filter • Audio multiplexing decoder dbx noise reduction decoder sound processor — Two external inputs — Quasi-surround — Bass control — Treble control — Volume control are all included in a single chip. Almost any soft of signal processing is possible through this IC. • Input level, separation adjustments and each mode control are possible through I2C bus. 48 pin QFP (Plastic) Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VCC 11 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –65 to +150 • Allowable power dissipation PD 0.6 Range of Operating Supply Voltage 9 ± 0.5 V °C °C W V ∗ A license of the dbx-TV noise reduction system is required for the use of this device. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99832-PS Block Diagram MAINOUT PCINT1 PLINT SUBOUT PCINT2 MAININ AUX1-L 34 33 10 11 12 21 9 8 AUX1-R LFLT MATRIX FLT LPF VCA VCO 1/4 1/2 TVSW 37 AUX2-L 36 AUX2-R FEXT1 FEXT2 39 TVOUT-L 38 TVOUT-R "STEREO" DeEm NRSW/FOMO/SAPC (+6dB) STIND LOGIC LPF WIDEBAND COMPIN 13 VCA LPF VCC 19 EXT1/EXT2/M1 SURR M2 ATT/ATTSW SURROUND 40 SURRTC 2 BASS-L BASS BASS BPF SAPVCO LPF DeEm VE VCA BASS "SAP" SAPIND HPF RMSDET SAPTC 18 TREBLE TREB TREB VOL-L "PONRES" 7 6 5 24 25 22 26 27 28 29 30 32 31 1 48 4 3 14 15 SCL VGR IREF SDA STIN VE DGND SAPIN VETC VCAIN VEOUT VCATC VEWGT TOUT-L SAPOUT VOLIN-L LSOUT-L VCAWGT LSOUT-R VOL-R SW VOL-L VOL-R –2– NOISE DET "NOISE" SPECTRAL LPF LPF AMP (+4dB) I2C BUS I/F GND 17 45 BASS-R 47 TRE-L NOISETC 23 41 TRE-R 44 RMSDET TOUT-R 43 VOLIN-R IREF CXA2134Q CXA2134Q Pin Configuration (Top View) VCAWGT AUX2-R AUX1-R VCATC VEOUT VEWGT AUX1-L VCAIN NC 36 35 34 AUX2-L 37 TVOUT-R 38 TVOUT-L 39 SURRTC 40 TRE-R 41 NC 42 VOLIN-R 43 TOUT-R 44 BASS-R 45 NC 46 TRE-L 47 VOLIN-L 48 1 2 3 33 32 31 30 29 28 27 26 25 24 SAPOUT 23 NOISETC 22 STIN 21 SUBOUT 20 NC 19 VCC 18 SAPTC 17 GND 16 NC 15 IREF 14 VGR 13 COMPIN 4 5 6 7 8 9 10 11 12 LSOUT-L DGND BASS-L PCINT1 SDA MAININ LSOUT-R MAINOUT PCINT2 SCL TOUT-L –3– PLINT SAPIN VETC VE CXA2134Q Pin Description Pin No. Symbol Pin voltage Equivalent circuit (Ta = 25°C, Vcc = 9V) Description VCC 1 TOUT-L 4.0V 147 1 44 580 580 Treble output pin. (Left channel) 44 TOUT-R 4.0V Treble output pin. (Right channel) Vcc 1.2k 1.2k 2 BASS-L 4.0V Bass filter pin. (Left channel) 5.4k 11k 147 2 11k 4V 45 45 BASS-R 4.0V Bass filter pin. (Right channel) VCC 3k 3 LSOUT-R 4.0V 580 3 4 580 LSOUT right channel output pin. 4 LSOUT-L 4.0V LSOUT left channel output pin. VCC 7.5k ↓ 35µ 2.1V ×2 4k ×5 5 SDA — 7.5k 4.5k 3k Serial data I/O pin. VIH > 3.0V VIL < 1.5V 5 –4– CXA2134Q Pin No. Symbol Pin voltage Equivalent circuit VCC 7.5k ↓ 35µ 2.1V 4k Description 6 SCL — 10.5k ×4 3k Serial clock input pin. VIH > 3.0V VIL < 1.5V 6 7 DGND — 7 Digital block GND. VCC 10k VCC 8 MAININ 4.0V 147 8 53k 4V VCC 15k ×4 Input pin of (L + R) signal from MAINOUT (Pin 9). 9 MAINOUT 4.0V 147 9 (L + R) signal output pin. ↓ 200µ 1k –5– CXA2134Q Pin No. Symbol Pin voltage Equivalent circuit VCC 147 10 Description 10 PCINT1 4.0V 30k 22k Stereo block PLL loop filter integrating pin. VCC 147 11 11 PCINT2 4.0V 2k 10k 10k ×2 4k VCC 20k 20k 147 12 PLINT 5.1V 20k 20k 12 Pilot cancel circuit loop filter integrating pin. (Connect a 1µF capacitor between this pin and GND.) 20k 10k VCC 50k 147 13 13 COMPIN 4.0V 22k 3V 4k 4k 4k 20k 3k Audio multiplexing signal input pin. 24k 16k –6– CXA2134Q Pin No. Symbol Pin voltage Equivalent circuit Description 3k 147 14 VGR 1.3V 11k 9.7k 19.4k ×4 VCC 11k 11k Band gap reference output pin. (Connect a 10µF capacitor between this pin and GND.) 14 2.06k VCC 40k 40k 30k 30k 15k ×2 30k VCC 15 IREF 1.3V 30p 1.8k 15 147 6.3k Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62kΩ (±1%) resistor between this pin and GND.) 16k 17 GND — 17 Analog block GND. VCC 8k 10k 3k 1k VCC 4k ↓ 50µ 18 18 SAPTC 4.5V Set the time constant for the SAP carrier detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) 19 Vcc — 19 Supply voltage pin. –7– CXA2134Q Pin No. Symbol Pin voltage 2k Equivalent circuit Vcc 2k 10P 4k Description 580 21 SUBOUT 4.0V 2k 2k 21 14.4k 580 147 (L – R) signal output pin. 2k 4k 1k VCC 22 STIN 23k 4.0V 11.7k 147 22 23k Input pin of (L – R) signal from SUBOUT (Pin 21). 147 25 18k 20k 4V Vcc 25 SAPIN 4.0V 18k 4V Input pin of (SAP) signal from SUPOUT (Pin 24). 8k 3.3k 10k 1k 2k 4k ×2 4V 3k Vcc 3k 23 NOISETC 3.0V Set the time constant for the noise detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) 200k 23 Vcc 5P 580 24 SAPOUT 4.0V 580 10k 24 SAP FM detector output pin. 147 24k ↓ 10µ 4k ↓ 50µ –8– CXA2134Q Pin No. Symbol Pin voltage Equivalent circuit VCC 7.5k Description 26 VE 4.0V 147 26 Variable de-emphasis integrating pin. (Connect a 2700pF capacitor and a 3.3kΩ resistor in series between this pin and GND.) Vcc 580 2.9V 4V 36k 27 VEWGT 4.0V 27 147 580 Weight the variable de-emphasis control effective value detection circuit. (Connect a 0.047µF capacitor and a 3kΩ resistor in series between this pin and GND.) 8k 30k ↓ 8µ 4k ↓ 50µ Vcc 28 VETC 1.7V ×4 ×4 28 4k ↓ 50µ 20k ↓ 7.5µ Determine the restoration time constant of the variable de-emphasis control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 3.3µF capacitor between this pin and GND.) Vcc 5P 580 29 VEOUT 4.0V 29 580 10k Variable de-emphasis output pin. (Connect a 4.7µF non-polar capacitor between Pins 29 and 30.) –9– CXA2134Q Pin No. Symbol Pin voltage Equivalent circuit VCC Description 47k 20k 47k 30 VCAIN 4.0V VCC 30 VCA input pin. Input the variable de-emphasis output signal from Pin 29 via a coupling capacitor. VCC ×4 31 ×4 31 VCATC 1.7V ↓ 50µ 4k ↓ 7.5µ 20k Determine the restoration time constant of the VCA control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 10µF capacitor between this pin and GND.) VCC 40k 40k 3p 580 32 VCAWGT 4.0V 32 2.9V 36k 580 147 Weight the VCA control effective value detection circuit. (Connect a 1µF capacitor and a 3.9kΩ resistor in series between this pin and GND.) ↓ 50µ 4k ↓ 8µ 30k 8k 33 34 36 37 AUX1-R AUX1-L AUX2-R AUX2-L 4.0V 10k VCC Right channel external input 1 pin. Left channel external input 1 pin. Right channel external input 2 pin. Left channel external input 2 pin. 4.0V 4.0V 147 33 27.5k 27.5k 34 36 37 4V 4.0V – 10 – CXA2134Q Pin No. Symbol Pin voltage Equivalent circuit VCC 3k Description 38 TVOUT-R 4.0V 580 580 TVOUT right channel output pin. 147 38 39 39 TVOUT-L 4.0V TVOUT left channel output pin. VCC 10k 40 SURRTC 580 40k 4.0V 40 20k 20k 24k 580 Set the center frequency of the Surround circuit phase shifter. The frequency is determined by the built-in resistor and the external capacitor. (Connect a 0.022µF capacitor between this pin and GND.) Vcc 41 TRE-R 4.0V 5.7k 1.2k 1.2k Treble filter pin. (Right channel) 5.7k 147 41 47 6k 47 TRE-L 4.0V Treble filter pin. (Left channel) VCC 43 VOLIN-R 4.0V 10k 147 43 48 Volume right channel input pin. 48 VOLIN-L 4.0V 66k 4V Volume left channel input pin. 16 20 35 42 46 NC — – 11 – Electrical Characteristics COMPIN input level (100% modulation level) (Ta = 25°C, VCC = 9V) Measurement conditions Filter Min. 37 440 –1.2 –3.0 — — 38/39 21 20 log ('12k'/'1k') 15kLPF 15kLPF 20 log ('100%'/'0%') 20 log ('NRSW = 0'/ 'NRSW = 1') 0dB = 49mVrms PILOT (fH) 0dB Main (L + R) (Pre-Emphasis: OFF) = 245mVrms SUB (L – R) (dbx-TV: OFF) = 490mVrms Pilot = 49mVrms SAP Carrier = 147mVrms fH = 15.734kHz Mode Typ. 47 490 0 –1.0 0.1 0.15 38/39 61 150 21 21 21 15kLPF 1kBPF fH BPF 0dB = 49mVrms ST 13 Change PILOT (fH) Level No. — MONO MONO MONO MONO MONO MONO ST ST ST ST ST SAP ST 13 13 13 SUB (L-R) 1kHz, NR OFF ST-L (R), 1kHz, 100% mod., NR ON, SAP Carrier (5fH) No signal Mono 1kHz 100% mod. Pre-em. ON Item 19 38/39 20 log ('5k'/'1k') 38/39 38/39 15kLPF 15kLPF 20 log ('100%'/'0%') 15kLPF 38/39 Signal Input pin Input signal Output pin Max. 57 540 1.0 1.0 0.5 0.5 Unit mA mVrms dB dB % % 1 13 13 13 13 13 13 13 13 13 13 SUB (L-R), 1kHz, 200% mod., NR OFF SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 12kHz, 30% mod., NR OFF SUB (L-R), 1kHz, 100% mod., NR OFF Mono 1kHz, Pre-em. ON Mono 1kHz 200% mod. Pre-em. ON Mono 1kHz 100% mod. Pre-em. ON Mono 12kHz 30% mod. 20 log Pre-em. ON ('12k'/'1k') Mono 5kHz 30% mod. Pre-em. ON Current consumption Icc 2 Main output level Vmain 3 Main de-emphasis frequency response FCdeem 4 Main LPF frequency response FCmain 5 Main distortion THDm 6 Main overload distortion THDmmax – 12 – 20 log (‘on level'/'off level') 7 Main S/N SNmain 69 190 –3.0 — — 21 39 21 56 60 — –9.0 BUS RETURN 3.5 –0.5 0.1 0.2 64 70 –38 –6.0 6.0 — 230 1.0 1.0 2.0 — — –27 –3.0 8.5 dB mVrms dB % % dB dB dB dB dB 8 Sub output level Vsub 9 Sub LPF frequency response FCsub 10 Sub distortion THDsub 11 Sub overload distortion THDsmax 12 Sub S/N SNsub 13 Crosstalk Stereo → SAP CTst 14 Sub pilot leak PCsub 15 Stereo ON level THst CXA2134Q 16 Stereo ON/OFF hysteresis HYst No. Mode Input signal Min. Max. 190 2.5 6.0 — — –9.0 2.0 23 38/39 38/39 38/39 15kLPF 38/39 38/39 23 23 15kLPF 23 440 — 1kBPF 20 log (M1 = "0"/M1 = "1") 38/39 — 440 3/4 440 1kBPF Mono 1kHz 100% mod. Pre-em. ON Item Unit mVrms dB % dB dB –6.5 4.0 35 35 35 35 490 –95 –95 490 490 3/4 1kBPF 3/4 — — 13 –75 –90 6.0 — — — — 540 –80 –80 540 540 –60 –80 dB dB dB dB dB dB mVrms dB dB mVrms mVrms Sine wave 1kHz, 490mVrms dB SAP SAP SAP SAP ST 0dB = 147mVrms 20 log (‘on level’/’off level’) 15kLPF 15kLPF BUS RETURN –12.0 13 1kBPF 39 SAP 1kHz 100% mod. 20 log ('NRSW = 1'/'NRSW = 0') NR ON, Pilot (fH) 60 13 SAP 1kHz, NR OFF 24 15kLPF 20 log ('100%'/'0%') 46 55 70 13 15kLPF 24 SAP 1kHz 100% mod. NR OFF — 2.5 13 24 SAP 10kHz, 30% mod. 20 log ('10k'/'1k') NR OFF –3.0 0 13 24 SAP 1kHz 100% mod. NR OFF 130 160 Symbol Input pin Filter Measurement conditions Output pin Typ. 17 SAP output level Vsap 18 SAP LPF frequency response FCsap 19 SAP distortion THDsap 20 SAP S/N SNsap 21 Cross talk SAP → Stereo CTsap 22 SAP 13 Change SAP Carrier (5fH) Level ST-L 300Hz 30% mod. 20 log ('Lch'/'Rch') NR ON ST-R 300Hz 30% mod. 20 log NR ON ('Rch'/'Lch') ST-L 3kHz 30% mod. NR ON 20 log ('Lch'/'Rch') 20 log ('Rch'/'Lch') ST-R 3kHz 30% mod. NR ON Sine wave 1kHz, 490mVrms Mono 1kHz 100% mod. 20 log (M1 = "0"/M1 = "1") Pre-em. ON SAP ON level THsap 23 ST ST ST ST EXT INT EXT INT EXT INT EXT 33/34 36/37 33/34 36/37 13 33/34 36/37 Sine wave 1kHz, 490mVrms Mono 1kHz 100% mod. Pre-em. ON SAP ON/OFF hysteresis 13 13 13 13 33/34 36/37 13 HYsap 24 ST separation 1 L → R STLsep1 – 13 – Sine wave 1kHz, 490mVrms 25 ST separation 1 R → L STRsep1 26 ST separation 2 L → R STLsep2 27 ST separation 2 R → L STRsep2 28 TVOUT output level Vtv 29 30 TVOUT mute amount MUtv1 MUtv2 31 LSOUT output level Vls 32 33 LSOUT cross talk EXT → INT CTls CXA2134Q 34 LSOUT cross talk INT → EXT dB No. EXT 33/34 36/37 1kBPF 3/4 — –90 –80 — No signal Mute (M2 = "0")/ DC difference when there is no signal 3/4 –25 0 25 15kLPF 15kLPF 15kLPF BASS = "3F" BASS = "0" TREBLE = "3F" TREBLE = "0" VOL-L = "0", VOL-R = "0" 1kBPF 3/4 3/4 3/4 3/4 4 4 3/4 3/4 — 9 –13 9 –13 — 1.5 4.5 3/4 67 77 0.03 11 –11 11 –11 –90 3.0 6.0 3/4 — 0.01 0.5 — 0.5 13 –9 13 –9 –80 4.8 7.5 Sine wave 1kHz, 490mVrms 20 log (M2 = "0"/M2 = "1") dB Item Input pin Symbol Mode Input signal Filter Measurement conditions Min. Typ. Max. Unit Output pin 35 LSOUT mute amount MUls 36 LSOUT DC offset OSls INT EXT EXT EXT EXT EXT EXT EXT EXT EXT EXT 34/37 34/37 Sine wave 10kHz, 490mVrms EXT Sine wave 330Hz, 490mVrms 33/34 36/37 Sine wave 1kHz, 490mVrms 33/34 36/37 Sine wave 10kHz, 490mVrms 33/34 36/37 Sine wave 10kHz, 490mVrms 33/34 36/37 Sine wave 100Hz, 490mVrms 33/34 36/37 Sine wave 100Hz, 490mVrms 33/34 36/37 Sine wave 1kHz, 2Vrms 33/34 36/37 Sine wave 1kHz, 490mVrms mV 37 LSOUT distortion THDls 33/34 36/37 Sine wave 1kHz, 490mVrms % dB % dB dB dB dB dB dB dB 38 LSOUT S/N SNls 39 LSOUT overload distortion THDlsmax 40 Bass maximum value TBmax 41 Bass minimum value TBmin 42 Treble maximum value TTmax – 14 – 43 Treble minimum value TTmin 44 Volume minimum value VOLmin 45 SURROUND frequency response 1 Sr1 46 SURROUND frequency response 2 Sr2 CXA2134Q CXA2134Q Electrical Characteristics Measurement Circuit S6 S5 S4 S3 S2 S1 SIGNAL GENERATOR V1 AC C24 4.7µ 36 35 SIGNAL GENERATOR V2 AC C23 4.7µ 34 SIGNAL SIGNAL GENE- GENERATOR RATOR BUF FILTER 15kHz LPF fH BPF 1kHz BPF MEASURES TANTALUM V3 AC C22 4.7µ 33 V4 AC TANTALUM R8 3.9k C21 1µ 32 31 C20 10µ 30 C19 4.7µ 29 C18 3.3µ R7 3k R6 3.3k C17 C16 0.047µ 2700p 27 26 25 C15 4.7µ 24 28 AUX1-L VCATC VETC VCAWGT VEOUT NC AUX2-R AUX1-R VEWGT VCAIN VE C25 4.7µ C26 4.7µ C27 4.7µ C28 0.022µ C29 4700p 37 AUX2-L 38 TVOUT-R SAPOUT NOISETC 23 C14 4.7µ 39 SAPIN TVOUT-L STIN 22 40 SURRTC SUBOUT 21 C13 4.7µ 41 TRE-R NC 20 42 NC VCC 19 C12 100µ VCC V5 9V GND 43 VOLIN-R C30 4.7µ SAPTC 18 C11 4.7µ 44 TOUT-R GND 17 GND 45 BASS-R NC 16 R5 62k ± 1% METAL C31 0.1µ 46 NC IREF 15 LSOUT-R LSOUT-L MAINOUT C32 4700p 47 TRE-L VOLIN-L VGR 14 TOUT-L BASS-L PCINT1 MAININ PCINT2 COMPIN C10 10µ 13 C9 4.7µ DGND PLINT 48 SIGNAL GENERATOR V6 AC GND SDA 1 C1 4.7µ C2 0.1µ 2 C3 4.7µ 3 4 C4 4.7µ R1 220 5 R2 220 6 SCL 7 8 C5 4.7µ 9 10 C6 5600P 11 12 R3 1MEG C8 1µ I2C BUS DATA DGND R4 C7 100k 0.012µ – 15 – CXA2134Q Adjustment Method The resister data is set to the standard value. 1. ATT adjustment 1) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the TVOUT-L output level. Then, adjust the “ATT” data for ATT adjustment so that the TVOUT-L output goes to the standard value (490mVrms). 2) Adjustment range: ±20% Adjustment bits: 4 bits 2.Separation adjustment 1) Input ST-L signal (modulation factor 30%, frequency 300Hz NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce TVOUT-R output to the minimum. 2) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to reduce TVOUT-R output to the minimum. 3) The adjustments in 1 and 2 above are performed to optimize the separation. 4) “WIDEBAND” “SPECTRAL” Adjustment range: ±30% Adjustment range: ±15% Adjustment bits: 6 bits Adjustment bits: 6 bits Note) Adjust this IC through tuner and IF when this IC is mounted on the set. – 16 – CXA2134Q Register Specifications Slave address Slave receiver 84H (1000 0100) Register table Sub address MSB LSB BIT7 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ M2 ∗ EXT1 EXT2 SURR BIT6 BIT5 TEST-DA BIT4 TEST1 SPECTRAL WIDEBAND NRSW ATTSW BASS TREBLE VOL-L VOL-R ∗: Don't care FOMO ∗ SAPC FEXT1 M1 FEXT2 ∗∗∗∗0000 ∗∗∗∗0001 ∗∗∗∗0010 ∗∗∗∗0011 ∗∗∗∗0100 ∗∗∗∗0101 ∗∗∗∗0110 ∗∗∗∗0111 ∗∗∗∗1000 Data BIT3 BIT2 ATT BIT1 BIT0 Slave transmitter 85H (1000 0101) Status registers STA1 BIT7 STA2 BIT6 STA3 BIT5 SAP STA4 BIT4 NOISE STA5 BIT3 — STA6 BIT2 — STA7 BIT1 — STA8 BIT0 — POWER STEREO ON RESET Note) The microcomputer reads both SAP and NOISE status and judges SAP discrimination. – 17 – CXA2134Q Description of Registers Control registers Register ATT SPECTRAL WIDEBAND TEST-DA TEST1 VOL-L VOL-R BASS TREBLE SURR NRSW FOMO EXT1 EXT2 FEXT1 FEXT2 M1 M2 ATTSW SAPC Number Classification∗1 of bits 4 6 6 1 1 6 6 6 6 1 1 1 1 1 1 1 1 1 1 1 A A A T T U U U U U U U U U U U U U S S Standard setting 9 1F 1F 0 0 3F 3F 1F 1F 0 0 0 0 0 0 0 1 1 0 0 Input level adjustment Adjustment of stereo separation (3kHz) Adjustment of stereo separation (300Hz) DAC test mode Test mode Left channel volume control Right channel volume control Bass control Treble control Quasi-surround function ON/OFF Selection of the output signal (Stereo mode, SAP mode) Forced MONO. (Left channel only is MONO during SAP output.) Selection of TV mode or external input mode Selection of external input 1 mode or external input 2 mode (EXT1 = 1) External input 1 forced MONO External input 2 forced MONO Selection of TVOUT mute function ON/OFF Selection of LSOUT mute function ON/OFF Main VCA ON/OFF Selection of SAP mode or L + R mode according to the presence of SAP broadcasting Contents ∗1 Classification U: User control A: Adjustment S: Proper to set T: Test Status registers Register PONRES STEREO SAP NOISE Number of bits 1 1 1 1 POWER ON RESET detection; Stereo discrimination of the COMPIN input signal; SAP discrimination of the COMPIN input signal; Noise level discrimination of the SAP input signal; Contents 1: RESET 1: Stereo 1: SAP 1: Noise – 18 – CXA2134Q Description of Control Registers ATT (4): Perform input level adjustment. 0 = Level Min. F = Level Max. SPECTRAL (6): Perform high frequency (fs = 3kHz) separation adjustment. 0 = Level Max. 3F = Level Min. WIDEBAND (6): Perform low frequency (fs = 300Hz) separation adjustment. 0 = Level Min. 3F = Level Max. TEST-DA (1): Set DAC output test mode. 0 = Normal mode 1 = DAC output test mode In addition, the following outputs are present at Pin 39. TVOUT-L (Pin 39): DA control DC level TEST1 (1): Monitor SAPBPF and NRBPF outputs. 0 = Normal mode 1 = SAPBPF, NRBPF outputs In addition, the following outputs are present at Pins 39 and 38. TVOUT-L (Pin 39): SAP BPF OUT TVOUT-R (Pin 38): NR BPF OUT LSOUT-L output signal level control 0 = Volume Min. 3F= Volume Max. –1.25 dB/STEP LSOUT-R output signal level control 0 = Volume Min. 3F= Volume Max. –1.25 dB/STEP LSOUT output bass control 0 = Bass Min. 1F = Bass Center 3F = Bass Max. VOL-L (6): VOL-R (6): BASS (6): TREBLE (6): LSOUT output treble control 0 = Treble Min. 1F = Treble Center 3F = Treble Max. – 19 – CXA2134Q SURR (1): Surround function selection 0 = Surround OFF 1 = Surround ON Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode Select TV mode or external input mode for TVOUT output. 0 = TV mode 1 = External input mode Select external input [1] mode or external input [2] mode for TVOUT output. (EXT1 = 1) 0 = External input [1] mode 1 = External input [2] mode Turn external input [1] to forced MONO. 0 = Normal mode 1 = External input [1] is forced MONO. Input the same signal to both AUX1-L and AUX1-R. Turn external input [2] to forced MONO 0 = Normal mode 1 = External input [2] is forced MONO Input the same signal to both AUX2-L and AUX2-R. Mute the TVOUT-L and TVOUT-R output. 0 = Mute ON 1 = Mute OFF Mute the LSOUT-L and LSOUT-R output. 0 = Mute ON 1 = Mute OFF Select BYPASS SW of MVCA 0 = Normal mode 1 = MVCA is passed Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L + R output is selected 1 = SAP output is selected – 20 – NRSW (1): FOMO (1): EXT1 (1): EXT2 (1): FEXT1 (1): FEXT2 (1): M1 (1): M2 (1): ATTSW (1) SAPC (1): CXA2134Q Description of Mode Control SAPC = 0 “Select dbx input and TV decoder output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) • During ST input: left channel: L, right channel: R • During other input: left channel: L + R, right channel: L + R NRSW = 1 (SAP output) • When there is “SAP” during SAP discrimination – left channel: SAP, right channel: SAP • When there is “No SAP”, output is the same as when NRSW = 0. SAPC = 1 “Select dbx input and TV decoder output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) As on the left NRSW NRSW = 1 (SAP output) • Regardless of the presence of SAP discrimination, dbx input: “SAP” left channel: SAP, right channel: SAP However, when there is no SAP, SAPOUT output is soft muted (–7dB) “Forced MONO” FOMO FOMO = 1 • During SAP output: left channel: L + R, right channel: SAP • During ST or MONO output: left channel: L + R, right channel: L + R Change the selection conditions for “MONO or ST output” and “SAP output”. SAPC = 0: Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination. SAPC – 21 – CXA2134Q Decoder Output and Mode Control Table 1 (SAPC = 1) Input signal mode ST 0 0 MONO ∗1 0 0 0 0 1 1 1 STEREO ∗1 1 1 1 1 1 0 0 MONO & SAP 0 0 0 0 1 1 STEREO & SAP 1 1 1 1 Mode detection SAP 0 0 0 ∗ ∗ ∗ 0 0 1 1 0 0 ∗ ∗ 1 1 1 1 1 1 1 1 1 1 1 1 NOISE 0 0 0 1 1 1 ∗ ∗ 1 1 0 0 1 1 ∗ ∗ 0 0 1 1 ∗ ∗ 0 0 1 1 Mode control NRSW 0 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 FOMO ∗ 0 1 ∗ 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAPC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 dbx input MUTE SAP SAP MUTE (SAP) (SAP) L–R MUTE L–R MUTE SAP SAP (SAP) (SAP) MUTE MUTE SAP SAP (SAP) (SAP) L–R MUTE SAP SAP (SAP) (SAP) Output Lch L+R SAP L+R L+R (SAP) L+R L L+R L L+R SAP L+R (SAP) L+R L+R L+R SAP L+R (SAP) L+R L L+R SAP L+R (SAP) L+R Rch L+R SAP SAP L+R (SAP) (SAP) R L+R R L+R SAP SAP (SAP) (SAP) L+R L+R SAP SAP (SAP) (SAP) R L+R SAP SAP (SAP) (SAP) Note (SAP) : The SAPOUT output signal is soft muted (approximately –7dB). The signal is soft muted when NOISE = 1. ∗ : Don’t care. ∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is input in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is output. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. – 22 – CXA2134Q Decoder Output and Mode Control Table 2 (SAPC = 0) Input signal mode ST 0 0 MONO ∗1 0 0 0 1 1 1 STEREO ∗1 1 1 1 1 1 0 0 0 MONO & SAP 0 0 0 0 0 1 1 1 STEREO & SAP 1 1 1 1 1 Mode detection SAP 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOISE ∗ 1 1 1 1 ∗ ∗ ∗ ∗ 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ∗ 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Mode control NRSW FOMO ∗ 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAPC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dbx input MUTE MUTE MUTE (SAP) (SAP) L–R MUTE L–R MUTE L–R MUTE (SAP) (SAP) MUTE MUTE SAP SAP MUTE MUTE (SAP) (SAP) L–R MUTE SAP SAP L–R MUTE (SAP) (SAP) Output Lch L+R L+R L+R (SAP) L+R L L+R L L+R L L+R (SAP) L+R L+R L+R SAP L+R L+R L+R (SAP) L+R L L+R SAP L+R L L+R (SAP) L+R Rch L+R L+R L+R (SAP) (SAP) R L+R R L+R R L+R (SAP) (SAP) L+R L+R SAP SAP L+R L+R (SAP) (SAP) R L+R SAP SAP R L+R (SAP) (SAP) Note (SAP) : The SAPOUT output signal is soft muted (approximately –7dB). The signal is soft muted when NOISE = 1. ∗ : Don’t care. ∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is input in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is output. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. – 23 – CXA2134Q Mode Control Table 3 M1 1 2 3 4 5 6 0 1 1 1 1 1 EXT1 – 0 1 1 1 1 EXT2 – – 0 0 1 1 FEXT1 – – 0 1 – – FEXT2 – – – – 0 1 TVOUT-L MUTE TV (L) AUX1-L AUX1-L AUX2-L AUX2-L TVOUT-R MUTE TV (R) AUX1-R AUX1-L AUX2-R AUX2-L TV (L) / TV (R) are selected in MATRIX TV (L): MONO, ST-L, SAP TV (R): MONO, ST-R, SAP – 24 – CXA2134Q Description of Operation The US audio multiplexing system possesses the base-band spectrum shown in Fig. 1. PEAK DEV kHz 50 AM-DSB-SC 50 25 25 L-R dbx-TV NR PILOT 15 SAP dbx-TV NR FM 10kHz 50 – 10kHz 2fH 3fH 4fH 5fH TELEMETRY FM 3kHz 3 6fH 6.5fH f L+R 5 50 – 15kHz fH fH = 15.734kHz Fig. 1. Base-band spectrum 2fHL0° fHL90° fHL0° I2C BUS DECODER MODE CONTROL (MAIN OUT) (MAIN IN) PLL (VCO 8fH) STEREO LPF MVCA PILOT DET (COMPIN) MAIN LPF DE.EM PILOT CANCEL SUB LPF L-R (DSB) DET 13 9 L+R WIDEBAND SUBVCA 4.7µ 8 (SUBOUT) (ST IN) MATRIX (Lch) NR SW to TVSW 21 L–R 4.7µ 22 A B SAP BPF SAP(FM) DET INJ. LOCK SAP LPF (SAP OUT) dbx-TV BLOCK (Rch) 24 (SAP IN) NOISE DET BUS DECODER 4.7µ I2C 25 MODE CONTROL SAP DET I2C BUS DECODER MODE CONTROL Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block) (ST IN) FIXED VARIABLE DEEMPHASIS DEEMPHASIS 22 (SAP IN) NR SW A (VE OUT) (VCA IN) B VCA to MATRIX 29 4.7µ HPF LPF LPF RMS DET RMS DET 30 25 Fig 3. dbx-TV block – 25 – CXA2134Q (AUX2-L) (AUX2-R) 4.7µ 37 36 (TVOUT-L) (TVOUT-R) (TOUT-L) BASS SURROUND VOL-R (TOUT-R) 44 TREBLE 1 48 (VOLIN-L) (LSOUT-L) VOL-L (AUX1-L) 39 TVSW 38 4 34 33 (AUX1-R) 3 (LSOUT-R) (Lch) (Rch) 43 (VOLIN-R) 4.7µ from MATRIX Fig. 4. Sound processor block (1) L + R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 13) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L – R signal and SAP signal are removed by MAIN LPF, and the frequency response is flattened (deemphasized) and input to the matrix. (2) L – R (SUB) The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3) SAP SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency response flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 24 output is soft muted. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25kHz after FM detection of SAP signal. – 26 – CXA2134Q (5) dbx-TV block Either the L – R signal or SAP signal input respectively from ST IN (Pin 22) or SAP IN (Pin 25) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Matrix, TVSW The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and SAP signals according to the BUS data and whether there is ST / SAP discrimination. “TVSW” switches the “MATRIX” output signal, external input signal (input to AUX1-L, R), external input signal (input to AUX2-L, R) and external forced MONO. (7) Sound processor block The sound processor block contains "SURROUND" (quasi-surround function), “BASS/TREBLE” tone control functions, and “VOLUME”. • Surround At "SURROUND", the L and R differential components are phase-shifted and these components are added to the left and right channels. When surround is OFF (SURR = 0) Inputs are output as is. Lout = Lin Rout = Rin { When surround is ON (SURR = 1) { Lout = Lin – 1 – jωRC 1 + jωRC 1 – jωRC 1 + jωRC (Lin – Rin) Rout = Rin + (Lin – Rin) { R = 24kΩ (On-chip) attached to Pin 40) C = 0.022µF (Externally (Lin, Lout) and Rin, (Rout) indicate the left- and right- channel I/O of the surround circuit. (8) Others “MVCA” is a VCA which adjusts the input signal level to the standard level of this IC. “Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 15) with GND become the reference current. – 27 – CXA2134Q Application Circuit AUX2 input AUX1 input 3.9k 4.7µ 4.7µ 4.7µ 4.7µ 1µ 36 35 34 33 32 31 10µ TANTALUM 3.3µ TANTALUM 4.7µ 3k 3.3k 0.047µ 2700p 30 29 28 27 26 25 VCAWGT NC AUX2-R AUX1-R VEWGT VCAIN AUX1-L VCATC 37 VEOUT SAPIN VETC VE 4.7µ 24 AUX2-L 38 TVOUT-R TVOUT output 4.7µ 39 TVOUT-L 4.7µ 40 SURRTC 0.022µ 41 TRE-R 4700p 42 NC SAPOUT NOISETC 23 4.7µ STIN 22 4.7µ SUBOUT 21 NC 20 100µ +9V VCC 19 43 VOLIN-R 4.7µ 44 TOUT-R SAPTC 18 4.7µ GND 17 GND 45 0.1µ BASS-R NC 16 62k ± 1% METAL 46 NC IREF 15 47 TRE-L VGR 14 MAINOUT 4700p 48 LSOUT-R LSOUT-L VOLIN-L 10µ TOUT-L BASS-L PCINT1 MAININ PCINT2 COMPIN DGND SCL PLINT 13 4.7µ SDA Composite baseband signal input 1 2 3 4 5 6 7 8 4.7µ 9 10 11 12 1MEG 5600P 100k 0.012µ 1µ 4.7µ 0.1µ 4.7µ 4.7µ 220 220 DGND LS output µ-com Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 28 – CXA2134Q I2C Bus Block Items (SDA, SCL) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 5) during 3mA inflow Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation Item Symbol VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD: STA tLOW tHIGH tSU: STA tHD: DAT tSU: DAT tR tF tSU: STO Min. 3.0 0 — — 0 3 — 0 4.7 4.0 4.7 4.0 4.7 0 250 — — 4.7 Typ. — — — — — — — — — — — — — — — — — — Max. 5.0 1.5 10 10 0.4 — 10 100 — — — — — — — 1 300 — ns µs ns µs µs V µA V mA pF kHz Unit I2C bus load conditions: Pull-up resistor 4kΩ (Connect to +5V) Load capacitor 200pF (Connect to GND) I2C Bus Control Signal SDA tBUF SCL P S tHD: STA tLOW tHD: DAT tHIGH tSU: DAT Sr tSU: STA tSU: STO P tR tF tHD: STA – 29 – CXA2134Q I2C Bus Signal There are two I2C bus signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal. • Accordingly there are 3 values outputs, H, L and Hi-Z. H L Hi-Z L • I2C transfer begins with Start Condition and ends with Stop Condition. Start Condition S Stop Condition P SDA SCL – 30 – CXA2134Q • I2C data Write (Write from I2C controller to the IC) Low during Write MSB Hi-Z SDA MSB LSB Hi-Z SCL S 1 2 3 Address 4 5 6 7 8 9 ACK 1 Sub Address 8 9 ACK MSB LSB Hi-Z Hi-Z 1 8 9 1 8 9 DATA (n) ACK DATA (n + 1) ACK DATA (n + 2) Hi-Z Hi-Z 8 DATA 9 ACK 1 DATA 8 9 P ACK ∗ Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically. • I2C data Read (Read from the IC to I2C controller) High during Read Hi-Z SDA SCL S 1 6 7 8 9 1 7 8 9 P Address ACK DATA ACK • Read timing MSB IC output SDA LSB SCL 9 1 2 3 4 5 6 7 8 9 Read timing ACK DATA ACK ∗ Data Read is performed during SCL rise. – 31 – CXA2134Q Input level vs. Distortion characteristics 1 (MONO) Input signal: MONO (Pre-emphasis on), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF Measurement point: TVOUT-L/R Input level vs. Distortion characteristics 2 (Stereo) Input signal: Stereo L = –R (dbx-TVNR ON), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, ST mode Measurement point: TVOUT-L/R 1.0 10 THD – Distortion [%] THD – Distortion [%] 0.1 1.0 Standard level (100%) –10 0 Input level [dB] –10 0 Input level [dB] 10 Standard level (100%) 10 Input level vs. Distortion characteristics 3 (SAP) Input signal: SAP (dbx-TVNR ON) 1kHz, 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, SAP mode Measurement point: TVOUT-L/R 10 THD – Distortion [%] 1.0 Standard level (100%) –10 0 Input level [dB] 10 – 32 – CXA2134Q Stereo LPF frequency response 10 5 Gain [dB] 0 –5 –10 0 20 40 60 80 100 Frequency [kHz] Main LPF and Sub LPF frequency response 30 Gain (FC main and FC sub) [dB] 20 10 0 –10 –20 –30 –40 –50 1 2 5 7 10 20 50 70 100 Frequency [kHz] SAP frequency response and group delay 100 20 5fH 10 Gain 90 80 Gain [dB] 60 0 50 40 –10 Group delay –20 20 40 3.8fH 60 80 6.2fH 100 30 20 10 0 120 Frequency [kHz] – 33 – Group delay [µs] 70 CXA2134Q Volume characteristics 0 –20 LSOUT output level [dB] –40 –60 –80 AUX1, 2 1kHz, 490mVrms Output: LSOUT –100 0 F 1F 2F 3F Control data VOL-L, VOL-R Input: – 34 – CXA2134Q Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.4 12.0 – 0.1 + 0.1 0.15 – 0.05 0.15 36 25 37 24 48 13 + 0.2 0.1 – 0.1 1 + 0.15 0.3 – 0.1 12 0.8 0.24 M + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.7g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 35 – 0.9 ± 0.2 13.5