CXA2153

CXA2153S Preamplifier for High Resolution Computer Display Description The CXA2153S is a bipolar IC developed for high resolution computer displays. Features • Built-in wide-band amplifier: 180MHz@–3dB (Typ.) • Input dynamic range: 1.0Vp-p (Typ.) • High gain preamplifier (15dB) • R, G and B incorporated in a single package (SDIP 30 pins) • I2C bus control Contrast control R/G/B drive control Brightness control OSD contrast control 4-channel DAC control output • Built-in gamma function • Built-in high-speed ABL blanking • Built-in sync separator for Sync on Green • Built-in blanking mixing function (with blanking level fixed at 0.4V) • Built-in OSD mixing function • Video period detection function • Built-in VBLK synchronous DAC refresh system Applications High resolution computer displays Structure Bipolar silicon monolithic IC 30 pin SDIP (Plastic) Absolute Maximum Ratings (Ta = 25°C, GND = 0V) • Supply voltage Vcc12 13 V Vcc5 5.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation 2.05 W PD • Pin voltage Vcc5 + 0.3V 1, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 (Pin) VREF (Pin 23) + 0.3V 18, 19, 20, 21, 25, 27, 29 (Pin) Recommended Operating Conditions Supply voltage Vcc12 12 ± 0.5 Vcc5 5 ± 0.25 V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99X02A1Y-PS SYNCIN 4 VREF 23 VCC12 22 Block Diagram G_BKG 20 R_BKG 21 B_BKG 19 G2 18 SDA Latch Regulator Clamp D/A Converter 16 17 12 LPF SYNC SEP. DRIVE Rch OSD GAIN Clamp BRIGHTNESS SYNC OFF Contrast 29 Gain Control AMP OSD/OSD_BLK Mix Buffer AMP Blanking Mix 14 SCL I2C Bus Decoder SYNCOUT 7 ABL ABL GAMMA1/GAMMA2/GM OFF POL1/POL2 Rch 1 RIN Gamma ROUT –2– Sharpness Gch (Same as Rch) SHP GAIN/ SHP WIDTH BLK Bch (Same as Rch) VDET LEVEL/VDET OFF Video Detector 15 VDET BLK Clamp Gch 27 3 GIN GOUT Bch 25 BIN BOUT 6 8 9 13 11 10 CLP OSD_B OSD_R OSD_G OSD_BLK CXA2153S CXA2153S Pin Configuration RIN VCC5 GIN SYNCIN GND BIN ABL OSD_BLK OSD_R 1 2 3 4 5 6 7 8 9 30 VCC12 29 ROUT 28 GND_R 27 GOUT 26 GND_G 25 BOUT 24 GND_B 23 VREF 22 VCC12 21 R_BKG 20 G_BKG 19 B_BKG 18 G2 17 SCL 16 SDA OSD_G 10 OSD_B 11 SYNCOUT 12 CLP 13 BLK 14 VDET 15 –3– CXA2153S Pin Description Pin No. Symbol Pin voltage Equivalent circuit VCC 1k VCC VCC Description 1 3 6 RIN GIN BIN 3.1V (CLAMP) 1 3 6 1k 1k RGB signal inputs. Input via the capacitor. 2 Vcc5 5V VCC VCC 100 VCC 5V power supply. 4 SYNCIN 2.9V 4 150 Sync-on-green signal input. Input via the capacitor. 5 GND VCC 5V VCC 500 10k 7 20k 10k VCC 2k VCC 500 GND 7 ABL 2.5V (when open) ABL input. VCC VCC 8 OSD_BLK 8 30k 5k 5k OSD_BLK control input. VILMAX = 0.8V VIHMIN = 2.8V –4– CXA2153S Pin No. Symbol Pin voltage Equivalent circuit Description VCC VCC VCC 9 10 11 OSD_R OSD_G OSD_B 5k 9 10 11 30k 5k OSD control input. VILMAX = 0.8V VIHMIN = 2.8V VCC VCC VCC VCC 20k 100 5k 12 SYNCOUT 12 200 200 Sync separator output of Syncon-green signal. I2C bus SOG off: Output at 0. Typ.: High = 4.2V Low = 0.2V (positive polarity) VCC VCC 13 CLP 13 30k Clamp pulse (positive polarity) input. VILMAX = 0.8V VIHMIN = 2.8V VCC VCC VCC 5k 5k 14 BLK 14 30k Blanking pulse input. Set the V blanking pulse width to 300µs or more. VILMAX = 1.2V VIHMIN = 4.7V –5– CXA2153S Pin No. Symbol Pin voltage Equivalent circuit VREF VCC VCC Description VCC 20k 100 10k 15 VDET 15 200 200 Video detector output. I2C bus VDET off: Output at 0. VCC 16 SDA 4k 16 I2C bus standard SDA (serial data) input/output. VILMAX = 1.5V VIHMIN = 3.5V VOLMAX = 0.4V VCC 17 SCL 4k 17 I2C bus standard SCL (serial clock) input. VILMAX = 1.5V VIHMIN = 3.5V 10k VREG VREG VCC 100 1k 21 20 19 18 R_BKG G_BKG B_BKG G2 21 20 19 18 100 1k BKG/G2 adjustment DAC outputs. The output DC is 1.5 to 5.5V. 22 30 Vcc12 12V 12V power supply –6– CXA2153S Pin No. Symbol Pin voltage Equivalent circuit Description VCC12 VCC12 23 VREF 9V 23 Band Gap 9V regulator. Connect with Vcc12 via a resistor of around 220Ω. It cannot be used as an external power supply. 28 26 24 GND_R GND_G GND_B 0V GNDs VCC12 VREG 29 27 25 ROUT GOUT BOUT VCC 29 27 25 R, G and B signal outputs. –7– CXA2153S I2C BUS Register Definitions Slave Address SLAVE RECEIVER: 40 (HEX) Register Table Sub Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch ∗ POL1 ∗ ∗ ∗ GAMMA1 SHP WIDTH POL2 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CONTRAST BRIGHTNESS R_BKG G_BKG B_BKG OSD GAIN G2 R_DRV G_DRV B_DRV SHP GAIN GAMMA2 0 D R OFF ∗: Don't Care VDET LVL VDET OFF SOG OFF GAM OFF Sub Address 0000 CONTRAST (8) Controls the gain common to the R, G and B channels. Since control is performed by multiplying with R/G/B DRIVE, the white balance can be adjusted by R/G/B DRIVE and the luminance can be adjusted by CONTRAST. 0: Output level minimum (0Vp-p) 255: Output level maximum (4.4Vp-p; with 0.7Vp-p input) Sub Address 0001 BRIGHTNESS (8) Controls the black level common to the R, G and B channels. 0: Black level minimum (0.8V) 255: Black level maximum (2.9V) Sub Address 0010 R_BKG (8) Controls Pin 21 (R BACKGROUND) output voltage. 0: Output voltage minimum (1.5V) 255: Output voltage maximum (5.5V) Controls Pin 20 (G BACKGROUND) output voltage. 0: Output voltage minimum (1.5V) 255: Output voltage maximum (5.5V) Controls Pin 19 (B BACKGROUND) output voltage. 0: Output voltage minimum (1.5V) 255: Output voltage maximum (5.5V) –8– Sub Address 0011 G_BKG (8) Sub Address 0100 B_BKG (8) CXA2153S Sub Address 0101 OSD GAIN (8) Controls the OSD gain common to the R, G and B channels. Since control is performed by multiplying with R/G/B DRIVE, the video white balance and tracking are obtained. 0: Gain minimum (0Vp-p) 255: Gain maximum (4.5Vp-p) Controls Pin 18 (G2) output voltage. 0: Output voltage minimum (1.5V) 255: Output voltage maximum (5.5V) Controls the gain for the R channel. Control is performed by multiplying with CONTRAST. Use this for adjusting the white balance. 0: Output level minimum (0Vp-p) 255: Output level maximum (4.4Vp-p; with 0.7Vp-p input) Controls the gain for the G channel. Control is performed by multiplying with CONTRAST. Use this for adjusting the white balance. 0: Output level minimum (0Vp-p) 255: Output level maximum (4.4Vp-p; with 0.7Vp-p input) Controls the gain for the B channel. Control is performed by multiplying with CONTRAST. Use this for adjusting the white balance. 0: Output level minimum (0Vp-p) 255: Output level maximum (4.4Vp-p; with 0.7Vp-p input) Controls the sharpness time constant switching. 0: OFF 1: 25ns 2: 50ns 3: 100ns Controls the sharpness gain. 0: Gain minimum (0dB) F: Gain maximum (6dB) ∗ Amplitude at SHP OFF is assumed to be 0dB. Controls the polarity of the correction at GAMMA1. 0: – correction 1: + correction Controls the gain of the inflection point 1 (15 IRE) at GAMMA. 0: 0 IRE correction 3: 9 IRE correction Controls the polarity of the correction at GAMMA2. 0: – correction 1: + correction –9– Sub Address 0110 G2 (8) Sub Address 0111 R_DRV (8) Sub Address 1000 G_DRV (8) Sub Address 1001 B_DRV (8) Sub Address 1010 SHP WIDTH (2) Sub Address 1010 SHP GAIN (4) Sub Address 1011 POL1 (1) Sub Address 1011 GAMMA1 (2) Sub Address 1011 POL2 (1) CXA2153S Sub Address 1011 GAMMA2 (4) Controls the gain of the inflection point 2 (60 IRE) at GAMMA. 0: 0 IRE correction 7: 20 IRE correction Controls the signal detection (VDET) slice level. 0: Slice level (160mV when RIN or GIN or BIN) 1: Slice level (200mV when RIN or GIN or BIN) Controls the video detection output. 0: Output on 1: Output off Controls the sync separator output. 0: Output on 1: Output off Controls the gamma function operation. 0: Gamma on 1: Gamma off Controls the VBLK synchronous DAC refresh function. The operation of this function is set to OFF when the power is turned on. 0: Function operation on 1: Function operation off Sub Address 1100 VDET LVL (1) Sub Address 1100 VDET OFF (1) Sub Address 1100 SOG OFF (1) Sub Address 1100 GM OFF (1) Sub Address 1100 D R OFF (1) – 10 – CXA2153S I2C BUS Logic System No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 High level input voltage Low level input voltage Low level output voltage SDA during current inflow of 3mA Maximum clock frequency Minimum waiting time for data change Minimum waiting time for data transfer start Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Maximum data preparation time Rise time Fall time Minimum waiting time for stop preparation Item Symbol VIH VIL VOL fSCL Min. 3.0 0 0 0 1.3 0.6 1.3 0.6 0.6 0 100 — — 0.6 Typ. — — — — — — — — — — — — — — Max. 5.0 1.5 0.4 400 — — — — — 900 — 1 300 — Unit V V V kHz µs µs µs µs µs ns ns µs ns µs tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO – 11 – CXA2153S Electrical Characteristics No. Measurement item 1 2 3 Current consumption (5V) Symbol Icc1 Measurement contents Vcc5 (5V) pin inflow current RGB signal input: None Vcc12 (12V) pin inflow current RGB signal input: None Pin inflow current when 12V OFF RGB signal input: None Min. Typ. Max. Unit 38 28 3.4 55 42 4.9 73 57 6.6 mA mA mA Current consumption Icc2 (12V) Current consumption Icc3 (12V OFF) TR Measure input rise time (TR1), input fall time (TF1), input rise time (TR2) and input fall time (TF2), then substitute these values into the following equations. 0.9 TR = √(TR22 – TR12), TF = √(TF22 – TF12) (Contrast = 7F, DRIVE = FF, BRIGHTNESS = 7F) 1.96 3 4 Pulse characteristics VIDEO amplitude 90% TR∗ TF∗ ns TF VIDEO amplitude 0% 1.6 3.1 4.6 5 Contrast control 1 GCONT1 Measure the level of the output signal amplitude Vout when a 0.7Vp-p video signal is input. GCONT1: Contrast = DRIVE = FF GCONT2: Contrast = 00/DRIVE = FF 4 4.4 4.8 Vp-p Input signal 0.7Vp-p 6 Contrast control 2 GCONT2 –100 0 120 mVp-p 7 Relative contrast GCONGAP Calculate the difference in the data obtained –180 in No.5 and No.6 between the channels. 0 180 mV – 12 – CXA2153S No. Measurement item Symbol Measurement contents Measure the level of the output signal amplitude Vout when a 0.7Vp-p video signal is input. Contrast = FF/DRIVE = 00 Min. Typ. Max. Unit 8 Drive control GDRV Input signal 0.7Vp-p –100 0 120 mVp-p GOSD1 Measure the OSD level of the output signal when the OSD pulse is input. GOSD1: OSD = FF/DRIVE = FF GOSD2: OSD = 00/DRIVE = FF OSD period RGB output signal 4 4.57 5.15 Vp-p 9 OSD gain control GOSD2 OSD level –330 0 360 mVp-p 10 Relative OSD OSDGAP Calculate the difference in the data obtained –200 in No.9 between the channels. Measure the black level of the RGB output signal. VBRT1: Brightness = 00 VBRT2: Brightness = FF 0 200 mV VBRT1 0.6 0.8 0.95 11 Brightness control RGB output signal V VBRT2 GND Black level 2.5 2.93 3.28 12 Relative brightness VBRTGAP Calculate the difference in the data obtained –200 in No.11 between the channels. Measure the BLK level of the output signal when a BLK pulse is input. 0 200 mV 13 BLK level VBLK BLK level GND 0.13 0.43 0.74 V – 13 – CXA2153S No. Measurement item Symbol Measurement contents Min. Typ. Max. Unit Sync separator output rise delay 14 Sync separator output fall delay SDLYR Vth = 50% Rise Delay Vth = 50% Sync-IN 6.5 8.5 11 ns Fall Delay SDLYF Sync-OUT 6.5 8.8 11 Sync separator output Sync-Hi 15 Sync separator output Sync-Lo Sync-Lo Sync-Hi GND 3.9 4 — V — 0.2 0.45 Sync separator 16 capacity SyncChk Gradually reduce the sync level when the duty is cycle 4.8% and 22.7% from 0.3Vp-p 0.24 and measure the sync level at which the sync signals can be separated. RGB input — — Vp-p VDET output rise delay 17 VDET output fall delay DDLYR Vth = 50% Rise Delay 0.7Vp-p Fall Delay 5.5 7.2 10 ns DDLYF Vth = 50% VDET output 8.5 11.9 15.5 VDET-Hi 18 VDET output VDET output 4 4.1 — V VDET-Lo VDET-Hi GND VDET-Lo — 0.25 0.4 – 14 – CXA2153S No. Measurement item DAC output voltage (BKG = 00) 19 DAC output voltage (BKG = FF) Symbol VBKG1 Measurement contents Measure the DAC output voltage (Pin 20) when BKG = 00/FF. Min. Typ. Max. Unit 1.25 1.45 1.67 V VBKG2 Input the crosshatch signal of Dot Clock 100MHz/ 0.7p-p to the RGB inputs, and measure the VDET output amplitude. VDET LEVEL = 0 5.45 5.7 5.95 20 VDET output amplitude VDET Input signal 0.7Vp-p 10ns 10ns 3.35 3.8 4.4 Vp-p Sharpness gain 1 SHP1 21 Sharpness gain 2 SHP2 Input a 10MHz sin wave to RGB at an amplitude of 0.1Vp-p, and measure the output level. (CONTRAST: 7F/DRIVE: FF/ABL: 5V) SHP1: SHP GAIN = F/SHP SW = 0 SHP2: SHP GAIN = 0/SHP SW = 3 SHP3: SHP GAIN = F/SHP SW = 3 Input signal 0.1Vp-p CLP potential (approximately 3.1V) 0.3 0.4 0.5 0.3 0.4 0.5 Vp-p Sharpness gain 3 SHP3 0.6 0.8 1.0 GAM1 GAM2 22 Gamma correction GAM3 GAM4 Input 15 [IRE] and 60 [IRE] amplitude signals (100 [IRE] = 0.7Vp-p) to the RGB inputs, and measure the output amplitude. GAM1: GAMMA1 = 3/POL1 = 1, Vin = 0.105Vp-p GAM2: GAMMA1 = 3/POL1 = 0, Vin = 0.105Vp-p GAM3: GAMMA2 = F/POL2 = 1, Vin = 0.42Vp-p GAM4: GAMMA2 = F/POL2 = 0, Vin = 0.42Vp-p (CONTRAST: 7F/DRIVE: FF/ABL: 5V) 0.5 0.65 0.8 0.05 0.15 0.25 Vp-p 1.8 2.1 2.4 0.8 1.0 1.25 – 15 – CXA2153S Control Characteristics CONTRAST Control Characteristics 5.0 4.5 4.0 Output level [Vp-p] Output level [Vp-p] 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 32 64 96 128 160 192 224 256 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 32 64 96 128 160 192 224 256 OSD GAIN Control Characteristics CONTRAST data OSD GAIN data DRIVE Control Characteristics 5.0 4.5 4.0 Output level [Vp-p] Output voltage [V] 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 32 64 96 128 160 192 224 256 DRIVE data 0.5 0 2.5 3.0 BRIGHTNESS Control Characteristics 2.0 1.5 1.0 32 64 96 128 160 192 224 256 BRIGHTNESS data ABL Control Characteristics 100 90 80 RGB output amplitude [%] Output voltage [V] 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 RGB BKG/G2 Control Characteristics 32 64 96 128 160 192 224 256 ABL pin voltage [V] – 16 – Control data CXA2153S Frequency Characteristic 14 12 10 8 Output gain [dB] 6 4 2 0 –2 –4 1 10 Input frequency [MHz] 100 1000 – 17 – CXA2153S Electrical Characteristics Measurement Circuit 47µF 0.1µF 47µF 75 2 5V 0.1µF 3 0.1µF 75 4 0.1µF 75 5 GND GND_G 26 Bch Output 6 0.1µF 75 7 ABL GND_B 24 0.1µF 10µF 8 OSD_BLK VREF 23 220 9 OSD_R VCC12 22 0.1µF 47µF 12V BIN BOUT 25 SYNCIN GOUT 27 Gch Output GIN GND_R 28 VCC5 ROUT 29 1 RIN VCC12 30 0.1µF Rch Output 12V 10 OSD_G R_BKG 21 11 OSD_B SYNC SEP Output 12 SYNCOUT G_BKG 20 DAC Output B_BKG 19 13 CLP G2 18 14 BLK VDET Output 15 VDET SCL 17 220 SDA 16 220 I2C Bus – 18 – CXA2153S Electrical Characteristics Measurement Circuit (Frequency Response) 1k 0.1µF 47µF 1 RIN VCC12 30 47µF 12V 75 2 5V 1k 0.1µF 3 0.1µF 75 4 0.1µF 1k 5 GND GND_G 26 SYNCIN GOUT 27 GIN GND_R 28 VCC5 ROUT 29 0.1µF Rch Output Gch Output Bch Output 6 0.1µF 75 7 5V 8 OSD_BLK VREF 23 220 9 OSD_R VCC12 22 0.1µF ABL GND_B 24 0.1µF 10µF 47µF 12V VREF BIN BOUT 25 10 OSD_G R_BKG 21 11 OSD_B SYNC SEP Output 12 SYNCOUT G_BKG 20 DAC Output B_BKG 19 13 CLP G2 18 14 BLK VDET Output 15 VDET SCL 17 220 SDA 16 220 I2C Bus – 19 – CXA2153S Application Circuit 47µF Rch Input 0.1µF 47µF 75 2 Gch Input 0.1µF 3 0.1µF Gch Output 4 75 0.1µF 5 Bch Input 6 0.1µF 75 7 ABL GND_B 24 0.1µF 10µF 8 OSD_BLK VREF 23 220 9 OSD_R VCC12 22 0.1µF 47µF 12V BIN BOUT 25 GND GND_G 26 Bch Output SYNCIN GOUT 27 GIN GND_R 28 VCC5 ROUT 29 1 RIN VCC12 30 0.1µF Rch Output 12V 10 OSD_G R_BKG 21 11 OSD_B SYNC SEP Output 12 SYNCOUT G_BKG 20 DAC Output B_BKG 19 13 CLP G2 18 14 BLK VDET Output 15 VDET SCL 17 220 SDA 16 220 I2C Bus Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 20 – CXA2153S Description of Operation 1. Sharpness function The RGB signals input to Pins 5, 7 and 10 are mixed at a ratio of 0.6G + 0.3R + 0.1B to form the Y signal. The high-frequency component is removed from this Y signal by a differentiation circuit, and the amplitude is controlled by a gain control circuit. The signal which undergoes gain control (sharpness component) has its amplitude clipped by a limiter circuit and is then added to the R, G and B signals. SHP GAIN = 0 (HEX) or SHP OFF = 1 No sharpness component 100% SHP GAIN = F (HEX) 100% 25ns (T SW = 1) 50ns (T SW = 2) 100ns (T SW = 3) 10% Section not sent to RGB output because of the limiter Limiter level = 30% (Typ.) ∗ The output level when RIN = GIN = BIN = 0.7Vp-p is set to 100%. 2. VBLK synchronous DAC refresh system The VBLK signal is removed from the composite BLK signal which has been input to Pin 14, and the data for each control DAC is overwritten all at once in synchronization with this VBLK signal. The received I2C bus data is held by a latch until the next VBLK signal arrives. As a result, I2C bus data transmission from the microcomputer is timing-free. Set the width of the V blanking pulse which is input to Pin 14 to 300µs or more. (See the next page) 3. Gamma correction function Using the output obtained when 700mVp-p RGB signals are input as a reference (100 [IRE]), the ±9 [IRE] (GAMMA1) and ±20 [IRE] (GAMMA2) waveforms can be corrected at the 15 [IRE] and 60 [IRE] inflection points, respectively. The polarity switching gain can be controlled separately for each point, enabling correction broken at two points. The I2C bus controls the polarity switching and gain correction. GAMMA1 GAMMA2 +20 [IRE] –20 [IRE] 100 [IRE] 100 [IRE] +9 [IRE] –9 [IRE] 0 15 [IRE] 100 [IRE] 0 60 [IRE] 100 [IRE] – 21 – CXA2153S VBLK Synchronous DAC Refresh System VBLK Transmission period Bus data transmission Data group (1) enable DAC refresh enable signal disable Data group (2) Data group (3) DAC refresh signal The latest data which was sent before VBLK is written to the DAC. In this case the data in (1) is written. The DAC is not rewritten while the bus data in the VBLK period is being transmitted. The transmitted data is held. The data in (3) written. The data in (2) written, if (3) is not transmitted. The VBLK signal is extracted from the composite BLK signal which has been input to Pin 14, and the DAC data for each control is rewritten all at once in synchronization with this VBLK signal. The received I2C bus data is held by a latch until the next VBLK signal arrives. Therefore, I2C bus data transmission from the microcomputer is timing-free. Set the width of the V blanking pulse which is input to Pin 14 to 300µs or more. Operation during power saving (Pin 22, VCC12 OFF) Only the sync separator function operates. All the other functions are shut down. – 22 – CXA2153S Notes on Operation 1. 2. 3. Set the output for ROUT, GOUT and BOUT for reception at high impedance. Make the wiring from ROUT, GOUT and BOUT to the power amplifier as short as possible. Connect the Vcc5, Vcc12 and VREF decoupling capacitors so that the ceramic capacitor and electrolytic capacitor are connected in parallel and the distance from the IC is less than 3mm. 4. Connect the clamp capacitors for RIN, GIN and BIN so that the distance from the IC is as short as possible. 5. Input the signals to RIN, GIN and BIN at low impedance via a clamp capacitor. 6. Set the output to OFF when the VDET/CSYNC output is not used. (Otherwise, this may cause the crosstalk to deteriorate.) 7. The VREF output cannot be used as an external power supply. 8. Turn the power on in the order of 5V → 12V, and off in the order of 12V → 5V. (Be sure to observe this order particularly during power-off, otherwise spots may remain on the screen.) 9. When applying blanking to the video period, the blanking pulse input to the BLK pin should have a high level of 4.7V or more. 10. When not using the sync separation function, connect the Sync In pin to GND through a capacitor, and set SOG_OFF = 1 (bus setting). 11. When there is no clamp pulse input to Pin 13 (CLP), the output potential rises. Always input a clamp pulse. – 23 – CXA2153S Package Outline Unit: mm 30PIN SDIP (PLASTIC) + 0.4 26.9 – 0.1 30 16 + 0.3 8.5 – 0.1 + 0.1 .05 0.25 – 0 15 1.778 1 0.5 MIN + 0.4 3.7 – 0.1 10.16 0° to 15° Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-30P-01 P-SDIP30-8.5x26.9-1.778 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 1.8g – 24 – 3.0 MIN Sony Corporation