CXA2174

CXA2174S US Audio Multiplexing Decoder Description The CXA2174S is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction and sound processor. Various kinds of filters are built-in this IC. Adjustment, mode control and sound processor control are all executed through I2C BUS. Features • Alignment-free VCO and filter • Audio multiplexing decoder dbx noise reduction decoder sound processor — One external input — Volume control are all included in a single chip. Almost any sort of signal processing is possible through this IC. • Input level, separation adjustments and each mode control are possible through I2C bus. Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting 30 pin SDIP (Plastic) Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C) 11 V • Supply voltage VCC • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1.35 W Range of Operating Supply Voltage 9 ± 0.5 V ∗ A license of the dbx-TV noise reduction system is required for the use of this device. Pin Configuration (Top View) NOISETC VCAWGT SAPOUT SUBOUT VCATC AUX-R VEOUT VEWGT VCAIN SAPIN AUX-L VETC STIN VE 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MAINOUT DGND SDA LSOUT-R PCINT1 MAININ PLINT GND VGR SCL LSOUT-L Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– COMPIN PCINT2 SAPTC IREF VCC E00815-PS Block Diagram AUX-L 30 29 TVSW EXTI/MI SUBOUT MAINOUT PCINT1 PCINT2 PLINT 8 7 9 10 17 STLPF LFLT MATRIX FLT LPF VCA VCO 1/4 1/2 "STEREO" DeEm NRSW/FOMO/SAPC (+6dB) STIND LOGIC LPF WIDEBAND COMPIN 11 VCA LPF MAININ 6 AUX-R VOL-R VOL-R VOL-L ATT VCC 16 VOL-L SCL VGR IREF SDA STIN VE DGND SAPIN VETC VCAIN SAPOUT VEWGT VEOUT VCAWGT VCATC –2– SAPVCO 1 2 LSOUT-R LSOUT-L GND 14 LPF DeEm NOISE DET "NOISE" "SAP" SAPIND SPECTRAL AMP (+4dB) I2C BUS I/F SW "PONRES" 5 4 3 20 21 18 22 23 24 25 26 28 27 LPF LPF RMSDET HPF RMSDET VE VCA BPF NOISETC 19 SAPTC 15 IREF 12 13 CXA2174S CXA2174S Pin Description Pin No. Symbol Pin voltage Equivalent circuit VCC 3k (Ta = 25°C, VCC = 9V) Description 1 LSOUT-R 4.0V 580 1 2 580 LSOUT right channel output pin. 2 LSOUT-L 4.0V LSOUT left channel output pin. VCC 7.5k ↓ 35µ 2.1V ×2 4k ×5 3 SDA — 7.5k 4.5k 3k Serial data I/O pin. VIH > 3.0V VIL < 1.5V 3 VCC 7.5k ↓ 35µ 2.1V 4k 10.5k ×4 3k 4 SCL — Serial clock input pin. VIH > 3.0V VIL < 1.5V 4 5 DGND — 5 Digital block GND. –3– CXA2174S Pin No. Symbol Pin voltage Equivalent circuit VCC 10k Description VCC 6 MAININ 4.0V 147 6 53k 4V VCC 15k ×4 VCC Input the (L + R) signal from MAINOUT (Pin 7). 7 MAINOUT 4.0V 147 7 (L + R) signal output pin. ↓ 200µ 1k VCC 147 8 8 PCINT1 4.0V 30k 22k VCC 147 9 Stereo block PLL loop filter integrating pin. 9 PCINT2 4.0V 2k 10k 10k ×2 4k –4– CXA2174S Pin No. Symbol Pin voltage Equivalent circuit VCC 20k 20k Description 147 10 PLINT 5.1V 20k 20k 10 Pilot cancel circuit loop filter integrating pin. (Connect a 1µF capacitor between this pin and GND.) ↓ 26µ 20k ↓ 50µ 10k VCC 24k 24k 14k 147 11 11 COMPIN 4.0V 34k 4V 24k Audio multiplexing signal input pin. 3k 147 12 VGR 1.3V 11k 9.7k 19.4k ×4 VCC 11k 11k Band gap reference output pin. (Connect a 10µF capacitor between this pin and GND.) 12 2.06k VCC 40k 40k 30k 30k 15k ×2 30k VCC 13 IREF 1.3V 30p 1.8k 13 147 6.3k Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62kΩ (±1%) resistor between this pin and GND.) 16k –5– CXA2174S Pin No. 14 Symbol Pin voltage — Equivalent circuit 14 Description GND Analog block GND. VCC 8k 10k 3k 1k VCC 4k ↓ 50µ 15 15 SAPTC 4.5V Set the time constant for the SAP carrier detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) 16 VCC — 16 Vcc 2k 2k 10P 4k Supply voltage pin. 580 17 SUBOUT 4.0V 2k 2k 14.4k 580 147 17 (L–R) signal output pin. 2k 4k 1k VCC 18 STIN 4.0V 23k 23k Input the (L-R) signal from SUBOUT (Pin 17). 11.7k 147 18 147 21 18k 4V 20k 4V 18k 21 SAPIN 4.0V Input the (SAP) signal from SAPOUT (Pin 20). –6– CXA2174S Pin No. Symbol Pin voltage Equivalent circuit Vcc 8k 3.3k Description 10k 1k 2k 4k 4V 3k Vcc 3k 19 NOISETC 3.0V ×2 Set the time constant for the noise detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) 200k 19 Vcc 5P 580 20 SAPOUT 4.0V 580 10k 20 147 SAP FM detector output pin. 24k ↓ 10µ 4k ↓ 50µ VCC 7.5k 22 VE 4.0V 147 22 Variable de-emphasis integrating pin. (Connect a 2700pF capacitor and a 3.3kΩ resistor in series between this pin and GND.) Vcc 580 2.9V 4V 36k 23 VEWGT 4.0V 23 147 580 Weight the variable de-emphasis control effective value detection circuit. (Connect a 0.047µF capacitor and a 3kΩ resistor in series between this pin and GND.) 8k 30k ↓ 8µ 4k ↓ 50µ –7– CXA2174S Pin No. Symbol Pin voltage Equivalent circuit Vcc Description 24 VETC 1.7V ×4 ×4 24 4k ↓ 50µ 20k ↓ 7.5µ Determine the restoration time constant of the variable de-rmphasis control effective value detection circuit. (the specified restoration time constant can be obtained by connecting a 3.3µF capacitor between this pin and GND.) Vcc 5P 580 25 VEOUT 4.0V 25 580 10k Variable de-emphasis output pin. (Connect a 4.7µF non-polar capacitor between Pins 25 and 26.) VCC 47k 20k 47k 26 VCAIN 4.0V VCC 26 VCA input pin. Input the variable de-emphasis output signal from Pin 25 via a coupling capacitor. VCC ×4 27 ×4 27 VCATC 1.7V ↓ 50µ 4k ↓ 7.5µ 20k Determine the restoration time constant of the VCA control effective value detection circuit. (the specified restoration time constant can be obtained by connecting a 10µF capacitor between this pin and GND.) –8– CXA2174S Pin No. Symbol Pin voltage Equivalent circuit VCC 40k 40k 3p Description 580 28 VCAWGT 4.0V 28 2.9V 36k 580 147 Weight the VCA control effective value detection circuit. (Connect a 1µF capacitor and a 3.9kΩ resistor in series between this pin and GND.) ↓ 50µ 4k↓ 8µ 30k 8k VCC 29 AUX-R 4.0V 10k Right channel external input pin. 29 23.5k 30 30 AUX-L 4.0V 23.5k 4V Left channel external input pin. –9– Electrical Characteristics COMPIN input level (100% modulation level) Main (L + R) (Pre-Emphasis: OFF) = 245mVrms SUB (L – R) (dbx-TV: OFF) = 490mVrms Pilot = 49mVrms SAP Carrier = 147mVrms fH = 15.734kHz Symbol — No signal 1/2 1/2 1/2 15kLPF 15kLPF 20 log ('100%'/'0%') 15kLPF 1/2 1/2 1/2 17 20 log ('12k'/'1k') 15kLPF 15kLPF 15kLPF 1kBPF 11 11 1kBPF 17 17 17 17 2 2 MONO MONO MONO MONO 11 11 11 11 11 11 11 11 11 11 11 Mode Input pin Input signal Filter Measurement conditions (Ta = 25°C, Vcc = 9V) Output pin Min. Typ. Max. Unit 23 440 –1.2 –3.0 — — 61 150 –3.0 — — 56 60 60 32 490 0 –1.0 0.1 0.15 69 190 –0.5 0.1 0.2 64 70 70 43 mA 540 mVrms 1.0 1.0 0.5 0.5 — dB dB % % dB 230 mVrms 1.0 1.0 2.0 — — — dB % % dB dB dB No. Item 1 Current consumption Icc 2 Main output level Vmain 3 FCdeem 4 Main de-emphasis frequency response Main LPF frequency response FCmain 20 log ('5k'/'1k') 20 log ('12k'/'1k') – 10 – MONO ST ST ST ST ST SAP ST 5 Main distortion THDm 6 Main overload distortion THDmmax MONO 7 Main S/N SNmain 8 Sub output level Vsub 9 Sub LPF frequency response FCsub 10 Sub distortion THDsub 11 Sub overload distortion THDsmax 12 Sub S/N SNsub 13 Crosstalk Stereo → SAP CTst CXA2174S 14 Cross talk SAP → Stereo CTsap Mono 1kHz 100% mod. Pre-em. ON Mono 5kHz 30% mod. Pre-em. ON Mono 12kHz 30% mod. Pre-em. ON Mono 1kHz 100% mod. Pre-em. ON Mono 1kHz 200% mod. Pre-em. ON Mono 1kHz, Pre-em. ON SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 12kHz, 30% mod., NR OFF SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 1kHz, 200% mod., NR OFF SUB (L-R) 1kHz, NR OFF ST-L (R) 1kHz, 100% mod., NR ON, SAP Carrier (5fH) SAP 1kHz 100% mod. NR ON, PILOT (fH) 20 log ('100%'/'0%') 20 log ('NRSW = 0'/ 'NRSW = 1') 20 log ('NRSW = 1'/'NRSW = 0') (Ta = 25°C, Vcc = 9V) Symbol 0dB = 49mVrms 20 log ('on level '/'off level') 20 20 log ('10k'/'1k') 20 15kLPF 20 log ('100%'/'0%') 15kLPF 0dB = 147mVrms 20 log ('on level' /'off level') 15kLPF 15kLPF 15kLPF 15kLPF EXT1 = '1' EXT1 = '1' M1 = '0' EXT1 = '1' EXT1 = '1' EXT1 = '1' 30/29 Sine wave 1kHz 490mVrms EXT EXT1 = '1' VOL-L = '0' VOL-R = '0' 1kBPF 15kLPF 15kLPF 15kLPF 1kBPF 20 20 –3.0 — 46 130 160 0 2.5 55 Mode Input pin Input signal Filter Measurement conditions No. Item Output pin Min. Typ. Max. Unit dB dB 190 mVrms 2.5 6.0 — –12.0 –9.0 –6.5 BUS RETURN 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2.0 23 23 23 23 440 — — — 80 4.0 35 35 35 35 490 –90 0.01 0.03 88 — –90 6.0 — — — — dB % dB dB dB dB dB dB dB 540 mVrms –80 0.3 0.3 — –80 dB % % dB dB 15 ST 11 Change PILOT (fH) Level Stereo ON level THst 16 SAP SAP SAP SAP SAP 1kHz, NR OFF 11 11 11 11 Stereo ON/OFF hysteresis HYst –9.0 –6.0 –3.0 BUS RETURN 2.0 6.0 10.0 17 SAP output level Vsap 18 SAP LPF frequency response FCsap 19 SAP distortion THDsap SAP 1kHz 100% mod. NR OFF SAP 10kHz 30% mod. NR OFF SAP 1kHz 100% mod. NR OFF 20 SAP S/N SNsap 21 SAP 11 Change SAP Carrier (5fH) Level SAP ON level THsap 22 ST ST ST ST EXT EXT EXT EXT EXT 30/29 30/29 30/29 30/29 30/29 11 11 11 11 SAP ON/OFF hysteresis HYsap – 11 – ST-L 300Hz 30% mod. NR ON ST-R 300Hz 30% mod. NR ON ST-L 3kHz 30% mod. NR ON ST-R 3kHz 30% mod. NR ON Sine wave 1kHz 490mVrms Sine wave 1kHz 490mVrms Sine wave 1kHz 490mVrms Sine wave 1kHz 2Vrms Sine wave 1kHz 490mVrms 23 ST separation 1 L → R STLsep1 24 ST separation 1 R → L STRsep1 25 ST separation 2 L → R STLsep2 26 ST separation 2 R → L STRsep2 27 LSOUT output level Vls 28 LSOUT mute attenuation MUls 29 LSOUT distortion THDls 30 LSOUT overload distortion THDlsmax 31 LSOUT S/N SNls CXA2174S 32 LSOUT volume maximum attenuation VOLmin Electrical Characteristics Measurement Circuit BUFF FILTERS 15kHz LPF fH BPF 1kHz BPF MEASURES S4 S3 S2 S1 SIGNAL GENERATOR V4 AC R2 3.9k C4 1µ C9 C12 0.047µ 2700P 23 22 20 21 19 18 17 28 25 24 27 26 C5 10µ C6 4.7µ C8 3.3µ C14 4.7µ C18 4.7µ R5 3k C17 4.7µ R7 3.3k C5 4.7µ 29 TANTALUM C2 4.7µ 30 TANTALUM SIGNAL GENERATOR V3 AC C20 100µ 16 VCC VE AUX-L VETC AUX-R VCAIN SAPIN STIN VCC VCATC VEOUT VEWGT SAPOUT VCAWGT NOISETC SUBOUT V2 9V GND SDA DGND MAINOUT PCINT2 COMPIN LSOUT-R SCL MAININ PCINT1 PLINT VGR GND LSOUT-L 1 2 3 C3 4.7µ I2C BUS DATA C7 4.7µ C10 5600p R1 220 R3 220 R6 1MEG 7 4 8 5 6 9 10 C13 1µ 11 C15 4.7µ 12 C16 10µ 13 R8 62k IREF 14 15 C19 4.7µ METAL ± 1% C1 4.7µ DGND R4 C11 100k 0.012µ SIGNAL GENERATOR V1 AC GND GND SAPTC – 12 – CXA2174S CXA2174S Adjustment Method 1. ATT adjustment 1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2) Input a 100Hz, 245mVrms sine wave signal to COMPIN and monitor the LSOUT-L output level. Then, adjust the “ATT” data for ATT adjustment so that the LSOUT-L output goes to the standard value (490mVrms). 3) Adjustment range: ±20% Adjustment bits: 4 bits 2. Separation adjustment 1) TEST BIT is set to “TEST1 = 0” and “TEST-DA = 0”. 2) Set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300Hz NR-ON) to COMPIN. At this time, adjust the “WIDEBAND” adjustment data to reduce LSOUT-R output to the minimum. 3) Next, set the frequency only of the input signal to 3kHz and adjust the “SPECTRAL” adjustment data to reduce LSOUT-R output to the minimum. 4) The adjustments in 2 and 3 above are performed to optimize the separation. 5) “WIDEBAND” “SPECTRAL” Adjustment range: ±30% Adjustment range: ±15% Adjustment bits: 6 bits Adjustment bits: 6 bits ∗ Adjust this IC through Tuner and IF when this IC is mounted in the set. – 13 – CXA2174S Register Specifications Slave address SLAVE RECEIVER 84H (1000 0100) Register table SUB ADDRESS MSB LSB BIT7 ∗ ∗ ∗ ∗ ∗ ∗ EXT1 ∗ BIT6 BIT5 TEST-DA ∗∗∗∗0000 ∗∗∗∗0001 ∗∗∗∗0010 ∗∗∗∗0011 ∗∗∗∗0100 ∗∗∗∗0101 DATA BIT4 TEST1 SPECTRAL WIDEBAND NRSW FOMO SAPC M1 BIT3 BIT2 ATT BIT1 BIT0 SLAVE TRANSMITTER 85H (1000 0101) VOL-L VOL-R ∗ : don't care Status Registers STA1 BIT7 STA2 BIT6 STA3 BIT5 SAP STA4 BIT4 NOISE STA5 BIT3 — STA6 BIT2 — STA7 BIT1 — STA8 BIT0 — POWER STEREO ON RESET Note) The micro computer reads both SAP and NOISE status and judges SAP discrimination. – 14 – CXA2174S Description of Registers Control registers Register ATT SPECTRAL WIDEBAND TEST-DA TEST1 EXT1 NRSW FOMO M1 SAPC VOL-L VOL-R Number of bits 4 6 6 1 1 1 1 1 1 1 1 1 Classification∗1 A A A T T U U U U S U U Standard setting 9 1F 1F 0 0 0 0 0 1 0 3F 3F Input level adjustment Adjustment of stereo separation (3kHz) Adjustment of stereo separation (300Hz) DAC test mode Test mode Selection of TV mode or external input mode Selection of the output signal (Stereo mode, SAP mode) Forced MONO (Left channel only is MONO during SAP output.) Selection of LSOUT mute function ON/OFF (0: mute ON, 1: mute OFF) Selection SAP mode or L + R mode according to the presence of SAP brodecasting Left channel volume control Right channel volume control Contents ∗1 Classification U: User control A: Adjustment S: Proper to set T: Test Status registers Register PONRES STEREO SAP NOISE Number of bits 1 1 1 1 POWER ON RESET detection; Stereo discrimination of the COMPIN input signal; SAP discrimination of the COMPIN input signal; Noise level discrimination of the SAP signal; Contents 1: RESET 1: Stereo 1: SAP 1: Noise – 15 – CXA2174S Description of Control Registers ATT (4): Perform input level adjustment. 0 = Level min. F = Level max. Perform high frequency (fs = 3kHz) separation adjustment. 0 = Level max. 3F = Level min. Perform low frequency (fs = 300Hz) separation adjustment. 0 = Level min. 3F = Level max. Set DAC output test mode. 0 = Normal mode 1 = DAC output test mode In addition, the following output are present at Pin 2. LSOUT-L (Pin 2): DA control DC level Monitor SAPBPF and NRBPF output 0 = Normal mode 1 = SAPBPF, NRBPF output In addition, the following outputs are present at Pins 1 and 2. LSOUT-L (Pin 2): SAP BPF OUT LSOUT-R (Pin 1): NR BPF OUT Select TV mode or external input mode 0 = TV mode 1 = External input mode Select stereo mode or SAP mode 0 = Stereo mode 1 = SAP mode Select forced MONO mode 0 = Normal mode 1 = Forced MONO mode Mute the LSOUT-L and LSOUT-R output. 0 = Mute ON 1 = Mute OFF SPECTRAL (6): WIDEBAND (6): TEST-DA (1): TEST1 (1): EXT1 (1): NRSW (1): FOMO (1): M1 (1): – 16 – CXA2174S SAPC (1): Select the SAP signal output mode When there is no SAP signal, the conditions for selecting SAP output are selected by SAPC. 0 = L + R output is selected 1 = SAP output is selected LSOUT-L output signal level control 0 = Volume min. 3F = Volume max. –1.25dB/STEP LSOUT-R output signal level control 0 = Volume min. 3F = Volume max. –1.25dB/STEP VOL-L (6): VOL-R (6): – 17 – CXA2174S Description of Mode Control Mode control SAPC = 0 “Select dbx input and TV decoder output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) • During ST input: left channel: L, right channel: R • During other input: left channel: L + R, right channel: L + R NRSW = 1 (SAP output) • When there is “SAP” during SAP discrimination – left channel: SAP, right channel: SAP • When there is “No SAP”, output is the same as when NRSW = 0. SAPC = 1 “Select dbx input and TV decoder output” Conditions: FOMO = 0 NRSW = 0 (MONO or ST output) As on the left NRSW = 1 (SAP output) NRSW • Regardless of the presence of SAP discrimination, dbx input: “SAP” left channel: SAP, right channel: SAP However, when there is no SAP, SAPOUT output is soft muted (–7dB) “Forced MONO” FOMO FOMO = 1 • During SAP output: left channel: L + R, right channel: SAP • During ST or MONO output: left channel: L + R, right channel: L + R Change the selection conditions for “MONO or ST output” and “SAP output”. SAPC SAPC = 0: Switch to SAP output when there is SAP discrimination. Do not switch to SAP output when there is no SAP discrimination. SAPC = 1: Switch to SAP output regardless of whether there is SAP discrimination. “MUTE” M1 = 0: LSOUT output is muted. M1 – 18 – CXA2174S Decoder Output and Mode Control Table 1 (SAPC = 1) Input signal mode ST 0 0 MONO ∗1 0 0 0 0 1 1 1 STEREO ∗1 1 1 1 1 1 0 0 0 MONO & SAP 0 0 0 1 1 STEREO & SAP 1 1 1 1 Mode detection SAP 0 0 0 ∗ ∗ ∗ 0 0 1 1 0 0 ∗ ∗ 1 1 1 1 1 1 1 1 1 1 1 1 NOISE 0 0 0 1 1 1 ∗ ∗ 1 1 0 0 1 1 ∗ ∗ 0 0 1 1 ∗ ∗ 0 0 1 1 Mode control NRSW 0 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 FOMO ∗ 0 1 ∗ 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAPC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 dbx input MUTE SAP SAP MUTE (SAP) (SAP) L–R MUTE L–R MUTE SAP SAP (SAP) (SAP) MUTE MUTE SAP SAP (SAP) (SAP) L–R MUTE SAP SAP (SAP) (SAP) Output Lch L+R SAP L+R L+R (SAP) L+R L L+R L L+R SAP L+R (SAP) L+R L+R L+R SAP L+R (SAP) L+R L L+R SAP L+R (SAP) L+R Rch L+R SAP SAP L+R (SAP) (SAP) R L+R R L+R SAP SAP (SAP) (SAP) L+R L+R SAP SAP (SAP) (SAP) R L+R SAP SAP (SAP) (SAP) Note (SAP) : The SAPOUT output signal is soft muted (approximately –7dB). The signal is soft muted when NOISE = 1. ∗ : Don’t care. ∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. – 19 – CXA2174S Decoder Output and Mode Control Table 2 (SAPC = 0) Input signal mode ST 0 0 MONO ∗1 0 0 0 1 1 1 STEREO ∗1 1 1 1 1 1 0 0 0 MONO & SAP 0 0 0 0 0 1 1 1 STEREO & SAP 1 1 1 1 1 Mode detection SAP 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOISE ∗ 1 1 1 1 ∗ ∗ ∗ ∗ 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Mode control NRSW ∗ 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FOMO ∗ 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SAPC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dbx input MUTE MUTE MUTE (SAP) (SAP) L–R MUTE L–R MUTE L–R MUTE (SAP) (SAP) MUTE MUTE SAP SAP MUTE MUTE (SAP) (SAP) L–R MUTE SAP SAP L–R MUTE (SAP) (SAP) Output Lch L+R L+R L+R (SAP) L+R L L+R L L+R L L+R (SAP) L+R L+R L+R SAP L+R L+R L+R (SAP) L+R L L+R SAP L+R L L+R (SAP) L+R Rch L+R L+R L+R (SAP) (SAP) R L+R R L+R R L+R (SAP) (SAP) L+R L+R SAP SAP L+R L+R (SAP) (SAP) R L+R SAP SAP R L+R (SAP) (SAP) Note (SAP) : The SAPOUT output signal is soft muted (approximately –7dB). The signal is soft muted when NOISE = 1. ∗ : Don’t care. ∗1 SAP or NOISE discrimination may be made during MONO or STEREO input when the noise is inputted in the weak electric field. Then microcomputer reads "NOISE" status from IC and decides whether SAP is outputted. "NOISE" status rises earlier than "SAP" status when the amount of noise is increased to COMPIN. – 20 – CXA2174S Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 1. PEAK DEV kHz 50 AM-DSB-SC 50 25 25 L-R dbx-TV NR PILOT 15 SAP dbx-TV NR FM 10kHz 50 – 10kHz 2fH 3fH 4fH 5fH TELEMETRY FM 3kHz 3 6fH 6.5fH f L+R 5 50 – 15kHz fH fH = 15.734kHz Fig. 1. Base band spectrum I C BUS DECODER MODE CONTROL (MAIN OUT) (MAIN IN) 2 PLL (VCO 8fH) STEREO LPF MVCA 2fHL0° fHL90° fHL0° PILOT DET (COMPIN) MAIN LPF DE.EM PILOT CANCEL SUB LPF L-R (DSB) DET 11 7 L+R WIDEBAND SUBVCA 4.7µ 6 (SUBOUT) (ST IN) MATRIX (Lch) NR SW to TVSW 17 L – R 4.7µ 18 SAP BPF SAP (FM) DET SAP LPF INJ. LOCK A (SAP OUT) (SAP IN) dbx-TV BLOCK B (Rch) 20 4.7µ NOISE DET I 2C BUS DECODER 21 MODE CONTROL SAP DET I 2C BUS DECODER MODE CONTROL Fig. 2. Overall block diagram (See Fig. 3 for the dbx-TV block) (ST IN) 18 (SAP IN) NR SW A FIXED VARIABLE DEEMPHASIS DEEMPHASIS (VE OUT) (VCA IN) B VCA to MATRIX 25 4.7µ HPF LPF LPF RMS DET RMS DET 26 21 Fig 3. dbx-TV block – 21 – CXA2174S (1) L + R (MAIN) After the audio multiplexing signal input from COMPIN (Pin 11) passes through MVCA, the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L – R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2) L – R (SUB) The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW circuit after passing through SUBVCA. (3) SAP SAP is an FM signal using 5fH as a carrier as shown in the Fig. 1. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. When there is no SAP signal, the Pin 20 output is soft muted. (4) Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5fH carrier amplitude. NOISE discrimination is performed by detecting the noise near 25kHz after FM detection of SAP signal. (5) dbx-TV block Either the L – R signal or SAP signal input respectively from ST IN (Pin 18) or SAP IN (Pin 21) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable deemphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) Matrix, TVSW The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and SAP signals according to the mode control and whether there is ST / SAP discrimination. “TVSW” switches the “MATRIX” output signal and external input signal. (7) Others “MVCA” is a VCA which adjusts the input signal level to the standard level of this IC. “Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 13) with GND become the reference current. – 22 – Application Circuit AUX INPUT 3.9k 3k 3.3µ 4.7µ 0.047µ 2700P 24 23 22 20 21 16 17 19 18 4.7µ 4.7µ 100µ 3.3k 4.7µ 10µ 1µ 28 25 27 26 4.7µ TANTALUM TANTALUM 4.7µ +9V 30 29 VE AUX-L VETC AUX-R VCATC VCAIN VEOUT VEWGT SAPIN SAPOUT STIN VCAWGT SDA DGND MAINOUT PCINT2 COMPIN NOISETC LSOUT-R SCL MAININ PCINT1 PLINT VGR GND SUBOUT LSOUT-L 1 3 1MEG 1µ 4.7µ 4.7µ 5600p 220 220 4 7 11 8 10 2 5 6 9 12 4.7µ 10µ 13 IREF 14 15 4.7µ 62k METAL ± 1% 4.7µ LS OUTPUT DGND µ-com 100k 0.012µ Composite baseband signal input GND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. SAPTC VCC – 23 – CXA2174S CXA2174S I2C BUS block items (SDA, SCL) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 High level input voltage Low level input voltage High level input current Low level input current Low level output voltage SDA (Pin 3) during 3mA inflow Maximum inflow current Input capacitance Maximum clock frequency Minimum waiting time for data change Minimum waiting time for start of data transfer Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation Item Symbol VIH VIL IIH IIL VOL IOL CI fSCL tBUF tHD: STA tLOW tHIGH tSU: STA tHD: DAT tSU: DAT tR tF tSU: STO Min. 3.0 0 — — 0 3 — 0 4.7 4.0 4.7 4.0 4.7 0 250 — — 4.7 Typ. — — — — — — — — — — — — — — — — — — Max. 5.0 1.5 10 10 0.4 — 10 100 — — — — — — — 1 300 — ns µs ns µs µs Unit V µA V mA pF kHz I2C BUS load conditions: Pull-up resistor 4kΩ (Connect to +5V) Load capacity 200pF (Connect to GND) I2C BUS Control Signal SDA tBUF SCL P S tHD: STA tLOW tHIGH tSU: STA tSU: DAT Sr tSU: STO P tR tF tHD: STA tHD: DAT – 24 – CXA2174S I2C BUS Signal There are two I2C signals, SDA (Serial DATA) and SCL (Serial CLOCK) signals. SDA is a bidirectional signal. • Accordingly there are 3 values outputs, H, L and Hi-Z. H L Hi-Z L • I2C transfer begins with Start Condition and ends with Stop Condition. Start Condition S Stop Condition P SDA SCL – 25 – CXA2174S • I2C data Write (Write from I2C controller to the IC) L during Write MSB SDA Hi-Z MSB LSB Hi-Z SCL S 1 2 3 4 5 6 7 8 9 1 8 9 Address MSB LSB Hi-Z Hi-Z ACK Sub Address ACK 1 8 9 1 8 9 DATA (n) ACK DATA (n+1) ACK DATA (n + 2) Hi-Z Hi-Z 8 9 1 8 9 P ∗ Data can be transferred in 8-bit units to be set as required. Sub address is incremented automatically. DATA ACK DATA ACK • I2C data Read (Read from the IC to I2C controller) H during Read Hi-Z SDA SCL S 1 6 7 8 9 1 7 8 9 P Address ACK DATA ACK • Read timing MSB IC output SDA LSB SCL 9 1 2 3 4 5 6 7 8 9 Read timing ACK DATA ACK ∗ Data Read is performed during SCL rise. – 26 – CXA2174S Input level vs. Distortion characteristics 1 (MONO) Input signal: MONO (Pre-emphasis on), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF Measurement point: LSOUT-L/R Input level vs. Distortion characteristics 2 (Stereo) Input signal: Stereo L = –R (dbx-TVNR ON), 1kHz 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, ST mode Measurement point: LSOUT-L/R 1.0 10 Distortion [%] Distortion [%] 0.1 1.0 Standard level (100%) –10 0 Input level [dB] –10 0 Input level [dB] 10 Standard level (100%) 10 Input level vs. Distortion characteristics 3 (SAP) Input signal: SAP (dbx-TVNR ON) 1kHz, 0dB = 100% modulation level VCC = 9V, 30kHz using LPF, SAP mode Measurement point: LSOUT-L/R 10 Distortion [%] 1.0 Standard level (100%) –10 0 Input level [dB] 10 – 27 – CXA2174S Stereo LPF frequency characteristics 10 Main LPF and Sub LPF frequency characteristics 30 5 Gain (FC main and FC sub) [dB] 20 10 0 –10 –20 –30 –40 –50 Gain [dB] 0 –5 –10 0 20 40 60 80 100 1 2 5 7 10 20 50 70 100 Frequency [kHz] Frequency [kHz] SAP frequency characteristics and group delay 100 20 5fH 10 Gain 90 80 –20 0 Volume charactiristics Gain [dB] 60 0 50 40 –10 Group delay 3.8fH 20 40 60 80 30 20 –20 6.2fH 100 10 0 120 Group delay [µs] 70 LSOUT output level [dB] –40 –60 –80 Input: AUXIN (Pins 29, 30) 1kHz, 490mVrms Output: LSOUT (Pins 1, 2) –100 0 1F 2F F Control data VOL-L, VOL-R 3F Frequency [kHz] – 28 – CXA2174S Package Outline Unit: mm 30PIN SDIP (PLASTIC) + 0.4 26.9 – 0.1 30 16 + 0.3 8.5 – 0.1 + 0.1 .05 0.25 – 0 15 1.778 1 0.5 MIN + 0.4 3.7 – 0.1 10.16 0˚ to 15˚ Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type. 0.5 ± 0.1 0.9 ± 0.15 PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-30P-01 P-SDIP30-8.5x26.9-1.778 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 1.8g – 29 – 3.0 MIN Sony Corporation