CXA2503

CXA2503AR Decoder/Driver/Timing Generator for Color LCD Panels For the availability of this product, please contact the sales office. Description The CXA2503AR is an IC designed exclusively to drive color LCD panels LCX005BK/BKB and LCX009AK/AKB. This IC greatly reduces the number of circuits and parts required to drive LCD panels by incorporating RGB decoder functions for video signals, driver functions, and a timing generator for driving panels onto a single chip. This chip has a built-in serial interface circuit and electronic attenuators which allow various mode settings and adjustments to be performed through direct control from an external microcomputer, etc. Features • Color LCD panels LCX005BK/BKB and LCX009AK/ AKB driver • Supports NTSC and PAL systems • Supports 16:9 wide display • Supports composite inputs, Y/C inputs and Y/color difference inputs • Serial interface circuit • Electronic attenuators (D/A converter) • BPF, trap and delay line • Sharpness function • 2-point γ correction circuit • R, G, B signal delay time adjustment circuit • Polarity inversion circuit (line inverted mode) • Supports external RGB input • Supports AC drive for LCD panel during no signal Applications • LCD viewfinders • Compact liquid crystal projectors • Compact LCD monitors Structure Bipolar CMOS IC 64 pin LQFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 6 • Supply voltage VCC1 – GND1, 3 VCC2 – GND2 14 VDD1 – VSS1 4.5 VDD2 – VSS2 4.5 • Analog input pin voltage VINA –0.3 to VCC1 • • • • V V V V V Digital input pin voltage VIND –0.3 to VDD1 + 0.3 V Operating temperature Topr –15 to +75 °C Storage temperature Tstg –40 to +125 °C Allowable power dissipation PD (Ta ≤ 75°C) 350mW Note) Operating conditions Supply voltage VCC1 – GND1, 3 4.25 to 5.25 VCC2 – GND2 11.0 to 13.5 VDD1 – VSS1 2.7 to 3.6 VDD2 – VSS2 2.7 to 3.6 Note) With substrate Size: 114.3 × 76.1 × 1.5mm Material: Glass fabric base epoxy V V V V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97910-PS CXA2503AR Block Diagram SIG.CENTER G OUT R OUT TEST4 TEST3 TEST2 B OUT GND2 LOAD DATA VCC2 FB R RGT 48 47 +12V 46 45 44 43 42 41 40 GND2 39 38 37 36 35 34 33 buf VCC1 49 +4.5V buf buf SEREAL BAS I/F VSS2 32 VSS2 B-Y IN 50 CLAMP R-Y IN 51 EXT COLOR & BALANCE C OUT 52 INT/EXT R-BRT BLK LIM 53 APC B-BRT APC 54 VXO HUE PS LPF BRT MATRIX VXO OUT 55 HUE COLOR CONTRAST CNTRAST COLOR CONT V REG 57 REG. ACC DET KILLER START UP 58 BPF PIC CONT C IN 59 ACC AMP HAFC PLL-COUNTER & DECODER HD EXT SW RGB γ -2 S/H γ -1 GAMMA D/A BRIGHT PALSW SUBBRIGHT VWIN VPAL COLOR HUE PAL ID PAL SW SCLK FB G FB B 31 VD2 DEMOD POL SW VGATE WIDE VTST 30 VD1 FRP 29 EN 28 VCK1 27 VCK2 26 VST VXO IN 56 25 TEST1 24 FLD IN 23 FLD OUT 22 HD F0 ADJ 60 FILT ADJ CLP BGP SBLK V-SEP CLAMP TRAP DL 1 HCNT H-PULSE 21 HCK1 GND3 61 GND3 Y IN 62 20 HCK2 HGATE H-SKEW DET SYNC SEP 19 HST PD 18 CLR PIC 63 TEST0 64 H. FILTER PLL +3V 17 VDD2 VCO ADJ GND1 1 2 3 4 5 6 7 8 9 10 11 12 VSS1 13 14 15 +3V 16 PWRST H.FIL OUT VCO ADJ RPD SYNC IN EXT B GND1 EXT G TRAP EXT R VD IN S.SEP IN –2– VDD1 VSS1 CKO CKI CXA2503AR Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol PWRST VD IN TRAP GND1 SYNC IN H.FIL OUT S.SEP IN EXT R EXT G EXT B VCO ADJ RPD VSS1 CKI CKO VDD1 VDD2 CLR HST HCK2 HCK1 HD FLD OUT FLD IN TEST1 VST VCK2 VCK1 EN VD1 VD2 VSS2 O O O O O O O O O O O O I I O I O I I I I O O I/O — I System reset External vertical sync input External trap connection Analog 4.5V GND Video input for sync separation Video output for sync input Sync separation circuit input External digital input R External digital input G External digital input B VCO adjustment voltage output Phase comparator output Digital 3V GND for oscillation cell Oscillation cell input Oscillation cell output Digital 3V power supply for oscillation cell Digital 3V power supply CLR pulse output H start pulse output H clock pulse 2 output H clock pulse 1 output HD pulse output Field identification output Field identification input Test (Leave this pin open.) V start pulse output V clock pulse 2 output V clock pulse 1 output EN pulse output VD1 pulse output VD2 pulse output Digital 3V GND Description Input pin for open status –3– CXA2503AR Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol SCLK DATA LOAD TEST2 TEST3 TEST4 RGT GND2 B OUT FB B G OUT FB G R OUT FB R VCC2 SIG.CENTER VCC1 B-Y IN R-Y IN C OUT BLK LIM APC VXO OUT VXO IN V REG START UP C IN F0 ADJ GND3 Y IN PIC TEST0 I/O I I I Serial interface clock input Serial interface data input Serial interface load input Test (Leave this pin open.) Test (Leave this pin open.) Test (Leave this pin open.) I Description Input pin for open status H H H Switches between Normal scan (H) and Reverse scan (L) Analog 12V GND H O O O O O O B output B signal DC voltage feedback circuit capacitor connection G output G signal DC voltage feedback circuit capacitor connection R output R signal DC voltage feedback circuit capacitor connection Analog 12V power supply I RGB output DC voltage adjustment Analog 4.5V power supply I I O I O O I O O I O B-Y demodulator input (or B-Y color difference signal input) R-Y demodulator input (or R-Y color difference signal input) Chroma signal output Black peak limiter level adjustment APC detective filter connection VXO output VXO input Constant voltage capacitor connection Startup time constant connection Chroma signal input Internal filter adjusting resistor connection Analog 4.5V GND I I I Y signal input Y signal frequency response adjustment Test (Leave this pin open.) (H: Pull up) –4– CXA2503AR Analog Block Pin Description Pin No. Symbol Pin voltage VDD2 2µA 1 Equivalent circuit Description 1 PWRST — 1k TG block system reset pin. The system is reset when this pin is connected to GND. Connect a capacitor between this pin and GND. GND1 VDD2 50k 50k 2 50k GND1 2 VDIN — External vertical sync signal input. VCC1 70µA 1k 300 3 130µA GND1 3 TRAP 2.2V External trap connection. Connect the trap between this pin and GND to remove the chroma component. VDD1 1k 5 SYNC IN 1.5V 5 1k 30µA GND1 2.1V Sync input. Normally inputs the Y signal. The standard signal input level is 0.5Vp-p (100% white level from the sync tip). VDD2 20k 6 6 H.FIL OUT 2.5V Outputs the video signal for input to the sync separation circuit. 20k GND1 –5– CXA2503AR Pin No. Symbol Pin voltage VDD2 Equivalent circuit Description 17k 7 S.SEP IN 1.0V 7 Sync separation circuit input. Input the H FILTER output signal. 1.8V 2.8V 10µA GND1 8 EXT-R VCC1 30µA 8 300 9 EXT-G — 9 10 50k 2.7V GND1 10 EXT-B External digital signal inputs. There are two threshold values: Vth1 (= 1.0V) and Vth2 (= 2.0V). When one of the RGB signals exceeds Vth1, all of the RGB outputs go to black level; when an input exceeds Vth2, only the corresponding output goes to white level. VCC2 11 VCO ADJ — 500 11 70µA GND2 VCO adjustment voltage output. 41 B OUT VCC2 41 50 50 40µA 43 G OUT VCC2 2 43 45 RGB signal outputs. 45 R OUT GND2 42 FB B VCC2 42 1k 44 FB G 2.5V 44 46 Smoothing capacitor connection for the feedback circuit of RGB output DC level control. Use a low-leakage capacitor because of high impedance. 46 FB R GND2 –6– CXA2503AR Pin No. Symbol Pin voltage VCC2 Equivalent circuit Description 150k 48 SIG. CENTER 6.0V 300 48 150k GND2 RGB output DC voltage control. When used with a VCC2 of 12V or more, apply 6V from an external source. VCC1 50 B-Y IN 50 500 500 10k — 51 R-Y IN 51 30µA GND1 50µA Color difference demodulation circuit inputs. Color difference signal is input when using Y/color difference input. At this time, the clamp level is approximately 2.8V. Pin 52 signal is input in other modes. (except D-PAL∗1) At this time, the DC level is approximately 2.0V. VCC1 52 C OUT 1.3V 52 350µA GND1 Color adjusted chroma signal output. The burst level is approximately 140mVp-p (typ.). (420mVp-p during D-PAL.) VCC1 50k 53 BLK LIM — 53 Sets the RGB output amplitude (black-black) clip level. GND1 VCC1 54 APC 2.7V 1k 54 APC detective filter connection. GND1 ∗1 D-PAL is a demodulation method that uses an external delay line during demodulation; S-PAL is a demodulation method that internally processes chroma demodulation. –7– CXA2503AR Pin No. Symbol Pin voltage Equivalent circuit Description VCC1 55 VXO OUT 2.9V 55 400µA GND1 VXO output. VCC1 500 56 VXO IN 3.2V 56 3k 3.2V GND1 VXO input. VCC1 57 V REG 3.6V 57 60k 30k GND1 Smoothing capacitor connection for the internally generated constant voltage source circuit. Connect a capacitor of 1µF or more. VCC1 0.5µA 58 START UP — 1k 58 GND1 Prevents output of the HST and VST pulses for driving LCD panels for a certain time during power-on. Connect a capacitor between this pin and GND. When not using this pin, connect to VCC1. VCC1 500 15p 59 C IN — 59 20k 30µA GND1 Video signal input when using composite signal input. Chroma signal input when using Y/C signal input. Leave this pin open when using Y/color difference input. –8– CXA2503AR Pin No. Symbol Pin voltage Equivalent circuit Description VCC1 1k 60 F0 ADJ 2.4V 60 15µA GND1 Connect resistance of 82kΩ between this pin and GND1 to adjust the internal filters using the outflow current value. VCC1 1k 62 Y IN 3.1V 62 70µA GND1 Y signal input. The standard signal input level is 0.5Vp-p (100% white level from the sync tip). Input at low impedance (75Ω or less). VCC1 20k 30k 63 PIC 2.25V 63 10k 2.25V 50µA 50µA Adjusts frequency response of luminance signal. Increasing the voltage emphasizes contours. GND1 –9– CXA2503AR Setting Conditions for Measuring Electrical Characteristics When measuring the electrical characteristics, the TG (timing generator) block must be initialized by performing Settings 1 and 2 below. Setting 1. System reset After turning on the power, set SW1 to ON and start up V1 from GND in order to activate the TG block system reset. (See Fig. 1-1.) Setting 2. Horizontal AFC adjustment Input SIG5 (VL = 0mV) to (A) and adjust serial bus register PLL ADJ so that WL and WH of the TP12 output waveform are the same. (See Fig. 1-2.) VDD SIG5 WS V1 (PWRST) TR TP12 TR > 10µs WL WH WL = WH Fig. 1-1. System reset Fig. 1-2. Horizontal AFC adjustment – 10 – CXA2503AR Electrical Characteristics – DC Characteristics Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required. VCC1 = 4.5V, VCC2 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25°C SW1, SW53, SW63 = ON SW8, SW9, SW10, SW59 = A SW50, SW51 = B V53 = 0V, V63 = 2.2V Set the serial bus registers to the "Serial Bus Register Initial Settings". Item Symbol Conditions Min. Typ. Max. Unit Power supply characteristics ICC11 Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the ICC1 current value. COMP input mode Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the ICC1 current value. Y/C input mode Input SIG4 to (A), (D) and (E). Measure the ICC1 current value. SW50, SW51 = A, SW59 = B Y/color difference input mode Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the ICC2 current value. Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the IDD current value. LCX009 mode Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the IDD current value. LCX005 mode 20 27 34 mA Current consumption VCC1 ICC12 19 26 33 mA ICC13 15 21 27 mA Current consumption VCC2 ICC2 3 5 8 mA IDD1 Current consumption VDD IDD2 4 6 8 mA 3.5 5 6.5 mA – 11 – CXA2503AR Item Symbol Conditions Min. Typ. Max. Unit Digital block I/O characteristics Input current FLDIN pin Input current High level input voltage Low level input voltage High level output voltage Output pins except CKO and RPD Low level output voltage Output pins except CKO and RPD High level output voltage CKO pin Low level output voltage CKO pin High level output voltage RPD pin Low level output voltage RPD pin Output off leak current RPD pin II1 II2 VIH VIL VOH1 Normal input pin VIN = VDD VIN = VSS –145 0.7VDD 0.3VDD 2.8 –60 –10 10 –24 µA µA V V V Input pin with pull-up resistor∗1 VIN = VSS CMOS input cell∗3 CMOS input cell∗3 IOH = –1mA∗2 VOL1 IOL = 1mA∗2 0.3 V VOH2 VOL2 VOH3 VOL3 IOFF IOH = –3mA IOL = 3mA IOH = –0.5mA IOL = 0.7mA High impedance status VOUT = VSS or VOUT = VDD 0.5VDD 0.5VDD VDD – 1.2 1.0 –40 40 V V V V µA ∗1 Input pins with pull-up resistors: SCLK, DATA, LOAD, RGT ∗2 Output pins except CKO and RPD: CLR, HST, HCK1, HCK2, HD, VD1, VD2, FLDOUT, VST, VCK1, VCK2, EN ∗3 CMOS input cells: FLDIN, SCLK, DATA, LOAD, RGT – 12 – CXA2503AR Electrical Characteristics – AC Characteristics Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required. VCC1 = 4.5V, VCC2 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25°C SW1, SW53, SW63 = ON SW8, SW9, SW10 = A SW50, SW51, SW59 = B V53 = 0V, V63 = 2.2V Set the serial bus registers to the "Serial Bus Register Initial Settings". Unless otherwise specified, measure the non-inverted outputs for TP41, TP43 and TP45. Item Y signal system Video maximum gain Contrast characteristics TYP Contrast characteristics MIN GV GCNTTP GCNTMN FCYYC Y signal frequency characteristics FCYCMN FCYCMP Picture adjustment variable amount 1 (composite input, LCX005 mode) Picture adjustment variable amount 2 (composite input, LCX009 mode) Picture adjustment variable amount 3 (Y/C input, LCX005 mode) Picture adjustment variable amount 4 (Y/C input, LCX009 mode) GSHP1X GSHP1N GSHP2X GSHP2N GSHP3X GSHP3N GSHP4X GSHP4N Input SIG4 to (A) and measure the ratio between the output amplitude (white – black) and input amplitude at TP43. Input SIG4 to (A) and measure the ratio between the output amplitude (white – black) and input amplitude at TP43. Input SIG4 to (A) and measure the ratio between the output amplitude (white – black) and input amplitude at TP43. Assume the output amplitude at TP43 when SIG1 (0dB, no burst, 100kHz) is input to (A) as 0dB. Vary the frequency of the input signal to obtain the frequency with an output amplitude of –3dB. Y/C input, V63 = 1.5V Composite input (NTSC), V63 = 2.2V Composite input (PAL), V63 = 2.2V 19 13 –9 5.0 2.5 3.0 8 12 –3 6 9 –4 10 15 –1 10 14 –2 0 2 2 1 22 17 –5 25 21 –1 dB dB dB MHz MHz MHz dB dB dB dB dB dB dB dB Symbol Conditions Min. Typ. Max. Unit Assume the output amplitude at TP43 when SIG7 (100kHz) is input to (A) as 0dB. Set SIG7 to 1.8MHz and measure GSHP1X and GSHP1N as the amounts by which the output amplitude at TP43 changes when V63 = 4V and 0V, respectively. Assume the output amplitude at TP43 when SIG7 (100kHz) is input to (A) as 0dB. Set SIG7 to 2.0MHz and measure GSHP2X and GSHP2N as the amounts by which the output amplitude at TP43 changes when V63 = 4V and 0V, respectively. Assume the output amplitude at TP43 when SIG7 (100kHz) is input to (A) as 0dB. Set SIG7 to 1.8MHz and measure GSHP3X and GSHP3N as the amounts by which the output amplitude at TP43 changes when V63 = 4V and 0V, respectively. Assume the output amplitude at TP43 when SIG7 (100kHz) is input to (A) as 0dB. Set SIG7 to 2.5MHz and measure GSHP4X and GSHP4N as the amounts by which the output amplitude at TP43 changes when V63 = 4V and 0V, respectively. Input SIG2 (0dB) to (A). Using a spectrum analyzer, measure the input and the 3.58MHz or 4.43MHz component of TP43, and obtain CRLEKY = 150mV × 10∆CLK/20 using their difference ∆CLK. Input SIG9 (VL = 150mV) to (A). Measure the delay time from the 2T pulse peak of the input signal to the peak of the non-inverted output at TP43. Y/C input Composite input (NTSC) Composite input (PAL) Carrier leak (residual carrier) CRLEKY 30 mV TDYYC Y signal I/O delay time TDYCMN TDYCMP 230 430 430 330 530 530 430 630 630 ns ns ns – 13 – CXA2503AR Item Chroma signal block Symbol Conditions Min. Typ. Max. Unit ACC amplitude characteristics 1 ACC1 ACC amplitude characteristics 2 ACC2 Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB/+6dB/–20dB, 3.58MHz burst/chroma phase = 180°, or 4.43MHz burst/chroma phase = ±135°) to (B). Measure the output amplitude at TP52, assuming the output corresponding to 0dB, +6dB and –20dB as V0, V1 and V2, respectively. ACC1 = 20 log (V1/V0) ACC2 = 20 log (V2/V0) SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz burst/chroma phase = 180°, or 4.43MHz burst/chroma phase = ±135°) to (B). Changing the SIG2 burst frequency, measure the frequency fl at which the TP41 output appears (the killer mode is canceled). NTSC: FAPCN = fl – 3579545Hz PAL: FAPCP = fl – 4433619Hz SW59 = A NTSC –3 0 3 dB PAL –3 0 3 dB NTSC –3 0 3 dB dB PAL –3 0 3 FAPCN NTSC ±500 Hz APC pull-in range FAPCP PAL ±500 Hz Color adjustment characteristics MAX Color adjustment characteristics MIN GCOLMX GCOLMN Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz burst/chroma phase = 180°) to (B). Assume the chroma output when serial bus register COLOR = 80H, 0FFH and 0H as V0, V1 and V2, respectively. GCOLMX = 20 log (V1/V0) GCOLMN = 20 log (V2/V0) SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, burst/chroma phase variable) to (B). Assume the phase at which the output amplitude at TP41 reaches a minimum when serial bus register HUE = 80H, 0FFH and 0H as θ0, θ1 and θ2, respectively. HUEMX = θ1 – θ0 HUEMN = θ2 – θ0 SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (level variable, 3.58MHz burst/chroma NTSC phase = 180°, or 4.43MHz burst/chroma phase = ±135°) to (B), and measure the output amplitude at TP41. Gradually reduce the SIG2 amplitude level and measure the PAL level at which the killer operation is activated. SW59 = A 4 6 dB –25 –15 dB HUE adjustment range MAX HUEMX –30 –40 deg HUE adjustment range MIN HUEMN 30 60 deg ACKN Killer operation input level ACKP –36 –30 dB –34 –28 dB – 14 – CXA2503AR Item Symbol VRBN Conditions Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz) to B and change the chroma phase. Assume the maximum amplitude at TP41 as VB, the maximum amplitude at TP43 as VG, and the maximum amplitude at TP45 as VR. VRBN = VR/VB, VGBN = VG/VB SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz) to B and change the chroma phase. Assume the phase at which the amplitude at TP41, TP43 and TP45 reaches a maximum as θB, θG and θR, respectively. θRBN = θR – θB, θGBN = θG – θB SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz) to B and change the chroma phase. Assume the maximum amplitude at TP41 as VB, the maximum amplitude at TP43 as VG, and the maximum amplitude at TP45 as VR. VRBP = VR/VB, VGBP = VG/VB SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz) to B and change the chroma phase. Assume the phase at which the amplitude at TP41, TP43 and TP45 reaches a maximum as θB, θG and θR, respectively. θRBP = θR – θB, θGBP = θG – θB SW59 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP41 when serial bus register COLOR = 80H as VC0, when COLOR = 0H as VC2, and when SIG1 is set to –10dB and COLOR = 0FFH as VC1. GEXCMX = 20 log (VC1/VC0) + 10 GEXCMN = 20 log (VC2/VC0) SW50, SW51 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D) and (E). Assume the output amplitude at TP41 as VB and the output amplitude at TP45 as VR. VEXCBL = VR/VB SW50, SW51 = A Input SIG5 (VL = 150mV) to (A) and SIG1 (–6dB, 100kHz, no burst) to (D) and (E). Assume the output amplitude at TP45 and TP41 when serial bus register HUE = 80H as VR0 and VB0, respectively, when HUE = 0FFH as VR1 and VB1, respectively, and when HUE = 0H as VR2 and VB2, respectively. GEXRMX = 20 log (VR1/VR0) GEXRMN = 20 log (VR2/VR0) GEXBMX = 20 log (VB1/VB0) GEXBMN = 20 log (VB2/VB0) SW50, SW51 = A Min. 0.53 Typ. 0.63 Max. 0.73 Unit Demodulation output amplitude ratio (NTSC) VGBN 0.25 0.32 0.39 Demodulation output phase difference (NTSC) θRBN 99 109 119 deg θGBN 230 242 254 deg VRBP Demodulation output amplitude ratio (PAL) VGBP 0.65 0.75 0.85 0.33 0.40 0.47 Demodulation output phase difference (PAL) θRBP 80 90 100 deg θGBP 232 244 256 deg Color difference input color adjustment characteristics MAX Color difference input color adjustment characteristics MIN GEXCMX 4 6 dB GEXCMN –20 –15 dB Color difference balance VEXCBL 0.8 1.0 1.2 GEXRMX Color difference input balance adjustment R GEXRMN 2 3 dB –3 –2 dB GEXBMX Color difference input balance adjustment B GEXBMN –3 –2 dB 2 3 dB – 15 – CXA2503AR Item Symbol Conditions Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP41 as VEXB and the output amplitude at TP43 as VEXBG. VEXGB = VEXBG/VEXB SW50, SW51 = A NTSC Min. 0.23 Typ. 0.25 Max. 0.28 Unit VEXGB G-Y matrix characteristics VEXGR PAL 0.17 0.19 0.21 Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (E). Assume the output amplitude at TP45 as VEXR and the output amplitude at TP43 as VEXRG. VEXGR = VEXRG/VEXR SW50, SW51 = A 0.48 0.53 0.58 RGB signal output block RGB signal output DC voltage VOUT Input SIG5 (VL = 0mV) to (A). Adjust serial bus register BRIGHT so that the output (black-black) at TP43 is 9Vp-p and measure the DC voltage at TP41, TP43 and TP45. Input SIG5 (VL = 0mV) to (A). Adjust serial bus register BRIGHT so that the output (black-black) at TP43 is 9Vp-p, measure the DC voltage at TP41, TP43 and TP45, and obtain the maximum difference between these values. Input SIG3 to (A). Vary V53 and measure the maximum value VLIMMX and minimum value VLIMMN of the voltage range (black – black) over which the black limiter operates for the TP41, TP43 and TP45 outputs. Assume the value when V53 = 0V as VLIMMX, and when V53 = 4.5V as VLIMMN. Input SIG5 (VL = 0mV) to (A) and measure the output (black – black) at TP41, TP43 and TP45 when serial bus register BRIGHT = 0H. Input SIG5 (VL = 0mV) to (A) and measure the output (black – black) at TP41, TP43 and TP45 when serial bus register BRIGHT = 0FFH. Input SIG5 (VL = 0mV) to (A) and measure the difference between the outputs (black-black) at TP41 and TP45 and the output (black – black) at TP43 when serial bus registers R-BRT = B-BRT = 0H and when R-BRT = B-BRT = 0FFH. Input SIG4 to (A) and obtain the level difference between the maximum and minimum non-inverted output amplitudes (white – black) at TP41, TP43 and TP45. Input SIG4 to (A) and obtain the level difference between the non-inverted output amplitudes (white – black) and the inverted output amplitudes at TP41, TP43 and TP45. Input SIG4 to (A) and obtain the level difference between the maximum and minimum black levels of both the inverted and non-inverted outputs at TP41, TP43 and TP45. 9.0 5.85 6.00 6.15 V RGB signal output DC voltage difference ∆VOUT 0 100 mV VLIMMX RGB output limiter operation voltage VLIMMN Vp-p 5.2 Vp-p BRTMX Amount of change in brightness BRTMN 9.0 Vp-p 4.0 Vp-p Amount of change in sub-brightness Difference in gain between RGB output signals Difference in RGB output inverted/ non-inverted gain Difference in black level potential between RGB output signals SBBRT ±1.5 ±2.0 V ∆GRGB –0.5 0 0.5 dB ∆GINV –0.5 0 0.5 dB ∆VBL 300 mV – 16 – CXA2503AR Item Symbol Gγ1 Conditions Input SIG8 to (A). Adjust the non-inverted output black level at TP43 to 6 – 4.5V with serial bus register BRIGHT and the noninverted output amplitude (white – black) at TP43 to 3.5V with serial bus register CONTRAST. Measure VG1, VG2 and VG3. Gγ1 = 20 log (VG1/0.0357) Gγ2 = 20 log (VG2/0.0357) Gγ3 = 20 log (VG3/0.0357) (See Fig. 5 for definitions of VG1, VG2 and VG3.) Input SIG8 to (A) and adjust serial bus register BRIGHT so that the output at TP43 is 9Vp-p (black – black). Read the point where the gain of the non-inverted output at TP43 changes when serial bus register γ1 = 0H and 0FFH from the input signal IRE level. Vγ1MN when γ1 = 0H, and Vγ1MX when γ1 = 0FFH. Input SIG8 to (A) and adjust serial bus register BRIGHT so that the output at TP43 is 9Vp-p (black – black). Read the point where the gain of the non-inverted output at TP43 changes when serial bus register γ2 = 0H and 0FFH from the input signal IRE level. Vγ2MN when γ2 = 0H, and Vγ2MX when γ2 = 0FFH. Min. 23.0 Typ. 26.0 Max. 29.0 Unit dB γ gain Gγ2 Gγ3 12.0 15.0 18.0 dB 18.0 22.0 26.0 dB Vγ1MN γ1 adjustment variable range Vγ1MX 0 IRE 100 IRE Vγ2MN γ2 adjustment variable range Vγ2MX Filter characteristics 100 IRE 0 IRE Amount of BPF attenuation ATBPF Assume the chroma amplitude at TP52 when SIG5 (VL = 0mV) is input to (A) and SIG1 (0dB at input center frequency (3.58MHz or 4.43MHz)) is input to (B) as 0dB. Obtain the amount by which the output at TP52 is attenuated when the frequencies noted on the right are input. SW59 = A NTSC 1.5MHz PAL 2.0MHz –16 –16 –7 –8 –40 –10 –10 –2 –3 –30 dB dB dB dB dB NTSC 5.5MHz PAL 6.8MHz ATRAPN Amount of TRAP attenuation ATRAPP Input SIG2 (0dB, 3.58MHz or 4.43MHz) to (A) NTSC and measure the output at TP43. Assume the amplitude at TP43 during Y/C input mode as 0dB, and obtain the amount of attenuation during PAL COMP input mode. Assume the amplitude of the 100kHz component of the output at TP43 when SIG5 (VL = 150mV) is input to (A) and SIG2 (0dB, 3.58MHz + 100kHz) is input to (B) as 0dB. Obtain the frequency which attenuates the beat component of the output by 3dB when the SIG2 frequency is increased with respect to 3.58MHz. –40 –30 dB R-Y, B-Y and LPF characteristics DEMLPF 0.8 1.0 1.3 MHz Sync separation, TG block Input SIG5 (VL = 0mV, VS = 143mV, WS variable) to (A) and confirm that it is synchronized with the HD output at TP22. Gradually narrow the WS of SIG5 from 4.7µs and obtain the WS at which synchronization with the HD output at TP22 is lost. Input SIG5 (VL = 0mV, WS = 4.7µs, VS variable) to (A) and confirm that it is synchronized with the HD output at TP22. Gradually reduce the VS of SIG5 from 143mV and obtain the VS at which synchronization with the HD output at TP22 is lost. Input sync signal width sensitivity WSSEP 2.0 µs Sync separation input sensitivity VSSEP 40 60 mV – 17 – CXA2503AR Item Symbol TDSYL Conditions Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV) to (A) and measure the delay time with the RPD output at TP12. TDSYL is from the falling edge of the input HSYNC to the falling edge of the RPD output at TP12, and TDSYH is from the falling edge of the input HSYNC to the rising edge of the RPD output at TP12. Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV, horizontal frequency variable) to (A) and confirm that NTSC it is synchronized with the HD output at TP22. Obtain the frequency fH at which the input and output are synchronized by changing the horizontal frequency of SIG5 from the non-synchronized condition. PAL HPLLN = fH – 15734 HPLLP = fH – 15625 Input SIG5 (VL = 0mV) to (A). Load = 30pF (See Fig. 3.) Input SIG5 (VL = 0mV) to (A). Measure HCK1/HCK2 and VCK1/VCK2. Load = 30pF (See Fig. 4.) Input SIG5 (VL = 0mV) to (A). Measure the HCK1/HCK2 duty. Load = 30pF Min. 430 Typ. 630 Max. 830 Unit ns Sync separation output delay time TDSYH 4.7 5.0 5.3 µs HPLLN Horizontal pull-in range HPLLP ±500 Hz ±500 Hz Output transition time (∗2 pins) tTLH tTHL 30 30 ns ns Cross-point time difference ∆T 10 ns HCK duty DTYHC 47 50 53 % External I/O characteristics VTEXTB External RGB input threshold voltage VTEXTW TD1EXT TD2EXT Input SIG5 (VL = 0mV) to (A) and SIG6 (VL variable) to (C). Raise the SIG6 amplitude (VL) from 0V and assume the voltage where the outputs at TP41, TP43 and TP45 go to black level as VTEXTB. Then raise the amplitude further and assume the voltage where these outputs go to white level as VTEXTW. Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 3V) to (C). Measure the rise delay time TD1EXT and the fall delay time TD2EXT of the outputs at TP41, TP43 and TP45. (See Fig. 2.) Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 1.7V) to (C). Measure the difference from the black level of the outputs at TP41, TP43 and TP45. Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C). Measure the difference from the black level of the outputs at TP41, TP43 and TP45. 3.5 0.8 1.0 1.2 V 1.8 50 50 2.0 100 100 2.2 150 150 V ns ns Propagation delay time between external RGB input and output Output blanking level during external RGB input EXTBK 0 V Output white level during EXTWT external RGB input V – 18 – CXA2503AR Item Serial transfer block Symbol Conditions Min. Typ. Max. Unit ts0 Data setup time ts1 th0 Data hold time th1 tw1L Minimum pulse width tw1H tw2 Other VPLLMN AFC adjustment voltage output range VPLLTP VPLLMX LOAD setup time, activated by the rising edge of SCLK. (See Fig. 6.) DATA setup time, activated by the rising edge of SCLK. (See Fig. 6.) LOAD hold time, activated by the rising edge of SCLK. (See Fig. 6.) DATA hold time, activated by the rising edge of SCLK. (See Fig. 6.) SCLK pulse width. (See Fig. 6.) SCLK pulse width. (See Fig. 6.) LOAD pulse width. (See Fig. 6.) 150 150 150 150 160 160 1 ns ns ns ns ns ns µs Measure the DC voltage of the output at TP11 when serial bus register PLL ADJ = 0H, 80H and 0FFH as VPLLMN, VPLLTP and VPLLMX, respectively. 5.65 7.4 9.15 5.8 7.5 9.3 5.95 7.6 9.45 V – 19 – Description of Electrical Characteristics Measurement Methods Serial Bus Register Initial Values Serial bus Mode settings DAC settings H-POSI HD-POSI B-BRT 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 10H 0H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 10H 0H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H HUE COLOR BRIGHT CONTRAST R-BRT γ1 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H γ2 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H (—: don't care, ADJ: adjustment, SET: setting) CXA2503AR Item System NTSC SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 SHS1 NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC — — — — — — — — — — — LCX005 LCX009 — — — — — Panel S/H Symbol Input Horizontal AFC adjustment COMP ICC11 COMP Current consumption VCC1 ICC12 Y/C ICC13 Y/color difference Current consumption VCC2 ICC2 COMP IDD1 Current consumption VDD COMP Power supply characteristics Setting 2 IDD2 COMP Input current II1 COMP Digital block I/O characteristics – 20 – Input current II2 COMP High level input voltage VIH COMP Low level input voltage VIL COMP High level output voltage VOH1 COMP Low level output voltage VOL1 COMP High level output voltage VOH2 COMP Low level output voltage VOL2 COMP High level output voltage VOH3 COMP Low level output voltage VOL3 COMP Output off leak current IOFF COMP Serial bus Mode settings DAC settings H-POSI HD-POSI B-BRT 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 10H 0H 80H 0FFH 80H 0H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H HUE COLOR BRIGHT CONTRAST R-BRT γ1 γ2 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H (—: don't care, ADJ: adjustment, SET: setting) System NTSC Through Through Through NTSC NTSC NTSC NTSC PAL NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC — Through Through Through Through — NTSC PAL — — — — LCX009 Through LCX009 Through LCX005 Through LCX005 Through LCX009 Through LCX009 Through LCX005 Through LCX005 Through LCX005 Through LCX005 Through LCX009 Through — — — Panel S/H Item Symbol Input Video maximum gain GV COMP Contrast characteristics GCNTTP TYP COMP Contrast characteristics GCNTMN COMP MIN FCYYC Y/C Y signal frequency response FCYCMN COMP FCYCMP COMP GSHP1X COMP Picture quality adjustment variable amount 1 GSHP1N COMP GSHP2X COMP Y signal block Picture quality adjustment variable amount 2 – 21 – GSHP2N COMP GSHP3X Y/C Picture quality adjustment variable amount 3 GSHP3N Y/C GSHP4X Y/C Picture quality adjustment variable amount 4 GSHP4N Y/C Carrier leak CRLEKY COMP TDYYC Y/C Y signal I/O delay time TDYCMN COMP TDYCMP COMP CXA2503AR Serial bus Mode settings DAC settings H-POSI HD-POSI B-BRT 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 96H 96H 80H 80H 80H 80H 80H 0H 0H 0H 10H 10H 10H Through 10H 0H 0H Through 0H 80H 80H 80H 80H 80H 80H 80H 80H 0H 80H 80H 80H 80H 80H 80H 96H 96H 96H 96H 96H 96H 96H 96H 96H 96H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 0H 0H 0H 80H 0H 0H 0H 0FFH 80H 0H 80H 0H 80H 0H 80H 0FFH 80H 80H 0H 80H 80H 80H 80H 0H 80H 80H 80H 80H 80H 0H 80H 80H 80H 80H 80H 0H 80H 80H 80H 80H 80H 0H 80H 80H 80H 80H 80H 0H 80H 80H 80H 80H 80H HUE COLOR BRIGHT CONTRAST R-BRT γ1 γ2 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H (—: don't care, ADJ: adjustment, SET: setting) CXA2503AR Item System NTSC PAL NTSC PAL NTSC PAL NTSC NTSC NTSC NTSC NTSC PAL NTSC NTSC NTSC NTSC PAL PAL PAL PAL — — — Through — Through — Through — Through — Through — Through — Through — Through — Through — Through — Through — Through — Through — Through — Through — Through — Through — Through Panel S/H Symbol Input ACC amplitude characteristics 1 ACC1 COMP ACC1 COMP ACC amplitude characteristics 2 ACC2 COMP ACC2 COMP FAPCN COMP APC pull-in range FAPCP COMP Color adjustment characteristics MAX GCOLMX COMP Color adjustment characteristics MIN GCOLMN COMP HUE adjustment characteristics MAX Chroma signal block – 22 – HUEMX COMP HUE adjustment characteristics MIN HUEMN COMP Killer operation input level ACKN COMP ACKP COMP VRBN COMP Demodulation output amplitude ratio NTSC VGBN COMP θRBN COMP Demodulation output phase difference NTSC θGBN COMP VRBP COMP Demodulation output amplitude ratio PAL VGBP COMP θRBP COMP Demodulation output phase difference PAL θGBP COMP Serial bus Mode settings DAC settings H-POSI HD-POSI B-BRT 80H 0H 10H 0FFH 80H 80H 80H 0H 80H HUE COLOR BRIGHT CONTRAST R-BRT γ1 γ2 0H System — Through — Panel S/H Item Symbol Input Color difference input color adjustment characteristics MAX — Through 0H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 0H 10H 10H 10H Through 0H 0H 0H 80H 80H 10H 80H 80H 80H 80H 80H 80H 80H 80H 80H ADJ ADJ ADJ ADJ 0H 0FFH 0B4H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H SET 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H Through Through Through Through Through Through Through Through Through Through Through Through Through Through Through 10H 10H 10H 0H 10H 0H 80H 80H 10H 0H 80H 10H 0H 80H 10H 0H 80H 10H 0H 0H 10H 0H 0FFH 10H 0H 0H 10H 0H 0FFH 10H 0H 80H 10H 0H 80H — — — — — NTSC PAL — — — — — — — — — — — — — — — — — — — — — — — — — — 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H SET 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H GEXCMX Y/color difference Color difference input color adjustment characteristics MIN GEXCMN Y/color difference 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H Color difference balance VEXCBL Color difference input balance adjustment R GEXRMX GEXRMN Chroma signal block Color difference input balance adjustment B GEXBMX GEXBMN RGB signal output block – 23 – — — — — — — — — G-Y matrix characteristics VEXGB VEXGR Y/color difference Y/color difference Y/color difference Y/color difference Y/color difference Y/color difference Y/color difference Y/color difference RGB signal output DC voltage VOUT RGB signal output DC voltage difference ∆VOUT RGB output limiter operation voltage VLIMMX VLIMMN Amount of change in brightness BRTMX BRTMN Amount of change in sub-brightness SBBRT Difference in gain between ∆GRGB RGB output signals CXA2503AR (—: don't care, ADJ: adjustment, SET: setting) Serial bus Mode settings DAC settings H-POSI HD-POSI B-BRT 80H 0H 10H 80H 80H 80H 80H 80H 0H HUE COLOR BRIGHT CONTRAST R-BRT γ1 γ2 0H System — — Through Panel S/H Item Symbol Input — Difference in RGB output inverted/ non-inverted gain — — 10H 80H 80H 80H 80H 80H 0H Through — 80H ∆GINV Difference in black level potential between ∆VBL RGB output signals — — 10H 80H ADJ ADJ ADJ ADJ ADJ ADJ ADJ 96H 80H 80H 80H 80H 96H 96H 96H ADJ 46H 46H 46H 46H 80H 80H 80H 80H ADJ ADJ 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H — — — — — — — — — — Through Through Through Through Through Through Through Through Through Through Through — — — — — — SET NTSC PAL NTSC — — — — — — — 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H Gγ1 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 78H 78H 78H 0H 0FFH 0H 0H 0H 0H 0H 0H 0D7H 0D7H 0D7H 0H 0H 0H 0FFH 0H 0H 0H 0H γ gain Gγ2 RGB signal output block Gγ3 γ1 adjustment variable Vγ1MN range Vγ1MX Filter characteristics – 24 – γ2 adjustment variable Vγ2MN range Vγ2MX Amount of BPF attenuation ATBPF COMP Amount of TRAP attenuation ATRAPN SET ATRAPP SET R-Y, B-Y and LPF characteristics DEMLPF Y/C (—: don't care, ADJ: adjustment, SET: setting) CXA2503AR Serial bus Mode settings DAC settings H-POSI HD-POSI B-BRT 80H 0H 10H 0H 80H 80H 80H 80H 80H HUE COLOR BRIGHT CONTRAST R-BRT γ1 γ2 0H System — — Through Panel S/H Item Symbol Input — Input sync signal width WSSEP sensitivity — — — Through 10H 0H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H 10H Through Through Through Through SHS1 SHS1 SHS1 SHS1 Through Through Through Through Through — — — — — — — — — — — — — — — NTSC PAL — — — — — — — — — — — — — — — — — — — — — — 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H Sync separation input sensitivity VSSEP 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H Sync separation output TDSYL delay time TDSYH Horizontal pull-in range HPLLN HPLLP Sync separation, TG block Output transition time tTLH tTHL Cross-point time difference External I/O characteristics Other – 25 – — — Through — — — — — — — — — — — — — 10H — — — 0H — — — 80H — — — 80H — — — ∆T HCK duty DTYHC External RGB input threshold voltage VTEXTB VTEXTW Propagation delay time TD1EXT between external RGB input and output TD2EXT Output blanking level during external RGB input EXTBK Output white level during EXTWT external RGB input 64H — — — 80H — — — 80H — — — 80H — — — 0H — — — 0H — — — (—: don't care, ADJ: adjustment, SET: setting) VPPLMN AFC adjustment voltage output range VPPLTP CXA2503AR VPPLMX CXA2503AR 3V SIG6 0V TP41, 43, 45 non-inverted output TD1EXT 50% TD2EXT Fig. 2. Conditions for measuring the delay between external RGB input and output 90% 50% 10% tTLH tTHL ∆T ∆T Fig. 3. Output transition time measurement conditions Fig. 4. Cross-point time difference measurement conditions White VG3 Non-inverted output VG2 3.5V Black 1.5V VG1 Fig. 5. γ characteristics measurement conditions – 26 – CXA2503AR DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 ts1 th1 SCLK 50% tw1H tw1L LOAD 50% ts0 th0 tw2 Fig. 6. Serial transfer block measurement conditions – 27 – CXA2503AR Input Waveforms SG No. Waveform Sine wave video signal:With/without burst Amplitude and frequency variable SIG1 150mV 143mV 150mV ← Value noted on left: 0dB Chroma signal: Burst, chroma frequency (3.579545MHz, 4.433619MHz) Chroma phase and burst frequency variable SIG2 150mV 143mV ← Value noted on left: 0dB Ramp waveform SIG3 143mV 1H 357mV 5-step staircase waveform 150mV SIG4 143mV 1H VL SIG5 VS fH WS VL amplitude variable VS variable: 143mV unless otherwise specified WS variable:4.7µs unless otherwise specified fH variable: 15.734kHz (NTSC) or 15.625kHz (PAL) unless otherwise specified – 28 – CXA2503AR SG No. 30µs 5µs Waveform VL amplitude variable SIG6 VL Horizontal sync signal 75mV Frequency variable SIG7 143mV 175mV 10-step staircase waveform 357mV SIG8 143mV 1H 2T pulse waveform VL SIG9 VS fH WS VL amplitude variable VS variable:143mV unless otherwise specified WS variable: .7µs unless otherwise specified 4 fH variable: 15.734kHz (NTSC) or 15.625kHz (PAL) unless otherwise specified – 29 – CXA2503AR Electrical Characteristics Measurement Circuit +12V ICC2 47µ 0.1µ TP45 TP43 TP41 100p 100p 100p S39 TP38 TP37 TP36 TP35 TP34 TP33 +4.5V 0.01µ 0.47µ ICC1 47µ 0.1µ SW50 A 0.01µ B A 0.01µ B SW51 TP52 49 VCC1 50 B-Y IN 51 R-Y IN 52 C OUT 53 BLK LIM V53 SW53 54 APC 15k 0.068µ 0.22µ ∗2 1µ 56 VXO IN 57 V REG 58 START UP (B) SW59 A 59 C IN B 82k ∗6 1µ 62 Y IN 63 PIC V63 S64 SW63 HST 19 CLR 18 TP19 TP18 60 F0 ADJ 61 GND3 HCK1 21 HCK2 20 TP21 TP20 HD 22 TP22 TEST1 25 FLD IN 24 FLD OUT 23 TP25 TP24 TP23 ∗1 55 VXO OUT VST 26 TP26 VCK2 27 TP27 48 47 46 45 0.47µ 44 43 0.47µ 42 41 40 39 38 37 36 35 34 33 B OUT FB G VCC2 G OUT TEST3 GND2 DATA FB R SIG.CENTER R OUT TEST2 TEST4 LOAD SCLK VSS2 32 VD2 31 VD1 30 EN 29 VCK1 28 TP31 TP30 TP29 TP28 VDD2 17 (D) (E) H.FIL OUT FB B RGT EXT B PWRST S.SEP IN SYNC IN 64 TEST0 VCO ADJ GND1 TRAP EXT G VD IN EXT R VSS1 CKI VDD1 RPD CKO 3V ICC3 1 SW1 V1 4.5V 2 3 4 5 6 7 750 B 8 9 10 11 12 13 14 ∗4 15 16 TP11 TP12 AB AB A 1k 10k 220p 33k 3300p 3.3µ 10k S2 0.033µ 0.47µ 68p 47µ 0.1µ ∗5 (A) SW8 SW9 SW10 (C) ∗3 0.01µ ∗1 Used crystal: KINSEKI CX-5F Frequency deviation: within ±30ppm, frequency temperature characteristics: within ±30ppm, load capacity: 16pF NTSC: 3.579545MHz PAL: 4.433619MHz ∗2 NTSC: none, PAL: 18pF ∗3 Varicap diode: 1T369 (SONY) ∗4 L value: 8.2µH during LCX005 mode 3.9µH during LCX009 mode ∗5 Trap (TDK) NTSC: NLT4532-S3R6B PAL: NLT4532-S4R4 ∗6 Resistance value tolerance: ±2%, temperature coefficient: ±200ppm or less – 30 – CXA2503AR Description of Operation The CXA2503AR incorporates the three functions of an RGB decoder block, an RGB driver block and a timing generator (TG) block onto a single chip using BiCMOS technology. 1) RGB decoder block • Input mode switching The input mode can be switched between composite input, Y/C input and Y/color difference input by the serial bus settings. During composite input: The composite signal is input to Pins 5, 59 and 62. During Y/C input: The Y signal is input to Pins 5 and 62, and the C signal to Pin 59. During Y/color difference input: The Y signal is input to Pins 5 and 62, the B-Y signal to Pin 50, and the R-Y signal to Pin 51. • System switching The input system can be switched between NTSC and PAL (DPAL using external delay line and SPAL) by the serial bus settings. • Trap, BPF The center frequency of the built-in trap and BPF can be switched to 3.58MHz during NTSC and 4.43MHz during PAL. During composite input, the Y signal enters the trap circuit and the C signal enters the BPF. These signals do not pass through the trap or BPF during Y/C input and Y/color difference input. • ACC detection, ACC amplifier The amplitude of the burst signal output from the ACC amplifier is detected and the ACC amplifier is controlled to maintain the burst signal amplitude at a constant level. • VXO, APC detection The VXO local oscillation circuit is a crystal oscillation circuit. The phases of the input burst signal and the VXO oscillator output are compared in the APC detection block, and the detective output is used to form a PLL loop that controls the VXO oscillation frequency, which means that the need for adjustments is eliminated. • External inputs These are digital inputs with two thresholds. When one of the RGB inputs is higher than the lower threshold Vth1 (≈ 1.0V), all RGB outputs go to black level. When the higher threshold Vth2 (≈ 2.0V) is exceeded, the output for only the signal in question goes to white level, while the other outputs remain at black level. – 31 – CXA2503AR 2) RGB driver block • γ correction In order to support the characteristics of LCD panels, the I/O characteristics are as shown in Fig. 1. The characteristics change as shown in Fig. 2 by adjusting the serial bus register γ1, and as shown in Fig. 3 by adjusting γ2. B' Output B A A Output A' B A Output B' B Input Input Input Fig. 1 Fig. 2 Fig. 3 • Sample-and-hold circuit As LCD panels sample RGB signals simultaneously, RGB signals output from the CXA2503AR must be sampled-and-held in sync with the LCD panel drive pulses. R S/H1 S/H4 HCK1 G S/H2 S/H4 A B B S/H3 S/H4 C SH1 SH2 SH3 SH4 RGT = H (normal) SHS1 SH1 SH2 SH3 SH4 B SHS2 A SHS3 C RGT = L (inverted) SHS1 SH1 SH2 SH3 SH4 B A SHS2 A C SHS3 C B SH1: R signal SH pulse SH2: G signal SH pulse SH3: B signal SH pulse SH4: RGB signal SH pulse Through Through Through A C C B B A Through Through Through C B A The sample-and-hold circuit performs sample and hold by receiving the SH1 to SH4 pulses from the TG block. Since LCD panels perform color coding using an RGB delta arrangement, each horizontal line must be compensated by 1.5 dots. This relationship is reversed during right/left inversion. This compensation timing is also generated by the TG block. The sample-and-hold timing changes according to the phase relationship with the HCK1 pulse, so the timing should be set to SHS1, 2 or 3 in accordance with the actual board. – 32 – CXA2503AR • RGB output RGB outputs (Pins 41, 43, and 45) are inverted each horizontal line by the FRP pulse supplied from the TG block as shown in the figure below. Feedback is applied so that the center voltage (Vsig center) of the output signal matches the reference voltage (VCC2 + GND2)/2 (or the voltage input to SIG CENTER (Pin 48)). In addition, the white level output is clipped by the Vsig center ±0.7V, and the black level output is clipped by the limiter operation point that is adjusted at the BLKLIM (Pin 53). Video IN FRP Black level limiter RGB OUT White level limiter Vsig center White level limiter Black level limiter 3) TG block • PLL and AFC circuits The TG block contains a PLL circuit phase comparator and frequency division counter, and a PLL circuit can be comprised by connecting an external VCO circuit. The PLL error detection signal is generated at the following timing. The phase comparison output of the entire bottom of HSYNC and the internal frequency division counter becomes RPD. RPD output is converted to DC error with the lag-lead filter, and then it changes the varicap capacitance to stabilize the oscillation frequency at 702fH in the LCX005BK/BKB and 1050fH in the LCX009AK/AKB. The PLL of this system is adjusted by setting the serial bus register PLL ADJ so that RPD changes in the center of the window as shown in the figure below. H SYNC WS RPD WL WH WL = WH • H position The horizontal display position can be set at 2fH intervals in 32 different ways by the serial bus settings. The picture center is set at the internal default value, but because there is a difference between the RGB signal and the drive pulse delays on the actual board, the picture center may not match the design center. In this case, adjust with the serial bus. – 33 – CXA2503AR • Right/left inversion The LCD panel is arranged in a delta pattern, where identical signal lines are offset by 1.5 dots from adjoining lines. For this reason, a 1.5-bit offset is attached to the horizontal start pulse (HST) between odd lines and even lines. HCK and S/H are also 1.5-bit offset in a similar manner. When the panel is driven by left scan (Reverse scan), this offset relationship is inverted for even and odd lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also changed. RGT = H: Right scan mode RGT = L: Left scan mode Right scan (Normal scan) Left scan (Reverse scan) H SCANNER V SCANNER Display area LCD panel • WIDE mode Setting the WIDE mode by switching the aspect ratio with the serial bus shifts the unit to WIDE mode. In this mode, the aspect ratio is converted through pulse eliminator processing, allowing 16:9 quasi-WIDE display. During WIDE mode, vertical pulse eliminator scanning of 1/4 for NTSC or 1/2 and 1/4 for PAL are performed, and the video signal is compressed to achieve a 16:9 aspect ratio. In addition, in areas outside the display area, black is displayed by performing high-speed scanning. The timing during high-speed scanning is a 2H cycle pulse consisting of normal drive (1H) and quadruplespeed drive (1H) and black signals are written in the 28 and 27 lines, respectively at the top and bottom of this display area. During this time, FRP is changed to a 4H cycle, HST to a 2H cycle, and EN and CLR are not output. See the attached sheets for detailed timing. Black display area Vertical high-speed scanning 28LINE (28LINE) 218LINE (225LINE) Display area Display area 163LINE (169LINE) Black display area 4:3 display Vertical pulse eliminator scanning 16:9 display (during normal-speed scanning) 27LINE (28LINE) Numbers in parentheses are for the LCX009AK/AKB. All other numbers are for the LCX005BK/BKB. – 34 – CXA2503AR During high-speed scanning During normal-speed scanning VCK1 Quadruple-speed scanning Normal-speed scanning HST 2H cycle FRP (internal pulse) 4H cycle SBLK (internal pulse) • AC driving of LCD panels during no signal HST, HCK1, HCK2, VST, VCK1, VCK2, HD, VD1, VD2 and FRP are made to run free so that the LCD panel is AC driven even when there is no composite sync from the SYNC IN pin. During this time, the HSYNC separation circuit stops and the PLL counter is made to run free. In addition, the VSYNC separation circuit is also stopped, so the auxiliary V counter is used to create the reference pulse for generating VD1 and VST. The cycle of this V counter is designed to be 269H for NTSC and 321H for PAL. However, when there is no vertical sync signal for 5 frames, the no signal state is assumed and the free running VD1 and VST pulses are generated from the next field. In addition, RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from causing errors due to phase comparison. – 35 – CXA2503AR Description of Serial Control Operation 1) Control method Control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of SCLK. This loading operation starts from the falling edge of LOAD and is completed at the next rising edge. (D13 to D15 are dummy data.) Digital block control data is established by the vertical sync signal, so if data is transferred multiple times for the same item, the data immediately before the vertical sync signal is valid. Analog (electronic attenuator) block control data becomes valid each time the LOAD signal is input. DATA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SCLK LOAD Serial transfer timing 2) Serial data map The serial data map is as follows. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 S/H phase VD HD Supported polarity polarity panel System Input switching 0 0 Y/color External FRP SYNC FRP256 Mode Aspect difference 1F VSYNC polarity GEN inversion clamp H-POSITION HUE COLOR BRIGHT CONTRAST R-BRT B-BRT γ1 γ2 PLL ADJ HD-POSITION 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 – 36 – CXA2503AR 3) Serial data mode settings • Input switching D1 D0 0 X Composite input (default) 1 0 Y/C input 1 1 Y/color difference input • System switching D3 D2 0 X NTSC (default) 1 0 D-PAL 1 1 S-PAL • Supported panel switching D4 0 LCX005 (default) 1 LCX009 • HD output polarity switching D5 0 Negative polarity (default) 1 Positive polarity • VD1 output polarity switching D6 0 Negative polarity (default) 1 Positive polarity • Sample-and-hold timing switching D8 D7 0 0 SHS1 (default) 0 1 SHS2 1 0 SHS3 1 1 Through (sample-and-hold not performed) • Y/color difference clamp position switching This switches the position at which the R-Y and B-Y input signals are clamped during Y/color difference input mode. D0 0 Pedestal position (default) 1 SYNC position • Aspect switching D1 0 4:3 (normal) (default) 1 16:9 (pulse eliminator WIDE) • Mode switching This is the test mode. Set to normal mode. D2 0 Normal mode (default) 1 Test mode – 37 – CXA2503AR • FRP256 field inversion This further inverts the polarity of the RGB output that is inverted every 1H for 256 fields. D3 0 OFF (default) 1 ON • Sync generator function This stops the HST, VST and FRP outputs of the TG block. D4 0 OFF (default) 1 ON • FRP polarity inversion function D5 0 ON (1H inversion) (default) 1 OFF (polarity not inverted) • External VSYNC input switching Internal VSYNC separation is not performed and an externally input VSYNC is used. D6 0 OFF (default) 1 ON • H position setting D4 D3 D2 D1 D0 0 0 0 0 0 to to to to to 1 0 0 0 0 (default) to to to to to 1 1 1 1 1 Variable in 2fH (= 1 bit) increments CLK (internal) 10001 HST 10000 01111 1 step 1 step • HD phase setting D9 D8 D7 D6 D5 0 0 0 0 0 (default) to to to to to 1 1 1 1 1 Variable in 4fH (= 1 bit) increments HSYNC HD 00000 11111 31 steps – 38 – CXA2503AR 4) Serial data electronic attenuator (D/A converter) settings • HUE D7 D6 1 0 • COLOR D7 D6 1 0 • BRIGHT D7 D6 1 0 • CONTRAST D7 D6 1 0 • R-BRT D7 D6 1 0 • B-BRT D7 D6 1 0 • γ-1 D7 D6 0 0 • γ-2 D7 D6 0 0 • PLL-ADJ D7 D6 1 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D5 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D4 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D3 0 D2 0 D2 0 D2 0 D2 0 D2 0 D2 0 D2 0 D2 0 D2 0 D1 0 D1 0 D1 0 D1 0 D1 0 D1 0 D1 0 D1 0 D1 0 D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default) D0 0 (default) – 39 – CXA2503AR LCX005BK/BKB and LCX009AK/AKB Color Coding Diagram The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note that the shaded region within the diagram is not displayed. LCX005BK/BKB pixel arrangement dummy1 HSW1 HSW2 HSW3 HSW174 HSW175 dummy2 to 5 dummy1 dummy2 Vline1 Vline2 Vline3 B B B G R G R G R G B R G B G B R 3 R B G B G B G B G B G B G R B R B R B R B R B R B G R G R G R G R G R G R B G B G B G B G B G B G R B R B R B R B R B R B G R G R G B G B G B R B R B R G R G R G B G B G B G B R G B R G B R G R G Photo-shielding B R BRG area BRGBRG G B R G B R G B R G B R G B R B G B G R B B G R B G R 13 B G R B G R B G B G R B G R B G R R B G R B G R G R B G R B G R R 2 R R R Display area GBR G R G R G R B G B G R B B G R B G R B G G R 218 222 Vline217 Vline218 dummy3 dummy4 R R 2 521 537 Basic specifications Total horizontal dots: 537H Horizontal display dots: 521H Total vertical dots: Vertical display dots: Total dots: Display dots: 222H 218H 119,214H 113,578H – 40 – CXA2503AR LCX009AK/AKB pixel arrangement dummy1 to 4 HSW1 HSW2 HSW267 HSW268 dummy5 to 8 dummy1 dummy2 Vline1 Vline2 Vline3 R R R B G B G B G B R B G R B R B R B R B R G B R G B 14 G R G R G R G R G R G R B G B G B G B G B G B G R B R B R B R B R B R B G R G R G R G R G R G R B G B G B R B R B R G R G R G B G B G B R B R B R B R G B R G B R G B G R G R G R G R G R G R RGB B Photo-shielding R area GB B G B G B G B G B G R B R B G R 13 R B G R B G R B G R B G R 1 R B G R B G R G R B G R 225 228 2 R B G R G R BRG G Display area B G B G B G R B R B G R R B G R B G R B B Vline224 Vline225 dummy3 R B R 800 827 Basic specifications Total horizontal dots: 827H Horizontal display dots: 800H Total vertical dots: Vertical display dots: Total dots: Display dots: 228H 225H 188,556H 180,000H – 41 – LCX005BK/BKB Horizontal Direction Timing Chart NTSC/PAL Unless otherwise specified, serial settings are the default values. RGT: H (Normal scan) 702fH MCK 4.7µs (52fH) 4.7µs (52fH) 2.0µs (22fH) 22.5fH 13fH 4.5µs (50fH) SYNC (BLK) HD HST HCK1 HCK2 – 42 – ODD FIELD EVEN FIELD 3.0µs (33fH) 5fH SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) 19.5fH VCK1 VCK2 0.5µs (6fH) CLR EN (PAL) VST/VD1 ODD LINE CXA2503AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Horizontal Direction Timing Chart NTSC/PAL Unless otherwise specified, serial settings are the default values. RGT: H (Normal scan) 702fH MCK 4.7µs (52fH) 4.7µs (52fH) 2.0µs (22fH) 21.0fH 13fH 4.5µs (50fH) SYNC (BLK) HD HST HCK1 HCK2 – 43 – ODD FIELD EVEN FIELD 3.0µs (33fH) 5fH SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) 18.0fH VCK1 VCK2 0.5µs (6fH) CLR EN (PAL) VST/VD1 EVEN LINE CXA2503AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Horizontal Direction Timing Chart NTSC/PAL Unless otherwise specified, serial settings are the default values. RGT: L (Reverse scan) 702fH MCK 4.7µs (52fH) 4.7µs (52fH) 2.0µs (22fH) 22.0fH 13fH 4.5µs (50fH) SYNC (BLK) HD HST HCK1 HCK2 – 44 – ODD FIELD EVEN FIELD 3.0µs (34fH) 5fH SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) 18.0fH VCK1 VCK2 0.5µs (5fH) CLR EN (PAL) VST/VD1 ODD LINE CXA2503AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Horizontal Direction Timing Chart NTSC/PAL Unless otherwise specified, serial settings are the default values. RGT: L (Reverse scan) 702fH MCK 4.7µs (52fH) 4.7µs (52fH) 2.0µs (22fH) 23.5fH 13fH 4.5µs (50fH) SYNC (BLK) HD HST HCK1 HCK2 – 45 – ODD FIELD EVEN FIELD 3.0µs (34fH) 5fH SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) 19.5fH VCK1 VCK2 0.5µs (5fH) CLR EN (PAL) VST/VD1 EVEN LINE CXA2503AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Horizontal Direction Timing Chart NTSC/PAL Unless otherwise specified, serial settings are the default values. RGT: H (Normal scan) 1050fH MCK 4.7µs (78fH) 4.7µs (78fH) 2.0µs (33fH) 22.5fH 4.5µs (73fH) 12fH SYNC (BLK) HD HST HCK1 HCK2 – 46 – ODD FIELD EVEN FIELD 3.0µs (50fH) 1fH SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) VCK1 44.5fH VCK2 0.5µs (8fH) CLR EN (PAL) VST/VD1 ODD LINE CXA2503AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Horizontal Direction Timing Chart NTSC/PAL Unless otherwise specified, serial settings are the default values. RGT: H (Normal scan) 1050fH MCK 4.7µs (78fH) 4.7µs (78fH) 2.0µs (33fH) 21.0fH 4.5µs (73fH) 12fH SYNC (BLK) HD HST HCK1 HCK2 – 47 – ODD FIELD EVEN FIELD 3.0µs (50fH) 1fH SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) VCK1 43.0fH VCK2 0.5µs (8fH) CLR EN (PAL) VST/VD1 EVEN LINE CXA2503AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Horizontal Direction Timing Chart NTSC/PAL Unless otherwise specified, serial settings are the default values. RGT: L (Reverse scan) 1050fH MCK 4.7µs (78fH) 4.7µs (78fH) 2.0µs (33fH) 22.0fH 4.5µs (73fH) 12fH SYNC (BLK) HD HST HCK1 HCK2 – 48 – ODD FIELD EVEN FIELD 3.0µs (51fH) 1fH SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) VCK1 43.0fH VCK2 0.5µs (7fH) CLR EN (PAL) VST/VD1 ODD LINE CXA2503AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Horizontal Direction Timing Chart NTSC/PAL Unless otherwise specified, serial settings are the default values. RGT: L (Reverse scan) 1050fH MCK 4.7µs (78fH) 4.7µs (78fH) 2.0µs (33fH) 23.5fH 4.5µs (73fH) 12fH SYNC (BLK) HD HST HCK1 HCK2 – 49 – ODD FIELD EVEN FIELD 3.0µs (51fH) 1fH SH3 (Internal pulse) SH1 (Internal pulse) SH4 (Internal pulse) SH2 (Internal pulse) FRP (Internal pulse) VCK1 44.5fH VCK2 0.5µs (7fH) CLR EN (PAL) VST/VD1 EVEN LINE CXA2503AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart NTSC (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST – 50 – 596fH 596fH EN CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 ODD FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart NTSC (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST – 51 – 246fH 246fH EN CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 EVEN FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart PAL (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST – 52 – 596fH 596fH EN CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 ODD FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart PAL (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST – 53 – 246fH 246fH EN CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 EVEN FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST – 54 – 714fH 714fH EN CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 ODD FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST – 55 – 314fH 314fH EN CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 EVEN FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart PAL (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST – 56 – 714fH 714fH EN CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 ODD FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart PAL (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST – 57 – 314fH 314fH EN CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 EVEN FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart NTSC WIDE 1/4 pulse elimination 163-line display area (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST EN – 58 – 596fH 596fH CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 SBLK (Internal pulse) ODD FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart NTSC WIDE 1/4 pulse elimination 163-line display area (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST EN – 59 – 246fH 246fH CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 SBLK (Internal pulse) EVEN FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart PAL WIDE 163-line display area (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST EN – 60 – 596fH 596fH CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 SBLK (Internal pulse) ODD FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart PAL WIDE 163-line display area (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST EN – 61 – 246fH 246fH CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 SBLK (Internal pulse) EVEN FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC WIDE 1/4 pulse elimination 169-line display area (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST EN – 62 – 714fH 714fH CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 SBLK (Internal pulse) ODD FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC WIDE 1/4 pulse elimination 169-line display area (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST EN – 63 – 314fH 314fH CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 SBLK (Internal pulse) EVEN FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart PAL WIDE 169-line display area (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST – 64 – 714fH 714fH EN CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 SBLK (Internal pulse) ODD FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart PAL WIDE 169-line display area (VD) SYNC (BLK) VST VCK1 VCK2 FRP (Internal pulse) HST – 65 – 314fH 314fH EN CLR FRP (Internal pulse) (1F inversion) FLD OUT VD1 HD VD2 SBLK (Internal pulse) EVEN FIELD CXA2503AR Note) The first and third rows of the timing chart "VD" and "BLK", respectively, are pulses indicated as a reference and are not pulses output from pins. FRP polarity is not specified for each line and field. CXA2503AR Application Circuit (NTSC/PAL, COMP and Y/C input) +12V 0.1µ 47µ To LCD panel +4.5V To Serial controller 0.01µ 48 47 0.47µ 46 45 0.47µ 44 43 0.47µ 42 41 40 39 38 37 36 35 34 33 G OUT TEST3 GND2 DATA FB R SIG.CENTER R OUT TEST2 +4.5V 49 VCC1 0.1µ 47µ 50 B-Y IN 0.01µ +4.5V 0.01µ 47k 0.01µ ∗1 52 C OUT 51 R-Y IN TEST4 B OUT LOAD SCLK VSS2 32 VD2 31 VD1 30 EN 29 VCK1 28 VCK2 27 VST 26 TEST1 25 FLD IN 24 To LCD panel FLD OUT 23 HD 22 HCK1 21 HCK2 20 HST 19 CLR 18 VDD2 17 53 BLK LIM 54 APC 15k 0.068µ 0.22µ ∗2 +4.5V 55 VXO OUT 56 VXO IN 1µ 57 V REG 58 START UP C IN Y/C COMP 59 C IN ∗6 82k 60 F0 ADJ 61 GND3 +4.5V 1µ 47k 0.01µ 63 PIC 62 Y IN FB G VCC2 H.FIL OUT FB B RGT EXT B SYNC IN PWRST 64 TEST0 VD IN EXT R VCO ADJ S.SEP IN GND1 TRAP EXT G VSS1 CKI VDD1 RPD CKO 1 0.01µ 2 3 4 5 6 7 750 8 9 10 11 12 13 14 ∗4 15 16 3V 0.47µ COMP/Y IN 0.033µ 1k 10k 220p 33k 3300p ∗3 68p 47µ 0.1µ ∗5 3.3µ 10k ∗1 Used crystal: KINSEKI CX-5F Frequency deviation: within ±30ppm, frequency temperature characteristics: within ±30ppm, load capacity: 16pF NTSC: 3.579545MHz PAL: 4.433619MHz ∗2 NTSC: none, PAL: 18pF ∗3 Varicap diode: 1T369 (SONY) ∗4 L value: 8.2µH during LCX005 mode 3.9µH during LCX009 mode ∗5 Trap (TDK), open during Y/C input NTSC: NLT4532-S3R6B PAL: NLT4532-S4R4 ∗6 Resistance value variation: ±2%, temperature coefficient: ±200ppm or less Connect to +4.5V during Y/C input Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 66 – CXA2503AR Application Circuit (NTSC/PAL, Y/color difference input) +12V 0.1µ 47µ To LCD panel +4.5V To Serial controller 0.01µ +4.5V 48 47 0.47µ 0.47µ 0.47µ 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SIG.CENTER G OUT TEST3 GND2 DATA FB R R OUT TEST2 0.1µ 47µ TEST4 B OUT LOAD SCLK VSS2 32 VD2 31 VD1 30 EN 29 VCK1 28 VCK2 27 VST 26 TEST1 25 FLD IN 24 To LCD panel FLD OUT 23 HD 22 HCK1 21 HCK2 20 HST 19 CLR 18 VDD2 17 49 VCC1 50 B-Y IN 0.1µ 51 R-Y IN 0.1µ B-Y IN R-Y IN +4.5V 47k 0.01µ 52 C OUT 53 BLK LIM 54 APC 55 VXO OUT 56 VXO IN +4.5V 57 V REG 58 START UP +4.5V 59 C IN 60 F0 ADJ 61 GND3 +4.5V 1µ 47k 0.01µ 63 PIC 62 Y IN 1µ FB G VCC2 H.FIL OUT FB B RGT EXT B SYNC IN PWRST 64 TEST0 VD IN EXT R VCO ADJ S.SEP IN GND1 TRAP EXT G VSS1 CKI VDD1 RPD CKO 1 0.01µ 2 3 4 5 6 7 750 8 9 10 11 12 13 14 ∗2 15 16 3V 0.47µ Y IN 0.033µ 1k 10k 220p 33k 3300p ∗1 68p 47µ 0.1µ 3.3µ 10k ∗1 Varicap diode: 1T369 (SONY) ∗2 L value: 8.2µH during LCX005 mode 3.9µH during LCX009 mode Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 67 – CXA2503AR Example of Representative Characteristics HUE adjustment characteristics 50 40 10 COLOR adjustment characteristics HUE adjustment angle [deg] 30 20 0 0 –10 –20 –30 –40 –50 –60 0 30 60 90 0C0 0F0 DAC value Gain [dB] 10 –10 –20 –30 –40 0 30 60 90 0C0 0F0 DAC value BRIGHT adjustment characteristics 8 7 14 13 5 10 CONTRAST adjustment characteristics Non-inverted output black level [V] Inverted output black level [V] 6 5 4 3 2 1 0 –1 –2 0 30 60 90 0C0 0F0 DAC value 12 11 10 9 8 7 6 5 4 0 Output gain [dB] –5 –10 –15 –20 –25 0 30 60 90 0C0 0F0 DAC value Non-inverted black Inverted black 10 SUB-BRIGHT adjustment characteristics 1.0 PLL adjustment voltage Voltage change with respect to G output [V] 0.5 9 Pin 11 output voltage [V] 0 30 60 90 0C0 0F0 0 8 –0.5 7 –1.0 6 –1.5 DAC value 5 0 30 60 90 0C0 0F0 DAC value – 68 – CXA2503AR Color difference balance adjustment 5 Black level limiter adjustment characteristics 10 9 3 Limiter level [Vp-p] 8 Gain [dB] 1 7 6 –1 –3 5 –5 0 30 60 90 DAC value 0C0 0F0 B-Y output R-Y output 4 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Pin voltage [V] – 69 – CXA2503AR Sharpness characteristics (COMP, NTSC, 005) 15 10 5 0 Sharpness characteristics (COMP, NTSC, 009) 10 5 0 –5 –10 –15 –20 –25 –30 Gain [dB] –5 –10 –15 –20 –25 –30 0 2 4 6 8 10 0V 2.25V 4V Frequency [MHz] Gain [dB] 0 2 4 6 8 10 0V 2.25V 4V Frequency [MHz] Sharpness characteristics (COMP, PAL, 005) 15 10 5 0 Sharpness characteristics (COMP, PAL, 009) 10 5 0 –5 –10 –15 –20 –25 –30 Gain [dB] –5 –10 –15 –20 –25 –30 0 2 4 6 8 10 0V 2.25V 4V Frequency [MHz] Gain [dB] 0 2 4 6 8 10 0V 2.25V 4V Frequency [MHz] Sharpness characteristics (Y/C, 005) 15 10 5 20 15 10 5 Sharpness characteristics (Y/C, 009) Gain [dB] 0 –5 –10 –15 –20 0 2 4 6 8 10 0V 2.25V 4V Frequency [MHz] Gain [dB] 0 –5 –10 –15 –20 0 2 4 6 8 10 0V 2.25V 4V Frequency [MHz] – 70 – CXA2503AR Notes on Operation The CXA2503AR contains digital circuits, so the set board pattern must be designed in consideration of undesired radiation, interference to analog circuits, etc. Care should also be taken for the following items when designing the pattern. • Make the IC power supply and GND patterns as plain as possible. In particular, GND and VSS should not be separated and should be connected to the same GND pattern as close to the pins as possible. • Connect the by-pass capacitors between the power supplies and GND as close to the pins as possible. • The trap connected to Pin 3 should be located as close to the pin as possible. Also, take care not to pass other signal lines close to this pin or the connected trap. • The wiring for the crystal and capacitor connected to Pins 55 and 56 should be as short as possible in order to prevent floating capacitance. Take care not to pass other signal lines close to these pins in order to prevent interference such as color unevenness. In addition, the APC pull-in characteristics vary significantly according to the characteristics of the used crystal and the wiring pattern, so be sure to thoroughly investigate these items before using the set. • The resistor connected to Pin 60 should be located as close to the pin as possible. Also, take care not to pass other signal lines close to this pin. The composite/Y signal and the external R-Y and B-Y signals are clamped at the inputs using the capacitors connected to the input pins, so these signals should be input at sufficiently low impedance. The C signal is received by the internal capacitor, so an appropriate DC bias should be applied to this signal from an external source and this signal should be input at low impedance. The smoothing capacitor of the DC level control feedback circuit in the output block should have a leak current with a small absolute value and variance. This IC has a MOS structure which is easily damaged by static electricity, so thorough measures should be taken to prevent electrostatic discharge. – 71 – CXA2503AR Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 10.0 ± 0.2 48 49 33 32 0.15 ± 0.05 0.1 A 64 17 1 1.25 0.5 + 0.08 0.18 – 0.03 16 1.7 MAX 0.1 M 0.1 ± 0.1 0° to 10° DETAIL A 0.5 ± 0.2 (0.5) PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42 ALLOY 0.3g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L061 LQFP064-P-1010-AY – 72 –