CXA2610AN

CXA2610AN Laser Driver Description The CXA2610AN is a laser driver IC for optical discs. This IC supports higher optical power output speeds. Features • LD driver with excellent driving capability • Write current of 250mA (max.) possible by setting the IIN2 (Pin 2) and IIN3 (Pin 5) external resistors • Rise time ≈ 3ns • Fall time ≈ 4ns • The oscillation frequency of the built-in oscillation circuit can be set from 100 to 600MHz by connecting the OSCFR (Pin 4) external resistor to GND. • The oscillator amplitude initial value of the built-in oscillation circuit can be set by connecting the OSCGA (Pin 12) external resistor to GND, and the oscillator amplitude can be adjusted by the IINR input current value. • Oscillation ON/OFF can be set as desired. • Single +5V power supply • TTL/CMOS control for control system Applications • CD-R driver • CD-RW driver • DVD driver • Writable optical driver • Laser diode current switching Structure Bipolar silicon monolithic IC Preliminary 16 pin SSOP (Plastic) Absolute Maximum Ratings • Supply voltage Vcc 5.5 • Operating temperature Topr –10 to +70 • Storage temperature Tstg –65 to +150 Operating Conditions Supply voltage V °C °C 4.5 to 5.5 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– PE00145-PS CXA2610AN Block Diagram IINR IIN2 GND OSCFR IIN3 CONTR CONT2 CONT3 1 2 3 4 5 6 7 8 V-I V-I Current SW Driver 16 Vcc 15 Vcc 14 LD0 13 GND V-I OSC 12 OSCGA 11 ENABLE TTL Delay 10 OSCENA 9 Vcc Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol IINR IIN2 GND OSCFR IIN3 CONTR CONT2 CONT3 Vcc OSCENA ENABLE OSCGA GND LD0 Vcc Vcc I/O I I — I I I I I — I I I — O — — Oscillation level adjustment. LD drive current setting input. Ground. Oscillation frequency adjustment. LD drive current setting input. LD drive current output setting. LD drive current output setting. LD drive current output setting. VCC. Oscillation ON for read/forced oscillation ON control. LD drive current ON/OFF control. (High: ON, Low: OFF) Oscillation level initial value setting. Ground. LD anode side connection. VCC. VCC. Description –2– Electrical Characteristics Control status Measurement condition and method CONTR CONT2 2.0 40 60 83 1.21 1.257 1.3 80 103 120 115 125 145 145 157 175 145 163 175 95 104 115 120 133 145 120 136 145 2.0 2.0 Current consumption when CONTR = Low for ICC2 (OSC: ON) — Pin voltage measurement Pin voltage measurement 1.3 2.0 Output current for IIN2 pin input 5V Output current for IIN3 pin input 5V 1.3 2.0 1.3 Current gain measurement for IINR (∆IOUT/∆IIN) Current gain measurement for IIN2 (∆IOUT/∆IIN) Current gain measurement for IIN3 (∆IOUT/∆IIN) 2.0 1.3 2.0 Output current for IINR pin input 5V — — 2.0 2.0 1.3 2.0 1.3 2.0 2.0 1.3 2.0 — 1.3 — — 1.3 2.0 Current consumption for IINR input voltage where oscillation level = 47mAp-p 2.0 1.3 OSC: L (write mode). LD: OFF 2.0 1.3 CONT3 OSCENA ENABLE mA mA mA V mV mA mA mA — — — Min. Typ. Max. Unit (Ta = 25°C, Vcc = 5V) Measurement No. Measurement item Symbol 1 Current consumption 1 ICC1 2 Current consumption 2 ICC2 3 Current consumption 3 ICC3 4 Pin voltage 1 VFR 5 Pin voltage 2 VLE 6 Output drive current IOUT1 7 Output drive current IOUT2 8 Output drive current IOUT3 9 Input/output current gain IGAIN1 10 Input/output current gain IGAIN2 –3– 1.3 L→H H→L 2.0 H→L 1.3 2.0 2.0 1.3 L→H H→L 1.3 2.0 2.0 2.0 1.3 H→L H→L 2.0 2.0 2.0 Oscillation frequency — — — — — — — — — — — — — — — 11 Input/output current gain IGAIN3 AC items IOUT = 40mA (CONTR) + 40mA (CONT2), settling 10 to 90% IOUT = 40mA (CONTR) + 40mA (CONT2), settling 10 to 90% IOUT = 40mA (CONTR) + 40mA (CONT2) Time from 50% of CONT3 (High → Low) to 50% of output final value Time from 50% of CONT3 (Low → High) to 50% of output final value Time from 50% of ENABLE (Low → High) to 50% of output final value Time from 50% of ENABLE (High → Low) to 50% of output final value 3 4 — 3.1 3.4 4.4 2.2 189 Oscillation level when IINR = 2V 60 77 85 ns ns % ns ns ns ns MHz mAp-p 12 Rise time TR 13 Fall time TF 14 Overshoot OVS 15 CONT delay 1 CDELAY1 16 CONT delay 2 CDELAY2 17 LD delay 1 LDELAY1 18 LD delay 2 LDELAY2 19 Oscillation frequency OSCFR 20 Oscillation level OSCLE Logic CONTR, CONT2, CONT3, OSCENA, ENABLE CONTR, CONT2, CONT3, OSCENA, ENABLE Input impedance for IINR, IIN2 and IIN3 2 175 252 375 1.3 V V Ω 21 Logic Low level VTHL 22 Logic High level VTHH CXA2610AN 23 Input resistance ZIN CXA2610AN Electrical Characteristics Measurement Circuit Vcc 22µ V1 3.9kΩ IINR V2 3.9kΩ IIN2 2 3 4.3kΩ 4 V5 3.9kΩ IIN3 V6 CONTR V7 CONT2 V8 CONT3 8 9 7 TTL Delay 10 6 11 V10 OSCENA 5 V-I OSC 12 V11 ENABLE V-I Current SW Driver 15 10Ω 14 13 20Ω 1 V-I 16 0.1µ GND –4– CXA2610AN Description of Functions (1) LD drive current value setting The current controlled by the current setting pins IINR, IIN2 and IIN3 is output from the LD0 pin. The current flowing to the LD0 pin can be set independently for IINR, IIN2 and IIN3 by CONTR, CONT2 and CONT3. (2) LD drive current forced OFF Forced OFF is enabled by setting the ENABLE pin Low. (3) Oscillation circuit The oscillation circuit is turned ON forcibly by setting the OSCENA pin Low. (OSCENA × CONTR × (CONT2 + CONT3)) The oscillation circuit is turned ON by setting the OSCENA pin High only for read. (OSCENA × CONTR × CONT2 × CONT3) (4) Oscillation frequency adjustment The oscillation frequency can be varied by the external resistance value connected to the OSCFR pin. (5) Oscillation level adjustment The oscillation level initial value can be set by the external resistance value connected to the OSCGA pin. The oscillation level can be adjusted by varying the IINR input current value. In addition, the read block DC compensation current IR that flows when oscillation is OFF is independent of the OSCGA pin external resistance value, and is constant. Level adjustment IO – Oscillator amplitude [mAp-p] Oscillator OFF IR – Output current [mA] Initial setting Oscillator amplitude [mAp-p] For large OSCGA external resistance (Io ≈ 0mA) For small OSCGA external resistance 2IR IO + 2 (IR – IO) IR IO IO 0 IINR input current [µA] 12 2k IR < IO IR > IO OSCGA external resistance [Ω] IINR input current [µA] IO ≈ OSCGA pin voltage 40 × OSCGA external resistance 9 [mAp-p] (6) Logic The logic table for the CONTR, CONT2, CONT3 and ENABLE pins is shown below. Be sure to also check the timing chart on page 7. ENABLE L H H H H H CONTR X H L L L L CONT2 X H H L H L CONT3 X H H H L L LD0 OFF OFF IINR IINR + IIN2 IINR + IIN3 IINR + IIN2 + IIN3 –5– CXA2610AN Notes on Operation • Locate the external resistors connected to the IINR, IIN2 and IIN3 pins close to the IC package to prevent the effect from other signal lines. • Make the wiring distance between the output LD0 pin and the laser diode as short as possible. If this wiring is longer, the output waveform characteristics show that the rise and fall times (Tr and Tf) become slower as the ringing becomes larger. • The external resistor connected to Pin 10 (OSCGA) should be within the range from 12Ω to 2kΩ. In addition, this resistance value should be set in consideration of the laser diode Ith so that the oscillation level at IINR = 0V does not exceed the read power. • Temperature assurance The junction temperature for the CXA2610AN laser driver should not exceed 150°C. In addition, the power consumption (PO) should be the allowable power dissipation (PD) or less, and the IC should be used with a lowered thermal resistance (θj-a) for board mounting so that normal operation is possible at the maximum operating temperature of 70°C. Widening the GND area on the set board and other heat radiation countermeasures within the set are necessary in order to lower θj-a. This is because the CXA2610AN thermal resistance (θj-a) differs according to the board, and the power consumption (PO) is also difficult to predict with future increases in power. Obtain the thermal resistance (θj-a) and power consumption (PO) of the package by the following method. Power consumption (PO): Oscillator ON state (OSC level = 47mAp-p) PO = (ICC2 + (total of each input current × 10)) × VCC + (IOP × (VCC – VOP)) ICC2: See page 3 of this Data Sheet. IOP: Output drive current flowing from the LD0 pin to the laser diode VOP: Laser diode operating voltage or, the power consumption can also be obtained as follows. PO = (ICC × VCC) – (IOP × VOP) ICC: Device current consumption (including IOP) during operation Thermal resistance (θj-a) when mounted on a board The diode temperature coefficient is –2.27mV/°C (1) ENABLE pin voltage – VCC pin voltage after applying 0V to the IINR, IIN2 and IIN3 pins = V1 (2) ENABLE pin voltage – VCC pin voltage immediately after applying 3V to IINR = V2 (3) ENABLE pin voltage – VCC pin voltage after applying 3V to the IINR pin and reaching a thermally balanced state = V3 The change in current consumption between (1) and (2) ∆ICC = (3V/(Rext + 250Ω)) × 104. This ∆ICC causes the ENABLE pin internal forward protective diode connection VCC voltage to vary (∆VCC) due to the effects of the wiring resistance from the VCC pin voltage which is used as the reference. The voltage fall coefficient (VR) used to correct this ∆VCC can be obtained by VR = (V1 – V2)/∆ICC. Using VR to apply correction to V3 yields the equation: (∆ICC × VR) + V3 = V4. From this, ∆Tj = (V4 – V2) mV/–2.27mV/°C, and θj-a = ∆Tj/PO [°C/W]. • Allowable power dissipation (PD) ≥ PO [W] PD = (150°C – ambient temperature)/θj-a • Maximum operating temperature 70 °C (150°C – ∆Tj) ≥ 70°C Thus, if θj-a can be lowered from these two conditions, the maximum operating temperature can also be raised. VCC Diode measurement point 1MΩ ENABLE 11 10 VCC 9 10V 5V 5V 5V Thermal Resistance Measurement Circuit –6– CXA2610AN Timing Chart LD0 ENABLE CONTR CONT2 CONT3 OSCENA Application Circuit 1 2 Voltage DAC 3 4 5 TTL/CMOS TTL/CMOS TTL/CMOS 6 7 8 IINR IIN2 GND OSCFR IIN3 CONTR CONT2 CONT3 Vcc 16 Vcc 15 LD0 14 GND 13 OSCGA 12 ENABLE 11 OSCENA 10 Vcc 9 TTL/CMOS TTL/CMOS LD Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –7– CXA2610AN Example of Representative Characteristics High frequency oscillator amplitude vs. Read current characteristics 250 200 Oscillator amplitude [mAp-p] 150 100 OSCGA external resistance value 20Ω 2kΩ 50 0 0 200 400 600 800 1000 1200 1400 IINR input current [µA] High frequency oscillator amplitude frequency dependence (OSCGA = 20Ω) 200 180 160 Oscillator amplitude [mAp-p] 140 120 100 80 60 40 20 0 Approximately 200MHz Approximately 400MHz 0 200 400 600 800 1000 1200 1400 IINR input current [µA] –8– CXA2610AN High frequency oscillator frequency vs. External resistance 700 600 500 Oscillator frequency [MHz] Oscillator frequency 400 300 200 100 0 1 OSCFR pin external resistance value [kΩ] 10 IIN3 input/output current characteristics 350 300 250 Output current [mA] 200 Supply voltage 4.5V 5V 5.5V 150 100 50 0 0 500 1000 1500 Input current [µA] 2000 2500 3000 –9– CXA2610AN Package Outline Unit: mm 16PIN SSOP (PLASTIC) ∗5.0 ± 0.1 + 0.2 1.25 – 0.1 0.1 16 9 A ∗4.4 ± 0.1 1 8 0.65 b B 0.13 M + 0.05 0.15 – 0.02 + 0.1 b=0.22 – 0.05 (0.22) 6.4 ± 0.2 b=0.22 ± 0.03 0.1 ± 0.1 0.5 ± 0.2 DETAIL B : SOLDER DETAIL B : PALLADIUM NOTE: Dimension “∗” does not include mold protrusion. 0° to 10° PACKAGE STRUCTURE DETAIL A PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-16P-L01 SSOP016-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.1g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 10 – + 0.03 0.15 – 0.01 (0.15)