CXA2697ER

CXA2697ER 5-Channel 2-LD Driver for Optical Disc Drive Description The CXA2697ER is a laser driver IC corresponded to DVD ×12 and capable of driving two high output lasers (CD/DVD) for writable optical discs. Features • CD write channel maximum drive current: 300mA (VCC = 3V, VCC_LD = 4.5V, VOP = 2.5V) • CD total maximum drive current: 370mA (VCC = 3.3V, VCC_LD = 5V, VOP = 2.5V) • DVD write channel maximum drive current: 270mA (VCC = 3V, VCC_LD = 4.5V, VOP = 3V) • DVD total maximum drive current: 360mA (VCC = 3.3V, VCC_LD = 5V, VOP = 3V) • Capable of generating five-value recording waveform through control of five channels • Rise/Fall times = 1ns • Read Channel: ×125 • Write Channel: ×470 • Read Channel has extensive low-noise design 1.5nA/√Hz (@20MHz, ILD = 35mA, Imod = 20mAp-p) • High frequency modulator circuit • Frequency variable range: 200 to 600MHz • Modulator amplitude can be set separately for CD and DVD. • DVD modulator amplitude switching function • Timing input for generating recording waveform can be adapted to both differential input (LVDS) and single-end input (3.3V CMOS/TTL). Applications CD-R, CD-RW, DVD-R, DVD-RW, DVD+R/RW, DVD-ROM and DVD-RAM for high-speed writable optical disc drives Structure Bi-CMOS IC Preliminary 32 pin VQFN (Plastic) Absolute Maximum Ratings • Supply voltage VCC 3.6 VCC_LD 5.5 • Storage temperature Tstg –65 to +150 • Allowable power dissipation TBD PD Operating Conditions • Supply voltage V V °C mW VCC 3 to 3.6 VCC_LD 4.5 to 5.5 • Operating temperature Topr –10 to +75 V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– PE03819-PS CXA2697ER Block Diagram and Pin Configuration 8 7 6 5 4 3 2 LDOUT1 9 xOUTEN2 OSCMOD OUTEN2 OSCEN LDEN1 LDEN2 GND2 GND1 1 LDEN OSC CONT DVD Side IIN1, 2: ×125 IIN3, 4, 5: ×470 32 OUTEN3 RAMP2 10 Iref Iref Iref Iref Iref Vref 31 xOUTEN3 RAMP1 11 OSC RAMP11 12 30 OUTEN4 29 xOUTEN4 VCC_LD 13 28 OUTEN5 R FREQ COMP 14 CD Side IIN1, 2: ×125 IIN3, 4, 5: ×470 27 xOUTEN5 R FREQ2 15 26 OUTENREF R FREQ1 16 25 VBG 17 LDOUT2 18 VCC2 19 VCC1 20 IIN5 21 IIN4 22 IIN3 23 IIN2 24 IIN1 –2– CXA2697ER Pin Description Pin No. 1 2 27 28 29 30 31 32 3 Symbol xOUTEN2 OUTEN2 xOUTEN5 OUTEN5 xOUTEN4 OUTEN4 xOUTEN3 OUTEN3 GND1 I/O I I I I I I I I — Pin voltage — — — — — — — — — — 1 29 2 30 27 31 28 32 2k Equivalent circuit Description IIN1 or IIN2 set current control signal input. IIN1 or IIN2 set current control signal input. IIN5 set current control signal input. (negative logic) 500 IIN5 set current control signal input. (positive logic) IIN4 set current control signal input. (negative logic) IIN4 set current control signal input. (positive logic) IIN3 set current control signal input. (negative logic) IIN3 set current control signal input. (positive logic) Ground. DVD modulator amplitude switching control signal. When OSCMOD = high, RAMP1 is selected. When OSCMOD = low, RAMP11 is selected. Modulator control signal. (positive logic) When OSCEN = high, the modulator waveform is output. 4 OSCMOD I — 500 4 5 5 OSCEN I — 6 LDEN2 I — 500 6 7 200k CD output control. (positive logic) 7 LDEN1 I — DVD output control. (positive logic) 8 GND2 — — — Ground. 9 LDOUT1 O — 9 DVD laser drive current output. Enabled when LDEN 1 = high and LDEN2 = low. –3– CXA2697ER Pin No. Symbol I/O Pin voltage Equivalent circuit Description Modulator amplitude setting 2. Enabled when LDEN1 = low and LDEN2 = high. Connects resistance to ground. 10 RAMP2 O — 10 300 11 RAMP1 O — 300 11 12 4p Modulator amplitude setting 1. Enabled when LDEN1 = high, LDEN2 = low and OSCMOD = high. Connects resistance to ground. Modulator amplitude setting 11. Enabled when LDEN1 = high, LDEN2 = low and OSCMOD = low. Connects resistance to ground. 12 RAMP11 O — 13 VCC_LD — — — Output stage supply voltage. 14 R FREQ COMP 300 O — 300 14 4p Modulator frequency variation adjustment. Connects resistance to ground. 15 R FREQ2 O — 300 15 16 300 Modulator frequency setting 2. Enabled when LDEN1 = low and LDEN2 = high. Connects resistance to ground. Modulator frequency setting 1. Enabled when LDEN1 = high and LDEN2 = low. Connects resistance to ground. 16 R FREQ1 O — 4p 17 LDOUT2 O — 17 CD laser drive current output. Enabled when LDEN1 = low and LDEN2 = high. 18 19 20 VCC2 VCC1 IIN5 I I I — — — 20 — — Supply voltage for timing system and current switch. Supply voltage for control system and modulator system. Current setting 5. 21 22 IIN4 IIN3 I I — — 500 1k 21 22 Current setting 4. Current setting 3. –4– CXA2697ER Pin No. Symbol I/O Pin voltage Equivalent circuit Description 23 IIN2 I — 100 23 24 700 Current setting 2. 24 IIN1 I — Current setting 1. 1k 25 VBG O 1.26V 25 1k 300 Internal reference voltage decoupling. 300 26 OUTENREF O 1/2VCC 26 500 Reference voltage output for current control signal. Connects decoupling capacitance to ground. 300 –5– CXA2697ER Electrical Characteristics Test No. 1 2 3 Measurement item Current consumption 1 Current consumption 1' Current consumption 2 Symbol Icc1 Icc1' Icc2 Min. Typ. Max. 1.4 23 75 2 34 2.6 45 (VCC = 3.3V, VCC_LD = 5V, Ta = 25°C) Unit mA mA mA Conditions LDEN1, 2 = L (LDEN1 = H, LDEN2 = L) or (LDEN1 = L, LDEN2 = H) LDEN1 = H, IOUT1 = 60mA, OSCEN = H, AMP = 20mAp-p LDEN = H, IOUT1 = 60mA, IOUT3 = 240mA (Duty = 25%), IOUT4 = 120mA (Duty = 50%), IOUT = IOUT1 + IOUT3 + IOUT4 LDEN = H, IOUT1 = 30mA, IOUT3 = 240mA (Duty = 25%), IOUT4 = 120mA (Duty = 50%), IOUT = IOUT1 + IOUT3 + IOUT4 110 145 4 Current consumption 3 Icc3 162 236 310 mA 5 Current consumption 3-1 Icc3_1 140 200 260 mA 6 7 8 9 10 11 12 13 14 15 Input voltage high level Input voltage low level LVDS Input voltage high level LVDS Input voltage low level LVDS Input voltage amplitude LD drive current 1, 2 LD drive current 3, 4, 5 (DVD) LD drive current 3, 4, 5 (CD) Total LD drive current 1 (DVD) Total LD drive current 2 (CD) Minimum LD drive current 1 (DVD) VSH VSL VDH VDL VPP IOUTR 2 — VCC 1.3 2.6 1.6 1 — — — — — V V V V V mA mA mA mA mA VCC = 3.3V, VCC_LD = 5V, VOP = 3V VCC = 3.3V, VCC_LD = 5V, VOP = 2.5V IIN = 0µA, LDEN1 = OUTEN2 = OUTEN3 = OUTEN4 = OUTEN5 = H IIN = 0µA, LDEN2 = OUTEN2 = OUTEN3 = OUTEN4 = OUTEN5 = H GND — 0.2 0 0.2 120 — — — — — — — — IOUTW1 270 IOUTW2 300 IOUT1 IOUT2 360 370 16 OFFSET1 — — 5 mA 17 Minimum LD drive current 2 (CD) OFFSET2 — — 5 mA 18 Output current noise 1 NOISE1 — 1.5 — f = 400MHz, ILD = 35mA, nA/√Hz Imod = 20mAp-p (20MHz: NOISE) f = 400MHz, ILD = 35mA, nA/√Hz Imod = 40mAp-p (20MHz: NOISE) 19 Output current noise 2 NOISE2 — –6– 1.5 — CXA2697ER Test No. 20 21 Measurement item Symbol Min. Typ. Max. Unit Conditions Propagation delay Rise time (Tr) DELAY TR — — 3 1 — — ns ns ILD = 50 to 100mA pulse Settling 10 to 90% (resistance load) ILD = 100 to 50mA pulse Settling 10 to 90% (resistance load) 22 Fall time (Tf) TF — 1 — ns 23 24 25 26 27 Input resistance 1 (Pins 23, 24) Input resistance 2 (Pins 20, 21, 22) Input/output gain 1, 2 Input/output gain 3, 4, 5 (DVD) Input/output gain 3, 4, 5 (CD) ZIINR ZIINW GAINR 0.56 0.8 1.04 1.05 1.5 1.95 110 125 140 510 510 kΩ kΩ — — — Based on linearity when ILD = 50 to 150mA (IREAD = 30mA) VCC_LD = 4.5V, VCC = 3V, V1 = 1.65V, RL = 5Ω, ILD = 270mA Based on linearity when ILD = 50 to 150mA (IREAD = 30mA) VCC_LD = 4.5V, VCC = 3V, V2 = 1V, RL = 5Ω, ILD = 300mA IIN1 = IIN2 = 250µA IIN2 output current precision based on IIN1 output current IIN1 = IIN2 = 500µA IIN2 output current precision based on IIN1 output current IIN1 = IIN2 = 750µA IIN2 output current precision based on IIN1 output current GAINW1 400 470 GAINW2 400 470 28 ILD control linearity 1 (DVD) LINEA1 –3 — 3 % 29 ILD control linearity 2 (CD) LINEA2 –3 — 3 % 30 Input/output R gain relative precision 1 Input/output R gain relative precision 2 Input/output R gain relative precision 3 Input/output W gain relative precision Input/output transmission band GACCU FBAND –5 — 5 % 31 –5 — 5 % 32 33 34 –5 –5 7 — — — 5 5 — % % MHz Frequency for input/output gain of –3dB –7– CXA2697ER Test No. 35 36 37 38 39 40 41 42 Measurement item Symbol Min. Typ. Max. Unit Condition Frequency variable range Amplitude variable range Frequency variation Frequency temperature characteristic Amplitude variation Amplitude temperature characteristic OSCEN response time (ON) OSCEN response time (OFF) VARIF VARIAMP FREQ TFREQ AMP TAMP OSCRES1 OSCRES2 200 — –10 — — — — — — — — TBD 31 TBD 5 5 600 11 — — — — — MHz fmod = 400MHz fmod = 400MHz fmod = 400MHz fmod = 300MHz fmod = 400MHz fmod = 300MHz, RAMP = 10kΩ % % mAp-p % ns ns Time to reach 90% of Read set current (same condition as current consumption 3) Time to reach 10% of Read set current (same condition as current consumption 3) Time to reach 90% of Write set current (same condition as current consumption 4) Time to reach 10% of Write set current (same condition as current consumption 4) 100 mAp-p 43 LDEN response time 1 (ON) RLDRES1 — — 1 µs 44 LDEN response time 1 (OFF) RLDRES2 — — 10 ns 45 LDEN response time 2 (ON) WLDRES1 — — 1 µs 46 LDEN response time 2 (OFF) WLDRES2 — — 10 ns –8– CXA2697ER Electrical Characteristics Measurement Circuit VCC VCC_LD 100 22µ 8 7 6 5 4 3 2 1 1µ 22µ 1µ OUTEN2 V1 5 9 LDOUT1 xOUTEN2 GND2 LDEN1 LDEN2 OSCEN OSCMOD GND1 GND GND 32 100 OUTEN3 10k 10 RAMP2 xOUTEN3 31 10k 11 RAMP1 OUTEN4 30 100 20k 12 RAMP11 xOUTEN4 29 1µ 22k 13 VCC_LD OUTEN5 28 100 14 R FREQ COMP xOUTEN5 27 11k 15 R FREQ2 OUTENREF 26 1µ 11k 16 R FREQ1 1µ VBG 25 LDOUT2 VCC2 VCC1 IIN5 IIN4 IIN3 IIN2 17 5 V2 18 19 20 21 22 23 24 1µ 1µ –9– IIN1 CXA2697ER Description of Operation (1) LD Drive Current Value Setting The current controlled by the current setting pins IIN1, IIN2, IIN3, IIN4 and IIN5 is output from the LDOUT1 and LDOUT2 pins. IIN1, IIN2, IIN3, IIN4 and IIN5 can be set respectively by OUTEN and xOUTEN for the output drive current from the LDOUT pin. (2) Differential Input and Single-end Input External processing is required for the differential input and single-end input switching. For the single-end input, if the device is used at the active Low, the OUTENREF pin and the OUTEN pin should be shorted externally; if it is used at the active High, the OUTENREF pin and the xOUTEN pin should be shorted externally. Leave the OUTENREF pin open for the differential input. (3) Modulator Circuit The modulator ON/OFF is controlled by the OSCEN pin. For the DVD side, the modulator frequency is varied by the external resistance connected to the RFREQ1 pin and the modulator amplitude can be varied by the external resistance connected to the RAMP1 pin when the OSCMOD is high, and the RAMP11 pin when it is low. For the CD side, the modulator frequency is varied by the external resistance connected to the RFREQ2 pin and the modulator amplitude can be varied by the external resistance connected to the RAMP2 pin. (4) R FREQ COMP Pin The current depending on the internal resistance is generated using the R FREQ COMP pin external resistance to suppress the dispersion of the modulator frequency depending on the internal resistance. The R FREQ COMP pin external resistance is recommended to be fixed to 22kΩ. (5) Modulator Level Adjustment The modulator level adjustment can be performed by varying the IIN1 input current value. Modulator OFF Imod – Modulator amplitude [Ap-p] Modulator amplitude Modulator level adjustment Iread – Output drive current [A] Imod Modulator level [Ap-p] Iread 0 IIN1 – Input current [A] RAMP resistance [Ω] RAMP pin voltage (1.26V) RAMP external resistance IIN1 input current [A] 1/2Imod Iread = IIN1 × 125 Imod ≈ × 200 Iread < 1/2Imod Iread >1/2Imod – 10 – CXA2697ER Description of Functions 1. Logic Table Output control IN1/IN2 IN3 IN4 IN5 LDOUT1 (DVD) OFF IIN1 × 125 IIN2 × 125 LDOUT2 (CD) OFF OFF OFF LDEN1 LDEN2 xOUTEN2 xOUTEN3 xOUTEN4 xOUTEN5 OSCEN OSCMOD L H H H H H H L L L L L L H L L L L L L L H H H H H H H X H L H H H H H L H H H H X X H H L H H L H H L H H L X X H H H L H L H H H L H L X X H H H H L L H H H H L L X X L L L L L L L L L L L L X X L L L L L L L L L L L L X IIN1 × 125 + IIN3 × 470 OFF IIN1 × 125 + IIN4 × 470 OFF IIN1 × 125 + IIN5 × 470 OFF IIN1 × 125 + (IIN3 + IIN4 + IIN5) × 470 OFF OFF OFF OFF OFF OFF OFF (INHIBIT) OFF IIN1 × 125 IIN2 × 125 IIN1 × 125 + IIN3 × 470 IIN1 × 125 + IIN4 × 470 IIN1 × 125 + IIN5 × 470 IIN1 × 125 + (IIN3 + IIN4 + IIN5) × 470 OFF (INHIBIT) Module control LDEN1 LDEN2 xOUTEN2 xOUTEN3 xOUTEN4 xOUTEN5 OSCEN OSCMOD L H H H L L H L L L L H H H X X X X X X X X X X X X X X X X X X X X X X X X X X X X X L H H L H X X H H L X X X OFF MODOFF LDOUT1 OFF OFF LDOUT2 MODON OFF (R FREQ1, RAMP1) MODON (R FREQ1, RAMP11) OFF OFF OFF (INHIBIT) OFF MODOFF MODON (R FREQ2, RAMP2) OFF (INHIBIT) Note: Module control does not depend on a data timing signals. – 11 – CXA2697ER 2. Timing Chart LDOUT1 IIN4 × 470 IIN3 × 470 IIN1 × 125 0mA LDEN1 LDEN2 OSCEN OSCMOD xOUTEN2 xOUTEN3 xOUTEN4 xOUTEN5 H: Imod large LDOUT1 H: Imod small IIN3 × 470 IIN1 × 125 0mA LDEN1 LDEN2 OSCEN H: RAMP1 (ex: Imod large) L: RAMP11 (ex: Imod small) OSCMOD xOUTEN2 xOUTEN3 xOUTEN4 xOUTEN5 – 12 – CXA2697ER Pp5 Pp4 Pp3 LDOUT1 Pp5: IIN5 Pp4: IIN4 Pp3: IIN3 IIN2 × 125 × 470 IIN1 × 125 0mA LDEN1 LDEN2 OSCEN OSCMOD xOUTEN2 xOUTEN3 xOUTEN4 xOUTEN5 – 13 – CXA2697ER Notes on Operation • Arrange the external resistance connected to the IIN1, IIN2, IIN3, IIN4 and IIN5 pins near the IC package to reduce the influence from other signal lines. • Wiring between the output LDOUT pin and the laser diode, and wiring between the Vcc_LD pin and external decoupling capacitance should be the shortest. Making the distance for wiring long increases output waveform overshoots and undershoots caused by the influence of wiring inductance. • The Vcc_LD pin's external decoupling capacitance ground can be grounded to the GND grounding the load from the LDOUT pin. This reverses the phase of the drive waveform at the LDOUT and Vcc_LD and moves in the direction that suppresses overshoots and undershoots. • Temperature guarantee Thermal resistance (θj-a) when the CXA2697ER is mounted on PWB varies according to the set (PWB) and because it is difficult to predict along with the tendency for higher power for power consumption (Po), the following points should be considered when using. Use in a range that does not exceed a junction temperature of 150°C. Also, power consumption (PO) should be below allowable power dissipation (PD). Use with the thermal resistance (θj-a) of the PWB mounting lowered so that it can be operated normally at a maximum operating temperature of 75°C. To lower θj-a, radiating measures on the set, such as widening the GND region with the set PWB are needed. Also, the diepad on the CXA2697ER 32-pin VQFN package is exposed on the surface, so thermal transmission from the IC surface is excellent. For that reason, it is possible to release heat to the set chassis thereby lowering the thermal resistance of the PWB mount. Find the thermal resistance (θj-a) when mounted on PWB and power consumption (PO) using the following method. Po = (Icc × Vcc) – (Iop × Vop) Icc: IC current consumption when operating (Including Iop) Iop: Output drive current flowed from the LDOUT pin to the Laser Diode Vop: Operating voltage of the laser diode Thermal resistance (θ j-a) when mounted on PWB Diode temperature coefficient XXmV/°C and the positive protection diode temperature characteristics are used to find this. The V2 voltage found in (2) below cancels the voltage decrease caused by the wiring resistance between the positive protection diode connection Vcc and the Vcc pins as reference and is measured to find the precise temperature characteristics of the positive protection diode. (1) V1 to LDEN pin voltage to Vcc pin voltage, Icc1 to current consumption when 0V is applied to the IIN1, IIN2, IIN3, IIN4 and IIN5 pins. (2) V2 to LDEN pin voltage to Vcc pin voltage immediately after applying the arbitrary voltage to the IINx pin. (3) V3 to LDEN pin voltage to Vcc pin voltage, Icc3 to current consumption when applying the arbitrary voltage to the IINx pin and heat reaches equilibrium. ∆Tj using the voltage drop (V1 to V2) between the positive protection diode connection Vcc and the Vcc pins that are the reference, as described above are: ∆Tj = ((V3 + (V1 – V2)) – V1)/XXmV/°C Thermal resistance (θj-a) is: θj-a = ∆Tj/(Icc3 – Icc1) × Vcc – Iop × Vop • Allowable power dissipation (PD) ≥ PO [W] PD = (150°C – Ambient temperature)/θj-a • Maximum operating temperature 75°C (150°C – ∆Tj) ≥ 75°C – 14 – VCC 18 LDEN VCC Pin voltage measurement point 1MΩ 6 6.6V 3.3V 3.3V 3.3V GND CXA2697ER Example of Representative Characteristics IIN1, IIN2 input current vs. CD/DVD output current characteristics Vcc_LD = 5V, Vcc = 3.3V, resistance load 180 160 400 350 CD/DVD output current [mA] IIN3, IIN4, IIN5 input current vs. CD/DVD output current characteristics Vcc_LD = 5V, Vcc = 3.3V, resistance load CD/DVD output current [mA] 140 120 100 80 60 40 20 0 0 200 400 600 800 1000 1200 1400 IIN1, IIN2 input current [µA] 300 250 200 150 100 50 0 0 100 200 300 400 500 600 700 800 900 IIN3, IIN4, IIN5 input current [µA] Modulator frequency control characteristics Imod = 40mAp-p (RAMP = 5kΩ) R FREQ COMP = 22kΩ 800 700 RAMP resistance value vs. Modulator waveform peak current characteristics fmod = 400MHz (R FREQ = 7kΩ) R FREQ COMP = 22kΩ 80 70 Modulator amplitude [mAp-p] Modulator frequency [MHz] 600 500 400 300 200 100 0 0 5 10 15 20 25 R FREQ resistance [kΩ] 60 50 40 30 20 10 0 0 5 10 15 20 25 RAMP resistance [kΩ] – 15 – CXA2697ER Application Circuit 1 Mode Control Logic CMOS 3.3/TTL 100 8 7 6 5 4 3 2 1 GND2 LDEN1 LDEN2 GND1 OUTEN2 LD1 OUTEN3 100 10k 10 RAMP2 xOUTEN3 31 10k 11 RAMP1 OUTEN4 30 100 20k 12 RAMP11 xOUTEN4 29 1µ 22k 13 VCC_LD OUTEN5 28 100 14 R FREQ COMP xOUTEN5 27 11k 15 R FREQ2 OUTENREF 26 1µ 11k 16 R FREQ1 1µ VBG 25 LDOUT2 VCC2 VCC1 IIN5 IIN4 IIN3 17 18 19 20 21 22 23 IIN2 24 LD2 1µ 1µ Voltage DAC Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 16 – IIN1 Timing Control Logic LVDS 9 LDOUT1 xOUTEN2 OSCEN OSCMOD 32 CXA2697ER Application Circuit 2 Mode Control Logic CMOS 3.3/TTL 8 7 6 5 4 3 2 1 GND2 LDEN1 LDEN2 GND1 OUTEN2 xOUTEN2 OSCEN OSCMOD LD1 9 LDOUT1 32 OUTEN3 10k 10 RAMP2 xOUTEN3 31 10k 11 RAMP1 OUTEN4 30 20k 12 RAMP11 xOUTEN4 29 1µ 22k 13 VCC_LD OUTEN5 28 14 R FREQ COMP xOUTEN5 27 11k 15 R FREQ2 OUTENREF 26 1µ 11k 16 R FREQ1 1µ VBG 25 LDOUT2 VCC2 VCC1 IIN5 IIN4 IIN3 17 18 19 20 21 22 23 IIN2 24 LD2 1µ 1µ Voltage DAC Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 17 – IIN1 Timing Control Logic CMOS 3.3/TTL CXA2697ER Package Outline Unit: mm 32PIN VQFN (PLASTIC) 4.8 4.4 2.3 C 24 17 0.675 0.05 S 1.4 0.8 ± 0.1 0.5 0.1 25 A 16 B 92 5. 32 PIN 1 INDEX 1 0.4 9 6 0. 45˚ C x4 0.1 S A-B C x4 0.1 S A-B C S 0.05 M S A-B C 0.03 ± 0.03 Solder Plating 0.13 ± 0.025 + 0.09 0.14 – 0.03 NOTE:1)The dimensions of the terminal section apply to the ranges of 0.1mm and 0.25mm from the end of a terminal. TERMINAL SECTION PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VQFN-32P-07 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.04g 0.125 ± 0.01 – 18 – 0.155 ± 0.02 Sony Corporation (0 8 .1 7) (0 .3 9)