CXA3001N

CXA3001N RX Gain Control Amplifier For the availability of this product, please contact the sales office. Description CXA3001N is an RX gain control amplifier for CDMA cellular mobile phone. Features • Wide gain control range • Linear gain slope • Noise figure Typ. 6dB at Gain = 45dB • Output IP3 Typ. +2dBm at Gain = 40dB • 2 input ports • Power save function included Absolute Maximum Ratings • Supply voltage • Operating temperature • Storage temperature • Allowable power dissipation • Supply voltage range • Logic input voltage • Signal input voltage • Differential signal input voltage Operating Conditions Supply voltage Applications • CDMA cellular mobile phone • CDMA & AMPS cellular phone Structure Bipolar sillicon monolithic IC 24 pin SSOP (Plastic) VCC Topr Tstg PD 6 –40 to +85 –65 to +150 420 –0.3 to 6 –0.3 to VCC +0.3 –0.3 to VCC +0.3 0 to 2.5 V °C °C mW V V V V 3.1 to 3.8 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95711-PP CXA3001N Block Diagram IF Input for CDMA CDMAIN CDMAINX SWITCH OUT OUTX SWITCH IF Output IF Input for FM FMIN FMINX Input Select MODE BP1 to External Capacitor BP2 Gain Control GCTL Supply Voltage VCC1, 2 Bias Driver Ground GND1, 2 CXA3001N Power Save PSV –2– CXA3001N Pin Configuration MODE 1 24 PSV VCC1 2 23 GCTL GND1 3 22 NC NC 4 21 NC CDMAIN 5 20 NC NC 6 CXA3001N CDMAINX 7 19 OUTX 18 NC NC 8 17 OUT FMIN 9 16 NC NC 10 15 VCC2 FMINX 11 14 GND2 BP1 12 13 BP2 –3– CXA3001N Pin Description Pin No. Symbol Pin voltage Typ. (V) Equivalent circuit VCC1 Description 30k 1 1 MODE Input select pin. CDMAIN for High. FMIN for Low. GND1 2 3 4 6 8 10 VCC1 GND1 3.6 0 Positive power supply. Ground. N.C. No connection. 5 CDMAIN 1.2 2k 2k Differential input pins for received CDMA IF signal. GND1 7 CDMAINX 1.2 5 7 9 FMIN 1.2 2k 2k Differential input pins for received FM IF signal. GND1 11 FMINX 1.2 9 11 VCC2 12 13 14 15 16 17 19 BP1 2.4 BP2 GND2 VCC2 N.C. OUT OUTX 1.7 1.7 –4– 0 3.6 19 Connected to GND with capacitor 0.01µF. 17 Ground for output stage. Positive power supply for output stage. 20k 20k 12 13 No connection. Differential output pins for received IF signal. GND2 CXA3001N Pin No. 18 20 21 22 Symbol Pin voltage Typ. (V) Equivalent circuit Description N.C. No connection. VCC1 23 GCTL 23 Gain control pin with a ripple filter. GND1 VCC1 24 PSV 24 40k Power save function pin. High: Active Low: Power save GND1 –5– CXA3001N Electrical Characteristics DC characteristics Parameter Current consumption 1 Current consumption 2 Current consumption 3 Current consumption 4 Input current pin 1H Input current pin 1L Input current pin 23H Input current pin 23L Input current pin 24H Input current pin 24L MODE high voltage MODE low voltage PSV high voltage PSV low voltage AC characteristics Parameter Symbol Conditions Min. 10 VMODE = "H" VGCTL = 2.3V VMODE = "H" VGCTL = 1.5V VMODE = "H" VGCTL = 0.7V VMODE = "H" VMODE = "L" VGCTL = 2.3V VMODE = "L" VGCTL = 1.5V VMODE = "L" VGCTL = 0.7V VMODE = "L" f = 85.38MHz Level = –50dBm Level = –30dBm Level = –10dBm VGCTL = 1 to 2V f = 85.38MHz Level = –50dBm Level = –30dBm Level = –10dBm VGCTL = 1 to 2V 37 –7.5 –55 57 37 –7.5 –55 57 41 –3 –49 60 41 –3 –49 60 Symbol ICC1 ICC2 ICC3 ICC4 IMODE H IMODE L IGCTL H IGCTL L IPSV H IPSV L VMH VML VPSH VPSL Conditions VGCTL = 1.5V, Pin 2 VGCTL = 1.5V, Pin 15 VPSV = 0.5V, Pin 2 VPSV = 0.5V, Pin 15 VMODE = 3V VMODE = 0.5V VGCTL = 3V VGCTL = 0.5V VPSV = 3V VPSV = 0.5V Pin 1 Pin 1 Pin 24 Pin 24 3 0.5 (VCC = 3.6V, Ta = 25°C) Typ. Max. 100 46 1.5 –44 63 46 1.5 –44 63 dB/V dB dB/V dB Unit MHz –10 3 0.5 V –10 10 –20 10 Min. 10 4.7 (VCC = 3.6V, Ta = 25°C) Typ. 14 6.6 Max. 19 9.0 1 1 10 µA Unit mA Operating frequency range FR Gain Gain Gain CDMA2.3 CDMA1.5 CDMA0.7 GCDMA2.3 GCDMA1.5 GCDMA0.7 GCLIN GFM2.3 GFM1.5 GFM0.7 GFMLIN CDMA Gain slope Gain Gain Gain FM2.3 FM1.5 FM0.7 FM Gain slope Input level 3rd order intercept point IIP3 VMODE = "H" GCDMA = 40dB∗ F1 = 86.38MHz F2 = 87.38MHz Measure of 85.38MHz VMODE = "H" GCDMA = 40dB∗ Used 1MHz BPF Measure of 85.38MHz –42 –38 dBm Noise Figure NF 6.5 9.5 dB ∗ Adjust GCTL voltage, and set the overall gain to 40dB. –6– CXA3001N Measurement Circuit V1 A1 V24 1 MODE PSV 24 A24 V2 A2 1k 0.01µ 2 VCC1 GCTL 23 0.01µ A23 V23 3 GND1 NC 22 10k V5 4 NC NC 21 1:3 CDMA INPUT 680n 1000p 1000p 5 CDMAIN NC 20 220 10k V19 1.2k 6 NC OUTX 19 1000p 3:1 OUTPUT 7 CDMAINX V7 NC 18 220 1000p V17 10k 10k V9 8 NC OUT 17 10k 1:3 FM INPUT 680n 1000p 10k V11 9 FMIN 1000p 1.2k 10 NC NC 16 0.01µ V15 A15 VCC2 15 11 FMINX GND2 14 0.01µ 0.01µ 12 BP1 V12 BP2 13 V13 1k 1k –7– CXA3001N Application Circuit 1µ VCC 0.1µ CDMA FM Active Sleep 0.01µ 1 2 3 24 23 22 0.01µ 21 20 CXA3001 19 18 17 16 15 14 13 0.01µ 0.01µ 220 220 1k Gain Control Voltage 1000p CDMA RX IF INPUT CDMA RX BPF ∗ ∗ 4 5 6 7 1000p FM RX IF INPUT FM RX BPF ∗ 1000p ∗ 8 9 10 11 1000p 12 0.01µ RX IF BPF RX IF OUTPUT ∗ Must be adjusting values to result a best impedance matching between BPF filter and this IC. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –8– CXA3001N Design Reference Values Single ended measurement Item Input resistance Input capacitance Output resistance Symbol RIN CIN ROUT f = 85.38MHz, VGCTL = 1.5V Conditions (VCC = 3.6V, Ta = 25°C) Typ. 900 9 30 Unit Ω pF Ω Notes on Operation 1) This IC is a wideband amplifier with wide gain control range. Separate Pin 3 (GND1) and Pin 14 (GND2) to prevent interference between input and output. Furthermore, the decoupling capacitors between Pins 2 and 3, Pins 14 and 15 should be as close to the IC as possible. 2) The resistors connected to Pins 17 and 19 should be as close to the IC as possible. 3) This IC assumes the excellent characteristics when the differential input impedance between Pins 5 and 7, Pins 9 and 11 is 500Ω. Refer to the Measurement Circuit for the external element settings, etc. 4) Connect the capacitors, which are connected to Pins 12 and 13, to Pin 14 (GND2). 5) Pay attention to handling this IC because its electrostatic discharge strength is weak. –9– CXA3001N Sensitivity 60 VCC = 3.6V 40 20 Power gain [dB] 0 –20 –40 T = –40deg T = 25deg T = 85deg –60 0 0.5 1 1.5 2 2.5 3 3.5 VGCTL [V] IIP3 0 VCC = 3.6V –10 –20 IIP3 [dBm] –30 –40 Ta = –40deg Ta = 25deg Ta = 85deg –40 –20 0 Power gain [dB] 20 40 60 –50 –60 –60 – 10 – CXA3001N Noise Figure 50 VCC = 3.6V 40 Ta = –40deg Ta = 25deg Ta = 85deg Noise figure [dB] 30 20 10 0 –60 –40 –20 0 Power gain [dB] 20 40 60 Gain Error from Room Temp. 6 VCC = 3.6V 4 Ta = –40deg Ta = 85deg 2 Gain error [dB] 0 –2 –4 –6 –60 –40 –20 0 Power gain [dB] 20 40 60 – 11 – CXA3001N Package Outline Unit: mm 24PIN SSOP (PLASTIC) 275mil ∗7.8 ± 0.1 24 13 + 0.2 1.25 – 0.1 0.10 A 0.1 ± 0.1 5.6 ± 0.1 7.6 ± 0.2 0° to 10° + 0.1 0.22 – 0.05 1 12 + 0.05 0.65 ± 0.12 0.15 – 0.02 DETAIL A NOTE : ∗NOT INCLUDE MOLD FINS. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-24P-L01 A SIMILAR TO SSOP024-P-0300 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING 42 ALLOY – 12 – 0.5 ± 0.2