CXA3003R

CXA3003R Baseband analog processing IC for dual-mode CDMA/FM cellular phone For the availability of this product, please contact the sales office. Description The CXA3003R is a baseband analog processing IC for dual-mode CDMA/FM cellular phone. The CXA3003R interfaces between the inter-frequency section and the digital processing circuitry of the telephone. The receive circuit functions primarily convert analog IF signals to the analog baseband frequency range and to convert the analog baseband signals into digital signals. Transmit circuits convert digital data into analog baseband signals which are then up-convert to the IF frequency range. Features • Receive signal path includes: · IF to baseband down conversion · Built-in trim-free low-pass filter for CDMA and FM · Built-in A/D convertor convert the RX base band signal to the digital signal · Analog output Receive Signal Strength Indicator (RSSI) for CDMA · Local Oscillator for I-Q mixer • Transmit signal path includes: · Built-in D/A convertor convert the digital I-Q data to the analog baseband signal · Built-in trim-free low-pass filter for CDMA and FM · Baseband to IF up-conversion · Local Oscillator for I-Q mixer · Built-in PLL for TX IF • Built-in House keeping A/D convertor • Low power consumption in all modes • Single 3.3 V power supply Applications • dual-mode CDMA/FM cellular telephone 80 pin LQFP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC –0.3 to 5.5 • Operating temperature Ta –55 to +125 • Storage temperature Tstg –65 to +150 Recommended Operating Conditions • Supply voltage VCC 3.3±0.165 • Operating temperature Ta –40 to +85 V °C °C V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E96434-TE CXA3003R Block Diagram GND BUFF VDD BUF RXQD3 RXQD2 RXQD1 CHIPX8 RXQD0 TXCLKB RXID3 RXID2 RXID1 TXCLK RXID0 TXD5 TXD4 TXD7 TXD3 60 RXFMSTRB 61 FMCLK 62 59 58 57 56 55 54 53 52 51 50 49 48 47 46 TXD6 45 44 43 42 TXD2 41 40 39 TXD0 GND ESD VDD DAC GND DAC NC NC DNC DNC CAP2 CAP1 NC TCXO4 NC NC TCXO NC LOCK DET VDD TXF GND TXF VDD SYNTH CDMA Q ADC CDMA I ADC Q DAC RXIFMDT 64 DNC 65 DNC 66 I DAC RXQFMDT 63 TXD1 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 FMQ ADC FMI ADC CDMA Q RX LPF CDMA Q TX LPF GND ADC 67 VDD ADC 68 QOFFSET 69 IOFFSET 70 HKADVCC 71 NC 72 FM Q RX LPF FM I RX LPF CDMA I RX LPF CDMA I TX LPF FM TX LPF CHIP X8 ADCDT 74 VCO ADCIN 76 VCO IDLEB 78 FMB 79 RXVCOOUT 80 RSSI SLEEPB 77 MODE CNTL 1 GND 2 RXVCO T1 3 RXVCO T2 4 GND RXIF 5 VDD RXIF 6 RXIFB 7 RXIF 8 RSSI 9 GND RX 10 11 12 13 14 15 16 17 PD 18 ADCENBL 75 1/2 ADCCLK 73 HK ADC PLL 1/2 1/4 19 —2— GND SYNTH TXIF GND TXIF VDD TXIF FM MOD TVCO T2 TVCO T1 PD ISET VDD RX PD OUT TXIFB CXA3003R Pin Description Pin No. 1 Symbol Typical Voltage (V) DC AC 0V 2 3 VDD RXIF Equivalent circuit Description GND Negative power supply pin. 2 RXVCO TI 1k 1k Receive VCO tuning pins. Connected to an external LC tank circuit for setting the receive VCO frequency. 3 RXVCO T2 GND RXIF 4 5 GND RXIF VDD RXIF 0V 3.3 V Negative power supply pin for RXIF block. Positive power supply pin for RXIF block. VDD RXIF 6 RXIFB 2V 250 250 2k 2k 6 7 Analog differential receive IF input pins. 2k 2k 7 RXIF 2V GND RXIF VDD RXIF 150 8 RSSI 8 Analog RSSI output pin. GND RXIF 9 10 GND RX VDD RX 0V 3.3 V —3— Negative power supply pin for RX block. Positive power supply pin for RX block. CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD TXIF 11 TXIFB 2.1 V 400 400 11 12 200 200 Analog differential transmit IF output pins. 12 TXIF 2.1 V GND TXIF 13 14 GND TXIF VDD TXIF 0V 3.3 V VDD TXF Negative power supply pin for TXIF block. Positive power supply pin for TXIF block. 150 15 FM MOD 1.5 V 15 Analog baseband signal output pin for FM. GND TXF 16 17 VDD TXIF 16 TVCO T1 1k 1k Transmit VCO tuning pins. Connected to an external LC tank circuit for setting the transmit VCO frequency. 17 TVCO T2 GND TXIF —4— CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD TXF 150 18 PD ISET 0.64 V 18 Current of PD OUT setting pin. GND TXF VDD TXF 6.25k 150 19 PD OUT 19 Transmit synthesizer charge pump output pin. 6.25k GND TXF 20 21 22 23 GND SYNTH 0V VDD SYNTH 3.3 V GND TXF VDD TXF 0V 3.3 V VDD SYNTH Negative power supply PLL block. Positive power supply PLL block. Negative power supply TX block. Positive power supply TX block. pin for pin for pin for pin for 150 24 LOCK DET 24 Transmit IF synthesizer lock detect output pin. GND SYNTH —5— CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD SYNTH 150 26 26 TCXO 2.2 V 20k 20k Input pins for External clock 19.68 MHz (TCXO). GND SYNTH 39 25 27 28 30 35 36 GND ESD 0V Negative power supply pin. NC Don't connect pins. VDD DAC 150 29 TCXO4 29 Output pin for TCXO/4 frequency. GND ESD VDD RX 31 32 CAP1 CAP2 31 32 The pins for External Capacitor. GND RX 33 34 37 DNC GND DAC 0V —6— Don't connect any line to this pin. Negative power supply pin for TXDA block. CXA3003R Pin No. 38 Symbol Typical Voltage (V) DC AC 3.3 V Equivalent circuit Description Positive power supply pin for TXDA block. VDD DAC VDD DAC 40 to 47 TXD0 to TXD7 40 41 42 43 45 60k 46 47 48 49 Transmit Data input pins for Transmit 8 bit D/A converter. TXD7 is the MSB. 48 49 TXCLK, TXCLKB 44 Differential transmit Clock input pins for Transmit 8 bit D/A converter. GND DAC 50 51 GND BUF VDD BUF 0V 3.3 V Negative power supply pin for A/D output block. Positive power supply pin for A/D output block. VDD BUF 52 CHIP x 8 Output pin for CHIPx8 divider with a ratio of 512/1025xTCXO. 57 52 53 to 56 57 to 60 RXID0 to RXID3 RXQD0 to RXQD3 53 58 54 55 56 59 60 Output pins for Receive CDMA 4 bit A/D converter of I signal. RXID3 is the MSB. Output pins for Receive CDMA 4 bit A/D converter of Q signal. RXQD3 is the MSB. GND BUF VDD ADC 61 RXFMSTRB 61 62 100k Strobe input pin for Receive FM 8 bit A/D converter. 62 FMCLK GND ADC Clock input pin for Receive FM 8 bit A/D converter. —7— CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD BUF 63 RXQFMDT Q serial data output pin for Receive FM 8bit A/D converter. 63 64 64 RXIFMDT GND BUF I serial data output pin for Receive FM 8bit A/D converter. 65 66 67 68 DNC GND ADC VDD ADC 0V 3.3 V Don't connect any line to this pins. Negative power supply pin for A/D converter block. Positive power supply pin for A/D converter block. VDD RX 69 QOFFSET 1.5 V 30k 30k Receive Q channel offset adjust input pin. 142k 142k 22k 150 70 69 70 IOFFSET 1.5 V 100k 150 Receive I channel offset adjust input pin. GND RX 71 72 HKADVCC NC 3.3 V Positive power supply pin for HKA/D converter block. Don't connect pin. —8— CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD BUF 73 ADCCLK Clock output pin for House Keeping 8 bit A/D converter. 73 74 74 ADCDT GND BUF Serial data output pin for House Keeping 8 bit A/D converter. VDD BUF 60k 75 75 ADCENBL Enable input pin for House Keeping 8 bit A/D converter. GND BUF HKADVCC 76 ADCIN 1.5 V 76 48.5k A/D analog input pin for House Keeping 8 bit A/D converter. GND ADC —9— CXA3003R Pin No. Symbol Typical Voltage (V) DC AC Equivalent circuit Description VDD ADC 77 77 78 79 SLEEPB, IDLEB, FMB 150 78 0V 79 Test mode switch pins. These pins control this IC function mode (∗1). GND ADC VDD RXIF 80 RXVCOOUT 80 Receive VCO output pin connected the external PLL IC. GND RXIF ∗1 Function Mode Function Mode CDMA RXTX CDMA Idle CDMA Sleep FM RXTX FM Idle FM Idle (Transition) FM RXTX (Transition) CDMA Sleep (Transition) FMB high high high low low low low high IDLEB high low low high low low high high SLEEPB high high low high high low low low Mode functions explain: 1. CDMA RXTX : This mode requires everything except the FMspecific circuits to be operating. 2. CDMA Idle : This mode powers down all transmit circuits and FM receive. 3. CDMA Sleep : This mode powers down everything except the TCXO divider and TCXO/4 output driver. 4. FM RXTX : This mode powers down all CDMA-specific circuits except the CHIPx8 synthesizer. 5. FM Idle : This mode powers down all transmit and CDMA Receive circuits. —10— CXA3003R Electrical Characteristics DC Characteristics (VDD=3.3 V±5 %, Ta=40 °C to 85 °C) Typ. 40 25 2 30 16 Max. 57 35 3 45 21 0.3xVDD 0.4 100 15 15 Unit Item Symbol Condition Min. Power supply current - CDMA RXTX IDD1 Power supply current - CDMA Idle IDD2 Power supply current - CDMA sleep IDD3 Power supply current - FM RXTX IDD4 Power supply current - FM Idle IDD5 ∗1 Logic High level input voltage VIH 0.7xVDD ∗1 Logic Low level input voltage VIL ∗1 Logic High level output voltage VOH 2.7 ∗1 Logic Low level output voltage VOL ∗1 Logic input Leakage current IL –100 ∗1 Input capacitance Digital input Cin-d ∗1 Load capacitance Digital output Cl-d ∗1 Load resistance Digital output Rl-d 100 k ∗1 : Logic Input pins = 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 61, 62, 75, 77, 78, 79 Logic Output pins =52, 53, 54, 55, 56, 57, 58, 59, 60, 63, 64, 73, 74 AC Characteristics TXCLK/TXCLKB vs. TXIQDATA for CDMA mode Item Data Setup to TXCLK/TXCLKB Transition Data Hold after TXCLK/TXCLKB Transition Symbol tsua tha Condition mA V µA pF Ω VDD=3.3 V±5 %, Ta=–40 °C to 85 °C Min. Typ. 50 ns 50 Max. Unit TXCLK (input) TXCLKB (input) tsua tha TXQDATA (input) TXCLK=4.9152MHz TXQ Data TXI Data Fig. 1 TXCLK/TXCLKB vs. TXIQDATA Timing Diagram for CDMA mode CHIPx8 vs. RXIQDATA Item Data Output stable prior to CHIPx8 fall Data Hold after CHIPx8 fall CHIPx8 raise time CHIPx8 fall time VDD=3.3 V±5 %, Ta=–40 °C to 85 °C Min. Typ. Max. Unit 20 15 ns 3 7.2 10 % to 90 %, Cload=15 pF 3 9.9 Condition —11— Symbol tsub thb trb tfb CXA3003R tsub Chip × 8 (output) thd RXIData RXQData (output) Fig. 2 CHIPx8 vs. RXIQDATA timing diagram TXCLK vs. RXDATA for FM mode Item Data setup to TXCLK transition Data Hold after TXCLK transition Symbol tsuc thc Condition VDD=3.3 V±5 %, Ta=–40 °C to 85 °C Min. Typ. Max. Unit 2.08 µs 2.08 TXCLK (input) TXCLKB (input) tsuc thc TX DATA (input) TXCLK=120kHz XXXX TX Data XXXX TX Data XXXX Fig. 3 TXCLK vs. RXDATA mode timing diagram for FM FMCLK, RXFMSTROBE vs. RXFMDATA (I, Q) VDD=3.3 V±5 %, Ta=–40 °C to 85 °C Item Symbol Condition Min. Typ. Max. Unit Strobe input valid to CLK Falling Edge tsud-s 0.69 Strobe input valid after CLK Falling Edge thd-s 2.08 Data out valid to CLK Rising Edge tsud-d 1.38 µs Data out valid after CLK Rising Edge thd-d 1.38 CLK High Time tclk-hi 1.38 CLK Low Time tclk-lo 1.38 RXFMDATA (I, Q) raise time trd 3 7.2 10 % to 90 %, Cload=15 pF ns RXFMDATA (I, Q) fall time tfd 3 9.9 —12— CXA3003R tclk-hi thd-d thd-s FMCLK (input) tclk-lo FMRXSTROBE (input) tsud-s tsud-d FXRXDATA (I, Q) (output) LSB+1 FMCLK=360kHz FMRXSTROBE=40kHz LSB XXX MSB MSB-1 LSB Fig. 4 FMCLK, FMRXSTROBE vs. RXFMDATA (I, Q) timing diagram Note : FM RXSTROBE pulse width must be ≤ one FMCLK period. ADCENABLE & ADC CLK vs. ADC DATA (VDD=3.3 V±5 %, Ta=–40 °C to 85 °C) Item Symbol Condition Min. Typ. Max. Unit Enable True to first Clock output ten-clk 6 µs Enable Pulse to end of conversion tdEn-EOC 16.8 Data out valid to CLK rising edge tsue-d 600 ns Data out valid after CLK rising edge the-d 600 Enable True Pulse width ten-pw 10 µs Output raise time tre 7.2 10 % to 90 %, Cl=15 pF ns Output fall time tfe 9.9 ADCENABLE ten-pw tsue-d ADCCLK ten-clk the-d ADCDATA MSB LSB tdEn-EOC ADCCLK=820kHz (TCXO÷24) Fig. 5 ADCENABLE & ADC CLK vs. ADC DATA timing diagram —13— CXA3003R VHF Local Oscillator Item VCO output Frequency Range Lock mode charge pump Output Current Acquisition Mode charge pump Output Current Maximum Iout Adjustment Range Acquisition Mode Disable Frequency Range Phase Detector Output Compliance Voltage Phase Detector Output Impedance Reference Input Frequency Phase Detector Frequency Reference Spurs Lock Detect Pull Down Voltage Lock Detect Off Leakage Current Phase Detect Unlock Deviation Threshold during FM Rate Tank Circuit Input Impedance External VCO Input Levels Symbol fvcot Icplt Icpat Icpmaxrt Condition VDD=3.3 V±5 %, Ta=–40 °C to 85 °C Min. Typ. Max. 260.76 15.5 160 18.6 µA Rset=40 kΩ Using Rset to vary nominal output current Acquisition mode initiated only by transition to any TX active mode 128 –40 192 +40 % Unit MHz Rset=40 kΩ 12.4 ∆fadt –1 k +1 k Hz Vopdt Zopdt freft fpdt rst VLldt ILedt PDfhdt PDfhrt Zit Vext 0.4 1M Ref.frequency/16 Rload≥10 kΩ to VDD VO=VDD Measured at TXIF Nominal Impedance into each pin 300 1.5 k 200 2k 600 2M 19.68 1.23 –80 VDD–0.4 V Ω MHz MHz dBc V µA kHz Hz Ω mVp-p 0.4 10 12 2.5 k 800 Receive VCO Item VCO output Frequency Range VCO Output Voltage Swing at 170 MHz Tank Circuit Input Impedance Symbol fvcor Vovr Zir Condition VDD=3.3 V±5 %, Ta=–40 °C to 85 °C Min. Typ. Max. 170.76 147 2k 2.5 k Unit MHz mVrms Ω Into 500 Ω//5 pF load, AC coupled load Nominal impedance into each pin 100 1.5 k —14— CXA3003R CDMA Receive Item Input Signal Level CDMA Sinusoid Single Tone jammer Desense Input Center Frequency Input Resistance Input Capacitance Input Referred Noise Spurious Content Jammer Related Spurious Content Offset Adjust Gain Offset Adjust Input Impedance A/D Converter Linearity Signal Path Gain Accuracy, Part to Part Signal Path Gain Accuracy, Total CDMA RX Residual Sideband Product Filter Attenuation Gain Flatness vs. Frequency Symbol Vincdcr Vinscr Jdcr ficcr Ricr Cicr IRNcr SCcr Jrscr Gadjocr Ziocr Ladcr ∆Gspcr ∆Gstcr RSpcr FA1cr FA2cr Gfcr ≥900 kHz ≥1.2 MHz 1 kHz to 630 kHz Condition VDD=3.3 V±5 %, Ta=–40 °C to 85 °C Min. Typ. Max. Unit 0.9 mVrms 5.38 mVp-p 0.13 0.5 dB 85.38 220.38 MHz 500 650 Ω 1.5 pF 70 –40 –32 –60 –50 135 –25 –18.4 –40 µVrms dBc dBc ≥900 kHz offset Differential From each pin to GND Sum of I&Q,measured from 1 kHz to 630 kHz Total of all harmonic and non-harmonic power Peak in-band spurious products 375 Full scale At nominal temp and VDD Over part to part, VDD, temp %Full scale/V 100 k 170 k 220 k Ω LSB –1.6 –2.1 1.6 dB 2.1 21 46 48 50 62 2.0 dBc dB dBp-p —15— CXA3003R CDMA Transmit Item Symbol VDD=3.3 V±5 %, Ta=–40 °C to 85 °C Condition I&Q in Quadrature Full Scale Signals.At nominal VDD and temp Differential From each pin to GND Min. 267 495 Typ. 300 500 40 35 30 dBc Sfdr3ct Csct Sfdr5ct Snr1ct Snr2ct focct Gerrct Perrct Afct I&Q in Quadrature, Full Scale Signals Even Harmonics Odd Harmonics IF±≥0.1 M to IF±60 kHz –1.3 –2.1 27 48 60 0.4 68 69 1 –50 –42 –18.4 –40 1.3 dB 2.1 dBc dBp-p dB %Full scale/V µVrms dBc 375 —17— CXA3003R FM Transmit Item IF Output Amplitude IF Load Resistance IF Load Capacitance IF Output impedance IF Signal to Noise Ratio, Noise Band1 IF Output Amplitude Variation IF Output Amplitude Drift Maximum Spurious Content : TX IF Harmonics FM Mod Output Voltage FM Mod load Resistance FM Mod Amplitude Variation FM Mod Spurious Free Dynamic Range, to 120 kHz FM Mod Signal to Noise Ratio, 1 kHz to 15 kHz Amplitude Flatness vs. Frequency, DC to 10 kHz Symbol Voifft Rlifft Clifft Zoft Snr1ft Voifvft ∆Voifdft Sceft Scoft Vmodft Rmodft ∆Vmodvft Sfdrft Over part to part , VDD and temp Two tone inputs Condition VDD=3.3 V±5 %, Ta=–40 °C to 85 °C Min. 124 495 Typ. 140 500 40 IF±≥0.1 M to IF±2.500 full-scale Positive full-scale 2.500 99.6 % of full-scale 2.492 …… …… 50.2 % of full-scale 1.504 49.8 % of full-scale 1.496 …… …… 0.4 % of full-scale 0.508 Negative full-scale 0.500 Less than negative