CXA3026

CXA3026Q 8-bit 120MSPS Flash A/D Converter Description The CXA3026Q is an 8-bit high-speed flash A/D converter capable of digitizing analog signals at the maximum rate of 120MSPS. ECL, PECL or TTL can be selected as the digital input level in accordance with the application. The TTL digital output level allows 1: 2 demultiplexed output. 48 pin QFP (Plastic) Features • Differential linearity error: ±0.5LSB or less Structure • Integral linearity error: ±0.5LSB or less Bipolar silicon monolithic IC • High-speed operation with a maximum conversion rate of 120MSPS Applications • Low input capacitance: 21pF • Magnetic recording (PRML) • Wide analog input bandwidth: 150MHz • Communications (QPSK, QAM) • Low power consumption: 760mW • LCDs • Low error rate • Digital oscilloscopes • Excellent temperature characteristics • 1: 2 demultiplexed output • 1/2 frequency divided clock output (with reset function) • Compatible with ECL, PECL and TTL digital input levels • Single +5V power supply operation available • Surface mounting package DVEE3 1 48 RESETN/E 47 RESET/E 46 RESETN/T 45 SELECT 44 INV 43 CLKOUT 42 DVCC2 41 DGND2 40 P1D7 39 P1D6 38 P1D5 37 P1D4 25 26 27 28 29 30 31 32 33 34 35 36 LEAD TREATMENT: PALLADIUM PLATING AGND AVCC AGND 3 AVCC VRM3 VRM2 VRM1 Pin Configuration (Top View) DGND3 12 11 10 CLK/E 13 CLKN/E 14 CLK/T 15 N.C. 16 N.C. 17 N.C. 18 DVCC2 19 DGND2 20 P2D0 21 P2D1 22 P2D2 23 P2D3 24 9 8 7 6 5 4 P2D4 DGND2 P1D1 VRB 2 VRT VIN P2D7 DVCC1 P1D0 P2D6 DGND1 P2D5 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– DVCC2 P1D2 P1D3 E94711D92 CXA3026Q Absolute Maximum Ratings (Ta = 25°C) • Unit Supply voltage AVCC, DVCC1, DVCC2 –0.5 to +7.0 V DGND3 –0.5 to +7.0 V DVEE3 –7.0 to +0.5 V DGND3 – DVEE3 –0.5 to +7.0 V VRT – 2.7 to AVCC V Analog input voltage VIN Reference input voltage VRT 2.7 to AVCC V VIN – 2.7 to AVCC V VRB |VRT – VRB| 2.5 V Digital input voltage ECL (∗∗∗/E∗1) DVEE3 to +0.5 V PECL (∗∗∗/E) –0.5 to DGND3 V TTL (∗∗∗/T, INV) –0.5 to DVCC1 V V other (SELECT) –0.5 to DVCC1 ∗2 (|∗∗∗/E – ∗∗∗N/E|) VID 2.7 V Storage temperature Tstg –65 to +150 °C Allowable power dissipation PD 2 W (when mounted on a glass fabric base epoxy board with 50mm x 50mm, 1.6mm thick) • • • • • Recommended Operating Conditions With a single power supply With dual power supplies Unit Min. Typ. Max. Min. Typ. Max. Supply voltage DVCC1, DVCC2, AVCC +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 V DGND1, DGND2, AGND –0.05 0 +0.05 –0.05 0 +0.05 V DGND3 +4.75 +5.0 +5.25 –0.05 0 +0.05 V –0.05 0 +0.05 –5.5 –5.0 –4.75 V DVEE3 Analog input voltage VIN VRB VRT VRB VRT V Reference input voltage VRT +2.9 +4.1 +2.9 +4.1 V VRB +1.4 +2.6 +1.4 +2.6 V |VRT – VRB| 1.5 2.1 1.5 2.1 V Digital input voltage ECL (∗∗∗/E) : VIH DGND3 – 1.05 DGND3 – 0.5 V : VIL DGND3 – 3.2 DGND3 – 1.4 V PECL (∗∗∗/E) : VIH DGND3 – 1.05 DGND3 – 0.5 V : VIL DGND3 – 3.2 DGND3 – 1.4 V TTL (∗∗∗/T, INV) : VIH 2.0 2.0 V : VIL 0.8 0.8 V other (SELECT) : VIH DVCC1 DVCC1 V : VIL DGND1 DGND1 V VID∗2 (|∗∗∗/E – ∗∗∗N/E|) 0.4 0.8 0.4 0.8 V Maximum conversion rate Fc (Straight mode) 100 100 MSPS (DMUX mode) 120 120 MSPS Ambient temperature Ta –20 +75 –20 +75 °C • • • • • • ∗1 ∗∗∗/E and ∗∗∗/T indicate CLK/E and CLK/T, etc. for the pin name. ∗2 VID: Input Voltage Differential ECL and PECL switching level DGND3 VIH (max.) VIL VTH (DGND3 – 1.2V) VID VIH VIL (min.) –2– CXA3026Q Block Diagram AVCC 5 VRT 11 r1 r/2 r 1 INV 44 DVCC1 30 DVCC2 19 31 42 DGND3 12 8 (MSB) 40 P1D7 39 P1D6 2 r r VRM3 9 r • • • 63 6bits 38 P1D5 LATCHA TTLOUT 8bits 37 P1D4 36 P1D3 35 P1D2 64 r 65 r r • • • 126 6bits 34 P1D1 6-bit LATCH + ENCODER 33 P1D0 (LSB) 8bits 127 VRM2 7 VIN 6 r 128 r 129 ENCODER (MSB) 28 P2D7 27 P2D6 26 P2D5 r VRM1 4 r • • • 191 6bits LATCHB TTLOUT 192 r 193 25 P2D4 24 P2D3 23 P2D2 22 P2D1 r r • • • 254 6bits 255 r2 VRB 2 CLK/T 15 CLK/E 13 CLKN/E 14 r/2 21 P2D0 (LSB) 16 Delay 17 18 N. C. D RESETN/T 46 RESETN/E 48 RESET/E 47 3 10 AGND Q Q Select 43 CLKOUT 45 29 20 32 41 DGND2 1 DVEE3 SELECT DGND1 –3– CXA3026Q Pin Description and I/O Pin Equivalent Circuit Pin No. 3, 10 Symbol AGND I/O Standard voltage level GND +5V (typ.) GND +5V (typ.) +5V (Typ.) (With a single power supply) GND (With dual power supplies) GND (With a single power supply) –5V (Typ.) (With dual power supplies) 16, 17 N.C. 18 13 CLK/E I Equivalent circuit Description Analog ground. Separated from the digital ground. Analog power supply. Separated from the digital power supply. Digital ground. Digital power supply. 5, 8 AVCC 20, 29 DGND1 32, 41 DGND2 19, 30 DVCC1 31, 42 DVCC2 12 DGND3 Digital power supply. Ground for ECL input. +5V for PECL and TTL input. 1 DVEE3 Digital power supply. –5V for ECL input. Ground for PECL and TTL input. No connected pin. Not connected with the internal circuits. Clock input. CLK/E complementary input. When left open, this pin goes to the threshold potential. Only CLK/E can be used for operation, but complementary input is recommended to attain fast and stable operation. Reset input. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. RESETN/E complementary input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. DGND3 14 CLKN/E I r 13 48 r ECL/ PECL 48 RESETN/E I 14 47 1.2V r r DVEE3 47 RESET/E I –4– CXA3026Q Pin No. Symbol I/O Standard voltage level Equivalent circuit DVCC1 r/2 Description 15 CLK/T I Clock input. TTL 15 46 r 1.5V 46 RESETN/T I DGND1 DVEE3 DVCC1 Reset input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. 44 INV I TTL 44 Data output polarity inversion input. When left open, this input goes to high level. (See Table 1. I/O Correspondence Table.) DGND1 DVEE3 DVCC1 45 SELECT Vcc or GND 45 Data output mode selection. (See Table 2. Operating Mode Table.) DGND1 DVEE3 11 VRT I 4.0V (typ.) r1 11 r/2 r Top reference voltage. By-pass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. Reference voltage mid point. By-pass to AGND with a 0.1µF chip capacitor. Reference voltage mid point. By-pass to AGND with a 0.1µF chip capacitor. Reference voltage mid point. By-pass to AGND with a 0.1µF chip capacitor. Bottom reference voltage. By-pass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. –5– 9 VRM3 VRB + 3 (VRT – VRB) 4 9 r r Comparator 1 Comparator 63 Comparator 64 7 VRM2 VRB + 2 (VRT – VRB) 4 7 r Comparator 127 Comparator 128 VRB + 4 VRM1 1 (VRT – VRB) 4 4 r Comparator 191 Comparator 192 r Comparator 255 r/2 2 r2 2 VRB I 2.0V (typ.) CXA3026Q Pin No. Symbol I/O Standard voltage level AVCC Equivalent circuit Comparator AVCC Description 6 VIN I VRT to VRB Analog input. 6 Vref DVEE3 AGND 33 to 40 21 to 28 P1D0 to P1D7 P2D0 to P2D7 O DVCC1 DVCC2 Port 1 side data output. O 21 to 28 TTL 100K 33 to 40 43 DGND2 DVEE3 Port 2 side data output. DGND1 43 CLKOUT O Clock output. (See Table 2. Operating Mode Table.) –6– CXA3026Q Electrical Characteristics (DVCC1, 2, AVCC, DGND3 = +5V, DGND1, 2, AGND, DVEE3 = 0V, VRT = 4V, VRB = 2V, Ta = 25°C) Item Resolution DC characteristics Integral linearity error Differential linearity error Analog input Analog input capacitance Analog input resistance Analog input current Reference input Reference resistance Reference current Offset voltage VRT side VRB side Digital input (ECL, PECL) Digital input voltage: High : Low Threshold voltage Digital input current : High : Low Digital input capacitance Digital input (TTL) Digital input voltage: High : Low Threshold voltage Digital input current : High : Low Digital input capacitance Digital output (TTL) Digital output voltage : High : Low Switching characteristics Maximum conversion rate Aperture jitter Sampling delay Clock high pulse width Clock low pulse width RESETN_CLK setup RESETN_CLK hold time CLKOUT output delay Data output delay Output rise time Output fall time EIL EDL CIN RIN IIN Rref∗3 Iref∗4 EOT EOB VIH VIL VTH IIH IIL Symbol Conditions Min. Typ. 8 ±0.5 ±0.5 21 4 0 75 9.7 2 2 DGND3 – 1.05 DGND3 – 3.2 DGND3 – 1.2 Max. Unit bits LSB LSB pF kΩ µA Ω mA mV mV V V V µA µA pF V V V µA µA pF V V MSPS ps ns ns ns ns ns ns ns ns ns ns VIN = 2Vp-p, Fc = 5MSPS VIN = +3.0V + 0.07Vrms 50 500 115 17.4 155 28 15 10 DGND3 – 0.5 DGND3 – 1.4 VIH = DGND3 – 0.8V VIL = DGND3 – 1.6V –50 –75 +50 0 5 VIH VIL VTH IIH IIL 2.0 0.8 1.5 VIH = 3.5V VIL = 0.2V –50 –500 0 0 5 VOH VOL Fc Taj Tds Tpw1 Tpw0 T_rs T_rh Td_clk Tdo1 Tdo2 Tr Tf IOH = –2mA IOL = 1mA DMUX mode 2.4 0.5 120 3 3.2 3.2 3.5 0 4.5 T∗5 6.5 10 4.5 6 CLK CLK RESETN – CLK RESETN – CLK DMUX mode 0.8 to 2.0V 0.8 to 2.0V (CL = 5pF) (CL = 5pF) (CL = 5pF) (CL = 5pF) (CL = 5pF) 7 T+1 8 2 2 8 T+2 10 ∗ These characteristics are for PECL input,unless otherwise specified. –7– CXA3026Q Item Dynamic characteristics Input bandwidth S/N ratio Symbol Conditions VIN = 2Vp-p, –3dB Fc = 120MSPS, fin = 1kHz Fs DMUX mode Fc = 120MSPS, fin = 29.999MHz Fs DMUX mode Fc = 120MSPS, fin = 1kHz Fs DMUX mode Error > 16LSB Fc = 120MSPS, fin = 29.999MHz Fs DMUX mode Error > 16LSB Fc = 100MSPS, fin = 24.999MHz Fs Straight mode Error > 16LSB Min. 150 Typ. Max. Unit MHz dB { { 46 40 dB TPS∗6 Error rate { { { ICC IEE Pd∗7 10–12 10–9 TPS 10–9 TPS Power supply Supply current Supply current Power consumption 125 0.4 660 145 0.6 760 185 0.8 960 mA mA mW ∗3 Rref: Resistance value between VRT and VRB ∗4 Iref = VRT – VRB Rref ∗5 T = 1 Fc ∗6 TPS: Times Per Sample 2 ∗7 Pd = (ICC + IEE) · VCC + (VRT – VRB) Rref INV VIN Step D7 VRT 255 254 . . . 128 127 . . . 1 0 11111 11111 . . . 10000 01111 . . . 00000 00000 1 D0 D7 111 110 000 111 001 000 00000 00000 . . . 01111 10000 . . . 11111 11111 0 D0 000 001 111 000 110 111 VRM2 VRB Table 1. I/O Correspondence Table –8– CXA3026Q Electrical Characteristics Measurement Circuit Current Consumption Measurement Circuit Sampling Delay Measurement Circuit Aperture Jitter Measurement Circuit 100MHz 5V Icc 4V VRT AVCC DVCC1 DVCC2 5V IEE DGND3 fr OSC1 φ: Variable Amp VIN CXA3026Q CLK 8 Logic Analizer 1024 samples 1.95V VIN CLK/E 5MHz PECL OSC2 2V VRB DGND2 DGND1 AGND ECL Buffer DVEE3 100MHz Integral Linearity Error Measurement Circuit Differential Linearity Error Measurement Circuit +V Aperture Jitter Measurement Method VRT VIN VRM2 VRB S1: ON when A < B S2: ON when A > B CLK ∆υ ∆t 129 128 127 126 125 S2 S1 –V AB Comparator VIN CXA3026Q 8 A8 to A1 A0 “0” DVM Controller B8 to B1 B0 “1” 000···00 to 111···10 8 Buffer CLK VIN σ (LSB) Sampling timing fluctuation (= aperture jitter) Where σ (LSB) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter Taj is: Taj = σ/ ∆υ ∆t = σ/ ( 256 × 2πf ) 2 Error Rate Measurement Circuit VIN 8 CXA3026Q CLK CLK Latch Signal Source A B + Latch Comparator A>B Pulse Counter Fc –1kHz 4 2Vp-p Sin Wave 16LSB Signal Source Fc 1/8 –9– CXA3026Q Description of Operating Modes The CXA3026Q has two types of operating modes which are selected with Pin 45 (SELECT). Operating mode DMUX mode Straight mode SELECT VCC GND Maximum conversion rate 120MSPS 100MSPS Data output Demultiplexed output 60Mbps Straight output 100Mbps Clock output The input clock is 1/2 frequency divided and output. 60MHz The input clock is inverted and output. 100MHz Table 2. Operating Mode Table 1. DMUX mode (See Application Circuit 1-(1), (2) and (3).) Set the SELECT pin to Vcc for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock. The 1/2 frequency divided clock, which has adequate setup time and hold time for the output data, is output from the CLKOUT pin. When resetting this 1/2 frequency divided clock, the low level of the RESET signal should be input to the RESETN pin (Pin 46or 48). The RESET signal requires the setup time (T_rs ≥ 3.5ns) and hold time (T_rh ≥ 0ns) to the clock rising edge because it is synchronized with and taken in the clock. Therefore, set the RESET signal to low for T_rs (min.) + T_rh (min.) = 3.5ns or longer to the clock rising edge. The reset period can be extended by making the low level period of the RESET signal longer because the clock output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start timing is regarded as not important, the timing where the RESET signal is set from high to low is not so consequence. However, when the reset is released this timing must become significant because the timing is used to commence the 1/2 frequency divided clock. In this case, the setup time (T_rs) is also necessary. See the timing chart for detail. (This chart shows the example of reset for 2T.) The A/D converter can operate at FC (min.) = 120MSPS in this mode. – 10 – CXA3026Q When the RESET signal is not used. CLK CXA3026Q CLK CLK CLKOUT 8bits DATA AA RESETN CXA3026Q CLK CLKOUT 8bits DATA BB RESETN When the RESET signal is used. CLK RESET signal CXA3026Q CLK CLK RESETN CLKOUT 8bits DATA (Reset period) A CXA3026Q CLK CLKOUT 8bits DATA (Reset period) B RESET signal RESETN 2. Straight mode (See Application Circuits 1-(4), (5) and (6).) Set the SELECT pin to GND for this mode. In this mode, data output can be obtained in accordance with the clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter as the system clock. The A/D converter can operate at Fc (min.) = 100MSPS in this mode. Digital input level and supply voltage settings The logic input level for the CXA3026Q supports ECL, PECL and TTL levels. The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and RESET signals) level. Digital input level ECL PECL TTL DVEE3 –5V 0V 0V DGND3 0V +5V +5V Supply voltage Application circuits ±5V +5V +5V (1) (4) (2) (5) (3) (6) Table 3. Logic Input Level and Power Supply Settings – 11 – CXA3026Q Application Circuit 1 (1) DMUX ECL input +5V(D) DG ECL RESET signal +5V(A) –5V(D) AG AG AG 48 47 46 45 44 43 42 41 40 39 38 37 1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 P2D0 to P2D7 8-bit Digital Data Latch 2 3 4 5 6 7 8 9 P1D0 to P1D7 8-bit Digital Data Latch 8-bit Digital Data 2V DG DG +5V(D) +5V(A) DG AG AG 10 4V 11 12 8-bit Digital Data ECL-CLK DG +5V(D) (2) DMUX PECL input +5V(D) DG PECL RESET signal +5V(A) AG AG DG AG 48 47 46 45 44 43 42 41 40 39 38 37 1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 10 P1D0 to P1D7 8-bit Digital Data Latch 8-bit Digital Data 2V DG DG +5V(D) +5V(D) AG AG +5V(A) 4V 11 12 8-bit Digital Data P2D0 to P2D7 8-bit Digital Data Latch PECL-CLK DG +5V(D) (3) DMUX TTL input +5V(D) DG TTL RESET signal AG AG DG 48 47 46 45 44 43 42 41 40 39 38 37 1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 10 P1D0 to P1D7 8-bit Digital Data Latch 8-bit Digital Data +5V(A) AG 2V DG DG +5V(D) +5V(D) +5V(A) AG AG 4V 11 12 8-bit Digital Data P2D0 to P2D7 8-bit Digital Data Latch TTL-CLK DG +5V(D) – 12 – CXA3026Q (4) Straight ECL input DG +5V(D) DG –5V(D) AG AG 48 47 46 45 44 43 42 41 40 39 38 37 1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 P1D0 to P1D7 8-bit Digital Data Latch 8-bit Digital Data +5V(A) AG 2V DG DG +5V(D) +5V(A) DG AG AG 10 4V 11 12 ECL-CLK ECL → TTL DG +5V(D) (5) Straight PECL input DG +5V(D) DG +5V(A) AG AG DG AG 48 47 46 45 44 43 42 41 40 39 38 37 1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 10 P1D0 to P1D7 8-bit Digital Data Latch 8-bit Digital Data 2V DG DG +5V(D) +5V(D) AG AG +5V(A) 4V 11 12 PECL-CLK PECL → TTL DG +5V(D) (6) Straight TTL input DG +5V(D) DG +5V(A) AG AG DG AG 48 47 46 45 44 43 42 41 40 39 38 37 1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 10 P1D0 to P1D7 8-bit Digital Data Latch 8-bit Digital Data 2V DG DG +5V(D) +5V(D) AG AG +5V(A) 4V 11 12 TTL-CLK DG +5V(D) – 13 – CXA3026Q Application Circuit 2 Straight Mode TTL I/O (When a single power supply is used) AG Analog input 4V AG +5V (D) DG 1µF AG 10µF short short 10µF +5V (A) AG 2V 1µF AG 12 11 10 9 8 7 6 5 4 3 2 1 DGND3 AGND 13 CLK/E RESETN/E 48 RESET/E 47 RESETN/T 46 SELECT 45 INV 44 CLKOUT 43 DVCC2 42 DGND2 41 P1D7 40 P1D6 39 P1D5 38 14 CLKN/E 15 CLK/T TTL CLK 16 N.C. 17 N.C. 18 N.C. 19 DVCC2 20 DGND2 21 P2D0 22 P2D1 23 P2D2 DGND1 DGND2 DVCC1 DVCC2 24 P2D3 DVEE3 P1D4 37 36 VRT AGND VRM3 AVCC VRM2 VIN AVCC VRM1 P1D0 P1D1 VRB 35 P2D4 P2D5 P2D6 P2D7 25 26 27 28 29 30 31 32 33 34 P2D5 P1D2 P1D3 P2D2 P2D3 P1D1 P1D2 (MSB) P2D7 P2D6 P1D3 P1D4 P1D5 Short the analog system and digital system at one point immediately under the A/D converter. See the Notes on Operation. is the chip capacitor of 0.1µF. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 14 – P1D6 (MSB) P1D7 (LSB) P2D0 P2D1 (LSB) P1D0 P2D4 CXA3026Q DMUX Mode Timing Chart (Select = VCC) Tds N–1 VIN N+3 N T N+1 CLK Tpw1 Tpw0 Tdo2; 8ns (typ.) 6.5ns (min.) 10ns (max.) 2.0V 0.8V N+4 4.5ns (typ.) N+5 N+6 N+7 N+2 P1D0 to D7 N+1 N+3 P2D0 to D7 N Tdo1 T + 1ns (typ.) 2.0V 0.8V N+2 ≈T Td_clk; 7ns (typ.) 8ns (max.) 4.5ns (min.) 2.0V CLK OUT (Reset period) 0.8V 4.5ns (min.) 8ns (max.) T_rh T_rs T_rh T_rs Td_clk 2.0V 0.8V ≈T 2.0V 0.8V RESET signal – 15 – CXA3026Q Straight Mode Timing Chart (Select = GND) N–1 VIN Tds 4.5ns (typ.) T N N+1 N+2 N+3 CLK Tpw1 Tpw0 Tdo2; 8ns (typ.) 6.5ns (min.) 10ns (max.) 2.0V 0.8V P1D0 to D7 N–4 N–3 N–2 N–1 N P2D0 to D7 N–5 2.0V 0.8V N–4 N–3 N–2 N–1 Td_clk; 7ns (typ.) 4.5ns (min.) 8ns (max.) CLK OUT (CLK is inverted and output.) 2.0V 0.8V RESET signal – 16 – CXA3026Q Timing of A/D Converter and Peripheral Circuit In the maximum clock rate of the DEMUX Mode, the timing of 3 channels of ADC CLK OUT in same phase is described in detail as below. For example, the CLK OUT from one of the ADC is used as the data latch clock. The clock delay and data delay are showed in the following specification, i.e. Td_clk 4.5ns (min.) to 8.0ns (max.) Tdo2 6.5ns (min.) to 10ns (max.) These values are considered in all the temperature change and power supply variation. When the maximum clock rate 120MSPS is used, the set-up time (ts) is seemed to be very small from above specifications. But the 3 channels of ADC are in the same circuit board, so that the DATA OUT delay and CLK OUT delay will be changed in same trend at the same condition of the temperature change and power supply variation. As a result, 0.5ns of the delay will be faster, when the highest temperature and highest power supply is used. Also, 0.5ns of the delay will be later, when the lowest temperature and lowest power supply is used. These delay can be omitted in this case. When Ta = 25°C, VCC = +5V, the clock delay and data delay are Td_clk 5.0ns (min.) to 7.5ns (max.) Tdo2 7.0ns (min.) to 9.5ns (max.) The timing of the DATA OUT and CLK OUT with above delay variation is showed in below. Consequently, the set-up time for the data latching can be obtained as ts (min.) = 3.5ns. The output delay change of the DATA OUT and CLK OUT due to the temperature change and the power supply variation should have the same trend of the delay change, the minimum ts = 3.5ns can be guaranteed at any temperature change and power supply variation. Analog input R CXA3026Q Vin P1D/out CLK P2D/out RESET CLK OUT CXA3026Q Vin P1D/out CLK P2D/out RESET CLK OUT CXA3026Q Vin P1D/out CLK P2D/out RESET CLK OUT 8ns ( = 1/120MSPS) 8bit 8bit Gate Array Latch Analog input G 8bit 8bit Analog input B CLK RESET 8bit 8bit CLK th-reset RESET signal Td_clk (min.) 5.0ns Td_clk (max.) 7.5ns Tdo2 (min.) 7.0ns Tdo2 (min.) 9.5ns ts (min.) 3.5ns th (min.) 7.5ns CLK OUT P1D/out P2D/out 16ns Note: In the timing chart, the values in the brackets < > are included all the temperature change and the power supply variation. – 17 – CXA3026Q Notes on Operation • The CXA3026Q is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation. General points for caution are as follows. — The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. — To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc and DVcc lines at one point each via a ferrite-bead filter Shorting the AGND and DGND patterns in one place immediately under the A/D converter improves A/D converter performance. — Ground the power supply pins (AVcc, DVcc1, DVcc2, DVEE3) as close to each pin as possible with a 0.1µF or larger ceramic chip capacitor. (Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DVEE3 pins to the DGND pattern.) — The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. • The analog input pin VIN has an input capacitance of approximately 21pF. To drive the A/D converter with proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit. keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. • The VRT and VRB pins must have adequate by-pass to protect them from high-frequency noise. By-pass them to AGND with approximately 1µF tantal capacitor and, 0.1µF chip capacitor as short as possible. • If the CLK/E pin is not used, by-pass this pin to DGND with an approximately 0.1µF capacitor. At this time, approximately DGND3 – 1.2V voltage is generated. However, this is not recommended for use as threshold voltage VBB as it is too weak. • When the digital input level is ECL or PECL level, ∗∗∗/E pins should be used and ∗∗∗/T pins left open. When the digital input level is TTL, ∗∗∗/T pins should be used and ∗∗∗/E pins left open. – 18 – CXA3026Q Example of Representative Characteristics Current consumption vs. Ambient temperature characteristics 170 Current consumption vs. Conversion rate characteristics response 170 Current consumption [mA] 160 Current consumption [mA] 160 fCLK – 1kHz 4 150 150 fin = DMUX mode CL = 5pF 140 140 130 –25 25 Ta – Ambient temperature [°C] 75 130 0 60 Fc – Conversion rate [MSPS] 120 Analog input current vs. Analog input voltage characteristics 20 200 Reference current vs. Ambient temperature characteristics Analog input current [µA] VRT = 4V VRB = 2V Reference current [mA] 3 4 15 100 10 0 2 –25 25 Ta – Ambient temperature [°C] 75 Analog input voltage [V] – 19 – CXA3026Q SNR vs. Input frequency response 50 Error rate vs. Conversion rate characteristics 10–6 fCLK – 1kHz 4 40 10–7 fin = Error Rate [TPS] Error > 16LSB 10–8 SNR [dB] 30 Fc = 120MSPS 10–9 20 1 3 5 10 30 50 10–10 120 140 Fc – Conversion rate [MSPS] 160 Input frequency [MHz] Maximum conversion rate vs. Ambient temperature characteristics Fc – Maximum conversion rate [MSPS] 170 fCLK – 1kHz 4 Error > 16LSB Error rate: 10–9 TPS fin = 160 150 140 130 –25 25 Ta – Ambient temperature [°C] 75 – 20 – CXA3026Q CXA3026Q Evaluation Board Description The CXA3026Q Evaluation Board is a special board designed to maximize and facilitate the evaluation performance of the CXA3026Q. After latching the CXA3026Q output data with a frequency divided clock, the analog signal can be regenerated by a 10-bit high-speed D/A converter. The latched data can also be extracted externally via a 24-pin cable connector. Features • Resolution: • Maximum conversion rate: • Supply voltage: • Dual analog input pins: 8 bits 120MSPS (min.) ±5.0V DIR.IN: AC coupling input pin AMP.IN: Operational amplifier input pin • Clock frequency division: 1/1 to 1/16 Absolute Maximum Ratings • Supply voltage VCC VEE +AMP –AMP –0.5 to +7.0 –7.0 to +0.5 –0.5 to +7.0 –7.0 to +0.5 V V V V Min. +4.75 –5.50 +3 –7 9 –0.75 1.5 0.8 Typ. +5.0 0 –5.0 +5 –5 10 0 2.0 1.0 Max. +5.25 –4.75 +7 –3 11 +1.05 2.2 1.2 Recommended Operating Conditions • Supply voltage VCC GND VEE +AMP –AMP | (+AMP) – (–AMP) | • Analog input AMP. IN DIR. IN • Clock input CLK. IN V V V V V V V Vp-p Vp-p – 21 – Block Diagram VRB. R1 OFFSET. R3 NORM INV SW1 SW2 SW3 D/A OUT (–1.0V) VRT. R2 SELECT DMUX Straight A/D INV D/A INV FULL SCALE. R4 FULL SCALE. R5 Vrb Vrt OFFSET D/A OUT (–1.0V) CON2 DIR IN 8 Vrt P1D0 to D7 A VIN CXA3026Q Vrb VRB CLK (PECL) (TTL) CLKOUT 8 B S1 P2D0 to D7 8 (TTL) VRT (TTL) (TTL) 8 8 (ECL) LATCH AGND 270Ω TTL/ECL AGND DAC 51Ω CON4 P1 side OUT AGND CON1 130Ω AMP IN 82Ω CON3 CLK IN VBB TTL/ECL 1kΩ 390Ω LATCH (ECL) DAC Counter PECL/TTL – AMP + AMP VEE GND VCC CON7 P1 side DATA CON8 P2 side DATA CON6 TTL/ECL – 22 – 4 (PECL) (TTL) S2 4 (TTL) AGND × (–2) AGND AGND 8 CON5 P2 side OUT AGND 51Ω 0.1µF DGND DGND 1kΩ (ECL) CXA3026Q CXA3026Q Pin Description and I/O Level Pin No. CON1 CON2 Symbol AMP. IN DIR. IN I/O I I Standard I/O level 0.95Vp-p 2.0Vp-p Current Description Doubles the analog input signal amplitude using the operational amplifier. The input impedance is 50Ω. AC coupling input. Suitable for sine waves and other repeating waveforms. The input impedance is 50Ω. The CXA3026Q operates at the PECL level clock using the sine wave-to-PECL conversion circuit. The input impedance is 50Ω. Allows the D/A converted waveform of the CXA3026Q port 1 side data to be observed. The output impedance is 50Ω. Allows the D/A converted waveform of the CXA3026Q port 2 side data to be observed. The output impedance is 50Ω. 0.8A The inside of the board is divided into analog and digital systems. –0.6A 40mA –40mA + side power supply for the operation amplifier. – side power supply for the operation amplifier. The CXA3026Q port 1 side data output is latched at the frequency divided clock and then output. The CXA3026Q port 2 side data output is latched at the frequency divided clock and then output. CON3 CLK. IN I 1.0Vp-p CON4 P1 side OUT O 0 to –1V CON5 P2 side OUT VCC GND O I I I I I O O 0 to –1V +5.0V 0V –5.0V +5.0V –5.0V TTL TTL CON6 VEE +AMP –AMP CON7 CON8 P1 side DATA P2 side DATA Board Adjustments and Settings 1. VRB.R1: CXA3026Q VRB voltage adjusting volume. 2. 3. 4. 5. 6. VRT.R2: OFFSET.R3: FULL SCALE.R4: FULL SCALE.R5: S1: CXA3026Q VRT voltage adjusting volume. Adjusting volume for matching the AMP.IN input and DIR.IN input signal ranges to the CXA3026Q input range. Full-scale adjusting volume for the port 1 D/A output. (–1V: Typ.) Full-scale adjusting volume for the port 2 D/A output. (–1V: Typ.) Switching junction for the dual analog input pins. Set as follows according to the input pins used. Junction Symbol AMP.IN DIR.IN 7. S2: A OPEN 0.1µF B SHORT 10kΩ 8. SW1 SELECT: 9. SW2 A/D INV: 10. SW3 D/A INV: Setting junction for the clock frequency division ratio. The operating speed after latching is determined by the frequency division ratio set here. When set to CLK OUT, it operates according to the CXA3026Q clock output. CXA3026Q output mode selector switch. CXA3026Q output polarity inversion switch. D/A converter output polarity inversion switch. – 23 – CXA3026Q Notes on Board Operation 1. The factory settings for the CXA3026Q Evaluation Board are as follows. VRB.R1 = 1.5V VRT.R2 = 3.0V OFFSET.R3 = 2.25V FULL SCALE.R4 = –1V FULL SCALE.R5 = –1V S1 A ... OPEN, B ... SHORT S2 8 ... SHORT (1/8 frequency division) When using the board in this condition, the input signals should be input at the amplitudes shown below. (The frequency is set as desired.) Analog input signal: CON1 (AMP.IN) 0V center, 800mVp-p or less Clock input signal: CON3 (CLK.IN) 0V center, 1.0Vp-p 2. When the analog signal is input from the CON1 (AMP.IN) pin, IC2:CLC404 limits the input dynamic range of the A/D converter's analog input signal according to the +AMP and –AMP supply voltages. The power supply for the operational amplifier can also be shifted to +AMP = +7.0V and –AMP = –3.0V to allow use with a wider input dynamic range. When the analog input signal is a sine wave or other repeating waveform, the signal can be input from the CON2 (DIR.IN) pin with AC coupling. In these cases, the input dynamic range is not limited by the +AMP and –AMP supply voltages, but the VRT level may be limited by IC3:NJM3403A. Therefore, the power supply for the operational amplifier should be shifted in the same manner as in 2. above. 3. 4. In the evaluation board of the CXA3026Q, CLC404 (Comlinear) is employed for IC2 to drive the analog input signal. Though, CLC505 (Comlinear) can also be used instead of CLC404, there should be a little change in the peripheral circuit in this case. – 24 – CXA3026Q CXA3026Q Evaluation Board Timing Chart N N+1 CON2 DIR IN 2Vp-p 0V N+3 N+2 CON3 CLK IN 1Vp-p 0V CXA3026Q CLK (PECL) CXA3026Q P1 side DATA N–4 (TTL) Approximately 6.0ns N–3 N–2 N–1 CON7 P1 side DATA CLK (TTL) Approximately 9.0ns CON7 P1 side DATA DATA N–6 (TTL) N–4 N–2 N–6 CON4 P1 side OUT (Analog regeneration waveform) 0 to –1V N–4 N–2 Operating Conditions CXA3026Q operating mode : Straight mode : DIR IN pin input Analog input : 1/2 frequency divided clock S2 setting – 25 – CXA3026Q Circuit Diagram CON6 –AMP +AMP VEE GND VCC L1 C1 33µF C2 33µF C3 33µF L2 C4 33µF L3 L4 C5 33µF L5 L6 C6 33µF –AMP +AMP AVEE DVEE AGND DGND AVCC DVCC DGND SW3 D/A INV SW2 A/D INV SW1 DVCC SELECT DVCC DGND C29 0.1µF D/A INV CLKOUT C28 0.1µF AGND –AMP AGND –AMP C7 1µF AGND C16 0.1µF C8 1µF C17 0.1µF P1D7 P1D6 P1D5 P1D4 P1D3 CLKOUT SELECT RESETN/T RESET/E DGND RESETN/E DGND2 DVCC2 P1D7 P1D6 P1D5 P1D4 INV R7 510 R1 2k D1 TL431CP R8 510 R2 1k R3 10k R9 7.5k 2 3 11 R12 390k 1 4 IC3A NJM3403A 48 47 46 45 44 43 42 41 40 39 38 37 IC3B NJM3403A 6 7 5 AGND CON2 DIR IN AGND R18 51 A B R17 43 S1 AVCC AGND C22 0.1µF C12 1µF C21 0.1µF DVCC C27 0.1µF DGND C24 0.1µF C26 0.1µF C11 1µF AGND C20 0.1µF C23 C25 0.1µF 0.1µF P1D2 P1D1 P1D0 R10 22k R11 200k AGND 1 DVEE3 2 VRB 3 AGND 4 VRM1 5 AVCC 6 VIN 7 VRM2 8 AVCC 9 VRM3 10 AGND 11 VRT 12 DGND3 CLKN/E DGND2 IC1 CXA3026Q P1D3 36 P1D2 35 P1D1 34 P1D0 33 DGND2 32 DVCC2 31 DVCC1 30 DGND1 29 P2D7 28 P2D6 27 P2D5 26 P2D4 25 P2D7 P2D0 P2D1 P2D2 P2D3 P2D6 P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 C34 0.1µF C33 0.1µF DGND DVCC DGND R6 51 AVCC CON1 AMP IN R13 82 AGND AGND R14 130 R15 270 2 3 AGND R16 4 270 6 IC2 7 CLC404 IC3C NJM3403A 10 8 9 C9 1µF AGND C18 0.1µF +AMP C10 1µF AGND C19 0.1µF +AMP CLK/E 13 14 15 16 17 18 19 20 21 22 23 24 C30 0.1µF DVCC R28 R29 82 82 CON3 CLK IN DGND C15 0.1µ R19 51 DGND IC4B 10H116 (PECL) 10 9 R20 1k 11 DGND DVCC 9 S1 7 S2 IC5 10H136 (PECL) 12 D0 11 D1 6 D2 5 D3 Q3 3 Q2 2 Q1 15 Q0 14 R21 390 R22 1k 7 6 R24 130 R23 82 IC4A 10H116 (PECL) 5 4 3 2 IC4C 10H116 (PECL) 13 12 15 14 R30 82 DVCC R27 130 DGND R25 R26 130 130 DVCC2 CLK/T N.C. N.C. N.C. DGND 13 CLK Cout 4 IC4D 10H116 (PECL) 1/16 1/8 1/4 1/2 CLK CLKN – 26 – CXA3026Q DGND DVcc 1 C35 0.1µF P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 IC14 74ALS34 1 2 DGND 1 OC 11 CLK P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 2 1D 3 2D 4 3D 5 4D 6 5D 7 6D 8 7D 9 8D IC6 74AS574 1Q 19 2Q 18 3Q 17 4Q 16 5Q 15 6Q 14 7Q 13 8Q 12 P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 16 S DVEE 11 IN8 12 IN7 13 IN6 14 IN5 17 IN4 18 IN3 19 IN2 20 IN1 IC9 MB767 OUT8 10 OUT7 9 OUT6 8 OUT5 7 OUT4 4 OUT3 3 OUT2 2 OUT1 1 1 MSB 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 DVEE C44 0.1µF R48 620 R37 82 DGND C45 0.1µF 1 OC 11 CLK P2D7 P2D6 P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 2 1D 3 2D 4 3D 5 4D 6 5D 7 6D 8 7D 9 8D IC7 74AS574 1Q 19 2Q 18 3Q 17 4Q 16 5Q 15 6Q 14 7Q 13 8Q 12 P2D7 P2D6 P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 16 S DVEE 11 IN8 12 IN7 13 IN6 14 IN5 17 IN4 18 IN3 19 IN2 20 IN1 IC10 MB767 OUT8 10 OUT7 9 OUT6 8 OUT5 7 OUT4 4 OUT3 3 OUT2 2 OUT1 1 R38 82 R49 620 10 LSB 11 NC 12 NC 13 CLKN 14 CLK IC12 CX20201-1 AGND 28 VREF 27 AVEE 26 NC 25 NC 24 NC 23 NC 22 NC 21 OUT 20 NC 19 AGND 18 DGND 17 INV 16 DVEE 15 C53 0.1µF DVEE AGND DGND AGND CON4 P1 side OUT C52 0.1µF D2 TL431CP C13 1µF AVEE C51 0.1µF R4 R42 2k 1k R43 270 IC14 74ALS34 3 4 5 9 11 13 1 3 5 6 8 10 12 2 4 6 CON7 P1 side DATA 2 IC15 74ALS34 DGND 25 26 DGND C43 0.1µF R47 620 AGND DGND R39 130 R40 130 DVEE 1 MSB 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 10 LSB IC13 CX20201-1 AGND 28 VREF 27 AVEE 26 NC 25 NC 24 NC 23 NC 22 NC 21 OUT 20 NC 19 AGND 18 DGND 17 INV 16 DVEE 15 C56 0.1µF DVEE AGND DGND AGND CON5 P2 side OUT C55 0.1µF D3 TL431CP C14 1µF AVEE C54 0.1µF AGND R5 R44 2k 1k R45 270 D/A INV CLKOUT DVEE C46 0.1µF DGND DGND R46 620 19 OE 17 VBB CLKOUT 24 D0 1 D0N 23 D1 22 D1N 21 D2 20 D2N 16 D3 15 D3N 14 D4 13 D4N 12 D5 11 D5N Q5 10 S2 C39 0.1µF Q4 9 1/1 DVCC 1 2 IC8 100390 Q2 4 1/4 Q3 8 1/2 11 A4 10 A3 Q1 3 1/8 7 A2 Q0 2 1/16 5 A1 IC11 10H124 6B Y1 2 Y1 4 Y2 1 Y2 3 Y3 15 Y3 12 Y4 14 Y4 13 R50 620 11 NC 12 NC 13 CLKN 14 CLK DGND 1/16 1/8 C50 0.1µF DGND R41 620 DVEE 1/4 1/2 CLK CLKN DVCC R31 82 R32 82 C32 0.1µF R33 82 R34 130 R35 130 R36 130 DGND P2D7 P2D6 P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 IC15 74ALS34 8 9 11 13 1 3 5 9 11 10 12 2 4 6 8 10 CON8 P2 side DATA DGND IC16 74ALS34 25 26 DGND – 27 – CXA3026Q Component List No. Product name IC1 CXA3026Q IC2 CLC404AJE IC3 NJM3403AM IC4 MC10H116L IC5 MC10H136L IC6, 7 74AS574N IC8 100390 IC9, 10 MB767P IC11 MC10H124L IC12, 13 CXA20201A-1 IC14 to 16 74ALS34 D1 to 3 TL431CP SW1 to 3 ATE1D-2F3-10 S1, 2 JX-1 CON1 to 5 01K0315 CON6 TJ-563 CON7, 8 (FAP-2601-1202) L1 to 6 ZBF503D-00 C1 to 6 Tantal capacitor C7 to 12 Tantal capacitor C15 Ceramic capacitor All parts other than those listed above Chip capacitor Function 8-bit A/D converter OP-AMP OP-AMP ECL Buffer ECL Countor TTL Latch PECL → TTL conversion TTL → ECL conversion TTL → ECL conversion 10-bit D/A converter TTL Buffer Shunt regulator Toggle switch Short pin BNC connector Power supply connector Flat cable connector Ferrite-bead filter 33µF 1µF 0.1µF 0.1µF No. R2 R1, 4, 5 R3 R46 to 50 R6, 18, 19 R7.8 R9 R10 R11 R12 R13, 23, 28 to 33, 37, 38 R14, 24 to 27, 34 to 36, 39, 40 R15, 16, 43, 45 R17 R20, 22, 42, 44 R21 R41 Product name RJ-5W-1K RJ-5W-2K RJ-5W-10K RGLD4X621J FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) FRD-25SR (0.25W) Function 1kΩ volume resistor 2kΩ volume resistor 10kΩ volume resistor 620Ω network resistor 51Ω 510Ω 7.5kΩ 22kΩ 200kΩ 390kΩ 82Ω 130Ω 270Ω 43Ω 1kΩ 390Ω 620Ω ∗ CON7 and 8 are not mounted when boards are shipped. (Manufacturer: YAMAICHI Electronics Co., Ltd.) CXA3026Q/AQ CXA3026Q/AQ EVALUATION BOARD Component side silk diagram – 28 – 74ALS34 74ALS34 74ALS34 CXA3026Q Component side pattern diagram Solder side pattern diagram – 29 – CXA3026Q Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.4 12.0 – 0.1 + 0.1 0.15 – 0.05 36 25 0.15 37 24 48 13 + 0.2 0.1 – 0.1 1 + 0.15 0.3 – 0.1 12 0.8 ± 0.12 M + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 ∗QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 30 – 0.9 ± 0.2 13.5