CXA3106AQ

CXA3106AQ PLL IC for LCD Monitor/Projector Description The CXA3106AQ is a PLL IC for LCD monitors/ projectors with built-in phase detector, charge pump, VCO and counter. The various internal settings are performed by serial data via a 3-line bus. Applicable LCD monitor/projector resolution are NTSC, PAL, VGA, SVGA, XGA, and SXGA etc. Features • Supply voltage: 5V ± 10% single power supply • Package: 48-pin QFP • Power consumption: 350mW • Sync input frequency: 10 to 100kHz • Clock output signal frequency: 10 to 160MHz • Clock delay: 1/16 to 20/16 CLK • Sync delay: 1/16 to 20/16 CLK • I/O level: TTL, PECL (complementary) • Low clock jitter • 1/2 clock output 48 pin QFP (Plastic) Functions • Phase detector enable • UNLOCK output • Output TTL disable function • Power save function (2 steps) Applications • CRT displays • LCD projectors • LCD monitors • Multi-media PECLVCC TTLGND PECLVCC DSYNCH DSYNCL Pin Configuration (Top View) CLK/2H 36 35 34 33 32 31 30 29 28 27 26 25 IOGND CLKH TTLVCC CLKL VBB CLK/2L IOGND 37 IOVCC 38 PLLVCC 39 PLLGND 40 VCOVCC 41 VCOGND 42 VCOHGND 43 IREF 44 RC2 45 RC1 46 IRGND 47 IRVCC 48 24 DSYNC 23 CLK 22 CLKN 21 CLK/2 20 CLK/2N 19 DGND 18 DVCC 17 UNLOCK 16 DIVOUT 15 SEROUT 14 CS 13 TLOAD 1 2 3 4 5 6 7 8 9 10 11 12 VCOH SYNCH SYNCL IOGND IOVCC SYNC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– SENABLE SDATA HOLD VCOL SCLK VCO E97812A03 CXA3106AQ Absolute Maximum Ratings (Ta = 25°C) • Supply voltage IOVCC, DVCC, TTLVCC, PECLVCC, PLLVCC, VCOVCC, IRVCC, –0.5 to +7.0 IOGND, DGND, TTLGND, VCOHGND, PLLGND, VCOGND, IRGND –0.5 to +0.5 Input voltage VCOH, VCOL, SYNCH, SYNCL, VCO, HOLD, SYNC, SENABLE, SCLK, SDATA, TLOAD, CS IOGND – 0.5 to IOVCC + 0.5 RC2 IRGND – 0.5 to IRVCC + 0.5 Output current SEROUT, DIVOUT, UNLOCK, CLK/2N, CLK/2, CLKN, CLK, DSYNC, CLK/2L, CLK/2H, CLKL, CLKH, DSYNCH, DSYNCL, VBB –30 to +30 IREF, RC1 –2 to +2 Storage temperature Tstg –65 to +150 Operating ambient temperature Ta –25 to +75 Allowable power dissipation 750 PD V V V V • • • • • mA mA °C °C mW Recommended Operating Conditions Min. IOVCC, DVCC, TTLVCC, PECLVCC, PLLVCC, VCOVCC, IRVCC IOGND, DGND, TTLGND, VCOHGND, PLLGND, VCOGND, IRGND • Digital input DIN (PECL) ∗1 H level DIN (PECL) ∗1 L level DIN (TTL) ∗2 H level DIN (TTL) ∗2 L level • SYNC, SYNCH, SYNCL input jitter • Operating temperature Ta ∗1 VCOH, VCOL, SYNCH, SYNCL ∗2 VCO, HOLD, SYNC, SENABLE, SCLK, SDATA, TLOAD, CS • Supply voltage 4.75 –0.05 IOVCC – 1.1 2.0 0.8 1.0 –20 +75 Typ. 5.00 0 Max. 5.25 0.05 IOVCC – 1.5 V V V V V ns °C –2– Block Diagram RC1 on/off 1 to 4 CLK TTLOUT Polarity 1bit on/off PECLOUT 1bit TTLOUT on/off 1/16 to 20/16 CLK Phase Detector VCO 1bit 2bit on/off 1bit TTLOUT on/off RESET 1/2 PECLOUT 1bit TTLOUT CLK/2 (TTL) MUX DIV1, 2, 4 PECLOUT 2bit 1bit 1/256 to 1/4096 CLK Programmable Counter 12bit 5bit Charge Pump Fine Delay 1bit TTLOUT NCLK (TTL) CLK (TTL) Latch 2bit Coarse Delay 1bit RC2 VCO (TTL) TTLIN DSYNC (TTL) DSYNC (PECL) VCO (PECL) logic PECLIN SYNC (TTL) TTLIN Polarity SYNC (PECL) PECLIN 1bit CLK (PECL) –3– on/off 1bit TTLIN 1bit on/off read out TTLOUT TTLOUT synthesizer power save 1bit SEROUT DIVOUT TLOAD HOLD (TTL) TTLIN NCLK/2 (TTL) CLK/2 (PECL) on/off 1bit unlock detect whole chip power save PECL UNLOCK DAC CONTROL REGISTER VBB IREF CS CXA3106AQ SENABLE SCLK SDATA CXA3106AQ Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol IOVCC IOGND VCOH VCOL VCO HOLD SYNCH SYNCL SYNC SENABLE SCLK SDATA TLOAD CS SEROUT DIVOUT UNLOCK DVCC DGND CLK/2N CLK/2 CLKN CLK DSYNC TTLGND TTLVCC IOGND PECLVCC CLK/2L CLK/2H CLKL CLKH DSYNCL DSYNCH VBB PECLVCC IOGND IOVCC PLLVCC PLLGND VCOVCC VCOGND VCOHGND IREF RC2 RC1 IRGND IRVCC Description Digital power supply Digital GND External VCO input External inverted VCO input External VCO input Phase detector disable signal input Sync input Inverted sync input Sync input Control signal (enable) Control signal (clock) Control signal (data) Programmable counter test input Chip select Register read output Programmable counter test output Unlock signal output Digital power supply Digital GND Inverted 1/2 clock output 1/2 clock output Inverted clock output Clock output Delay sync signal output TTL output GND TTL output power supply Digital GND PECL output power supply Inverted 1/2 clock output 1/2 clock output Inverted clock output Clock output Delay sync signal output Inverted delay sync signal output PECL reference voltage PECL output power supply Digital GND Digital power supply PLL circuit analog power supply PLL circuit analog GND VCO circuit analog power supply VCO circuit analog GND VCO SUB analog GND Charge pump current preparation External pin for LPF External pin for LPF IREF analog GND IREF analog power supply –4– Reference voltage level 5V 0V PECL PECL TTL TTL PECL PECL TTL TTL TTL TTL TTL TTL TTL TTL TTL 5V 0V TTL TTL TTL TTL TTL 0V 5V 0V 5V PECL PECL PECL PECL PECL PECL PECLVCC – 1.3V 5V 0V 5V 5V 0V 5V 0V 0V 1.3V 1.7 to 4.4V 2.1V 0V 5V CXA3106AQ Pin Description and I/O Pin Equivalent Circuit Pin No. Symbol I/O Reference voltage level Equivalent circuit Description Digital power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. Digital GND. Digital power supply. Digital GND. TTL output GND. TTL output power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. Digital GND. PECL output power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. PECL output power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. Digital GND. Digital power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. PLL circuit analog power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. PLL circuit analog GND. VCO circuit analog power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. VCO circuit analog GND. VCO SUB analog GND. IREF analog GND. IREF analog power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. 1 IOVCC — 5V 2 18 19 25 IOGND DVCC DGND TTLGND — — — — 0V 5V 0V 0V 26 TTLVCC — 5V 27 IOGND — 0V 28 PECLVCC — 5V 36 PECLVCC — 5V 37 IOGND — 0V 38 IOVCC — 5V 39 PLLVCC — 5V 40 PLLGND — 0V 41 VCOVCC — 5V 42 43 47 VCOGND — 0V 0V 0V VCOHGND — IRGND — 48 IRVCC — 5V –5– CXA3106AQ Pin No. Symbol I/O Reference voltage level Equivalent circuit Description External VCO input. Programmable counter test input (switchable by a control register). When using the VCO PECL input, open the Pin 5 VCO TTL input. External inverted VCO input. When open, this pin goes to the PECL threshold voltage (IOVcc – 1.3V). Only the pin 3 VCOH input with VCOL input open can be also operated but complementary input is recommended in order to realize stable high-speed operation. Sync input. When using the SYNCH PECL input, open the Pin 9 SYNC TTL input. The sync signal can be switched between positive/negative polarity by an internal register. 3 VCOH I PECL IOVCC 4 VCOL I PECL r 3 4 7 8 r 7 SYNCH I PECL IOGND 8 SYNCL I PECL Inverted sync input. When open, this pin goes to the PECL threshold voltage (IOVcc – 1.3V). Only the Pin 7 SYNCH input with SYNCL input open can be also operated but complementary input is recommended in order to realize stable high-speed operation. –6– CXA3106AQ Pin No. Symbol I/O Reference voltage level Equivalent circuit Description External VCO input. Programmable counter test input (controlled by a control register). When using the VCO TTL input, open the Pin 3 VCOH and Pin 4 VCOL PECL inputs. Phase detector disable signal. Active high. When this pin is high, the phase detector output is held. This pin goes to high level when open. (See the HOLD Timing Chart.) Sync input. When using the SYNC TTL input, open the Pin 7 SYNCH and Pin 8 SYNCL PECL inputs. The sync signal can be switched between positive/negative polarity by a control register. Control signal (enable) for setting the internal registers. When SENABLE is low, registers can be written; when high, registers can be read. (See the Control Register Table and Control Timing Chart.) Control signal (clock) for setting the internal registers. When SENABLE is low, SDATA is loaded to the registers at the rising edge of SCLK. When SENABLE is high, the register contents are output from SEROUT at the falling edge of SCLK. (See the Control Register Table and Control Timing Chart.) Control signal (data) for setting the internal registers. (See the Control Register Table and Control Timing Chart.) Programmable counter test input. This pin is normally open status and high. Register contents can be loaded immediately to Programmable counter by setting TLOAD low during the programmable counter test mode. 5 VCO I TTL 6 HOLD I TTL 9 SYNC I TTL IOVCC r/2 r 5 10 10 SENABLE I TTL 6 11 9 12 13 IOGND 1.5V 2r 11 SCLK I TTL 12 SDATA I TTL 13 TLOAD I TTL –7– CXA3106AQ Pin No. Symbol I/O Reference voltage level Equivalent circuit Description IOVCC 14 CS I TTL 14 Chip select. When low, all circuits including the register circuit are set to the power save mode. When high, all circuits are set to operating mode. IOGND 15 SEROUT O TTL Register read output. When SENABLE is high, the register contents are output from SEROUT at the falling edge of SCLK. (See the Control Register Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. Programmable counter test output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. IOVCC TTLVCC 16 DIVOUT O TTL 20 CLK/2N O TTL 100k 15 22 16 23 20 24 Inverted 1/2 clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. 1/2 clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. Inverted clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. Clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. Delay sync signal output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) and switched between positive/negative polarity by a control register. 21 CLK/2 O TTL IOGND 21 TTLGND 22 CLKN O TTL 23 CLK O TTL 24 DSYNC O TTL –8– CXA3106AQ Pin No. Symbol I/O Reference voltage level Equivalent circuit Description TTLVCC 17 UNLOCK O TTL 17 IOGND TTLGND Unlock signal output. This pin is an open collector output, and pulls in the current when a phase difference occurs. The UNLOCK sensitivity can be adjusted by connecting a capacitor and resistors to this output as appropriate. (See the UNLOCK Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register. Inverted 1/2 clock output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor. 1/2 clock output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor. Inverted clock output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor. Clock output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor. Delay sync signal output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor. Inverted delay sync signal output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor. 29 CLK/2L O PECL 30 CLK/2H O PECL IOVCC PECLVCC 31 CLKL O PECL 30 32 34 29 31 33 32 CLKH O PECL IOGND 33 DSYNCL O PECL 34 DSYNCH O PECL –9– CXA3106AQ Pin No. Symbol I/O Reference voltage level Equivalent circuit Description PECLVCC 35 VBB O PECLVCC –1.3V IOGND 35 PECL reference voltage. When used, ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. IRVCC 44 IREF O 1.3V 44 IRGND IOGND Charge pump current preparation. Connect to GND via an external resistor (1.6kΩ). Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. 45 RC2 O 1.7 to 4.4V IRVCC VCOVCC 46 45 External pin for LPF. See the Recommended Operating Circuit for the external circuits. Note that external resistors and capacitors should be metal film resistors and temperature compensation capacitors which are relatively unaffected by temperature change. External pin for LPF. See the Recommended Operating Circuit for the external circuits. VCOGND IRGND 100 46 RC1 O 2.1V IOGND – 10 – Control Register Table DATA DAT6 DATA3 DATA1 7 VCO DIV Bit 1 0 0 11 VCO DIV Bit 9 0 18 N/A∗1 25 FINE DELAY Bit 1 28 C.Pump Bit 1 35 CLK Enable NCLK Enable 38 DIVOUT Enable 39 Read out power 36 DSYNC POL 40 Synth power N/A∗1 26 FINE DELAY Bit 0 29 C.Pump Bit 0 37 SYNC POL 41 VCO By-pass∗2 1 1 1 CXA3106AQ ADDRESS DATA2 DATA0 ADDR2 MSB ADDR1 8 VCO DIV Bit 0 12 VCO DIV Bit 8 19 0 1 1 1 0 1 6 VCO DIV Bit 2 10 VCO DIV Bit 10 17 N/A∗1 24 FINE DELAY Bit 2 27 PD POL ADDR0 LSB Register No. 2 5 VCO DIV Bit 3 9 VCO DIV Bit 11 13 16 N/A∗1 23 FINE DELAY Bit 3 DIV 1, 2, 4 DIV 1, 2, 4 Bit 0 Bit 1 N/A∗1 22 FINE DELAY Bit 4 20 COARSE COARSE DELAY DELAY Bit 0 Bit 1 21 14 15 VCO DIV Bit 6 VCO DIV Bit 5 VCO DIV Bit 4 3 4 Register Name DATA7 MSB DATA5 DATA4 register read no 1 Register 1 DIVREG1 VCO DIV Bit 7 register read no Register 2 DIVREG2 register read no Register 3 CENFREREG – 11 – 31 33 CLK/2 Enable 34 DSYNC Enable NCLK/2 Enable 32 register read no Register 4 DELAYREG 1 0 0 register read no Register 5 CPREG 1 0 1 register read no 30 Register 6 TTLPOLREG UNLOCK Enable 1 1 0 register read no Register 7 TESTPOWREG ∗1 Register read no. 15 to 19 are N/A. ∗2 VCO By-pass at register read no. 41 is a MUX control bit in Block Diagram. CXA3106AQ Electrical Characteristics Item Symbol Conditions Min. (Ta = 25°C, VCC = 5V, GND = 0V) Typ. Max. Unit Current consumption (excluding output current) Current consumption 1 Current consumption 2 Current consumption 3 Digital input Digital high level input voltage (PECL) Digital low level input voltage (PECL) VCOL, SYNCL input open voltage (PECL) Digital high level input current (PECL) Digital low level input current (PECL) Digital high level input voltage (TTL) Digital low level input voltage (TTL) Digital high level input current (TTL) Digital low level input current (TTL) HOLD characteristics RC1 input pin leak current HOLD signal set-up time HOLD signal hold time Digital output Digital high level output voltage (PECL) Digital low level output voltage (PECL) PECL output reference voltage Digital high level output voltage (TTL) Digital low level output voltage (TTL) VOH1 VOL1 VBB VOH2 VOL2 RL = 330Ω RL = 330Ω RL = 330Ω CL = 10pF CL = 10pF 2.7 0.5 PECLVCC –1.3 PECLVCC –1.1 PECLVCC –1.6 V V V V V Ileak Ths Thh 20 20 1.0 nA ns ns VIH1 VIL1 VIO IIH1 IIL1 VIH2 VIL2 IIH2 IIL2 VIH = 2.7V VIL = 0.5V –200 –500 VIH = IOVCC – 0.8V VIL = IOVCC – 1.6V –100 –200 2.0 0.8 –20 –100 IOVCC –1.3 100 0 IOVCC –1.15 IOVCC –1.5 V V V µA µA V V µA µA ICC1 ICC2 ICC3 CS = H, Synth Power = 1 CS = H, Synth Power = 0 CS = L 40 5 3 70 19 14 105 38 24 mA mA mA – 12 – CXA3106AQ Item UNLOCK output UNLOCK output current SYNC input Symbol Conditions Min. Typ. Max. Unit Iunlock –30 mA SYNC input frequency range Fin DSYNC output DSYNC output variable coarse delay time setting resolution DSYNC output variable coarse delay time DSYNC output variable fine delay time setting resolution DSYNC output variable fine delay time VCO characteristics DIV output frequency operation range 1 DIV output frequency operation range 2 DIV output frequency operation range 3 VCO lock range VCO gain 1 VCO gain 2 VCO gain 3 Charge pump current 1 Charge pump current 2 Charge pump current 3 VCO counter bits FVCO1 FVCO2 FVCO3 Vlock KVCO1 KVCO2 KVCO3 Kpd1 Kpd2 Kpd3 Rdiv2 DIV = 1/1 DIV = 1/2 DIV = 1/4 C.Pump Bit = 00, IREF = 1.6kΩ C.Pump Bit = 10, IREF = 1.6kΩ C.Pump Bit = 11, IREF = 1.6kΩ DIV = 1/1 DIV = 1/2 DIV = 1/4 Rdsync1 10 100 kHz 2 bit Td1 1 4 CLK Rdsync2 5 bit Td2 1/16 20/16 CLK 40 20 10 1.7 240 120 60 80 350 1350 400 200 100 100 400 1600 12 160 80 40 4.4 640 320 160 130 500 1800 MHz MHz MHz V Mrad/sv Mrad/sv Mrad/sv µA µA µA bit – 13 – CXA3106AQ Item CLK (CLK, CLK/2) output CLK output (PECL) frequency range 1 CLK output (PECL) frequency range 2 CLK output (PECL) frequency range 3 Symbol Conditions Min. Typ. Max. Unit Fclk1PECL DIV = 1/1 Fclk2PECL DIV = 1/2 Fclk3PECL DIV = 1/4 10% to 90%, RL = 330Ω 10% to 90%, RL = 330Ω DIV = 1/1 DIV = 1/2 DIV = 1/4 10% to 90%, CL = 10pF 10% to 90%, CL = 10pF CL = 10pF 40 20 10 1.0 1.0 40 20 10 2.0 2.0 40 3.0 3.0 50 1.5 1.5 160 80 40 2.0 2.0 80 80 40 4.0 4.0 60 MHz MHz MHz ns ns MHz MHz MHz ns ns % CLK, CLK/2 output (PECL) TrPECL rise time CLK, CLK/2 output (PECL) TfPECL fall time CLK output (TTL) frequency range 1 CLK output (TTL) frequency range 2 CLK output (TTL) frequency range 3 CLK, CLK/2 output (TTL) rise time CLK, CLK/2 output (TTL) fall time CLK output (PECL, TTL) duty SYNC input (PECL) and CLK output (PECL) delay offset CLK output (PECL) and DSYNC output (PECL) phase difference CLK output (PECL) and CLK/2 output (PECL) phase difference CLK output (PECL) and DIVOUT output (TTL) rise phase difference CLK output (PECL) and DIVOUT output (TTL) fall phase difference Fclk1TTL Fclk2TTL Fclk3TTL TrTTL TfTTL Dclk2 Td3 CL = 10pF 1 ns Td4 CL = 10pF 1.5 2.4 3.0 ns Td5 CL = 10pF 0.0 0.8 1.0 ns Td6 CL = 10pF 10 14 19 ns Td7 CL = 10pF 8 11 14 ns DSYNC, CLK, CLK/2 PECL output and TTL output Td8 phase difference CL = 10pF 1.5 3.0 4.5 ns – 14 – CXA3106AQ Item CLK (CLK, CLK/2) output Symbol Conditions Min. Typ. Max. Unit CLK vs. SYNC output jitter (NTSC) Tj1p-p triggered at SYNC Fsync = 15.73kHz (Crystal) Fclk = 12.27MHz N = 780 triggered at SYNC Fsync = 31.47kHz (Crystal) Fclk = 25.18MHz N = 800 triggered at SYNC Fsync = 48.08kHz (Crystal) Fclk = 50.00MHz N = 1040 triggered at SYNC Fsync = 56.48kHz (Crystal) Fclk = 75.00MHz N = 1328 triggered at SYNC Fsync = 80kHz (Crystal) Fclk = 136.00MHz N = 1700 triggered at DSYNC 3.0 5.0 8.0 ns CLK vs. SYNC output jitter (VGA) Tj2p-p 1.0 2.0 3.0 ns CLK vs. SYNC output jitter (SVGA) Tj3p-p 0.9 1.6 2.5 ns CLK vs. SYNC output jitter (XGA) Tj4p-p 0.8 1.5 2.0 ns CLK vs. SYNC output jitter (SXGA) Tj5p-p 0.6 1.0 1.4 ns CLK vs. DSYNC output jitter Tj6p-p Control registers SCLK frequency SENABLE setup time SENABLE hold time SDATA setup time SDATA hold time SENABLE setup time SENABLE hold time SCLK TENS TENH TDS TDH TNENS TNENH 0.1 ns in write/read mode in write mode in write mode in write mode in read mode in read mode in read mode 3 0 3 0 3 0 12 MHz ns ns ns ns ns ns – 15 – CXA3106AQ Description of Block Diagram Sync Input Sync signals in the range of 10 to 100kHz can be input. Input supports both positive and negative polarity. PECL input can also be a single input. When SYNC is positive polarity, the clock is regenerated in synchronization with the rising edge of the sync signal. When SYNC is negative polarity, the clock is regenerated in synchronization with the falling edge of the sync signal. VCO oscillation stops when there is no sync input. Register: SYNC POL SYNC input polarity 1 Positive 0 Negative Phase Detector The phase detector operates at the sync input frequency of 10 to 100kHz. The PD input polarity should be set to the default PD POL = 1. Phase comparison is performed at the edges. The input circuit of the phase detector does not contain a hysteresis circuit, so the waveform must be shaped at the front end of the CXA3106AQ when inputting a noisy signal. The phase detector HOLD signal is supplied by TTL. (See the HOLD Timing Chart.) The PLL UNLOCK signal is output by an open collector. (See the UNLOCK Timing Chart.) Charge Pump The gain (I, I/4, I/16) can be varied by changing the charge pump current using 2 bits of control register. Register: C.Pump bit 1 Register: C.Pump bit 0 Charge pump current 0 0 100µA 1 0 400µA 1 1 1600µA LPF This is a loop filter comprised of the external capacitors and resistor. Be sure to use metal film resistors with little temperature variation and a temperature-compensated capacitor. In particular, the 0.33µF capacitor should be equivalent to high dielectric constant series capacitor type B or better. (electrostatic capacitance change ratio ±10%: T = –25 to +85°C) VCO The VCO oscillator frequency covers from 40 to 160MHz. VCO Rear-end Counter The VCO output is frequency divided to 1/1, 1/2 or 1/4 by switching 2 bits of control register. The operating range can be expanded to 10 to 160MHz by combining the counter with a VCO frequency divider. Register: DIV 1, 2, 4 bit 1 Register: DIV 1, 2, 4 bit 0 Counter frequency divisions 0 0 1/1 1 0 1/2 1 1 1/4 – 16 – CXA3106AQ Feedback Programmable Counter This counter can be set as desired from 256 to 4096 using 12 bits. Frequency divisions = (m + 1) × 8 + n, n: 3 bits (VCO DIV bits 0 to 2), m: 9 bits (VCO DIV bits 3 to 11) When the register value is changed, the new setting is actually loaded to the counter when the counter value becomes "all 0". Clock Output When SYNC input is positive polarity, the clock is regenerated in synchronization with the rising edge of the sync signal. The clock output delay time can be changed in the range of 1/16 to 20/16 CLK using 5 bits of control register. (See the I/O Timing Chart.) Output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock TTL output can also be turned off independently. Register: Clock Enable Clock output status 1 ON 0 OFF 1/2 Clock Output Reset is performed at the delay sync timing and the clock output is frequency divided by 1/2. (See the I/O Timing Chart.) Both odd and even output are TTL and PECL output. TTL output can also be turned off independently. Register: Clock Enable Clock output status 1 ON 0 OFF Delay Sync Output The front edge of the delay sync pulse is latched by the pulse obtained by frequency dividing the CLK regenerated by the PLL, so there is almost no jitter with respect to CLK. This front edge can be used as the reset signal for the system timing circuit. The rear edge of the delay sync pulse is latched by the CLK regenerated by the PLL. This relationship is undefined for one clock as shown in the Timing Chart. The delay sync output delay time can be varied in two stages. First, the delay time can be varied in the range of 1/16 to 20/16 CLK using 5 bits of control register, and then in the range of 1 to 4 CLK using 2 bits of control register. In other words, the total delay time is ((1/16 to 20/16) + (1 to 4)) CLK. (See the I/O Timing Chart.) DSYNC output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock TTL output can also be turned off. Register: Clock Enable Clock output status Lower delay line FINE DELAY bits 0 to 4 Delay time Upper delay line COARSE DELAY bits 0 to 1 Delay time Register: DSYNC POL DSYNC output polarity 1 ON 0 OFF 00000 1/16CLK 00001 2/16CLK ············ ············ 10011 20/16CLK 00 1CLK 1 Positive 01 2CLK 0 Negative – 17 – 10 3CLK 11 4CLK CXA3106AQ Control Circuit (3-bit address, 8-bit data) The timing and input methods are described hereafter. Feedback programmable counter control VCO rear-end counter control Fine delay line control Coarse delay line control Charge pump current DAC control Phase detector input positive/negative polarity control Sync input positive/negative polarity control Delay sync output positive/negative polarity control Clock TTL output OFF function Inverted clock TTL output OFF function 1/2 clock TTL output OFF function Inverted 1/2 clock TTL output OFF function Delay sync TTL output OFF function UNLOCK output OFF function Programmable counter input switching Power save with register contents held Register read function power ON/OFF Programmable counter TTL output OFF function REGISTER1, 2 REGISTER3 REGISTER4 REGISTER4 REGISTER5 REGISTER5 REGISTER6 REGISTER6 REGISTER6 REGISTER6 REGISTER6 REGISTER6 REGISTER6 REGISTER6 REGISTER7 REGISTER7 REGISTER7 REGISTER7 12bit 2bit 5bit 2bit 2bit 1bit 1bit 1bit 1bit 1bit 1bit 1bit 1bit 1bit 1bit 1bit 1bit 1bit VCO DIV Bit0 to 11 DIV1, 2, 4 Bit0, Bit1 FINE DELAY Bit0 to 4 COARSE DELAY Bit0, Bit1 C.Pump Bit0, Bit1 PD POL SYNC POL DSYNC POL CLK Enable NCLK Enable CLK/2 Enable NCLK/2 Enable DSYNC Enable UNLOCK Enable VCO By-pass Synth power Read out power DIVOUT Enable Power Save The CXA3106Q realizes 2-step power saving (all OFF, control registers only ON). This is controlled by a control register and the chip selector. Step 1: Chip selector control CS Power save status H Power ON L All OFF Step 2: Control register control Register: Synth power Power save status 1 Power ON 0 Control registers only ON Readout Circuit (during test mode) The control register contents can be read by serial data from SEROUT. (See the Control Register Timing Chart.) Register: Read out power Readout status 0 1 Function OFF Function ON – 18 – CXA3106AQ Programmable Counter Output (during test mode) The programmable counter output is TTL output from the DIVOUT pin. (See the I/O Timing Chart.) This output is normally not used. Register: DIVOUT Enable DIVOUT output status 0 OFF 1 ON TLOAD input (during test mode) This control signal forcibly loads the control register contents to the programmable counter. This signal is normally not used. TLOAD H L Forced load control status Function OFF Function ON VCO input (during test mode) This is the programmable counter test signal input pin. This pin can be switched internally by the MUX circuit. TTL and PECL input are possible. This pin is normally not used. Register: VCO By-pass Input status 1 0 Internal VCO External input – 19 – CXA3106AQ Control Register Timing 1) Write mode Many CXA3106AQ functions can be controlled via a program. Characteristics are changed by setting the internal control register values via a serial interface comprised of three pins: SENABLE (Pin 10), SCLK (Pin 11) and SDATA (Pin 12). The write timing diagram is shown below. Input the 8-bit data and 3-bit register address MSB first to the SDATA pin. Some registers are not 8 bits, but the data is input aligned with the LSB side in these cases. (See the Register Table.) SENABLE is the enable signal and is active low. SCLK is the transfer clock signal, and data is loaded to the IC at the rising edge. When SENABLE rises, SCLK must be high. (Registers are set at the rising edge of SENABLE.) When SENABLE falls, SCLK may be either high or low. SENABLE SDATA 8bit DATA 3bit ADDRESS SCLK Enlarged Enlarged TENS SENABLE TENH SDATA SCLK TDS TDH For example, when inputting a 16-bit signal, the initial 5 bits are invalid and the latter 11 bits are valid. This is to say that the latter 11 bits are loaded to the register. SENABLE 5bit Invalid DATA 8bit DATA 3bit address SDATA SCLK – 20 – CXA3106AQ The settings of the frequency divider (2 bits, DIV1, 2, 4) and programmable counter (12 bits, VCODIV) at the rear end of the VCO are transferred in the order shown below. (The data will be set when the three registers are transferred.) First DIVREG2, CENFREREG and DIVREG1 are set, and then the data is transferred independently at the timings shown below. DIVREG2 (upper 4 bits of VCODIV) ↓ CENFREREG (2 bits of DIV1, 2, 4) ↓ DIVREG1 (lower 8 bits of VCODIV) All three of the above registers must be changed even when changing only DIV1, 2, 4 (2 bits). This is the same when changing only VCODIV (12 bits). SENABLE SDATA SCLK DIVREG2 CENFREREG DIVREG1 – 21 – CXA3106AQ 2) Read mode Data can be transferred from the shift register to the data register only when SENABLE is high. Binary data can be read from the data register by inputting SCLK when SENABLE is high. Data is loaded from the data register to the SCAN PATH circuit each time one clock is input to SCLK, and is output sequentially from the register read no. 1 data (VCODIV bit 7) through the SEROUT pin. When the 41st SCLK clock pulse is input, the register read no. 41 data (VCO By-pass) is output. Then, when the 42nd clock pulse is input to SCLK, the output returns to the register read no. 1 data (VCODIV bit 7) and the data output is repeated. Also, the data output from the SCAN PATH circuit is automatically reloaded even when the shift register data is changed during data output. Note) Since all registers do not have 8 bits, only the valid bits of each register are loaded to the SCAN PATH circuit. (See the Control Register Table for the actual register read no.) SCLK CLK I/P SHIFT REGISTER, 11 BITS NEN 8 BIT DATA 3 BIT ADDRESS SENABLE TR 7 DATA REGISTERS (41 LATCHES). REGISTERS ARE DIFFERENT LENGTHS UP TO 8 BIT EN CLK SCAN PATH, 1 ELEMENT PER REGISTER BIT SEROUT Block Diagram during Read Mode TNENS SENA TNENH SEROUT READ NO. 1 READ NO. 2 READ NO. N SCLK 1 2 N Timing Chart during Read Mode – 22 – Timing Charts 1. I/O timing Td3 (typ. 1ns) 0 1 2 3 4CLK SYNC input (positive polarity) (PECL) 1CLK CLK output (PECL) 1/16CLK to 20/16CLK Td2 8CLK Td7 (typ. 11ns) – 23 – Td4 (typ. 2.4ns) 1CLK Td5 (typ. 0.8ns) DIVOUT output (TTL) Td6 (typ. 14ns) (1 to 4) CLK DSYNC output (positive polarity) (PECL) Td1 RESET (internal signal) CLK/2 output (PECL) CXA3106AQ CXA3106AQ 2. HOLD timing SYNC input (SYNC POL = 1) SYNC input (SYNC POL = 0) DIVOUT output (TTL) Thh HOLD input (TTL) Ths Thold The phase comparison output is held and fixed VCO output frequency is output. Thh Ths CLK output HOLD signal set-up time (Ths) is a time from the rising edge of HOLD signal to the falling edge of DICOUT. Or, when SYNC POL = 1, it is a time from the falling edge of HOLD signal to the rising edge of SYNC; when SYNC POL = 0, it is the time from the falling edge of HOLD signal to the falling edge of SYNC. HOLD signal hold time (Thh) is the time from the falling edge of DIVOUT to falling edge of HOLD signal. Or, when SYNC POL = 1, it is the time from the rising edge of SYNC to the rising edge of HOLD signal; when SYNC POL = 0, it is the time from the falling edge of SYNC to the rising edge of HOLD signal. When the HOLD input is held, the CLK frequency fluctuation can be calculated as follows. ∆V –Q C Ileak SW I VCO ∆f I SW +Q C · ∆V = Q = Ileak · Thold C: ∆V: Ileak: Thold: Loop filter capacitance Voltage variation due to leak current Internal amplifier leak current Hold time ∆V = Ileak · Thold/C ∆f = ∆V · KVCO = Ileak · Thold/C · KVCO For example, assuming f = 100MHz, Ileak = 1nA, Thold = 1ms, C = 0.33µF, and KVCO = 2π · 65MHz, then: ∆V = 1 × 10–9 · 1 × 10–3/(0.33 × 10–6) = 3 × 10–6 [V] ∆f = 1 × 10–9 · 1 × 10–3/(0.33 × 10–6) · 65 × 106 = 197 [Hz] – 24 – CXA3106AQ 3. Relationship between SYNC input and DSYNC output during HOLD SYNC internal signal DIVOUTN internal signal J K Q Q DSYNC internal signal CK CLK When the above SYNC internal and DIVOUTN internal signals are input, the DSYNC internal signal is output as shown the table below. First, when SYNC = L and DIVOUTN = L, it does not stand up because the output of Q = DSYNC = L and Q = DSYNC = H∗∗ (unchanged with the previous data) is exclusive logic. And, Q = DSYNC = H∗∗ is the impossible output. Therefore, it is as follows. 1. DSYNC = L when SYNC = L and DIVOUTN = L. 2. DSYNC = H∗ or L∗ (unchanged with the previous data) when SYNC = H and DIVOUTN = L. 3. DSYNC = H when DIVOUTN = H (SYNC = H or L) SYNC L L H H DIVOUTN L H L H J L H L L L L K L L H L L H Q L ∗∗ H L L∗ H∗ L Q H ∗∗ L H H∗ L∗ H DSYNC H ∗∗ L H H∗ L∗ H (∗) and (∗∗) are unchanged with the previous data. – 25 – CXA3106AQ The polarity of SYNC internal signal and DSYNC internal signal has a relationship between the setting of the respective SYNC POL and DSYNC POL. The below diagrams are the examples that show the relationship between SYNC input and DSYNC output and between the SYNC POL and DSYNC POL during HOLD. CASE1 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC Thh HOLD input Ths Thh Ths SYNC Input SYNC internal signal (SYNC POL = 1) DIVOUTN internal signal 8CLK 8CLK 8CLK 8CLK 8CLK 8CLK DSYNC internal signal DSYNC output (DSYNC POL = 1) 8CLK 8CLK CASE2 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC Thh HOLD input Ths Thh Ths SYNC Input SYNC internal signal (SYNC POL = 0) DIVOUTN internal signal 8CLK 8CLK 8CLK 8CLK 8CLK 8CLK DSYNC internal signal DSYNC output (DSYNC POL = 0) – 26 – CXA3106AQ CASE3 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC Thh HOLD input Ths SYNC Input Ths Thh SYNC internal signal (SYNC POL = 1) DIVOUTN internal signal 8CLK 8CLK 8CLK 8CLK 8CLK 8CLK DSYNC internal signal DSYNC output (DSYNC POL = 1) CASE4 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC Thh HOLD input Ths Thh Ths SYNC Input SYNC internal signal (SYNC POL = 0) DIVOUTN internal signal 8CLK 8CLK 8CLK 8CLK 8CLK 8CLK DSYNC internal signal DSYNC output (DSYNC POL = 0) – 27 – CXA3106AQ CASE5 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC Thh HOLD input Ths Thh Ths SYNC Input SYNC internal signal (SYNC POL = 1) DIVOUTN internal signal 8CLK 8CLK 8CLK 8CLK 8CLK 8CLK DSYNC internal signal DSYNC output (DSYNC POL = 1) CASE6 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC 1/fSYNC Thh HOLD input Ths Thh Ths SYNC Input SYNC internal signal (SYNC POL = 0) DIVOUTN internal signal 8CLK 8CLK 8CLK 8CLK 8CLK 8CLK DSYNC internal signal DSYNC output (DSYNC POL = 0) – 28 – CXA3106AQ 4. UNLOCK timing Inside the IC Outside the IC VCC I2 R1 Signal from phase comparator unlock detect S1 I1 S2 C R2 UNLOCK The unlock detect output is an open collector. When unlock detect output S1 goes high, the current I1 is pulled in. The UNLOCK sensitivity can be adjusted by connecting external resistors (R1, R2) and a capacitor (C) to this output pin as appropriate and changing these values. Operation during three modes is described below. CASE 1: When there is no phase difference, that is to say, when the PLL is locked. The S1 signal is low and the S2 signal is high. The UNLOCK output remains low. S1 S2 threshold level UNLOCK CASE 2: When there is a phase difference, that is to say, when the S1 signal goes high and low as shown in the figure below, the fall slew rate of the S2 signal is determined by the current I1 flowing into that open collector. Therefore, increasing the resistance R1 causes the S2 signal fall slew rate to become slower. Also, since the S2 signal rise slew rate is determined by the current I2, reducing the resistance R2 causes the S2 signal rise slew rate to become faster. If this integrated S2 signal does not fall below the threshold level of the next inverter, the UNLOCK signal stays low, and the PLL is said to be locked. S1 S2 threshold level UNLOCK CASE 3: However, even if a phase difference exists as shown above, if the resistance R1 is reduced, the current I1 flowing into the open collector increases, and the S2 signal fall slew rate becomes faster. Also, if the resistance R2 is increased, the S2 signal rise slew rate becomes slower. If this integrated S2 signal falls below the threshold level of the next inverter, the UNLOCK signal goes from low to high, and the PLL is said to be unlocked. S1 S2 threshold level UNLOCK – 29 – CXA3106AQ Charge Pump and Loop Filter Settings The CXA3106Q's charge pump is a constant-current output type as shown below. VCC S1 To LPF S2 When a constant-current output charge pump circuit is used inside the PLL, the phase detector output acts as a current source, and the dimension of its transmittance KPD is A/rad. Also, when considering the VCO input as a voltage, the LPF transmittance dimension must be expressed in ohms (Ω = V/A). Therefore, the PLL transmittance when a constant-current output charge pump circuit is used is as follows. PD ωr 1/S θr + – θo N KPD (A/rad) LPF F (S) (Ω) VCO KVCO (rad/sV) ω0 counter 1/N 1/S ω0/N The PLL closed loop transmittance is obtained by the following formula. θo/N θr = KPD · F (S) · KVCO · 1/N · 1/S ... (1) 1 + KPD · F (S) · KVCO · 1/N · 1/S Here, KPD, F (S), and KVCO are: KPD: Phase comparator gain F (S): Loop filter transmittance KVCO: VCO gain (A/rad) (Ω) (rad/sV) ∗1 The reason for the 1/S inside the phase detector is as follows. t θo (t)/N = ∫ o ω0 (t)/Ndt + θo (t = 0)/N ... (a) θo (t = 0) = 0 t θo (t)/N = ∫ o ω0 (t)/Ndt ... (b) Performing Laplace conversion: θo (S)/N = 1 W0 (S)/N ... (c) S – 30 – CXA3106AQ The loop filter F (S) is described below. The loop filter smoothes the output pulse from the phase comparator and inputs it as the DC component to the VCO. In addition to this, however, the loop filter also plays an important element in determining the PLL response characteristics. Typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. However, the CXA3106AQ's LPF is a current input type active filter as shown below, so the following calculations show an actual example of deriving the PLL closed loop transmittance when using this type of filter and then using this transmittance to create a formula for setting the filter constants. Current input type active filter C ii –A –Vo –1 Vo R The filter transmittance is as follows. VO 1 + VO = (R + ) A SC 1 + SRC A · SC 1+A 1 + Sτ A · SC 1+A The Bode diagram for formula (2) is as follows. log scale gain [dB] F (S) = 1 τ log w = ∴τ = RC 0 log w Here, assuming A > 1, then: F (S) = 1 + Sτ ........................... (2) SC phase [deg] –45deg –90 Next, substituting (2) into (1) and obtaining the overall closed loop transmittance for the PLL: KPD · KVCO · τ NC = S2 + ·S+ KPD · KVCO NC θo/N θr KPD · KVCO · τ NC ... (3) KPD · KVCO ·S+ NC = S2 2ζωnS + ωn2 + 2ζωnS + ωn2 ............................................ (4) ωn = √ KPD · KVCO ...................................................... (5) NC 1 2 ζ= ωnτ ................................................................. (6) – 31 – CXA3106AQ Here, ωn and ζ are as follows. ωn characteristic angular frequency: The oscillatory angular frequency when PLL oscillation is assumed to have been maintained by the loop filter and individual loop gains is called the characteristic angular frequency: ωn. ζ damping factor: This is the PLL transient response characteristic, and serves as a measure of the PLL stability. It is determined by the loop gain and the loop filter. A capacitor C2 is added to the actual loop filter. This added capacitor C2 is used to reduce the R noise, and a value of about 1/10 to 1/1000 of C1 should be selected as necessary. Current input type active filter with added capacitor C2 C2 C1 ii –A R –1 –Vo Vo The filter transmittance is as follows. F (S) = 1 + C1 · R · S S ((C1 + C2) + C1 · C2 · R · S) The Bode diagram for formula (7) is as follows. log scale gain [dB] = 1 + τ1 · S .................. (7) S (C1 + C2) (1 + τ2 · S) 1 τ1 1 τ2 τ1 = C1 · R τ2 = C1 · C2 · R C1 + C2 0 log w log w phase [deg] –45deg Here, assuming C2 = C1/100, then: τ2 = C1 · C1/100 · R C1 + C1/100 1 C1 · R 101 1 τ1 101 –90 = = – 32 – CXA3106AQ Next, the various parameters inside an actual CXA3106AQ are obtained. The CXA3106AQ's charge pump output block and the LPF circuit are as follows. C2 R1 C1 46 VCC 100µA or 400µA or 1600µA 100k To VCO S1 45 CXA3106Q 100µA or 400µA or 1600µA S2 20k 100 First, KPD is as follows. KPD = 100µ/2π or 400µ/2π or 1600µ/2 π (A/rad) Typical KVCO characteristics curves for the CXA3106Q's internal VCO are as follows. VCO frequency [MHz] 150 VCO DIV = 1/1 VCO DIV = 1/2 100 50 VCO DIV = 1/4 2 3 VCO input voltage [V] 4 Therefore, KVCO is as follows. KVCO = 2π · 65M or 2π · 32.5M or 2π · 16.25M (rad/sV) – 33 – CXA3106AQ ωn and ζ calculated for various types of computer signals are shown below. Here, the various parameters are as follows. FSYNC: Input H sync frequency FCLK: Output clock frequency KPD∗2π: Phase comparator gain ∗2π (KPD*2π = +100 or 400 or 1600) KVCO/2π: VCO gain (when VCO DIV = 1/1, KVCO/2π = 65) (when VCO DIV = 1/2, KVCO/2π = 65/2) (when VCO DIV = 1/4, KVCO/2π = 65/4) N: Counter value C1: Loop filter capacitance value R1: Loop filter resistance value Resolution FSYNC FCLK kHz NTSC NTSC NTSC PAL PAL PAL MHz KPD C.Pump N DIV1.2.4 C1 KVCO/2π × 2π setting setting setting µA Bit1 Bit0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MHz/V 65/4 65/4 65/4 65/4 65/4 65/4 65/4 65/4 65/4 65/4 65/2 65/2 65/2 65/2 65/2 65/2 65/2 65/2 65/2 65/2 65/1 65/1 65/1 65/1 65/1 Bit1 Bit0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 µF R1 Ω ωn fn ζ kHzrad kHz 0.40 1.37 0.65 2.23 0.57 1.93 0.36 1.25 0.59 2.04 0.52 1.76 0.77 2.62 0.79 2.70 0.76 2.60 0.77 2.65 0.99 3.38 0.97 3.33 0.97 3.33 0.98 3.35 0.98 3.34 0.93 3.18 0.86 2.95 0.87 2.97 0.87 2.98 0.87 2.97 1.20 4.12 1.08 3.71 1.09 3.72 1.09 3.72 1.08 3.68 15.734 12.27 100 15.734 18.41 400 15.734 24.55 400 15.625 14.69 100 15.625 22.03 400 15.625 29.38 400 640 × 480 31.47 25.18 400 0.33 3300 2.51 1170 0.33 3300 4.10 1560 0.33 3300 3.55 940 0.33 3300 2.29 1410 0.33 3300 3.74 1880 0.33 3300 3.24 848 800 864 832 0.33 3300 4.82 0.33 3300 4.96 0.33 3300 4.77 0.33 3300 4.87 PC-98 640 × 400 24.82 21.05 400 VGA MAC 640 × 480 35.00 30.24 400 VESA 640 × 480 37.86 31.50 400 SVGA 800 × 600 35.16 36.00 400 SVGA 800 × 600 37.88 40.00 400 SVGA 800 × 600 46.88 49.50 400 SVGA 800 × 600 48.08 50.00 400 SVGA 800 × 600 53.67 56.25 400 MAC 832 × 624 49.72 57.28 400 XGA 1024 × 768 48.36 65.00 400 XGA 1024 × 768 56.48 75.00 400 XGA 1024 × 768 60.02 78.75 400 MAC 1024 × 768 60.24 80.00 400 XGA 1024 × 768 68.68 94.50 400 SXGA 1280 × 1024 46.43 78.75 400 SXGA 1280 × 1024 63.98 108.00 400 SXGA 1280 × 1024 79.98 135.00 400 SXGA 1280 × 1024 91.15 156.96 400 1024 0.33 3300 6.20 1056 0.33 3300 6.11 1056 0.33 3300 6.11 1040 0.33 3300 6.15 1048 0.33 3300 6.13 1152 0.33 3300 5.85 1344 0.33 3300 5.41 1328 0.33 3300 5.45 1312 0.33 3300 5.48 1328 0.33 3300 5.45 1376 0.33 3300 7.57 1696 0.33 3300 6.82 1688 0.33 3300 6.83 1688 0.33 3300 6.83 1722 0.33 3300 6.76 – 34 – CXA3106AQ CLK Jitter Evaluation Method The regenerated CLK is obtained by applying Hsync to the CXA3106AQ. Apply this CLK to a digital oscilloscope and observe the CLK waveform using Hsync as the trigger. trigger Hsync Pulse Generator CXA3106AQ CLK ch1 Digital Oscilloscope H Back Sync Porch Active Video Front Porch Computer signal 15 to 25% of Tsync Hsync Tsync = 1/fsync CLK Enlarged Trigger Enlarged Enlarged Enlarged CLK Tjp-p The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in the figure. The CLK jitter size varies according to the difference in the relative position with respect to Hsync. Therefore, when the observation point is changed, the CLK jitter at that point is observed. The figure below shows an typical example of the CLK jitter for the CXA3106AQ. The CLK jitter increases slightly at the rising edge of Hsync (in the case of positive polarity), and then settles down thereafter. However, this is not a problem as the active pixels start after about 20% of the H cycle has passed from the rising edge of Hsync. Jitter amount [Tjp-p] 0 1/4 · Tsync 2/4 · Tsync Observation points 3/4 · Tsync Tsync – 35 – CXA3106AQ Example of Representative Characteristics KVCO characteristics 250 300 Ta = +75°C Ta = +25°C Ta = –25°C KVCO Temperature characteristics 200 250 DIV = 1/1 Output Frequency [MHz] Output Frequency [MHz] 4.5 200 150 DIV = 1/2 100 DIV = 1/4 50 150 100 50 0 1.5 2.0 2.5 3.0 3.5 VCO Control Voltage [V] 4.0 0 1.5 2.0 2.5 3.0 3.5 4.0 VCO Control Voltage [V] 4.5 Coarse Delay Td1 vs Coarse Delay Bit 5 Ta = –25°C Ta = +25°C Ta = +75°C 25 Fine Delay Td2 vs Fine Delay Bit Ta = –25°C Ta = +25°C Ta = +75°C Coarse Delay Td1 [CLK] 4 Fine Delay Td2 [1/16 CLK] 0 1 2 Coarse Delay Bit 3 20 15 3 10 2 5 1 0 0 5 10 Fine Delay Bit 15 20 Jitter peak-peak vs Output Frequency 5.0 NTSC/PAL, DIV = 1/4, CP = 10 VGA, DIV = 1/4, CP = 10 SVGA, DIV = 1/2, CP = 10 XGA, DIV = 1/2, CP = 10 SXGA, DIV = 1/1, CP = 11 4.0 Jitter peak-peak [ns] 3.0 2.0 1.0 0.0 0 20 40 60 80 100 Output Frequency [MHz] 120 140 160 – 36 – CXA3106AQ Notes on Operation • Be sure not to separate the analog and digital power supplies, and the analog and digital GND. • The ground pattern should be as wide as possible. Using a multi-layer substrate with a mat ground is recommended. • Ground the power supply pins of the IC with a 0.1µF or larger ceramic chip capacitor as close to each pin as possible. • Be sure to accurately match the I/O characteristic impedance in order to ensure sufficient performance during high-speed operation. • Design the set so that the loop filter (external) is located at the minimum distance. (See the CXA3106AQ PWB.) – 37 – CXA3106AQ (1) Recommended PECL I/O circuit The peripheral circuits mainly use PECL for digital input and output. Of course, PECL and TTL can also be mixed. In this case, disable the TTL outputs with the control registers. PECL level output pins 330Ω GND 36 35 34 33 32 31 30 29 28 27 26 25 DSYNCL CLK/2H IOGND PECLVCC 37 IOGND 38 IOVCC 39 PLLVCC PECLVCC DSYNCH TTLGND TTLVCC CLK/2L CLKH VBB CLKL DSYNC 24 CLK 23 CLKN 22 CLK/2 21 CLK/2N 20 DGND 19 DVCC 18 100Ω 40 PLLGND 41 VCOVCC 42 VCOGND 100pF 0.33µF ∗3 1.6kΩ 44 IREF 45 RC2 46 RC1 47 IRGND 43 VCOHGND VCC 100kΩ UNLOCK output∗2 UNLOCK 17 10nF DIVOUT 16 GND SEROUT 15 CS 14 1200pF 3.3kΩ Loop Filter ∗4 SENABLE SYNCH SYNCL VCOH IOVCC VCOL HOLD SYNC 1 2 3 4 5 6 7 8 9 10 11 12 GND Control Register SDATA IOGND 48 IRVCC TLOAD 13 VCO SCLK VCC (+5.0V) Notes) ∗1 Unless otherwise specified, all capacitors are 0.1µF. ∗2 Vary the external resistor and capacitor values of the UNLOCK output as necessary. ∗3 This external resistor (1.6kΩ) should be a metal film resistor in consideration of temperature characteristics. ∗4 The loop filter's capacitors and resistor should also be temperature compensated. HOLD SYNCH, SYNCL: PECL level complementary input – 38 – CXA3106AQ (2) Recommended TTL I/O circuit The peripheral circuits mainly use TTL for digital input and output. Of course, PECL and TTL can also be mixed. 36 35 34 33 32 31 30 29 28 27 26 25 DSYNCL CLK/2H IOGND PECLVCC PECLVCC DSYNCH TTLGND TTLVCC CLK/2L CLKH VBB CLKL TTL level output pins DSYNC 24 CLK 23 CLKN 22 CLK/2 21 CLK/2N 20 DGND 19 DVCC 18 100Ω 37 IOGND 38 IOVCC 39 PLLVCC 40 PLLGND 41 VCOVCC 42 VCOGND 100pF 0.33µF ∗3 1.6kΩ 44 IREF 45 RC2 46 RC1 47 IRGND 43 VCOHGND VCC 100kΩ UNLOCK output∗2 UNLOCK 17 10nF DIVOUT 16 GND SEROUT 15 CS 14 1200pF 3.3kΩ Loop Filter ∗4 SENABLE SYNCH SYNCL VCOH IOVCC VCOL HOLD SYNC 1 2 3 4 5 6 7 8 9 10 11 12 GND Control Register SDATA IOGND 48 IRVCC TLOAD 13 VCO SCLK VCC (+5.0V) Notes) ∗1 Unless otherwise specified, all capacitors are 0.1µF. ∗2 Vary the external resistor and capacitor values of the UNLOCK output as necessary. ∗3 This external resistor (1.6kΩ) should be a metal film resistor in consideration of temperature characteristics. ∗4 The loop filter's capacitors and resistor should also be temperature compensated. HOLD SYNC: TTL level input – 39 – CXA3106AQ Connecting the CXA3106AQ with Sony ADC (Demultiplex Mode) When connecting the PLL output to A/D converters with built-in demultiplex function such as the CXA3026AQ/CXA3026Q/CXA3086Q (Sony), a simple system can be configured by connecting the CLK (PECL) and CLKN (PECL) outputs of the CXA3106AQ to the CLK (PECL) and CLKN (PECL) inputs of each A/D converter, respectively, and the 1/2 CLK (PECL) and 1/2 CLKN (PECL) outputs of the CXA3106AQ to the RESETN (PECL) and RESET (PECL) inputs of each A/D converter, respectively. (when the PLL counter value N is an even number) Wiring Diagram R VIN CLK (PECL) CLKN (PECL) RESETN (PECL) RESET (PECL) ADC CXA3026AQ CXA3026Q CXA3086Q 8 or 6 TTL 8 or 6 TTL G VIN CLK (PECL) CLKN (PECL) RESETN (PECL) RESET (PECL) ADC CXA3026AQ CXA3026Q CXA3086Q 8 or 6 TTL 8 or 6 TTL B VIN CLK (PECL) CLKN (PECL) RESETN (PECL) RESET (PECL) ADC CXA3026AQ CXA3026Q CXA3086Q 8 or 6 TTL 8 or 6 CMOS LOGIC RESET (TTL) CLK (TTL) 1/2 CLK (TTL) TTL 1/2 CLKN (PECL) 1/2 CLK (PECL) CLKN (PECL) DSYNC (TTL) CLK (PECL) • CXA3026AQ 8bit 140MSPS ADC • CXA3026Q 8bit 120MSPS ADC • CXA3086Q 6bit 140MSPS ADC PLL CXA3106AQ – 40 – CXA3106AQ CXA3106AQ and Sony ADC (Demultiplex Mode) Timing The CXA3106AQ and CXA3026Q/CXA3026AQ/CXA3086Q timings are shown below. Here, the important timings are as follows. (The clock cycle is labeled as T.) • Within the A/D converters Clock input vs. reset input The setup time is T–1ns and the hold time is 0ns, satisfying the A/D converter specifications. • Within the CMOS LOGIC at the rear end of the A/D converters A/D converter data output vs. 1/2 clock output timing The setup time is T–4.5ns and the hold time is T–0.5ns. (These timings also include combinations of three A/D converters from different lots, and are defined for all operating temperatures and all operating supply voltages. See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.) • Within the CMOS LOGIC at the rear end of the A/D converters DSYNC signal from CXA3106AQ vs. A/D converter 1/2 clock output The setup time is T–3ns and the hold time is T–5ns. CXA3106AQ T CLK (PECL) out 3 to 7.5ns DSYNC (TTL) out 0 to 1ns 1/2CLK (PECL) out ∗ See the CXA3026AQ/Q and CXA3086Q specifications. CXA3026Q CXA3026AQ CXA3086Q 4.5 to 8ns Thold min. T–5ns Tsetup min. T–3ns Tsetup min. Thold min. T–4.5ns T–0.5ns 1/2CLK (TTL) out DATA (TTL) out – 41 – CXA3106AQ Connecting the CXA3106AQ with Sony ADC (Straight Mode) When connecting the PLL output to A/D converters such as the CXA3026AQ/CXA3026Q/CXA3086Q (Sony), a simple system can be configured as shown below. Wiring Diagram R VIN CLK (PECL) CLKN (PECL) ADC CXA3026AQ CXA3026Q CXA3086Q 8 or 6 TTL G VIN CLK (PECL) CLKN (PECL) ADC CXA3026AQ CXA3026Q CXA3086Q 8 or 6 TTL B VIN CLK (PECL) CLKN (PECL) ADC CXA3026AQ CXA3026Q CXA3086Q 8 or 6 TTL CMOS LOGIC RESET (TTL) CLK (TTL) CLKN (PECL) DSYNC (TTL) CLK (PECL) CLK (TTL) • CXA3026AQ 8bit 140MSPS ADC • CXA3026Q 8bit 120MSPS ADC • CXA3086Q 6bit 140MSPS ADC PLL CXA3106AQ – 42 – CXA3106AQ CXA3106AQ and Sony ADC (Straight Mode) Timing The CXA3106AQ and CXA3026Q/CXA3026AQ/CXA3086Q timings are shown below. Here, the important timings are as follows. (The clock cycle is labeled as T.) • Within the CMOS LOGIC at the rear end of the A/D converters A/D converter data output vs. clock output from CXA3106AQ The setup time is T–8.5ns and the hold time is 2ns. (These timings also include combinations of three A/D converters from different lots, and are defined for all operating temperatures and all operating supply voltages. See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.) • Within the CMOS LOGIC at the rear end of the A/D converters DSYNC signal from CXA3106AQ vs. clock output from CXA3106AQ The setup time is T–4.5ns and the hold time is 1.5ns. CXA3106AQ T CLK (PECL) out 1.5 to 4.5ns CLK (TTL) out 1.5 to 3ns DSYNC (TTL) out Thold min. 1.5ns Tsetup min. T–4.5ns CXA3026Q CXA3026AQ CXA3086Q Tsetup min. T–8.5ns 6.5ns min DATA (TTL) out 10ns max Thold min. 2ns – 43 – CXA3106AQ CXA3106AQ-PWB (CXA3106AQ Evaluation Board) The CXA3106AQ-PWB is an evaluation board for the CXA3106AQ PLL-IC. This board makes it possible to easily evaluate the CXA3106AQ's performance using the supplied control program (Note: IBM PC/AT, MSDOS 5.0 and newer US mode specifications). Features • Two input level (TTL and PECL) SYNC input • Two output level (TTL and PECL) CLK, CLK2 and DSYNC output • Supply voltage: +5.0V Absolute Maximum Ratings (Ta = 25°C) Supply voltage VCC –0.5 to +7.0 Recommended Operating Conditions • Supply voltage VCC 4.75 to 5.25 GND 0 • Digital input (PECL) DIN (High) DIN (Low) (TTL) DIN (High) DIN (Low) • Operating ambient temperature Ta –20 to +75 Block Diagram V V V VCC – 1.1 VCC – 1.5 GND + 2.0 GND + 0.8 °C V (Min.) V (Max.) V (Min.) V (Max.) Loop Filter VCO input (PECL/TTL) DSYNC output (PECL/TTL) CLK output (PECL/TTL) CLK/2 output (PECL/TTL) VBB (PECL) SYNC input (PECL/TTL) CXA3106AQ 48pin QFP SEROUT (TTL) 3 CONTROL BUS (TTL) SENABLE, SCLK, SDATA DIVOUT (TTL) UNLOCK (TTL) – 44 – CXA3106AQ Setting Methods and Notes on Operation Input pins This PWB supports TTL single and PECL complementary input. Input pins: SYNC: TTL level input, 10 to 100kHz SYNCL: PECL low level input, 10 to 100kHz SYNCH: PECL high level input, 10 to 100kHz VCO: VCOL: VCOH: Output pins This PWB supports TTL single and PECL complementary output. DSYNCH, DSYNCL: PECL level complementary delay SYNC outputs. The output range is 10 to 160kHz. DSYNC: CLKH, CLKL: CLK, CLKN: CLK/2H, CLK/2L: CLK/2, CLK/2N: VBB: TTL level delay SYNC output. The output range is 10 to 100kHz. TTL level input. This is a test pin and is therefore normally not used. PECL low level input. This is a test pin and is therefore normally not used. PECL high level input. This is a test pin and is therefore normally not used. PECL level complementary CLK outputs. The output range is 10 to 160MHz. TTL level complementary CLK outputs. The output range is 10 to 80MHz. PECL level complementary 1/2 CLK outputs. The output range is 5 to 80MHz. TTL level complementary CLK outputs. The output range is 5 to 80MHz. Outputs the PECL amplitude threshold voltage. SEROUT: TTL level control register serial data output. DIVOUT: TTL level internal programmable counter test output. UNLOCK: TTL level UNLOCK output. This pin requires external circuits such as appropriate capacitors and resistors. See the IC specifications for a detailed description. PECL outputs (VBB, DSYNCH, DSYNCL, CLKH, CLKL, CLK/2H, CLK/2L) are output constantly, but TTL outputs (DSYNC, CLK, CLKN, CLK/2, CLK/2N, SEROUT, DIVOUT, UNLOCK) are controlled by the respective control registers. Therefore, the enable/disable settings should be made in accordance with the application. See the following pages for the setting method. – 45 – CXA3106AQ Jumper Wire Settings S1, S2: These enable/disable HOLD (Pin 6). HOLD is active high, so the jumper wire should be connected to S2 (HOLD = low) for normal use. When using HOLD, connect the jumper wire to S1 (HOLD = high). (For the initial setting, the jumper wire is connected to S2.) S3, S4: These enable/disable TLOAD (Pin 13). Connect the jumper wire to S4 (TLOAD = high) for normal use. When using TLOAD, connect the jumper wire to S3 (TLOAD = low). (For the initial setting, the jumper wire is connected to S4.) S5, S6: These enable/disable CS (Pin 14). Connect the jumper wire to S6 (CS = high) for normal use. When using Power Save, connect the jumper wire to S5 (CS = low). (For the initial setting, the jumper wire is connected to S6.) Supplied Program This PWB is equipped with a control program that facilitates evaluation of the CXA3106AQ. Operation methods and precautions are as follows. 1) Compatible personal computers Use an IBM PC/AT or compatible machine equipped with a 25-pin D-SUB parallel port (printer port). Also, operating systems which support the program are MS-DOS 5.0 or newer and MS-Windows 3.1 or newer. (When using Windows, start the program from the DOS window.) 2) Connect the supplied cable Connect the supplied cable to the parallel port of the personal computer and the DBUS1 connector of the CXA3106AQ-PWB. D-SUB 25-pin parallel connector pin arrangement 1 13 2pin : SCLK 3pin : SDATA 4pin : SENABLE 11pin : SERIN 19pin : GND 14 25 3) Connect the power cable and supply power to the CXA3106AQ-PWB 4) Start the program A) Boot the personal computer and then shift to the directory containing the program. B) Set MS-DOS to US mode. → US Return or Enter C) Input the program name. → ∗1CXA3106A or CXA3106B Return or Enter → Move to the program screen. ∗1 Only one of either CXA3106A or CXA3106B can be used as the program name depending on the printer port setting of the personal computer. – 46 – CXA3106AQ 5) Description of the program screen A) When the program is started, the following initial screen is displayed. Please type the name of the initialization file OR press ENTER. The file extention.INI should not be included. The default file when ENTER is pressed is CXA3106.INI Filename > _ When this screen appears, press the Return or Enter key. The screen shifts to the function setting screen. B) Function settings When the program is loaded, the following function setting screen appears. CXA3106 PLL REGISTERS Divisor 1344 Divider 2 Coarse Delay 00 Fine Delay 10 Charge Pump 10 Polarity SYNC 1 DSYNC 1 PD 1 Power SCAN OFF SYNTH ON VCO Bypass ON O/P Enable DIVOUT OFF UNLOCK OFF DSYNC OFF CLK2 OFF NCLK2 OFF CLK1 OFF NCLK1 OFF Use arrow keys to select data bit. Press ENTER to toggle and load data. Use Pg Up and Pg Dn to increment/decrement divisor and fine delay registers. Press a to abort, s to scan registers MIXED SIGNAL SYSTEMS JAN 1997 – 47 – CXA3106AQ Divisor This is used to input the frequency division ratio of the program counter. The value can be changed as desired from 9 to 4111 by moving the cursor to the position of the number and pressing the Return or Enter key. (Note: The operating range of the CXA3106AQ is from 256 to 4096.) The value can also be incremented or decremented by one step by pressing the Page Up or Page Down key, respectively. The internal VCO has an oscillator frequency of 40 to 160MHz, so the output frequency and Divider (VCO frequency divider) setting range are as follows. 40 1/1 Divider = 1 160 Divider 1/2 20 Divider = 2 80 1/4 10 40 Divider = 4 50 100 O/P Frequency [MHz] 150 Divider This sets the VCO output frequency division ratio to 1/1, 1/2 or 1/4. The frequency division ratio changes repeatedly in the order of 1/1 → 1/2 → 1/4 → 1/1 each time the cursor is moved to the position of the number and the Return or Enter key is pressed. Coarse Delay This is the DSYNC upper delay time setting. The value can be changed by moving the cursor to the position of the number and pressing the Return or Enter key. The delay time variable range settings are "00" (1 CLK), "01" (2 CLK), "10" (3 CLK) or "11" (4 CLK). Fine Delay This is the DSYNC lower delay time setting. The value can be changed by moving the cursor to the position of the number and pressing the Return or Enter key. The value can also be incremented or decremented by one step by pressing the Page Up or Page Down key, respectively. The delay time can be varied from 1/16 CLK to 32/16 CLK by setting "0" to "31", respectively. Charge Pump This is the charge pump circuit KI setting. The value can be changed by moving the cursor to the position of the number and pressing the Return or Enter key. KI can be set to "00" (about 100µA), "10" (about 400µA) or "11" (about 1.6mA). The setting "01" is not used. (Setting "01" is the same as setting "00".) Polarity These are the SYNC, DSYNC and PD (Phase Detector) polarity inversion settings, and should be set as necessary such as when inverting the SYNC input and DSYNC output waveforms. The setting value "1" is positive polarity, and "0" is negative polarity. These should normally all be set to "1". (Fix PD to "1" other than during test mode.) – 48 – CXA3106AQ Power SCAN: This is the control register read setting. When this is ON, the control register serial data is output from SEROUT (Pin 15). This should normally be set to OFF. SYNTH: This is the enable/disable setting for this IC. This should normally be set to ON. VCO Bypass: This is set to OFF when testing the program counter. This should normally be set to ON. O/P Enable These are the enable/disable settings for each TTL output (DIVOUT, UNLOCK, DSYNC, CLK2, NCLK2, CLK1 and NCLK1). Set to ON when performing evaluation using TTL output. – 49 – CXA3106AQ C) Description of readout mode This program has a function (readout mode) that reads the contents written to the control registers from the CXA3106AQ SEROUT (Pin 15) and displays these contents on the screen. This function is described below. 1) Set SCAN to ON at the function setting screen. 2) Press the S key. The following screen appears. SCAN RESULT, CXA3106 PLL REGISTERS Register 1 DIVREG1 00111000 Register 2 DIVREG2 0101 Register 3 CENFREREG 1011111 Register 4 DELAYREG 0010000 Register 5 CPREG 100 Register 6 TTLPOLREG 00000011 Register 7 TESTPOWREG 0111 Press r to return to PLL REGISTERS MENU. Press a to abort MIXED SIGNAL SYSTEMS AUG 1996 This screen conforms to the Control Register Table listed in the CXA3106AQ specifications. 3) Press the R key to return to the original function setting screen. D) Quit the program Press the A key to quit the program. – 50 – CXA3106AQ Substrate Pattern (parts surface) Substrate Pattern (solder surface) – 51 – CXA3106AQ VCO VCOL VCOH VCC GND BNC3 BNC2 BNC1 C21 33µ + R1 PR10 VBB CXA3106Q/AQ PWD v1.2 R8 BNC4 SYNCH R19 R3 R10 PR8 DSYNCL R2 R9 PR9 DSYNCH S1 S2 BNC5 SYNCL IC1 R7 R14 PR6 CLKL R4 R11 PR7 CLKH BNC6 SYNC S3 S4 S5 S6 R6 R13 PR1 CLK/2L R5 R12 PR5 CLK/2H 81C 02C 4C 6C 2C 7C Silk Screen (solder surface) – 52 – C9 C8 5C DBUS1 Control Register PR2 SEROUT PR3 DIVOUT PR4 UNLOCK PR11 CLK/2N PR12 CLK/2 PR13 CLKN PR14 CLK PR15 DSYNC Silk Screen (parts surface) 1C 91C 21C 41C 31C 01C 11C C3 81C 51C 71C 61C PWB Circuit Diagram R18 C19 3.3k 0.33µ GND VCC R19 1.6k C11 100p C3 0.1µ 48 47 46 45 44 42 41 43 40 39 38 37 C12 0.1µ C4 0.1µ C5 0.1µ C6 0.1µ C20 1200p BNC1 VCOH BNC2 VCOL C10 0.1µ VCC C1 0.1µ R1 C13 0.1µ R2 C14 0.1µ R3 C15 0.1µ R4 C8 0.1µ C18 0.1µ R7 C16 0.1µ C9 0.1µ R5 C17 0.1µ 24 R6 R13 330 R12 330 R14 330 R11 330 R10 330 R9 330 R8 330 GND BNC3 RC1 RC2 IRVCC IREF IRGND VCOVCC VCOGND BNC4 3 4 DSYNCL 33 CLKH 32 CLKL 31 CXA3106AQ 7 8 CLK/2L 29 PECLVCC 28 IOGND 27 TTLVCC 26 TTLGND 25 9 SYNC 10 SENABLE 11 SCLK 12 SDATA SYNCL SYNCH CLK/2H 30 5 VCO HOLD S1 6 S2 VCOL VCOH DSYNCH 34 2 IOGND VCOHGND 1 PECLVCC 36 VBB 35 IOVCC PLLGND PLLVCC IOGND C2 0.1µ IOVCC VCO PR10A VBB PR9A DSYNCH PR8A DSYNCL PR7A CLKH PR6A CLKL PR5A CLK/2H PR1A CLK/2L SYNCH BNC5 SYNCL BNC6 SYNC Control Register UNLOCK 13 14 15 16 21 S5 S6 S3 S4 C7 0.1µ 17 18 19 20 TLOAD CS SEROUT DIVOUT DVCC DGND CLK/2N CLK/2 GND 22 23 CLKN CLK DSYNC – 53 – GND VCC PWR1 C21 33µ VCC PWR2 GND GND PR2A PR4A PR3A SEROUT DIVOUT UNLOCK DBUS1 1 5 PR15A DSYNC PR14A CLK PR13A CLKN PR12A CLK/2 PR11A CLK/2N CXA3106AQ Note) R1 to R7 are not mounted. CXA3106AQ Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.4 12.0 – 0.1 + 0.1 0.15 – 0.05 36 25 0.15 37 24 48 13 + 0.2 0.1 – 0.1 1 + 0.15 0.3 – 0.1 12 0.8 ± 0.12 M + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 ∗QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 54 – 0.9 ± 0.2 13.5 Sony Corporation