CXA3201AN

CXA3201AN RX Gain Control Amplifier Description CXA3201AN is an RX gain control amplifier suitable for CDMA cellular/PCS phone. Features • Wide gain control range • Linear gain slope • Wideband operation (50MHz to 300MHz) • Very small package (16 Pin SSOP) • Low voltage operation • Two input ports • Power save function included Absolute Maximum Ratings • Supply voltage VCC 6 V • Operating temperature Topr –55 to +125 °C • Storage temperature Tstg –65 to +150 °C • Allowable Power dissipation PD 330 mW • Supply voltage range –0.3 to 6 V • Logic input voltage –0.3 to VCC + 0.3 V • Signal input voltage –0.3 to VCC + 0.3 V • Differential signal input voltage 0 to 2.5 V Operating Condition Supply voltage Applications CDMA cellular/PCS phone Structure Bipolar silicon monolithic IC 16 pin SSOP (Plastic) VCC 2.7 to 3.8 V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98909A8Y CXA3201AN Block Diagram IF Input for CDMA CDMA IN CDMA INX OUT SWITCH OUTX IF Output IF Input for FM FM IN FM INX Input Select MODE Gain control GCTL Supply Voltage VCC1, 2 Bias Driver Ground GND Power Save PSV Pin Configuration CDMA IN CDMA INX GND FM IN FM INX GND MODE PSV 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GCTL VCC1 VCC1 VCC2 GND GND OUTX OUT –2– CXA3201AN Pin Description Pin No. Symbol Pin voltage TYP (V) Equivalent circuit Description VCC1 1 CDMA IN 1.15 2k 1 2 2k Differential input pins for received CDMA IF signal. 2 CDMA INX 1.15 GND 3 6 11 12 GND 0 Ground. VCC1 4 FM IN 1.15 2k 4 5 2k Differential input pins for received FM IF signal. 5 FM INX 1.15 GND VCC1 7 7 MODE — 30k Input select pin. CDMA IN for High FM IN for Low. GND VCC1 8 PSV — 8 135k Power save function pin. High: Active Low: Power save GND –3– CXA3201AN Pin No. Symbol Pin voltage TYP (V) Equivalent circuit Description VCC2 460 460 12.3k 9 OUT — 9 10 12.3k Differential output pins for received CDMA IF signal. Open collector output. 10 OUTX — GND 13 14 15 VCC2 VCC1 3.0 3.0 Positive power supply for output stage. Positive power supply. VCC1 8k 8k 16 GCTL — 200 16 Gain control pin. 6k 6k GND –4– CXA3201AN Electrical Characteristics DC Characteristics Parameter Current consumption 1 Current consumption 2 Input current pin 7H Input current pin 7L Input current pin 8H Input current pin 8L Input current pin 16H Input current pin 16L MODE high voltage MODE low voltage PSV high voltage PSV low voltage Symbol ICC1 ICC2 ImodeH ImodeL IpsvH IpsvL IgctlH IgctlL VmH VmL VpsH VpsL Conditions Vpsv = 3.0V, Vgctl = 1.5V, Pin 13, 14 Vpsv = 0 V, Vgctl = 1.5V, Pin 13, 14 Vmode = 3.0V Vmode = 0.5V Vpsv = 3.0V Vpsv = 0 V Vgctl = 3.0V Vgctl = 0.5V Pin 7 Pin 7 Pin 8 Pin 8 2.5 0.5 –1 2.5 0.5 V –15 1 –1 1 µA (VCC = 3.0V, Ta = 27°C) Min. Typ. Max. Unit 7 10 10.2 27 15 50 1 mA AC Characteristics Parameter Operating frequency range Gain CDMA2.4 Gain CDMA1.5 Gain CDMA0.6 CDMA Gain slope Gain FM2.4 Gain FM1.5 Gain FM0.6 FM Gain slope Input level 3rd order intercept point Noise Figure Symbol Fr GCDMA2.4 GCDMA1.5 GCDMA0.6 GCLIN GFM2.4 GFM1.5 GFM0.6 GFMLIN Vmode = "H", f = 210.38MHz, Vgctl = 2.4V Vmode = "H", Vgctl = 1.5V Vmode = "H", Vgctl = 0.6V Vmode = "H", Gain CDMA at Vgctl = 2.0V – Gain CDMA at Vgctl = 1.0V Vmode = "L", f = 85.38MHz, Vgctl = 2.4V Vmode = "L", Vgctl = 1.5V Vmode = "L", Vgctl = 0.6V Vmode = "L", Gain FM at Vgctl = 2.0V – Gain FM at Vgctl = 1.0V Vmode = "H", GCDMA = 40dB∗1 f1 = 209.38MHz, f2 = 211.38MHz Measure of 210.38MHz Vmode = "H", GCDMA = 40dB∗1 Measure of 210.38MHz Conditions (VCC = 3.0V, Ta = 27°C) Min. Typ. Max. Unit 50 42 –7 –59 58 42 –7 –59 58 46 –3 –55 61 46 –3 –55 61 300 MHz 50 1 –51 64 50 1 –51 64 dB/V dB dB/V dB IIP3 –42 –38 dBm NF 5 8 dB ∗1 Adjust GCTL voltage, and set the overall gain to 40dB. –5– CXA3201AN Measurement Circuit 1000p ∗1 CDMA INPUT 1000p∗2 180n 10k 1 CDMA IN GCTL 16 A16 V16 2 CDMA INX VCC1 15 0.01µ V14 3 GND 1000p ∗1 FM INPUT ∗3 1000p 1.5µ 5 FM INX GND 12 240 6 GND V7 A7 V8 A8 8 PSV OUT 9 7 MODE OUTX 10 ∗1 OUTPUT GND 11 240 VCC1 14 A14 4 FM IN VCC2 13 0.01µ ∗1 TOKO, Inc. B5FL 616DS-1135 ∗2 Coilcraft, Inc. 0805HS-181TKBC ∗3 Coilcraft, Inc. 1008CS-152XKBC –6– CXA3201AN Application Circuit VCC Gain Control Voltage 1000p 1 CDMA IN CDMA RX IF INPUT ∗ ∗ 2 CDMA INX 1000p 3 GND 1000p 4 FM IN FM RX IF INPUT ∗ ∗ 5 FM INX 1000p 6 GND CDMA FM Active Sleep 8 PSV OUT 9 7 MODE OUTX 10 GND 11 ∗ GND 12 VCC2 13 VCC1 14 VCC1 15 GCTL 16 1k 0.01µ 100p 0.01µ 1000p RX IF OUTPUT 1000p ∗ ∗ Must be adjusting values to result a best impedance matching between BPF filter and this IC. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –7– CXA3201AN Design Reference Values Single ended measurement Item Input resistance Input capacitance Output resistance Output capacitance Symbol Rin Cin Rout Cout f = 210.38MHz, Vgctl = 1.5V Conditions (VCC = 3.0V, Ta = 27°C) Typ. 1.6 1.4 5.9 0.85 Unit kΩ pF kΩ pF Notes on Operation 1) This IC is a wideband amplifier with wide gain control range. The decouping capacitors between GND Pin and VCC Pin should be as close to the IC as possible. 2) The resistors connected to Pins 9 and 10 should be as close to the IC as possible. 3) This IC assumes the excellent characteristics when the differential input impedance between Pins 1 and 2, Pins 4 and 5 is 500Ω. Refer to the Measurement Circuit for the external element settings, etc. 4) Pay attention to handling this IC because its electrostatic discharge strength is weak. –8– CXA3201AN Sensitivity 60 VCC = 3.0V 40 20 –10 0 IIP3 VCC = 3.0V Power gain [dB] –20 0 –20 –40 –60 –80 0 0.5 1 1.5 Vgctl [V] 2 2.5 3 IIP3 [dBm] –30 –40 T = –40°C T = 27°C T = 85°C T = –40°C T = 27°C T = 85°C –50 –60 –80 –60 –40 –20 0 20 40 60 Power gain [dB] Noise Figure 25 VCC = 3.0V 20 4 6 Gain Error from Room Temp VCC = 3.0V Noise figure [dB] 15 Gain error [dB] 2 0 10 –2 T = –40°C T = 85°C 5 T = –40°C T = 27°C T = 85°C 0 10 20 30 40 50 60 –4 0 –10 –6 –80 –60 –40 –20 0 20 40 60 Power gain [dB] Power gain [dB] –9– CXA3201AN Package Outline Unit: mm 16PIN SSOP (PLASTIC) ∗5.0 ± 0.1 + 0.2 1.25 – 0.1 0.1 16 9 A ∗4.4 ± 0.1 1 8 0.65 + 0.05 0.15 – 0.02 + 0.1 0.22 – 0.05 0.13 M 0.1 ± 0.1 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-16P-L01 SSOP016-P-0044 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.1g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 10 – 0.5 ± 0.2 6.4 ± 0.2