CXA3252N

CXA3252N All Band TV Tuner IC with On-chip PLL Description The CXA3252N is a monolithic TV tuner IC which integrates local oscillator and mixer circuits for VHF band, local oscillator and mixer circuits for UHF band, an IF amplifier and a tuning PLL onto a single chip, enabling further miniaturization of the tuner. Features • Superior cross modulation • Supports both IF double-tuned filter and adjacent channel trap. • Balanced UHF oscillator (4 pins) with excellent oscillation stability • Supports both I2C and 3-wire bus modes • Automatic identification of 18, 19 or 27-bit control (during 3-wire bus mode) • On-chip high voltage drive transistor for charge pump • Reference frequency selectable from 31.25, 50 or 62.5 kHz (when using a 4 MHz crystal) • Low-phase noise synthesizer • On-chip 4-output band switch (supports output voltages from 5 to 9 V) • 32 pin SSOP Applications • TV tuners • VCR tuners • CATV tuners Structure Bipolar silicon monolithic IC 32 pin SSOP (Plastic) Absolute Maximum Ratings (Ta=25 °C) • Supply voltage V VCC1, VCC2 −0.3 to + 5.5 VCC3 −0.3 to +10.0 V • Storage temperature Tstg −55 to + 150 °C • Allowable power dissipation Operating Conditions • Supply voltage V VCC3 4.75 to 9.45 V • Operating temperature Topr −25 to +75 °C PD 580 mW (when mounted on a printed circuit board) VCC1, VCC2 4.75 to 5.30 This IC has the pins whose electrostatic discharge strength is weak as the operating frequency is high and the high-frequency process is used for this IC. Take care of handling the IC. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E00301-TE CXA3252N Block Diagram and Pin Configuration CL DA 1 2 BUS Interface ADSW 32 /CE 31 VCC3 Shift Register BS3 BS1 3 4 Divider 1/64, 80, 128 REF OSC 30 REFOSC IFIN1 5 IFIN2 6 BS2 Band SW Driver Programable Divider 14/15bit IF AMP VCC1 Phase Detector Charge Pump 29 CPO 28 VT 7 8 VSW LOCK Det 27 NC BS4 26 IFOUT 9 V.REG 25 GND2 Bus Select Buffer 24 VCC2 MIXout1 10 MIXout2 11 GND1 12 BYP/MS 13 VHFin 14 Buffer VHF MIX UHF OSC 23 UOSCB2 22 UOSCE2 21 UOSCE1 20 UOSCB1 19 VOSC2 Buffer UHFin1 15 UHFin2 16 VHF UHF MIX VHF OSC 18 GND 17 VOSC1 –2– CXA3252N Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol CL DA BS3 BS1 IFIN1 IFIN2 BS2 BS4 VCC1 MIXOUT1 MIXOUT2 GND1 BYP/MS VHFIN UHFIN1 UHFIN2 VOSC1 GND VOSC2 UOSCB1 UOSCE1 UOSCE2 UOSCB2 VCC2 GND2 IFOUT NC VT CPO REFOSC VCC3 ADSW/CE CLOCK/SCL (I C bus) DATA/SDA (I2C bus) Band switch output 3 Band switch output 1 (VHF low band) IF amplifier input 1 IF amplifier input 2 Band switch output 2 (VHF high band) Band switch output 4 Analog circuit Vcc MIX output (open collector) MIX output (open collector) Analog circuit GND VHF input GND and control bus switching VHF input UHF input UHF input VHF oscillator (base input) GND VHF oscillator (collector output) UHF oscillator (base pin) UHF oscillator (emitter pin) UHF oscillator (emitter pin) UHF oscillator (base pin) PLL circuit Vcc PLL circuit GND IF amplifier output OPEN Tuning voltage output (open collector) Charge pump output (loop filter connection) Crystal connection Band switch power supply Enable/address selection (I2C bus) 2 Description –3– CXA3252N Pin Description and Equivalent Circuit Pin No. Symbol Pin Voltage [V] 23 Equivalent circuit Description 1 CL — 1 40k Clock input. 23 2 DA — 2 40k DATA input. 2.5p 20 31 3 BS3 ON : 4.8 OFF : 0.0 3 8 8 BS4 Band switch outputs. The pin corresponding to the selected band goes High. 31 4 BS1 4 2.1 7 BS2 8 12k 25k 8 5 IFIN1 2.1 5 6 1.2k 5k 5k 6 IFIN2 9 VCC1 — Analog circuit power supply. –4– CXA3252N Pin No. Symbol Pin Voltage [V] Equivalent circuit 10 11 Description 10 MIXOUT1 — Mixer output. These pins output the signal with open collector, and they must be connected to the power supply via the load. 11 MIXOUT2 — 12 GND1 — 3.8 during VHF reception 9 14 3k — 24 15p 3k 76k 24k Analog circuit GND. 13 BYP/MS 3.8 during UHF reception Pin 12 : VHF input grounding and control bus switching. Pin 13 : VHF input. Input format is the unbalanced input. 2.6 during VHF reception 14 VHFin 0.1 during UHF reception 13 2.6 during UHF reception 9 15 16 3k 3k 15 UHFin1 0.1 during VHF reception 2.6 during UHF reception UHF inputs. Input the signal to Pins 14 and 15 symmetrically or ground either of Pin 14 or 15 with the capacitor and input the signal to the rest. 16 UHFin2 0.1 during VHF reception 2.1 during VHF reception 9 400 19 50 17 3k 3k 17 VOSC1 2.3 during UHF reception 4.2 during VHF reception External resonance circuit connection for VHF oscillator. 19 VOSC2 5.0 during UHF reception 18 GND — — GND for separating the analog and PLL systems. –5– CXA3252N Pin No. Symbol 20 UOSCB1 21 UOSCE1 22 UOSCE2 Pin Voltage [V] 2.1 during UHF reception 2.3 during VHF reception 1.4 during UHF reception 1.8 during VHF reception 1.4 during UHF reception 1.8 during VHF reception Equivalent circuit 9 23 22 21 20 3k 3k Description External resonance circuit connection for UHF oscillator. 23 UOSCB2 24 25 VCC2 GND2 2.1 during UHF reception 2.3 during VHF reception — — 9 — — PLL circuit power supply PLL circuit GND. 26 IFOUT 2.7 26 I/F output. 27 NC — 24 — 28 VT — 29 28 70 29 CPO 2.0 Varicap drive voltage output. This pin outputs the signal with open collector, and this must be connected to the tuning power supply via the load. Charge pump output. Connects the loop filter. 24 60k 30p 30 30p 30 REFOSC 4.3 Crystal connection for reference oscillator. 31 VCC3 — 23 150k — Power supply for external supply. 32 ADSW/CE 1.25 (when open) 3 50k 5p I2C bus setting : Address selection. Bits 1 and 2 of the address byte are controlled. 3-wire bus setting : Enable input. –6– CXA3252N Electrical Characteristics Circuit Current Item Circuit current A AICCU Circuit current D DICC Symbol AICCV Measurement conditions VCC1 current, band switch output open during VHF operation VCC1 current, band switch output open during UHF operation VCC2 current Min. Typ. (VCC=5 V, Ta=25°C) Max. Unit mA mA mA OSC/MIX/IF Amplifier Block Item Symbol CG1 Conversion gain CG2 CG3 CG4 NF1 Noise figure *1, *2 NF2 NF3 NF4 CM1 CM2 CM3 CM4 Maximum output power Pomax ∆ fsw1 ∆ fsw2 Switch ON drift *4 Measurement conditions VHF operation fRF=55 MHz VHF operation fRF=360 MHz UHF operation fRF=360 MHz UHF operation fRF=800 MHz VHF operation fRF=55 MHz VHF operation fRF=360 MHz UHF operation fRF=360 MHz UHF operation fRF=800 MHz VHF operation fD=55 MHz, fUD=±12 MHz VHF operation fD=360 MHz, fUD=±12 MHz UHF operation fD=360 MHz, fUD=±12 MHz UHF operation fD=800 MHz, fUD=±12 MHz 50 Ω load saturation output VHF operation fOSC=100 MHz ∆ f from 3 s to 3 min after switch ON VHF operation fOSC=405 MHz ∆ f from 3 s to 3 min after switch ON UHF operation fOSC=405 MHz ∆ f from 3 s to 3 min after switch ON UHF operation fOSC=845 MHz ∆ f from 3 s to 3 min after switch ON Min. Typ. Max. Unit dB dB dB dB dB dB dB dB dBµ dBµ dBµ dBµ dBm kHz kHz kHz kHz 1% cross modulation *1,*3 ∆ fsw3 ∆ fsw4 –7– CXA3252N Item Symbol ∆ fst1 ∆ fst2 Measurement conditions VHF operation fOSC=100 MHz ∆ f when Vcc 5 V changes ±5% VHF operation fOSC=405 MHz ∆ f when Vcc 5 V changes ±5% UHF operation fOSC=405 MHz ∆ f when Vcc 5 V changes ±5% UHF operation fOSC=845 MHz ∆ f when Vcc 5 V changes ±5% 10 kHz offset 10 kHz offset Phase comparison frequency of 62.5 kHz, CP : 1 Min. Typ. Max. Unit kHz kHz kHz kHz dBc/Hz dBc/Hz dB msec msec Supply voltage drift *4 ∆ fst3 ∆ fst4 Oscillator phase noise Reference leak Lock-up time *1 *2 C/N V C/N U REFL LUT 1 LUT 2 Value measured with untuned input. NF meter direct-reading value (DSB measurement). *3 Value with a desired reception signal input level of −30 dBm, an interference signal of 100 kHz/30 % AM, and an interference signal level where S/I=46 dB measuered with a spectrum analyzer. *4 Value when the PLL is not operating. –8– CXA3252N PLL Block Item CL, DA pins “H” level input voltage “L” level input voltage “H” level input current “L” level input current CE input “H” level input voltage “L” level input voltage “H” level input current “L” level input current SDA output “H” output leak current “L” output voltage CPO (charge pump) Output current 1 Leak current 1 Output current 2 Leak current 2 VT (VC voltage output) Maximum output voltage Minimum output voltage LOCK “H” output voltage “L” output voltage REFOSC Oscillation frequency range Input capacitance Negative resistance Band SW Output current Saturation voltage Leak current IBS VSAT LeakBS When ON When ON Source current=20 mA When OFF 120 0.5 –25 240 3 mA mV µA FXTOSC CXTOSC RNEG Crystal source impedance 3 22 24 –2 12 26 –1 MHz pF kΩ VLOCKH VLOCKL When locked When unlocked VCC-0.5 0 VCC 0.5 V V VTH VTL 0.5 33 0.8 V V ICPO1 LeakCP1 ICPO2 LeakCP2 Byte4/Bit6=0 Byte4/Bit6=0 Byte4/Bit6=1 Byte4/Bit6=1 ±140 ±200 ±35 ±50 ±75 30 ±300 100 µA nA µA nA VIH VIL Vin=5.5 V Iout=–3 mA GND 5 0.4 V V VIH VIL IIH IIL VIH=VCC VIL=GND 3 GND –100 35 VCC 1.5 –200 100 V V µA µA VIH VIL IIH IIL VIH=VCC VIL=GND 3 GND 0 –0.3 VCC 1.5 –0.1 –4 V V µA µA Symbol Measurement conditions Min. Typ. Max. Unit –9– CXA3252N Item Bus timing (I C bus) SCL clock frequency Start waiting time Start hold time “L” hold time “H” hold time Start setup time Data hold time Data setup time Rise time Fall time Stop setup time Bus timing (3-wire bus) Data setup time Data hold time Enable waiting time Enable setup time Enable hold time 2 Symbol fSCL tWSTA tHSTA tLOW tHIGH tSSTA taHDAT tSDAT tR tF tSSTO tSD tHD tWE tSE tHE Measurement conditions Min. 0 1300 600 1300 600 600 1300 600 Typ. Max. 400 Unit kHz ns ns ns ns ns ns ns 300 300 600 300 600 300 300 600 ns ns ns ns ns ns ns ns –10– CXA3252N Electrical Characteristics Measurement Circuit (I2C bus control) +30V 22k 8200p 1.2k 6.8k 0.047µ 100p +5V 47k 3.3µ 1n 2.6φ 2.5t 0.5p 0.5p 1T363 7p XTAL 4MHz 47k 100p 32 31 30 29 28 27 1n 6p 26 25 24 23 22 2p 21 6p 20 19 18 17 47k 56p 56p 20 16p 47k 1p 1n 1T362 1T363 150p 47k 1T363 3.2φ 2.5t 1n 47k 51 0.75p 33p 47k 3.2φ 5.5t 1n 47k 51 IFOUT ADSW/CE VCC3 REFOSC IFOUT VCC2 VT VOSC2 UOSCB2 UOSCE2 UOSCE1 UOSCB1 CXA3252N BYP/MS MIXout1 MIXout2 UHFin1 15 1n 1n IFIN1 IFIN2 1 2 3 4 5 6 12p 12p 7 8 9 10 2k 11 12 13 14 16 UHFin2 1n UHF IN 200 200 200 240 240 240 240 4.5t 4.5t 56p 56p 2.2µ ADSW SCL SDA +5V 100 1n VHF IN Unmarked Ls are air coils with a wire diameter of 0.5 mm. –11– VHFin GND1 VCC1 BS3 BS1 BS2 BS4 DA CL VOSC1 CPO NC GND2 GND CXA3252N Electrical Characteristics Measurement Circuit (3-wire bus control) +30V 22k 8200p 1.2k 6.8k 0.047µ 100p +5V 47k 3.3µ 1n 2.6φ 2.5t 0.5p 0.5p 1T363 7p XTAL 4MHz 47k 100p 32 ADSW/CE 33p 47k 3.2φ 5.5t 3.2φ 2.5t 1n 47k 51 1n 47k 51 0.75p IFOUT 1T363 150p 47k 1T363 47k 56p 6p 2p 22 UOSCE2 1p 56p 6p 21 UOSCE1 1n 1T362 20 16p 1n 30 REFOSC 47k 31 VCC3 29 CPO 28 VT 27 NC 26 IFOUT 25 GND2 24 VCC2 23 UOSCB2 20 UOSCB1 19 VOSC2 18 GND UHFin1 17 VOSC1 CXA3252N BYP/MS MIXout1 MIXout2 IFIN1 IFIN2 1 2 3 4 5 6 12p 12p 7 8 9 10 2k 11 12 13 14 15 16 1n 240 240 4.5t 4.5t 1n 1n UHFin2 GND1 VHFin VCC1 BS3 BS1 BS2 BS4 DA CL 1n 200 200 200 240 240 56p 56p 2.2µ ADSW SCL SDA +5V 100 1n VHF IN UHF IN Unmarked Ls are air coils with a wire diameter of 0.5 mm. –12– CXA3252N Application Circuit (I2C bus control) +30V +5V 22k 4.7n 10k 100p 2.2n 10k 10k 100 SWD 3.2φ 1n 5.5t SWD 47k 1.2k 39k 82n 1.2k 47k 2p 10k 2.2φ 1.5t IFOUT 0.5p 10k XTAL 4MHz 3k 32 ADSW/CE 150p 1n 3.2φ 2.5t 0.5p 330p 1T363 1T363 15p 100p 16p 31 VCC3 ADSW 1n 10k 3.3µ 10p 1n 100p 5p 6p 21 UOSCE1 2p 1T362 20p 20 100p 30 REFOSC 29 CPO 28 VT 27 NC 26 IFOUT 25 GND2 24 VCC2 23 UOSCB2 22 UOSCE2 20 UOSCB1 19 VOSC2 18 GND UHFin1 17 VOSC1 CXA3252N BYP/MS MIXout1 MIXout2 IFIN1 IFIN2 1 2 3 4 3.2φ 7.5t 5 150p 6 7 8 VCC1 BS3 BS1 BS2 BS4 DA CL 9 10 2k 11 12 13 14 15 16 200 47p 47p 200 68p L1 56p 56p 1n 1n 1n 1000p 3.2φ 9.5t 1000p CL DA VHF IN UHF IN 100 3.3µ 1n 1n Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –13– UHFin2 VHFin GND1 CXA3252N Application Circuit (3-wire bus control) +30V +5V 22k 4.7n 10k 100p 2.2n 10k 10k 100 SWD 3.2φ 1n 5.5t SWD 47k 1.2k 39k 82n 1.2k 47k 2p 10k 2.2φ 1.5t IFOUT 0.5p 10k XTAL 4MHz 3k 32 ADSW/CE 150p 1n 3.2φ 2.5t 0.5p 330p 1T363 1T363 15p 100p 16p 31 VCC3 ADSW 1n 10k 3.3µ 10p 1n 100p 5p 6p 21 UOSCE1 2p 1T362 20p 20 100p 30 REFOSC 29 CPO 28 VT 27 NC 26 IFOUT 25 GND2 24 VCC2 23 UOSCB2 22 UOSCE2 20 UOSCB1 19 VOSC2 18 GND UHFin1 17 VOSC1 CXA3252N BYP/MS MIXout1 MIXout2 IFIN1 IFIN2 1 2 3 4 3.2φ 7.5t 5 150p 6 7 8 VCC1 BS3 BS1 BS2 BS4 DA CL 9 10 2k 11 12 13 14 15 16 200 47p 47p 200 68p L1 56p 56p 1n 1n 1n 1n 1000p 3.2φ 9.5t 1000p CL DA VHF IN UHF IN 100 3.3µ 1n 1n Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –14– UHFin2 VHFin GND1 CXA3252N Description of Functions The CXA3252N is a ground wave broadcast tuner IC which converts frequencies to IF in order to tune and detect only the desired reception frequency of VHF, CATV and UHF band signals. In addition to the mixer, local oscillation and IF amplifier circuits required for frequency conversion to IF, this IC also integrates a PLL circuit for local oscillation frequency control onto a single chip. The functions of the various circuits are described below. 1. Mixer circuit This circuit outputs the frequency difference between the signal input to VHFIN or UHFIN and the local oscillation signal. 2. Local oscillation circuit A VCO is formed by externally connecting an LC resonance circuit composed of a varicap diode and inductance. 3. IF amplifier circuit This circuit amplifies the mixer IF output, and consists of an amplifier stage and low impedance output stage. 4. PLL circuit This PLL circuit fixes the local oscillation frequency to the desired frequency. It consists of a programmable divider, reference divider, phase detector, charge pump and reference oscillator. The control format supports both the I2C bus and 3-wire bus formats. During I2C bus control, the frequency steps of 31.25, 50 or 62.5 kHz can be selected by the frequency division setting value of the data-based referencedivider. During 3-wire bus control, these frequency steps can be selected by the combination of the data length (18 or 19 bits) and the voltage applied to the BYP/MS pin. 5. Band switch circuit The CXA3252N has four sets of built-in PNP transistors for switching between the VL, VH and UHF bands and for switching the FM trap, etc. These PNP transistors can be controlled by the bus data. The emitters for these PNP transistors are connected to an independent power supply pin (VCC3) from the oscillator, mixer and PLL circuits, and support either 5 V or 9 V as the RF amplifier power supply. –15– CXA3252N Description of Analog Block Operation (See the Electrical Characteristics Measurement Circuit.) VHF oscillator circuit • This circuit is a differential amplifier type oscillator circuit. Pin 19 is the output and Pin 17 is the input. Oscillation is performed by connecting an LC resonance circuit including a varicap to Pin 19 via coupled capacitance, inputting to Pin 17 with feedback capacitance, and applying positive feedback. • The amplifier between Pins 17 and 19 has an extremely high gain. Therefore, care should be taken to avoid creating parasitic capacitance, resistance or other feedback loops as this may produce abnormal oscillation. VHF mixer circuit • The mixer circuit employs a double balanced mixer with little local oscillation signal leakage. The input format is base input type, with Pin 13 grounded via a capacitor and the RF signal input to Pin 14. (Pin 13 can also be used to switch the PLL mode according to the applied DC voltage value.) • The RF signal is converted to IF frequency by oscillator signal and output from Pins 10 and 11. Pins 10 and 11 are open collectors, so external power supply is necessary. In addition, single-tuned filters are connected to Pins 10 and 11. UHF oscillator circuit • This oscillator circuit is designed so that two collector ground type Colpitts oscillators perform differential oscillation operation via an LC resonance circuit including a varicap. • Resonance capacitance is connected between Pins 20 and 21, Pins 21 and 22, and Pins 22 and 23, and an LC resonance circuit including a varicap is connected between Pins 20 and 23. UHF mixer circuit • This circuit employs a double balanced mixer like the VHF mixer circuit. The input format is base input type, with Pins 15 and 16 as the RF input pins. The input method can be selected from balanced input consisting of differential input to Pins 15 and 16 or unbalanced input consisting of grounding Pin 15 via a capacitor and input to Pin 16. • Pins 10 and 11 are the mixer outputs. Pins 10 and 11 are open collectors, so external power supply is necessary. In addition, single-tuned filters are connected to Pins 10 and 11. IF amplifier circuit • Pins 5 and 6 are IF amplifier inputs with an input impedance of approximately 1 kΩ. • The signals frequency converted by the mixer are output from Pins 10 and 11, so Pins 10 and 11 are connected to Pins 5 and 6 via capacitors. ( A neighboring channel trap circuit can be formed by connecting a L and C parallel circuit instead of capacitors.) • The signal amplified by the IF amplifier is output from Pin 26. The output impedance is approximately 75 Ω. –16– CXA3252N Description of PLL Block This IC supports both I2C bus and 3-wire bus control. The I2C bus conforms to the standard I2C bus format, and bidirectional bus control is possible consisting of a write mode in which various data are received and a read mode in which various data are sent. The 3-wire bus is equipped with an 18- or 19-bit auto identify function, and the frequency step can be switched according to the voltage applied to the BYP/MS pin. The PLL of this IC does not have a fixed frequency division circuit and performs high-speed phase comparison, providing low reference leak and quick lock-up time characteristics. Pin Function Table Symbol CL DA ADSW/CE I2C bus SCL input SDA I/O Address selection 3-wire bus CLOCK input DATA input ENABLE input 1) PLL Mode Setting Method The selected control bus is set according to the BYP/MS pin (Pin 13) voltage. BYP/MS pin GND OPEN VCC Control bus I2C Bus 3-wire bus 3-wire bus During 3-wire bus control, the transferred bit length (18, 19 or 27 bits) is automatically identified. During 18- or 19-bit transfer, the frequency steps in the table below are set according to the combination of the BYP/MS pin voltage and the bit length. This IC does not have a fixed frequency division circuit, so the phase comparison frequency becomes the frequency step. BYP/MS Pin voltage OPEN OPEN or VCC VCC VCC Reference Divider 64 128 Selectable from 64, 80 or 128 80 80 Phase comparison frequency 62.5 kHz 31.25 kHz 62.5 kHz/ 50.0 kHz/ 31.25 kHz 50.0 kHz 50.0 kHz Frequency Step* 62.5 kHz 31.25 kHz 62.5 kHz/ 50.0 kHz/ 31.25 kHz 50.0 kHz 50.0 kHz Transfer bit length 18 19 27 18 19 * Phase comparison frequency and frequency step are for when the crystal oscillation=4 MHz. –17– CXA3252N 2) Programming The VCO lock frequency is obtained according to the following formula. fosc = fref × (32 M + S) fosc : local oscillator frequency fref : phase comparison frequency M : main divider frequency division ratio S : swallow counter frequency division ratio The variable frequency division ranges of M and S are as follows, and are set as binary. S < M ≤ 1023 (S < M ≤ 511 during 18-bit transfer) 0 ≤ S ≤ 31 3) I2C Bus Control This IC conforms to the standard I2C bus format, and bidirectional bus control is possible consisting of a write mode in which various data are received and a read mode in which various data are sent. Write and read modes are recognized according to the setting of the final bit (R/W bit) of the address byte. Write mode is set when the R/W bit is “0” and read mode is set when the R/W bit is “1”. –18– CXA3252N 3-1) Address settings Up to four addresses can be selected by the hardware bit settings, so that multiple PLL can exist within one system. The responding address can be set according to the ADSW/CE pin voltage. 1 Address “CE” pin voltage 0 to 0.1 VCC OPEN or 0.2 VCC to 0.3 VCC 0.4 VCC to 0.6 VCC 0.9 VCC to VCC Hardware bits 3-2) Write mode Write mode is used to receive various data. In this mode, byte 1 contains the address data, bytes 2 and 3 contain the frequency data, byte 4 contains the control data, and byte 5 contains the band switch data. These data are latch transferred in the manner of byte 1, byte 2 + byte 3, and byte 4 + byte 5. When the correct address is received and acknowledged, the data is recognized as frequency data if the first bit of the next byte is “0”, and as control data and band switch data if this bit is “1”. Also, when data transmission is stopped part-way, the previously programmed data is valid. Therefore, once the control and band switch data have been programmed, 3-byte commands consisting of the address and frequency data are possible. Further, even if the I2C bus stop conditions are not met, data can be input by sending the start conditions and the new address. MA1 0 0 1 1 MA0 0 1 0 1 1 0 0 0 MA1 MA0 R/W –19– CXA3252N The control format is as shown in the table below. Write-mode : Slave Receiver MSB MODE Address byte Divider byte 1 Divider byte 2 Control byte Band SW byte X : Don’t care bit7 1 0 M2 1 X bit6 1 M9 M1 CP X bit5 0 M8 M0 0 X bit4 0 M7 S4 CD X bit3 0 M6 S3 X BS4 bit2 MA1 M5 S2 R1 BS3 bit1 MA0 M4 S1 R0 BS2 LSB bit0 0 M3 S0 OS BS1 A A A A A A : MA0, MA1 : M0 to : S0 to : CD : OS : CP : BS1 to BS4 R0, R1 : Acknowledge bit address setting main divider frequency division ratio setting swallow counter frequency division ratio setting charge pump OFF (when “1”) varicap output OFF (when “1”) charge pump current switching (200 µA when “1”, 50 µA when “0”) : band switch control (output PNP transistor ON when “1”) reference divider frequency division ratio setting. (see the Reference Divider Frequency Division Ratio Table) Reference Divider Frequency Division Ratio Table R1 0 1 X X : Don’t care R0 1 1 0 Reference divider 128 64 80 –20– CXA3252N 3-3) Read mode In read mode, power- on reset operation status the phase comparator locked/unlocked status and 5-level A/ D converter input pin voltage status are transmitted and output to the master. The read data format is as shown in the table below. Read mode : Slave Transmitter MODE Address byte Status byte bit7 1 X bit6 1 FL bit5 0 1 bit4 0 1 bit3 0 1 bit2 MA1 0 bit1 MA0 0 bit0 1 0 A A A : Acknowledge bit MA0, MA1 : address setting FL : lock detection signal (1 : locked, 0 : unlocked) –21– CXA3252N Example of Representative Characteristics Circuit current vs. Supply voltage 1 60 58 56 54 52 50 48 46 44 42 40 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 10 4.6 4.8 5 5.2 5.4 VHF UHF 20 Circuit current vs. Supply voltage 2 DICC-Circuit current [mA] AICC-Circuit current [mA] 15 VCC1-Supply voltage [V] Band SW output voltage vs. Output current (BS1, BS2, BS3, BS4) 9.2 9.0 8.8 8.6 5.0 4.8 4.6 4.4 0 5 10 15 20 25 Output current [mA] I/O characteristics (Untuned input) 20 10 0 VCC2-Supply voltage [V] Band SW output voltage vs. Output current 9.2 9.0 8.8 8.6 5.0 4.8 4.6 4.4 0 1 2 3 4 5 6 Output current [mA] VCC3=5V VCC3=9V VCC3=9V Output voltage [V] VCC3=5V IF output level [dBm] –10 –20 –30 –40 –50 –60 –60 fRF=145MHz (VHF) fRF=495MHz (UHF) fIF is both f=45MHz –50 –40 –30 –20 –10 0 10 20 RF level [dBm] –22– Output voltage [V] CXA3252N Conversion gain vs. Reception frequency (Untuned input) 40 fIF=45MHz Noise figure vs. Reception frequency (Untuned input, in DSB) 20 fIF=45MHz CG-Conversion gain [dB] NF-Noise figure [dB] 30 VHF (Low) 20 VHF (High) UHF 15 VHF (Low) VHF (High) UHF 10 10 5 0 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] 0 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] CM-Cross modulation [dBµ] Next adjacent cross modulation vs. Reception frequency (Untuned input) 400 120 VHF (Low) VHF (High) UHF 300 100 200 80 60 40 20 0 0 100 200 300 400 500 600 700 800 900 Reception frequency [MHz] fIF=45MHz fUD=fD+12MHz fUD=fD–12MHz (100kHz, 30%AM) Oscillation frequency power supply fluctuation (PLL off) Vcc–5% Vcc+5% (Vcc=5V) VHF (Low) VHF (High) +B drift [kHz] 100 UHF 0 –100 –200 –300 –400 0 100 200 300 400 500 600 700 800 900 Oscillation frequency [MHz] PCS beat characteristics +20 +10 0 –10 fIF IF output level [dBm] –20 –30 fBeat –40 –50 –60 –70 –80 –40 VHF (Low) fLocal=95MHz fP=49.25MHz fC=52.83MHz (fP–12dB) fS=53.75MHz (fP–1.7dB) fIF=45.75MHz fBeat=fIF±920kHz –30 –20 –10 0 +10 +20 SG output level [dBm] (fP level) –23– CXA3252N Tuning Response Time 1 VHF (Low) 95MHz → VHF (High) 395MHz (CP=1) T=27.2msec 5.0V/div Offset 10.0V –40,0000ms 10,0000ms 10.0ms/div 60,0000ms real time VHF (Low) 95MHz → VHF (High) 395MHz (CP=0) T=75.6msec 5.0V/div Offset 10.0V –130,000ms 20,0000ms 30.0ms/div 170,000ms real time –24– CXA3252N Tuning Response Time 2 UHF 413MHz → UHF 847MHz (CP=1) T=34.2msec 5.0V/div Offset 10.0V –40,0000ms 10,0000ms 10.0ms/div 60,0000ms real time UHF 413MHz → UHF 847MHz (CP=0) T=86.0msec 5.0V/div Offset 10.0V –70,0000ms 30,0000ms 20.0ms/div 130,000ms real time –25– CXA3252N Tuning Response Time 3 VHF (High) 395MHz → VHF (Low) 95MHz (CP=1) T=12.6msec 5.0V/div Offset 10.0V –40,0000ms 10,0000ms 10.0ms/div 60,0000ms real time VHF (High) 395MHz → VHF (Low) 95MHz (CP=0) T=39.2msec 5.0V/div Offset 10.0V –100,000ms 0,00000ms 20.0ms/div 100,000ms real time –26– CXA3252N Tuning Response Time 4 UHF 847MHz → UHF 413MHz (CP=1) T=15.0msec 5.0V/div Offset 10.0V –40,0000ms 10,0000ms 20.0ms/div 600,000ms real time UHF 847MHz → UHF 413MHz (CP=0) T=50.0msec 5.0V/div Offset 10.0V –100,000ms 0,00000ms 20.0ms/div 100,000ms real time –27– CXA3252N IF output spectrum 10dB/div VHF (Low) fRF=55MHz fL0=100MHz RF input level : –40dBm CENTER 45.0MHz #RES BW 1.0kHz #VBW 10Hz SPAN 100.0kHz SWP 30.0 sec IF output spectrum 10dB/div VHF (High) fRF=350MHz fL.0=395MHz RF input level : –40dBm CENTER 45.0MHz #RES BW 1.0kHz #VBW 10Hz SPAN 100.0kHz SWP 30.0 sec –28– CXA3252N IF output spectrum 10dB/div UHF fRF=800MHz fL0=845MHz RF input level : –40dBm CENTER 45.0 270MHz #RES BW 1.0kHz #VBW 10Hz SPAN 100.0kHz SWP 30.0 sec –29– CXA3252N VHF Input Impedance j50 j25 j100 BYP/MS 0 50MHz 1000p 13 14 VHFin S11 16 350MHz –j25 –j100 –j50 UHF Input Impedance j50 j25 j100 UHFin1 0 1000p 15 UHFin2 S11 350MHz 800MHz –j25 –j100 –j50 –30– CXA3252N IF Output Impedance j50 j25 j100 45MHz 38MHz 0 –j25 –j100 –j50 –31– CXA3252N Package Outline Unit : mm 32PIN SSOP(PLASTIC) 11.0 0.1 x4 0.1 S A B A x2 17 B 0.2 S A B 1.45MAX S 32 5.6 7.6 A 1 0.1 16 0.65 0.13 M S A 0.25 0.1 ± 0.05 0.6 ± 0.15 0.1 S + 0.1 0.22 – 0.06 (0.22) B 0˚ to 8˚ DETAIL A (0.5) DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SSOP-32P-L01 SSOP032-P-0056 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUMA PLATING COPPER ALLOY 0.1g (0.15) + 0.05 0.15 – 0.02 Sony Corporation –32–