CXA3256R

CXA3256R 8-bit 120MSPS Flash A/D Converter Description The CXA3256R is an 8-bit high-speed flash A/D converter capable of digitizing analog signals at the maximum rate of 120MSPS. ECL, PECL or TTL can be selected as the digital input level in accordance with the application. The TTL digital output level allows 1: 2 demultiplexed output. The CXA3256R is easier to be used by adding the new functions to the CXA3246Q and adopting a ultra-small package. Features • Differential linearity error: ±0.5LSB or less • Integral linearity error: ±0.5LSB or less • High-speed operation with a maximum conversion rate of 120MSPS • Low input capacitance: 10pF • Wide analog input bandwidth: 250MHz • Low power consumption: 500mW • Power saving function • 1: 2 demultiplexed output • 1/2 frequency-divided clock output (with reset function) • Compatible with ECL, PECL and TTL digital input levels • TTL output "H" levels: 2.8V (Typ.) • Output voltage control function (VOCLP) • +3.3V line CMOS IC direct connecting available • Single +5V power supply operation available • Ultra-small surface mounting package (48-pin LQFP) DGND3 AGND VRM3 48 pin LQFP (Plastic) LEAD TREATMENT: PALLADIUM PLATING Structure Bipolar silicon monolithic IC Applications • Magnetic recording (PRML) • Communications (QPSK, QAM) • LCDs • Digital oscilloscopes AVCC 12 11 10 CLK/E 13 CLKN/E 14 CLK/T 15 SELECT2 16 VOCLP 17 PS 18 DVCC2 19 DGND2 20 PAD0 21 PAD1 22 PAD2 23 PAD3 24 9 8 7 6 5 VRB 2 4 3 DVEE3 1 48 RESETN/E 47 RESET/E 46 RESETN/T 45 SELECT1 44 INV 43 CLKOUT 42 DVCC2 41 DGND2 40 PBD7 39 PBD6 38 PBD5 37 PBD4 25 26 27 28 29 30 31 32 33 34 35 36 DGND2 PBD1 AGND AVCC VRM2 VRT VRM1 Pin Configuration (Top View) VIN PAD7 PAD5 DVCC1 PBD0 PAD4 PAD6 DGND1 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– DVCC2 PBD2 PBD3 E98305A8X-PS CXA3256R Absolute Maximum Ratings (Ta = 25°C) Unit AVCC, DVCC1, DVCC2 –0.5 to +7.0 V DGND3 –0.5 to +7.0 V DVEE3 –7.0 to +0.5 V DGND3 – DVEE3 –0.5 to +7.0 V VRT – 2.7 to AVCC V • Analog input voltage VIN • Reference input voltage VRT 2.7 to AVCC V VIN – 2.7 to AVCC V VRB |VRT – VRB| 2.5 V • Digital input voltage ECL/PECL input pin DVEE3 – 0.5 to DGND3 + 0.5 V V TTL input pin DGND1 – 0.5 to DVCC1 + 0.5 SELECT2 pin DGND1 – 0.5 to DVCC1 + 0.5 V V VOCLP pin DGND1 – 0.5 to DVCC1 + 0.5 VID∗1 (|∗∗∗/E – ∗∗∗N/E|) 2.7 V • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 1.4 W (when mounted on a two-layer glass fabric base epoxy board with dimentions of 50mm × 50mm, 1.6mm thick) • Supply voltage Recommended Operating Conditions With a single power supply With dual power supply Unit Min. Typ. Max. Min. Typ. Max. Supply voltage DVCC1, DVCC2, AVCC +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 V DGND1, DGND2, AGND –0.05 0 +0.05 –0.05 0 +0.05 V DGND3 +4.75 +5.0 +5.25 –0.05 0 +0.05 V –0.05 0 +0.05 –5.5 –5.0 –4.75 V DVEE3 Analog input voltage VIN VRB VRT VRB VRT V Reference input voltage VRT +2.9 +4.1 +2.9 +4.1 V VRB +1.4 +2.6 +1.4 +2.6 V |VRT – VRB| 1.5 2.1 1.5 2.1 V Digital input voltage ECL/PECL input pin : VIH DVEE3 + 1.5 DGND3 DVEE3 + 1.5 DGND3 V : VIL DVEE3 + 1.1 VIH – 0.4 DVEE3 + 1.1 VIH – 0.4 V TTL input pin : VIH 2.0 2.0 V : VIL 0.8 0.8 V SELECT2 pin : VIH DVCC1 DVCC1 V : VIL DGND1 DGND1 V VOCLP pin DGND1 + 2.4 DVCC1 DGND1 + 2.4 DVCC1 V VID∗1 (|∗∗∗/E – ∗∗∗N/E|) 0.4 0.8 0.4 0.8 V Maximum conversion rate Fc (Straight mode) 100 100 MSPS (DMUX mode) 120 120 MSPS Ambient temperature Ta –20 +75 –20 +75 °C • • • • • • ∗1 VID: Input Voltage Differential ECL and PECL switching level DGND3 VIH (max.) VIL VTH (DGND3 – 1.2V) VID VIH VIL (min.) –2– CXA3256R Pin Description [Symbol] DVEE3 VRB AGND VRM1 AVCC VIN VRM2 AVCC VRM3 AGND VRT DGND3 CLK/E CLKN/E CLK/T SELECT2 VOCLP PS DVCC2 DGND2 PAD0 to PAD7 DGND1 DVCC1 DVCC2 DGND2 PBD0 to PBD7 DGND2 DVCC2 CLKOUT INV SELECT1 RESETN/T RESET/E RESETN/E [Pin No.] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 to 28 29 30 31 32 33 to 40 41 42 43 44 45 46 47 48 [Description] Digital power supply Bottom reference voltage Analog ground Reference voltage mid point Analog power supply Typical voltage level with a single power supply Typical voltage level with dual power supply 0V –5.0V 1.4 to 2.6V 1.4 to 2.6V 0V 0V — — +5V +5V VRB to VRT VRB to VRT Analog signal input — — Reference voltage mid point Analog power supply +5V +5V Reference voltage mid point — — Analog ground 0V 0V Reference voltage (typ.) 2.9 to 4.1V 2.9 to 4.1V Digital power supply +5V 0V ECL/PECL clock input PECL ECL ECL/PECL clock input PECL ECL TTL clock input TTL TTL Data output switching DGND1 or Open or DVcc1 DGND1 or Open or DVcc1 TTL high level clamp Clamp voltage Clamp voltage Power saving TTL TTL Digital power supply +5V +5V Digital ground 0V 0V PA side data output TTL TTL Digital ground 0V 0V Digital power supply +5V +5V Digital power supply +5V +5V Digital ground 0V 0V PB side data output TTL TTL Digital ground 0V 0V Digital power supply +5V +5V Clock output TTL TTL Data output polarity inversion TTL TTL Output mode selection TTL TTL TTL reset input TTL TTL ECL/PECL reset input PECL ECL ECL/PECL reset input PECL ECL –3– CXA3256R Block Diagram AVCC 5 VRT 11 r1 r/2 r 1 INV 44 DVCC1 30 DVCC2 19 31 42 DGND3 12 8 (MSB) 40 PBD7 39 PBD6 2 r r VRM3 9 r • • • 63 6bit 38 PBD5 LATCH B TTLOUT 8bit 37 PBD4 36 PBD3 35 PBD2 64 r 65 r r • • • 126 6bit 34 PBD1 6bit LATCH + ENCODER 127 VRM2 7 VIN 6 r 128 r 129 ENCODER 33 PBD0 (LSB) (MSB) 28 PAD7 27 PAD6 26 PAD5 r VRM1 4 r • • • 191 6bit LATCH A LATCH B TTLOUT 192 r 193 25 PAD4 24 PAD3 23 PAD2 22 PAD1 8bit 6bit r r • • • 254 255 r2 VRB 2 CLK/T 15 CLK/E 13 CLKN/E 14 r/2 21 PAD0 (LSB) 16 SELECT2 17 VOCLP 18 PS D Q Q Select 43 CLKOUT RESETN/T 46 RESETN/E 48 RESET/E 47 3 10 AGND 45 SELECT1 29 DGND1 20 32 41 DGND2 1 DVEE3 –4– CXA3256R Pin Description and I/O Pin Equivalent Circuit Pin No. 3, 10 Symbol AGND I/O Standard voltage level GND +5V (typ.) GND +5V (typ.) +5V (typ.) (With a single power supply) GND (With dual power supply) GND (With a single power supply) –5V (typ.) (With dual power supply) DVCC1 Equivalent circuit Description Analog ground. Separated from the digital ground. Analog power supply. Separated from the digital power supply. Digital ground. Digital power supply. 5, 8 AVCC 20, 29 DGND1 32, 41 DGND2 19, 30 DVCC1 31, 42 DVCC2 12 DGND3 Digital power supply. Ground for ECL input. +5V for PECL and TTL inputs. 1 DVEE3 Digital power supply. –5V for ECL input. Ground for PECL and TTL inputs. 16 SELECT2 I DVCC1 or Open or DGND1 r r 16 r DGND1 Data output switching. Data is output from both the PA side and PB side by setting this pin open. When set to DVcc1 level, only the PA side output port outputs the data, makes the PB side high impedance. When set to DGND1 level, only the PB side output port outputs the data, makes the PA side high impedance. TTL output high level clamp. The TTL high level voltage is clamped to the approximately same value as the voltage applied to this pin. Even if this pin is left open, the TTL high level is clamped to approximately 2.8V. DVCC2 3k 17 VOCLP I Clamp voltage 3.5k 17 DGND2 –5– CXA3256R Pin No. Symbol I/O Standard voltage level DVCC1 Equivalent circuit Description 18 PS I TTL 18 Power saving. When left open, this pin goes to high level. When set to low level, the power saving state is established. DGND1 13 CLK/E I Clock input. CLK/E complementary input. When left open, this pin goes to the threshold voltage. Only CLK/E can be used for operation, but complementary inputs are recommended to attain fast and stable operation. Reset signal input. When set to low level, the built-in CLK frequency divider circuit can be reset. RESETN/E complementary input. When left open, this pin goes to the threshold voltage. Only RESETN/E can be used for operation. Clock input. TTL Reset signal input. When left open, this pin goes to high level. When set to low level, the built-in CLK frequency divider circuit can be reset. Data output polarity inversion input. When left open, this input goes to high level. (See Table 1. I/O Correspondence Table.) Data output mode selection. (See Table 2. Operation Mode Table.) 14 CLKN/E I DGND3 ECL/ PECL 48 RESETN/E I 13 48 14 47 DVEE3 47 RESET/E I 15 CLK/T I DVCC1 46 RESETN/T I 44 INV I TTL 15 46 or 44 , 45 DGND1 DVEE3 1.5V 45 SELECT1 Vcc or GND –6– CXA3256R Pin No. Symbol I/O Standard voltage level 4.0V (typ.) Equivalent circuit Description Top reference voltage. By-pass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. Reference voltage mid point. By-pass to AGND with a 0.1µF chip capacitor. Reference voltage mid point. By-pass to AGND with a 0.1µF chip capacitor. Reference voltage mid point. By-pass to AGND with a 0.1µF chip capacitor. Bottom reference voltage. By-pass to AGND with a 1µF tantal capacitor and a 0.1µF chip capacitor. 11 VRT I r1 11 r/2 r 9 VRM3 VRB + 3 (VRT – VRB) 4 9 r r Comparator 1 Comparator 63 Comparator 64 7 VRM2 VRB + 2 (VRT – VRB) 4 7 r Comparator 127 Comparator 128 VRB + 4 VRM1 1 (VRT – VRB) 4 4 r Comparator 191 Comparator 192 r Comparator 255 r/2 2 r2 2 VRB I 2.0V (typ.) AVCC Comparator AVCC 6 VIN I VRT to VRB Analog input. 6 Vref DVEE3 AGND 21 to 28 33 to 40 PAD0 to PAD7 PBD0 to PBD7 O DVCC1 DVCC2 Port A side data output. TTL output; the high level is clamped to approximately 2.8V. Port B side data output. TTL output; the high level is clamped to approximately 2.8V. Clock output. (See Table 2. Operation Mode Table.) TTL output; the high level is clamped to approximately 2.8V. O 21 to 28 TTL 100k 33 to 40 43 DGND2 DVEE3 DGND1 43 CLKOUT O –7– CXA3256R Electrical Characteristics (AVCC, DVCC1, 2, DGND3 = +5V, AGND, DGND1, 2, DVEE3 = 0V, VRT = 4V, VRB = 2V, Ta = 25°C) Item Resolution DC characteristics Integral linearity error Differential linearity error Analog input Analog input capacitance Analog input resistance Analog input current Reference input Reference resistance Reference current Offset voltage VRT side VRB side Digital input (ECL, PECL) Digital input voltage: High : Low Threshold voltage Digital input current : High : Low Digital input capacitance Digital input (TTL) Digital input voltage: High : Low Threshold voltage Digital input current : High : Low Digital input capacitance Digital output (TTL) Digital output voltage : High : Low Switching characteristics Maximum conversion rate Aperture jitter Sampling delay Clock high pulse width Clock low pulse width Reset signal setup time Reset signal hold time Clock output delay Data output delay Output rise time Output fall time EIL EDL CIN RIN IIN Rref∗2 Iref∗3 EOT EOB VIH VIL VTH IIH IIL Symbol Conditions Min. Typ. 8 ±0.5 ±0.5 10 20 100 600 3.3 8 1.5 Max. Unit bits LSB LSB pF kΩ µA Ω mA mV mV V V V µA µA pF V V V µA µA pF VIN = 2Vp-p, Fc = 5MSPS VIN = +3.0V + 0.07Vrms 7 0 400 2.7 6 0 DVEE3 + 1.5 DVEE3 + 1.1 40 285 740 5.0 10 3 DGND3 VIH – 0.4 DGND3 – 1.2 VIH = DGND3 – 0.8V VIL = DGND3 – 1.6V –50 –50 20 20 5 VIH VIL VTH IIH IIL 2.0 1.5 VIH = 3.5V VIL = 0.2V –10 –20 0.8 5 0 5 VOH VOL Fc Taj Tds Tpw1 Tpw0 T_rs T_rh Td_clk Tdo1 Tdo2 Tr Tf IOH = –2mA IOL = 1mA DMUX mode 2.4 0.5 120 1.2 3.0 4.5 1.0 –0.5 3.0 3.5 10 1.4 1.6 V V MSPS ps ns ns ns ns ns ns ns ns ns ns CLK CLK RESETN – CLK RESETN – CLK DMUX mode 0.8 to 2.0V 0.8 to 2.0V (CL = 5pF) (CL = 5pF) (CL = 5pF) (CL = 5pF) (CL = 5pF) 4.5 T∗4 + 0.5 5.0 1 1 7.0 7.5 ∗ These characteristics are for PECL input unless otherwise specified. –8– CXA3256R Item Dynamic characteristics Input bandwidth SNR Symbol Conditions VIN = 2Vp-p, –3dB Fc = 120MSPS, fin = 1kHz Fs DMUX mode Fc = 120MSPS, fin = 29.999MHz Fs DMUX mode Fc = 120MSPS, fin = 1kHz Fs DMUX mode Error > 16LSB Fc = 120MSPS, fin = 29.999MHz Fs DMUX mode Error > 16LSB Fc = 100MSPS, fin = 24.999MHz Fs Straight mode Error > 16LSB Min. 250 Typ. Max. Unit MHz dB { { 46 42 dB TPS∗5 Error rate { { { ICC + IEE AICC DICC1 DICC2 IEE ICC+IEE AICC DICC1 DICC2 IEE 10–12 10–9 TPS 10–9 TPS Power supply Supply current AVcc Pin supply current DVcc1 pin supply current DVcc2 pin supply current DGND3 pin supply current Supply current for PS AVcc pin supply current for PS DVcc1 pin supply current for PS DVcc2 pin supply current for PS DGND3 pin supply current for PS 70 45 20 5 0.5 98 140 87 36 15 1.5 5 1.5 1.5 1.5 0.5 mA mA mA mA mA mA mA mA mA mA mW mW Power consumption Pd∗6 Power consumption for PS Pd∗7 ∗2 Rref: Resistance value between VRT and VRB ∗3 Iref = VRT – VRB Rref ∗4 T = 1 Fc ∗5 TPS: Times Per Sample 2 ∗6 Pd = (ICC + IEE) · VCC + (VRT – VRB) Rref ∗7 Pd = (ICC + IEE) · VCC 400 0.3 500 700 25 –9– CXA3256R INV VIN Step D7 VRT 255 254 . . . 128 127 . . . 1 0 11111 11111 . . . 10000 01111 . . . 00000 00000 1 D0 D7 111 110 000 111 001 000 00000 00000 . . . 01111 10000 . . . 11111 11111 0 D0 000 001 111 000 110 111 VRM2 VRB Table 1. I/O Correspondence Table – 10 – CXA3256R Electrical Characteristics Measurement Circuit Current Consumption Measurement Circuit 5V Icc 4V VRT AVCC DVCC1 DVCC2 PS 5V IEE DGND3 Sampling Delay Measurement Circuit Aperture Jitter Measurement Circuit 100MHz Amp OSC1 φ: Variable VIN fr CLK CXA3256R 8 Logic Analizer 1024 samples ECL Buffer 1.95V VIN CLK/E 5MHz PECL OSC2 2V VRB DGND2 DGND1 AGND DVEE3 100MHz Integral Linearity Error Measurement Circuit Differential Linearity Error Measurement Circuit +V Aperture Jitter Measurement Method VRT VIN VRM2 VRB S1: ON when A < B S2: ON when A > B CLK ∆υ ∆t 129 128 127 126 125 S2 S1 –V AB Comparator VIN CXA3256R 8 A8 to A1 A0 “0” DVM Controller B8 to B1 B0 “1” 000···00 to 111···10 8 Buffer CLK VIN σ (LSB) Sampling timing fluctuation (= aperture jitter) Where σ (LSB) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter Taj is: Taj = σ/ ∆υ ∆t A B Comparator A>B Pulse Counter = σ/ ( 256 × 2πf ) 2 Error Rate Measurement Circuit Signal Source VIN 8 CXA3256R CLK CLK Latch Fc – 1kHz 4 2Vp-p Sine Wave + Latch 16LSB Signal Source Fc 1/8 – 11 – CXA3256R Description of Operation Modes The CXA3256R has two types of operation modes which are selected with Pin 45 (SELECT). Operation mode DMUX mode Straight mode SELECT1 Maximum pin conversion rate VCC GND 120MSPS 100MSPS Data output Demultiplexed output 60Mbps Straight output 100Mbps Clock output The input clock is 1/2 frequency divided and output. 60MHz The input clock is inverted and output. 100MHz Table 2. Operation Mode Table 1. DMUX mode (See Application Circuit 1-(1), (2) and (3).) Set the SELECT1 pin to Vcc for this mode. In this mode, the clock frequency is divided by 2 in the IC, and the data is output after being demultiplexed by this 1/2 frequency-divided clock. The 1/2 frequency-divided clock, which has adequate setup time and hold time for the output data, is output from the clock output pin. When using the multiple CXA3256R in DMUX mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example on the next page. As a countermeasure, the CXA3256R has a function that resets the 1/2 frequency-divided clocks. When resetting this 1/2 frequency-divided clock, the low level of the reset signal should be input to the RESETN pin (Pin 46 or 48). The reset signal requires the setup time (T_rs ≥ 1.0ns) and hold time (T_rh ≥ –0.5ns) to the clock rising edge because it is synchronized with and taken in the clock. The reset period can be extended by making the low level period of the reset signal longer because the clock output pin is fixed to low (reset) during the low level period at the clock rising edge. If the reset start timing is regarded as not important, the timing where the reset signal is set from high to low is not so consequence. However, when the reset is released the timing where the reset signal is set from low to high must become significant because the timing is used to commence the 1/2 frequency-divided clock. In this case, the setup time (T_rs) is also necessary. See the timing chart for detail. (This chart shows the example of reset for 2T.) The A/D converter can operate at Fc (min.) = 120MSPS in this mode. – 12 – CXA3256R When the reset signal is not used CLK CXA3256R CLK CLK CLKOUT 8bit DATA AA RESETN CXA3256R CLK CLKOUT 8bit DATA BB RESETN When the reset signal is used CLK Reset signal CXA3256R CLK CLK RESETN CLKOUT 8bit DATA (Reset period) A CXA3256R CLK CLKOUT 8bit DATA (Reset period) B Reset signal RESETN 2. Straight mode (See Application Circuits 1-(4), (5) and (6).) Set the SELECT1 pin to GND for this mode. In this mode, data output can be obtained in accordance with the clock frequency applied to the A/D converter for applications which use the clock applied to the A/D converter as the system clock. The A/D converter can operate at Fc (min.) = 100MSPS in this mode. Digital input level and supply voltage settings The logic input level for the CXA3256R supports ECL, PECL and TTL levels. The power supplies (DVEE3, DGND3) for the logic input block must be set to match the logic input (CLK and reset signals) level. Digital input level ECL PECL TTL DVEE3 –5V 0V 0V DGND3 0V +5V +5V Supply voltage Application circuits ±5V +5V +5V (1) (4) (2) (5) (3) (6) Table 3. Logic Input Level and Power Supply Settings Description of SELECT2 pin The CXA3256R has the two systems of data output. The SELECT2 pin is used to select the port where the data is output. SELECT2 pin Open Vcc1 GND1 Data output Output possible to both PA and PB Output possible to PA, and PB output is high impedance. Output possible to PB, and PA output is high impedance. – 13 – CXA3256R Application Circuit 1 (1) DMUX ECL input ECL RESET signal +5V(D) DG +5V(A) –5V(D) AG AG AG 48 47 46 45 44 43 42 41 40 39 38 37 1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 PAD0 to PAD7 8 bit Digital Data Latch 2 3 4 5 6 7 8 9 PBD0 to PBD7 8 bit Digital Data Latch 8 bit Digital Data 2V DG DG +5V(D) +5V(A) DG AG AG 10 4V 11 12 8 bit Digital Data ECL-CLK DG +5V(D) (2) DMUX PECL input PECL RESET signal +5V(D) DG +5V(A) AG AG DG AG 48 47 46 45 44 43 42 41 40 39 38 37 1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 10 PBD0 to PBD7 8 bit Digital Data Latch 8 bit Digital Data 2V DG DG +5V(D) +5V(D) AG AG +5V(A) 4V 11 12 8 bit Digital Data PAD0 to PAD7 8 bit Digital Data Latch PECL-CLK DG +5V(D) (3) DMUX TTL input +5V(D) DG TTL RESET signal AG AG DG 48 47 46 45 44 43 42 41 40 39 38 37 1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 10 PBD0 to PBD7 8 bit Digital Data Latch 8 bit Digital Data +5V(A) AG 2V DG DG +5V(D) +5V(D) +5V(A) AG AG 4V 11 12 8 bit Digital Data PAD0 to PAD7 8 bit Digital Data Latch TTL-CLK DG +5V(D) – 14 – CXA3256R (4) Straight ECL input DG +5V(D) DG –5V(D) AG AG 48 47 46 45 44 43 42 41 40 39 38 37 1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 PBD0 to PBD7 8 bit Digital Data Latch 8 bit Digital Data +5V(A) AG 2V DG DG +5V(D) +5V(A) DG AG AG 10 4V 11 12 ECL-CLK ECL → TTL DG DG +5V(D) (5) Straight PECL input DG +5V(D) DG +5V(A) AG AG DG AG 48 47 46 45 44 43 42 41 40 39 38 37 1 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 2 3 4 5 6 7 8 9 10 PBD0 to PBD7 8 bit Digital Data Latch 8 bit Digital Data 2V DG DG DG +5V(D) +5V(A) +5V(D) AG AG 4V 11 12 PECL-CLK PECL → TTL DG DG +5V(D) (6) Straight TTL input DG +5V(D) DG +5V(A) AG AG DG AG 48 47 46 45 44 43 42 41 40 39 38 37 1 2V 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 8 bit Digital Data PAD0 to PAD7 8 bit Digital Data Latch 2 3 4 5 6 7 8 9 10 +5V(D) AG AG +5V(A) 4V 11 12 TTL-CLK DG +5V(D) +5V(D) – 15 – DG +5V(D) CXA3256R Application Circuit 2 DMUX Mode TTL I/O (When a single power supply is used) AG Analog input 4V AG +5V (D) DG 1µF AG 10µF short short 10µF +5V (A) AG 2V 1µF AG 12 11 10 9 8 7 6 5 4 3 2 1 DGND3 AGND 13 CLK/E RESETN/E 48 RESET/E 47 RESETN/T 46 SELECT1 45 INV 44 CLKOUT 43 DVCC2 42 DGND2 41 PBD7 40 PBD6 39 PBD5 38 C∗ 14 CLKN/E 15 CLK/T TTL CLK 16 SELECT2 17 VOCLP Clamp voltage 18 PS C∗ 19 DVCC2 20 DGND2 21 PAD0 22 PAD1 23 PAD2 DGND1 DGND2 DVCC1 DVCC2 24 PAD3 DVEE3 PBD4 37 36 VRT AGND VRM3 AVCC VRM2 VIN AVCC VRM1 PBD0 PBD1 VRB 35 PAD4 PAD5 PAD6 PAD7 25 26 27 28 29 30 31 32 33 34 C∗ PBD2 PBD3 (MSB) PAD7 Short the analog system and digital system at one point immediately under the A/D converter. See the Notes on Operation. is the chip capacitor of 0.1µF. Also, C∗ is important to suppress the noise generated during the TTL output circuit is operating. Place C∗ at the fixed position between the pins with the shortest distance. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 16 – PBD6 (MSB) PBD7 (LSB) PAD0 PAD1 (LSB) PBD0 PAD2 PAD3 PBD3 PBD4 PBD5 PAD4 PAD5 PAD6 PBD1 PBD2 CXA3256R DMUX Mode Timing Chart (Select = VCC) Tds N–2 VIN (Pin 6) N–1 T N N+2 N+3 1.4ns (typ.) N+4 N +5 N+6 N+1 CLK (Pin 13) Tpw1 Tpw0 Tdo2; 5.0ns (typ.) 3.5ns (min) 7.5ns (max) PAD0 to D7 (Pins 21 to 28) 2.0V 0.8V N N+2 PBD0 to D7 (Pins 33 to 40) Td_clk; 4.5ns (typ.) 7.0ns (max) 3.0ns (min) CLK OUT (Pin 43) 2.0V 0.8V 2.0V 0.8V N+1 Tdo1 T + 0.5ns (typ.) 2.0V 0.8V ≈T N+3 ≈T (Reset period) 2.0V 0.8V T_rh RESETN (Pin 48) T_rs T_rh T_rs – 17 – CXA3256R Straight Mode Timing Chart (Select = GND) N–1 VIN (Pin 6) Tds 1.4ns (typ.) T N N+1 N+2 N+3 CLK (Pin 13) Tpw1 Tpw0 Tdo2; 5.0ns (typ.) 3.5ns (min) 7.5ns (max) PAD0 to D7 (Pins 21 to 28) N–4 2.0V 0.8V N–3 N–2 N–1 N PBD0 to D7 (Pins 33 to 40) N–3 2.0V 0.8V N–2 N–1 N N+1 Td_clk; 4.5ns (typ.) 3.0ns (min) 7.0ns (max) CLK OUT (CLK is inverted and output.) (Pin 43) 2.0V 0.8V – 18 – CXA3256R Notes on Operation • The CXA3256R has the PECL and TTL input pins for the clock and reset input pins. When the clock is input in PECL level, inputting the reset signal in PECL level is recommended. Also, when the clock is input in TTL level, inputting the reset signal in TTL is recommended. • The impedance of the input signal should be properly matched to ensure the CXA3256R's stable operation at the high speed. • In the CXA3256R, all the TTL input pins become the high level when left open. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation. General points for caution are as follows. — The ground pattern should be as large as possible. It is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. — To prevent interference between AGND and DGND and between AVcc and DVcc, make sure the respective patterns are separated. To prevent a DC offset in the power supply pattern, connect the AVcc and DVcc lines at one point each via a ferrite-bead filter, etc. Shorting the AGND and DGND patterns in one place immediately under the A/D converter improves A/D converter performance. — Be sure to turn the analog and digital power supplies on simultaneously. If not simultaneously, the IC does not operate correctly. — Ground the power supply pins (AVcc, DVcc1, DVcc2, DVEE3) as close to each pin as possible with a 0.1µF or larger ceramic chip capacitor. (Connect the AVcc pin to the AGND pattern and the DVcc1, DVcc2 and DVEE3 pins to the DGND pattern.) — It is recommended to place the ceramic chip capacitor of 0.1µF or more, in particular, between DVcc2 and DGND2 with the shortest distance. This has the effect to suppress the noise generated when the CXA3256R TTL output circuit operates. — The digital output wiring should be as short as possible. If the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. • The analog input pin VIN has an input capacitance of approximately 10pF. To drive the A/D converter with the proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit, keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. • The VRT and VRB pins must have adequate by-pass to protect them from high-frequency noise. By-pass them to AGND with approximately 1µF tantal capacitor and 0.1µF chip capacitor as short as possible. • If the CLKN/E pin is not used, by-pass this pin to DGND with an approximately 0.1µF capacitor. At this time, approximately DGND3 – 1.2V voltage is generated. However, this is not recommended for use as the threshold voltage VBB because it is too weak. – 19 – CXA3256R • When the digital input level is ECL or PECL level, ∗∗∗/E pins should be used and ∗∗∗/T pins left open. When the digital input level is TTL, ∗∗∗/T pins should be used and ∗∗∗/E pins left open. • The CXA3256R TTL output high level is clamped to approximately 2.8 V in the IC.This makes it possible to directly interface with the 3.3V system CMOS IC. However,the CXA3256R has the VOCLP pin which is used to clamp the TTL output high level. See the Example of Representative Characteristics for the relationship between the VOCLP pin and the TTL high level. • The CXA3026Q has the output pins P1∗∗ and P2∗∗. However, in the CXA3256R, these symbols are changed as PA∗∗and PB∗∗. At this time, the P1 side of the CXA3026Q is changed to the PB side for the CXA3256R; the P2 side of the CXA3026Q to the PA side for the CXA3256R. • The pipeline delay of the CXA3256R is smaller by one clock, compared to that of CXA3026Q. – 20 – CXA3256R Example of Representative Characteristics Current consumption vs. Ambient temperature characteristics 110 110 Current consumption vs. Conversion rate characteristics Current consumption [mA] 105 Current consumption [mA] 105 fCLK – 1kHz 4 100 100 fin = DMUX mode CL = 5pF 95 95 90 –25 25 Ta – Ambient temperature [°C] 75 90 0 60 Fc – Conversion rate [MSPS] 120 Analog input current vs. Analog input voltage characteristics 4 100 Reference current vs. Ambient temperature characteristics Analog input current [µA] VRT = 4V VRB = 2V Reference current [mA] 3 4 3 50 2 0 2 –25 25 Ta – Ambient temperature [°C] 75 Analog input voltage [V] – 21 – CXA3256R SNR vs. Input frequency response 50 Error rate vs. Conversion rate characteristics 10–6 fCLK – 1kHz 4 40 10–7 fin = Error Rate [TPS] Error > 16LSB 10–8 SNR [dB] 30 Fc = 120MSPS 10–9 20 1 3 5 10 30 50 10–10 120 140 Fc – Conversion rate [MSPS] 160 Input frequency [MHz] Maximum conversion rate vs. Ambient temperature characteristics Fc – Maximum conversion rate [MSPS] 170 fCLK – 1kHz 4 Error > 16LSB Error rate: 10–9 TPS fin = 3 TTL output high level vs. VOCLP pin 160 TTL output high level [V] TTL high level when VOCLP is open. 2 150 140 1 130 –25 25 Ta – Ambient temperature [°C] 75 0.5 1 3 VOCLP pin voltage [V] 5 – 22 – CXA3256R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.2 ∗ 36 37 7.0 ± 0.1 25 24 S (8.0) A 48 1 0.5 + 0.08 0.18 – 0.03 + 0.2 1.5 – 0.1 12 13 (0.22) + 0.05 0.127 – 0.02 0.13 M 0.1 ± 0.1 0.1 0.5 ± 0.2 S 0° to 10° 0.5 ± 0.2 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 23 –