CXA3328EN

CXA3328TN/EN Analog Signal Processor RX-IF IC for W-CDMA Cellular Phones Description The CXA3328TN/EN is an analog signal processor RX-IF IC for W-CDMA cellular phones. This IC contains a gain control amplifier and quadrature demodulator. Features • Wide gain control range • Linear gain slope • Wide band (100 to 600MHz) • Small package 16-pin TSSOP (CXA3328TN) 16-pin VSON (CXA3328EN) • Low voltage operation (2.7 to 3.3V) Absolute Maximum Ratings • Supply voltage VCC • Operating temperature Topr • Storage temperature Tstg Operating Conditions • Supply voltage • Operating temperature 16 pin TSSOP (Plastic) 16 pin VSON (Plastic) –0.3 to 5.5 –55 to +125 –65 to +150 V °C °C VCC Ta 2.7 to 3.3 –25 to +85 V °C Structure Bipolar silicon monolithic IC GND_BUF GND_BUF VCC_BUF Block Diagram VCONT QX IX Q 16 15 14 13 12 11 10 AGC CONT SWITCH 1/2 1/4 1 2 3 4 5 6 7 VCC_IF LOCAL SW LOCAL IN GND_IF Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. GND_IF –1– E00738D24-PS GND_R IN INX I 9 8 CXA3328TN/EN Pin Description Pin No. Symbol Typical pin voltage [V] Equivalent Circuit Vcc_IF Pin Description 20k 1 2 1, 2 IN, INX 2.85 20k IF differential input. GND_IF 3, 4 5 GND_IF Vcc_IF 0 2.85 Vcc_IF GCA, quadrature demodulator block ground. GCA, quadrature demodulator block VCC. 30k 6 6 LOCAL SW — Local frequency division ratio setting. High: 1/4 frequency division Low: 1/2 frequency division GND_IF Vcc_IF 2k 7 7 LOCAL IN — 50 0.5k 2k Local input. GND_R GND_IF 8 GND_R 0 Vcc_BUF Local signal GND. 9, 10, 12, 13 I, IX, Q, QX 9 1.5 10 12 13 Baseband I, Q outputs. GND_BUF –2– CXA3328TN/EN Pin No. 11, 14 15 Symbol GND_BUF Vcc_BUF Typical pin voltage [V] 0 2.85 Equivalent Circuit Pin Description Output buffer block ground. Output buffer block VCC. Vcc_IF 16k 16k 40k 16 VCONT — 16 Gain control voltage input. 12k 12k GND_IF –3– CXA3328TN/EN Electrical Characteristics Current Consumption Item Current Consumption Symbol Icc Conditions Vcont = 1.3V MeasureMeasurement circuit ment point 1 A Min. 8 (VCC = 2.85V, Ta = 27°C) Typ. 11 Max. 15 Unit mA I/O Resistance Item Input resistance VCONT pin LO input resistance Symbol RIVC RILO Conditions DC measurement: VIN = 2.85V DC measurement: IIN = 2mA DC measurement: IOUT = 100µA MeasureMeasurement circuit ment point 1 1 1 B C D, E F, G Min. 10 37.5 80 (VCC = 2.85V, Ta = 27°C) Typ. — 50 250 Max. — 62.5 550 Unit kΩ Ω Ω Output resistance ZOUT I, IX, Q, QX pins IF I/O Resistance (Design Values) Item IF input resistance IF input capacitance Symbol RIIF CIIF Conditions Differential between Pins 1 and 2 380MHz Differential between Pins 1 and 2 380MHz Min. — — (VCC = 2.85V, Ta = 27°C) Typ. 2.6 2 Max. — — Unit kΩ pF Input Conditions Item IF input frequency 1 IF input frequency 2 LO input frequency LO input level Symbol FRXIF1 FRXIF2 FLO VLO Conditions LOCAL SW = “L” LOCAL SW = “H” Min. — — — –18 (VCC = 2.85V, Ta = 27°C) Typ. 380 190 760 –15 Max. — — — –12 Unit MHz MHz MHz dBm –4– CXA3328TN/EN GCA Block Item Input conversion noise figure Symbol NF Conditions Gain = +65dB Measure- Measurement circuit ment point 3 A, B C, D A, B C, D (VCC = 2.85V, Ta = 27°C) Min. — Typ. — Max. 10 Unit dB Input conversion 3rd intercept point Gain = +65dB FRXIF = 382MHz IIP3_1 FLO = 760MHz LOCAL SW = “L” Gain = –10dB FRXIF = 382MHz IIP3_2 FLO = 760MHz LOCAL SW = “L” GF FRXIF = 382 ± 2.5MHz LOCAL SW = “L” FLO = 2 × (FRXIF + 2) MHz Vcont = 0.3 [V], 30mVp-p differential output FRXIF = 382MHz FLO = 760MHz LOCAL SW = “L” Vcont = 2.3 [V], 100mVp-p differential output FRXIF = 382MHz FLO = 760MHz LOCAL SW = “L” Ta = –25 to +85°C 2 –58 — — dBm 2 A, B C, D A, B C, D –10 — — dBm Gain flatness 2 –0.25 — 0.25 dB Minimum gain GMIN 2 A, B C, D — –25.5 –20.5 dB Maximum gain GMAX 2 A, B C, D A, B C, D 67.5 72.5 — dB Gain temperature error GERR 2 –4 — 4 dB –5– CXA3328TN/EN Quadrature Demodulator Block Item I/Q maximum output amplitude I/Q output band width I/Q phase error Symbol Conditions RL = 10kΩ, CL = 10pF FRXIF = 382MHz FLO = 760MHz LOCAL SW = “L” –3dB band width FRXIF = 382MHz FLO = 760MHz LOCAL SW = “L” FRXIF = 382MHz FLO = 760MHz LOCAL SW = “L” DC measurement MeasureMeasurement circuit ment point 2 A, B C, D A, B C, D A, B C, D A, B C, D A, B C, D (VCC = 2.85V, Ta = 27°C) Min. Typ. Max. Unit VMAX 500 — — mVp-p VBW PERR 2 2 5 –4 13 — — 4 MHz deg I/Q output VBL amplitude balance I-IX/Q-QX DC offset VOFST 2 2 –1.5 –200 — — 1.5 200 dB mV Local Frequency Division Ratio LOCAL SW (Pin 6) L H Frequency division ratio 1/2 1/4 –6– CXA3328TN/EN Electrical Characteristics Measurement Circuit 1 B GND_BUF VCC_BUF VCONT G F GND_BUF E D QX IX Q 16 15 14 13 12 11 10 I 9 AGC CONT SWITCH 1/2 1/4 1 IN INX 2 GND_IF 3 4 GND_IF VCC_IF 5 LOCAL SW 6 LOCAL IN 7 GND_R 8 ∗1 82n 100p 1µ 600 ∗2 TRANS 50 : 500Ω FRXIF C A ∗1 LQN21A (MURATA MFG. CO., LTD.) ∗2 616DS-1135 (TOKO, Inc.) –7– CXA3328TN/EN Electrical Characteristics Measurement Circuit 2 D 10k 10000p VCC_BUF VCONT GND_BUF C 10k 10000p 10p GND B 10k 10000p 10p IX A 10k 10000p 10p I 10p QX Q 16 15 14 13 12 11 10 9 AGC CONT SWITCH 1/2 1/4 1 IN INX 2 GND_IF 3 4 GND_IF VCC_IF 5 LOCAL SW 6 LOCAL IN 7 GND_R 8 ∗1 82n 100p 1µ 600 ∗2 TRANS 50 : 500Ω FRXIF FLO ∗1 MURATA LQN21A ∗2 TOKO 616DS-1135 –8– CXA3328TN/EN Electrical Characteristics Measurement Circuit 3 D 10k 10000p GND_BUF VCC_BUF VCONT C 10k 10000p 10p GND B 10k 10000p 10p IX A 10k 10000p 10p I 10p QX Q 16 15 14 13 12 11 10 9 AGC CONT SWITCH 1/2 1/4 1 IN INX 2 GND_IF 3 4 GND_IF VCC_IF 5 LOCAL SW 6 LOCAL IN 7 GND_R 8 ∗1 82n 100p 600 1µ FLO ∗1 MURATA LQN21A –9– CXA3328TN/EN Application Circuit To LPF Vcc GND_BUF GND_BUF VCC_BUF VCONT QX IX Q 16 15 14 13 12 11 10 I 9 AGC CONT SWITCH 1/2 1/4 1 IN INX 2 GND_IF 3 GND_IF 4 VCC_IF 5 LOCAL SW 6 LOCAL IN 7 GND_R 8 ∗ ∗ RX BPF From receive RF circuit Vcc Local signal ∗ Adjust this value so that the impedance matching with this IC is optimum. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXA3328TN/EN Description of Operation 1. Outline of Operation This IC performs the signal processing between the analog transmit baseband processing block and the analog transmit RF processing block of the cellular phone. The figure below shows the general circuit block diagram for the portable cellular phone using this IC. The input of this IC is connected to the analog RF processing block; the output is connected to the baseband signal processing block. CXA3328TN/EN LPF RF receive/transmit processing CXG1110EN Digital processing mobile station modem CODEC CXA3309ER LPF 2. IC Internal Signal Flow An IF signal and a local signal are input to this IC as shown in the figure below. The IF signal is gaincontrolled to the necessary level by the gain control amplifier and is input to the quadrature demodulator block. The local signal is 1/2 or 1/4 frequency-divided. Also, that signal becomes the quadrature I/Q local signal via the FF phase shifter and quadrature-demodulated with the IF signal to become the baseband signal. OUT (I) IF OUT (Q) 1/2 Local 1/4 Phase Shifter, Switch – 11 – CXA3328TN/EN Notes on Operation 1. IF Input The IF signal is differentially input to the IN pin and INX pin of this IC. IF is input to the input pin by AC coupling. The value of the AC coupling is selected so that the transfer power from the receive RF circuit is maximum. CXA3328TN/EN 1 From receive RF circuit RX BPF ∗ ∗ 2 ∗ This value must be the value taken for the optimum impedance matching between the BPF filter and this IC. 2. Notes on Power Supplies The CXA3328TN/EN is designed to operate by a 2.85V stabilized power supply to allow use with the battery driven portable phones. Using multiple voltage regulators throughout the phone is recommended to minimize the power supply noise in the CXA3328TN/EN power supply input. The recommended power supply range for the CXA3328TN/EN is 2.7 to 3.3V. Decouple the power supplies around the CXA3328TN/ EN using 1µF capacitor for each VCC pin. Locate this capacitor as close to the pins as possible, and minimize the series inductance for the pin connections. Using an additional 1nF decoupling capacitor in parallel to the 1µF capacitor is recommended to further reduce the high frequency noise in the power supply input to the CXA3328TN/EN. – 12 – CXA3328TN/EN Example of Representative Characteristics Voltage gain vs. Control voltage Vcont 80 70 60 50 Voltage gain [dB] 40 30 20 10 0 –10 –20 –30 0 0.5 1 1.5 Vcont [V] 2 2.5 3 Noise figure vs. Voltage gain 80 70 60 Noise figure [dB] 50 40 30 20 10 0 –10 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 Voltage gain [dB] IIP3 vs. Voltage gain 10 0 –10 –20 IIP3 [dBm] –30 –40 –50 –60 –70 –80 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 Voltage gain [dB] – 13 – CXA3328TN/EN Package Outline CXA3328TN Unit: mm 16PIN TSSOP (PLASTIC) 1.2MAX 4.1 2.05 A 16 X S B 9 X2 0.2 SAB 0.08 S 0.1 (3.0) 0.1 ± 0.05 0.25 2.9 0.1 X 0.5 0.1 SA B 0˚ to 8˚ 0.08 M S A B 0.2 ± 0.02 + 0.036 0.22 – 0.03 DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSSOP-16P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.03g SCT & Kokubu Ass’y 16PIN TSSOP (PLASTIC) 1.2MAX 4.1 2.05 A 16 X S B 9 X2 0.2 SAB 0.08 S 0.1 (3.0) 0.1 ± 0.05 0.25 2.9 0.1 X 0.5 0.1 SA B 0˚ to 8˚ 0.08 M S A B 0.2 ± 0.02 + 0.036 0.22 – 0.03 DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TSSOP-16P-L01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.03g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18µm – 14 – 0.1 ± 0.01 + 0.026 0.12 – 0.02 0.45 ± 0.1 1 8 X4 3.9 0.1 ± 0.01 + 0.026 0.12 – 0.02 0.45 ± 0.1 1 8 X4 3.9 CXA3328TN/EN Package Outline CXA3328EN Unit: mm 16PIN VSON (PLASTIC) 0.9 MAX 0.6 3.5 A S 0.35 ± 0.1 2.5 0.05 S B 0.4 1.4 4x 2x 0.2 S B 0.35 ± 0.1 0.2 S A B 0.23 ± 0.02 0.05 M S A-B 0.03 ± 0.03 0.2 ± 0.01 Soldrer Plating 0.13 ± 0.025 + 0.09 0.14 – 0.03 NOTE: 1) The dimensions of the terminal section apply to the ranges of 0.1mm and 0.25mm from the end of a terminal. TERMINAL SECTION PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VSON-16P-01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.02 g SCT & Kokubu Ass’y 16PIN VSON (PLASTIC) 0.9 MAX 0.6 3.5 A S 0.35 ± 0.1 2.5 0.05 S 0.5 ± 0.2 2.7 B 0.4 1.4 4x 2x 0.2 S B 0.35 ± 0.1 0.2 S A B 0.23 ± 0.02 0.05 M S A-B 0.03 ± 0.03 0.2 ± 0.01 Soldrer Plating 0.13 ± 0.025 + 0.09 0.14 – 0.03 NOTE: 1) The dimensions of the terminal section apply to the ranges of 0.1mm and 0.25mm from the end of a terminal. TERMINAL SECTION PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VSON-16P-01 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.02 g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18µm 0.5 ± 0.2 2.7 – 15 – Sony Corporation