CXA3562R

CXA3562R LCD Driver Description The CXA3562R is a driver IC developed for use with Sony polycrystalline silicon TFT LCD panels. It supports digital 2-parallel and single input, and the input data is analog demultiplexed into 12 phases and output. The CXA3562R can directly drive an LCD panel, and the VCOM setting circuit and precharge pulse waveform generator are also on-chip. Features • Supports 10-bit 2-parallel and single input • Supports signals up to UXGA (1/2 clock when using UXGA signals) • Low output deviation by on-chip output offset cancel circuit • Supports both line inversion and dot and line inversion • On-chip timing generator with ECL • VCOM voltage generation circuit • Precharge pulse waveform generation circuit Applications LCD projectors and other video equipment Absolute Maximum Ratings (VSS = 0V) • Supply voltage VCC 16 V VDD 5.5 V • Operating temperature Topr –20 to +70 °C • Storage temperature Tstg –65 to +150 °C • Allowable power dissipation PD 2300 mW Recommended Operating Conditions • Supply voltage VCC 15.0 to 15.5 VDD 4.75 to 5.25 • Operating temperature Topr –20 to +70 100 pin LQFP (Plastic) V V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01115-PS CXA3562R Block Diagram and Pin Configuration VCOM_OFST VCOM_OUT SID_OUTX 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 D_A9 76 D_A8 77 D_A7 78 D_A6 79 D_A5 80 D_A4 81 D_A3 82 D_A2 83 D_A1 84 D_A0 85 GND 86 GND 87 GND 88 GND 89 GND 90 D_B9 91 D_B8 92 D_B7 93 D_B6 94 D_B5 95 D_B4 96 D_B3 97 D_B2 98 D_B1 99 D_B0 100 CAL_PLS Offset Cancel Level Gen. TG FRP_OD FRP_EV D/A S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H D/A S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H SID Gen. Vref Gen. Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel VCOM Gen. SH_OUT1 SID_OUT F/H_CNT VREF_O SL_SCN PRG_LV SL_DAT VREF_I SL_INV SID_LV TEST DIRC GND GND GND GND GND PRG VDD VCC NC PS 50 PVCC 49 SH_OUT2 48 NC 47 SH_OUT3 46 NC 45 SH_OUT4 44 NC 43 SH_OUT5 42 NC 41 SH_OUT6 40 GND 39 GND 38 PGND 37 GND 36 GND 35 SH_OUT7 34 NC 33 SH_OUT8 32 NC 31 SH_OUT9 30 NC 29 SH_OUT10 28 NC 27 SH_OUT11 26 PVCC 1 TEST 2 MCLK 3 MCLKX 4 FRP 5 SHST 6 POSCTR0 7 POSCTR1 8 POSCTR2 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CAL_IH CAL_IL GND GND GND GND GND SHTEST SIG.C CAL_OL POSCTR3 CAL_OH GND NC SIG_OFST DCFBOFF SH_OUT12 –2– CXA3562R Pin Description Pin No. Symbol I/O Standard voltage level VDD Equivalent circuit Description 2 3 MCLK MCLKX I PECL differential (amplitude 0.4V or more between VDD to 2V) or TTL input 140k 1k 2 1k 3 60k GND 8k 140k 100µ 60k Dot clock input. PECL differential input or TTL input. For TTL input, input to MCLK and connect MCLKX to GND through a capacitor. VDD 50k 4 FRP I High: ≥2.0V Low: ≤0.8V 192 4 LCD panel AC drive inversion timing input. High: inverted Low: non-inverted See the Timing Chart. GND VDD 50k 192 5 5 SHST I High: ≥2.0V Low: ≤0.8V GND Internal sample-and-hold timing circuit reset pulse input. This pin is also used as the offset cancel level insertion timing input. A reset is applied to the internal timing generator at the falling edge. Output phase adjustment. The output phase is adjusted in MCLK period units when SL_DAT (Pin 72) is high, and in 1/2 MCLK period units when SL_DAT is low. VDD 6 7 8 9 POSCTR0 POSCTR1 POSCTR2 POSCTR3 50k I High: ≥2.0V Low: ≤0.8V 192 6 7 8 9 GND VDD 30k VCC 20µ 16 SIG.C I 1 to 5.0V 16 Signal center voltage (inversion folded voltage) adjustment input. The SH_OUT output center voltage can be adjusted in the range from 7.0 to 8.0V. GND VDD 30k VCC 10µ 17 SIG_OFST I 0 to 5.0V 17 GND Output signal offset adjustment from signal center voltage. The SH_OUT output 100% white level (at 3FF input) voltage can be adjusted in the range from 0 to 1V from the center voltage. –3– CXA3562R Pin No. Symbol I/O Standard voltage level Equivalent circuit VCC 40µ 1k 145 18 19 GND Description 18 19 CAL_OL CAL_OH O 3.0 to 6.0V 9.0 to 12.0V Level output for canceling the offset between channels. Connect directly to CAL_IL and CAL_IH, respectively. VCC 20k 21 22 CAL_IH CAL_IL O 9.0 to 12.0V 3.0 to 6.0V 30k 21 22 GND VDD 24k 24k 145 24 20µ Level input for canceling the offset between channels. Connect directly to CAL_OL and CAL_OH, respectively. When using two CXA3562R, connect the CAL_IL and CAL_IH of both chips to the CAL_OL and CAL_OH of only one CXA3562R. Offset cancel function off. Normally connect to GND to use with the offset cancel function on. High (offset cancel function off) when open. 24 DCFBOFF I GND GND PVCC 25 27 25, 27, 29, 31, SH_OUT12 33, 35, to 41, 43, SH_OUT1 45, 47, 49, 51 300 29 31 33 35 41 43 45 47 49 51 O 1.5 to 13.5V 300 Demultiplexed output of AC inverse driven video signals. Can be connected directly to the LCD panel. GND VCC 80µ 100k 500 145 53 500 53 VCOM_OUT O 5.0 to 8.0V LCD panel common voltage output. Can be set in the range from the SH_OUT center potential Vsig.c to Vsig.c – 2V by VCOM_OFST. GND VDD 2k VCC 80µ 54 VCOM_OFST I 0 to 5.0V 54 100 GND LCD panel common voltage adjustment. VCOM_OUT can be set in the range from the SH_OUT center potential Vsig.c to Vsig.c – 2V by inputting 0 to 5V. –4– CXA3562R Pin No. Symbol I/O Standard voltage level VCC Equivalent circuit Description Precharge waveform output. SID_OUTX outputs the inverse of SID_OUT based on the output center voltage. These pins cannot directly drive the LCD panel, so input to the LCD panel with an external a buffer. VCC 100k 0.2p 145 56 100k 0.2p GND 57 56 57 SID_OUTX SID_OUT O 1.5 to 13.5V VDD 29µ 58 59 PRG_LV SID_LV I 1.0 to 5.0V 50k 58 50k 59 GND Precharge level setting. Adjusts the SID_OUT and SID_OUTX output potential. PRG_LV is reflected when the PRG input pin (Pin 60) is high, and SID_LV is reflected when PRG is low. VDD 100k VCC 10k 60 PRG I High: ≥2.0V Low: ≤0.8V 60 50µ GND Timing pulse input for switching the Pins 56 and 57 output levels. (See PRG_LV (Pin 58) and SID_LV (Pin 59).) VDD 70µ 10µ 68 VREF_I I 3.2V 68 1k 280µ GND 33.3k Internal D/A converter reference voltage input. Normally connect directly to VREF_O. VDD 2k 69 VREF_O O 3.2V 20µ 20k 12.4k GND 69 Reference voltage output. Normally connect directly to VREF_I, and connect to GND through a 0.5 to 1.0µF capacitor. VDD 50k 70 F/H_CNT I High: ≥2.0V Low: ≤0.8V Open: Low 192 70 200k GND SH_OUT output timing selection. High: SH_OUT1 to SH_OUT6 and SH_OUT7 to SH_OUT12 are output at different timing. Low: SH_OUT1 to SH_OUT12 are output at the same timing. –5– CXA3562R Pin No. Symbol I/O Standard voltage level VDD Equivalent circuit Description 70k 66 PS I 5V 66 180k GND 30µ Power saving. Power saving mode when set to low level. Low (power saving mode) when open. Normally connect to VDD. Power GND. Power VCC. 15V power supply. 5V power supply. 38 55 67 PGND VCC VDD GND 15.5V 15.5V 5V 26, 50 PVCC 11 to 15, 20, 36, 37, 39, GND 40, 61 to 65, 86 to 90 23, 28, 30, 32, 34, 42, NC 44, 46, 48, 52 GND GND. VDD 1µ 2k 192 1 75 20µ GND 1, 75 TEST O 1.7 to 3.2V DAC output monitor test. Normally connect to VDD. VDD 20k 250k 20k 20k 20k 10 SHTEST I 2.5V 192 10 250k GND 10µ 10µ Test. Leave open. VDD 50k 71 DIRC I High: ≥2.0V Low: ≤0.8V 192 71 Scan direction setting. High: output as a time series in ascending order of output pin symbol (in order from SH_OUT1 to SH_OUT12) Low: output in descending order GND –6– CXA3562R Pin No. Symbol I/O Standard voltage level Equivalent circuit Description VDD 50k 72 SL_DAT I High: ≥2.0V Low: ≤0.8V Open: Low 192 72 200k GND Digital input mode switch setting. High: single input from the A port Low: parallel input from both the A and B ports VDD 73 SL_SCN I High: ≥2.0V Low: ≤0.8V Open: High 200k 192 73 50k GND A and B port input switching interlocked/non-interlocked setting relative to scan direction setting during parallel input. High: A and B port switching interlocked to DIRC Low: fixed regardless of DIRC VDD 50k 74 SL_INV I High: ≥2.0V Low: ≤0.8V Open: Low 192 74 200k GND SH_OUT odd-numbered and even-numbered output polarity inverted/non-inverted setting. High: odd-numbered and evennumbered outputs inverted Low: non-inverted VDD 50k 76 to 85 D_A9 to D_A0 I High: ≥2.0V Low: ≤0.8V 192 76 to 85 A port digital data input. GND VDD 50k 91 to 100 D_B9 to D_B0 I High: ≥2.0V Low: ≤0.8V 192 91 to 100 B port digital data input. GND –7– CXA3562R Electrical Characteristics Measurement Circuit VDD 1µ 47p 47p VCC A VDD VCOM_OFST SID_OUTX SH_OUT1 SID_OUT 360p VCOM_OUT A VCC F/H_CNT VREF_O SL_SCN PRG_LV SL_DAT VREF_I SL_INV SID_LV TEST DIRC GND GND GND GND GND PRG VDD 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 TEST 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 NC PS 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 D_A9 D_A8 D_A7 D_A6 D_A5 D_A4 D_A3 D_A2 D_A1 D_A0 GND GND GND GND GND D_B9 D_B8 D_B7 D_B6 D_B5 D_B4 D_B3 D_B2 D_B1 D_B0 PVCC SH_OUT2 NC SH_OUT3 NC SH_OUT4 NC SH_OUT5 NC SH_OUT6 GND GND PGND GND GND SH_OUT7 NC SH_OUT8 NC SH_OUT9 NC SH_OUT10 NC SH_OUT11 PVCC 360p 360p 360p 360p 360p 360p 360p 360p 360p 360p 2 MCLK 3 MCLKX 4 FRP 5 SHST 6 POSCTR0 7 POSCTR1 8 POSCTR2 9 POSCTR3 10 SHTEST 11 GND 12 GND 13 GND 14 GND 15 GND 16 SIG.C 17 SIG_OFST 18 CAL_OL 19 CAL_OH 20 GND 21 CAL_IH 22 CAL_IL 23 NC 24 DCFBOFF 25 SH_OUT12 A VCC VDD 360p VCC 15.5V VDD 5V –8– CXA3562R Electrical Characteristics No. 1 2 3 4 Item Digital input resolution Digital input setup time Digital input hold time MCLK input frequency range 1 MCLK input frequency range 2 Symbol n TS TH fMCLK1 SHST, D_A[9:0] and D_B[9:0] minimum setup time relative to MCLK input. (PELL) SHST, D_A[9:0] and D_B[9:0] minimum hold time relative to MCLK input. (PECL) SL_DAT: 5V; maximum frequency at which the internal timing generator and D/A converter operate normally. SL_DAT: 0V; maximum frequency at which the internal timing generator and D/A converter operate normally. Measure the VREF_O (Pin 69) voltage. Measurement points Measurement conditions Min. Typ. Max. Unit — 2 3 30 10 — — — — — — 80 bit ns ns MHz 5 6 7 8 fMCLK2 60 — 100 MHz 3.32 4.83 4.83 V V V V VREF_O output VVREF_O voltage range SH_OUT amplitude 1 SH_OUT amplitude 2 SH_OUT minimum amplitude VSHOUT1p-p VOUT1 VSHOUT2p-p VOUT2 3.10 3.20 Measure the SH_OUT1 voltage 4.44 4.50 difference at D_A[9:0]: 000h and 3FFh. Measure the SH_OUT2 voltage 4.44 4.50 difference at D_B[9:0]: 000h and 3FFh. Lower the VREF_I voltage and adjust the amplitude; minimum amplitude at which SH_OUT1 can be output at D_B[9:0]: 000h and 3FFh. Load capacitance = 360pF; measure slew rate at 10 to 90% of output waveform rise and fall when D_A[9:0] is varied from 000h to 3FFh and from 3FFh to 000h. Minimum voltage at which sampleand-hold outputs VOUT1 to VOUT12 can be output. Maximum voltage at which sampleand-hold outputs VOUT1 to VOUT12 can be output. Value obtained by subtracting minimum VOUT1 to VOUT12 value from maximum VOUT1 to VOUT12 value at D_A[9:0]: 200h and D_B[9:0]: 200h. Value obtained by subtracting minimum VOUT1 to VOUT12 value from maximum VOUT1 to VOUT12 value at D_A[9:0]: 000h or 3FFh and D_B[9:0]: 000h or 3FFh. Value obtained by subtracting minimum VOUT1 to VOUT12 value from maximum VOUT1 to VOUT12 value at D_A[9:0]: 200h and D_B[9:0]: 200h. (when using two CXA3562R) 4 — 9 VOUTMINp-p VOUT1 — 10 SH_OUT slew rate SROUT VOUT1 to VOUT12 160 300 — V/µs SH_OUT 11 minimum output voltage SH_OUT 12 maximum output voltage VMIN VOUT1 to VOUT12 VOUT1 to VOUT12 VOUT1 to VOUT12 1.5 — — V VMAX — — 13.6 V Output deviation 13 between DOUT1 channels 1 Output deviation 14 between DOUT2 channels 2 — 3 10 mVp-p VOUT1 to VOUT12 — 10 40 mVp-p 15 Output deviation DIC1 between ICs 1 VOUT1 to VOUT12 — 10 — mVp-p –9– CXA3562R No. Item Measurement Symbol points Measurement conditions Value obtained by subtracting minimum VOUT1 to VOUT12 value from maximum VOUT1 to VOUT12 value at D_A[9:0]: 000h or 3FFh and D_B[9:0]: 000h or 3FFh. (when using two CXA3562R) PRG: 0V; measure VSID_LV and VSID at FRP: 0V, and VSID_LV and VSIDX at FRP: 5V. Calculate as ASID1 = VSID(X)/VSID_LV. PRG: 5V; measure VPRG_LV and VSID at FRP: 0V, and VPRG_LV and VSIDX at FRP: 5V. Calculate as ASID2 = VSID(X)/VPRG_LV. Load capacitance = 47pF, PRG: 0V; input a repeating high/low pulse to FRP (Pin 4), and apply DC input voltage so that VSID and VSIDX are 2.5V/11.5V. Measure slew rate at 10 to 90% of output waveform rise and fall. VOUT1 center voltage when SIG.C (Pin 16) is varied from 1 to 5V. D_A[9:0]: 3FFh, FRP: 0V, D_B[9:0]: 3FFh; value obtained by subtracting VOUT1 from VOUT1 center voltage when SIG_OFST (Pin 17) is varied from 1 to 5V. Min. Typ. Max. Unit 16 Output deviation DIC2 between ICs 2 VOUT1 to VOUT12 — 20 — mVp-p SID output 17 gain 1 ASID1 VSID_LV VSID VSIDX VPRG_LV VSID VSIDX 1.9 2.0 2.1 times SID output 18 gain 2 ASID2 1.9 2.0 2.1 times 19 SID output slew rate SRSID VSID VSIDX 15 50 — V/µs 20 Signal center VSIG adjustable range SH_OUT offset VSIGOFST adjustable range VCOM VCOM adjustable range VDD current consumption VCC current consumption IDD ICC VOUT1 7 — 8 V 21 VOUT1 0 — 1 V 22 23 24 VCOM IVDD IVCC1 IVCC2 IVDD IVCC1 IVCC2 — — VCOM_OUT voltage when VCOM_OFST Vc – (Pin 54) is varied from 0 to 5V. 2.5 IDD = IVDD ICC = IVCC1 + IVCC2 (no digital data input) GND (Pin 66), ICC = IVDD + IVCC1 + IVCC2 VVREF_I = 3.2V VVREF_I = 3.2V 59 21 — 85 40 Vc 112 59 V mA mA Current consumption in 25 IPS power saving mode 26 27 Differential linearity error DLE 4 8 15 mA –0.7 –1.2 — — 0.7 1.2 LSB LSB Integral linearity ILE error – 10 – CXA3562R Description of Operation The flow of internal operations is described below. The digital signals input to D_A9 to D_A0 and D_B9 to D_B0 are internally D/A converted into approximately 1.5V (at VREF_I: 3.2V) analog signals. After that, the signal that has been demultiplexed into 12 phases is amplified by a factor of three times, inverted at the signal center potential according to FRP and output. , The output level relative to the digital input changes according to the following settings. A: SIG_OFST voltage B: VREF_I voltage VCC C: SIG.C voltage B A A 1023 C B 512 0 Digital IN SH_OUT Signal Center GND 1. Digital input block The CXA3562R can be set to single input from only the A port or parallel input from both the A and B ports, and port switching by right/left inversion is also possible in parallel input mode. This makes it possible to support various systems. In single input mode, the signal is internally demultiplexed to 2-parallel format and input to the D/A converter. 2. D/A converter block The internal D/A converter has two systems for odd-numbered and even-numbered outputs. The voltage input from VREF_I becomes the 100% white level potential of the analog converted signal, and this amplitude is a maximum 1.5Vp-p with respect to input data of 000h to 3FFh. 3. Sample-and-hold (S/H) block The odd-numbered and even-numbered D/A converter outputs are input to the odd-numbered and evennumbered sample-and-hold blocks, respectively. The signals are converted from time series signals into 6-phase cyclic parallel signals by the sample-and-hold group which is appropriately controlled by the internal timing generator. For forward scan, the signals are output in the ascending order of SH_OUT1, SH_OUT2, SH_OUT3 ... SH_OUT12. For reverse scan, this order is inverted and the signals are output in descending order. Connect the signals to the LCD panel according to the order used. The timing of each sample-and-hold pulse is shown on the following pages. These pulses are not output and are used only inside the IC. – 11 – CXA3562R Single input mode DAC 10bit D_A[9:0] D D D_A1 D D D_A2 DAC_O S/H DAC D_B2 D MCLK MCLK/2 S/H D_A[9:0] MCLK D_A1 D_A2 D_B2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 0 1 2 3 1 4 5 3 4 6 7 5 6 8 9 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 0 2 DAC_O DIRC: H SH1_1_2 SH1_3_4 SH1_5_6 SH1_7_8 SH1_9_10 SH1_11_12 SH2_1_6 SH2_7_12 F/H_CNT: L SH3A_1_12 F/H_CNT: H SH3B_1_6 SH3B_7_12 DIRC: L SH1_1_2 SH1_3_4 SH1_5_6 SH1_7_8 SH1_9_10 SH1_11_12 SH2_1_6 SH2_7_12 F/H_CNT: L SH3A_1_12 F/H_CNT: H SH3B_1_6 SH3B_7_12 1 3 CH1 to CH12 simultaneous output timing CH1 to CH6 simultaneous output timing CH7 to CH12 simultaneous output timing CH1 to CH12 simultaneous output timing CH1 to CH6 simultaneous output timing CH7 to CH12 simultaneous output timing – 12 – CXA3562R 2-parallel input mode DAC 10bit D_A[9:0] D D D D_A2 DAC_O S/H DAC 10bit D_B[9:0] MCLK D D D_B2 S/H D_A[9:0] D_B[9:0] MCLK D_A2 D_B2 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DAC_O DIRC: H SH1_1_2 SH1_3_4 SH1_5_6 SH1_7_8 SH1_9_10 SH1_11_12 SH2_1_6 SH2_7_12 F/H_CNT: L SH3A_1_12 F/H_CNT : H SH3B_1_6 SH3B_7_12 DIRC: L SH1_1_2 SH1_3_4 SH1_5_6 SH1_7_8 SH1_9_10 SH1_11_12 SH2_1_6 SH2_7_12 F/H_CNT: L SH3A_1_12 F/H_CNT: H SH3B_1_6 SH3B_7_12 –1 1 3 CH1 to CH12 simultaneous output timing CH1 to CH6 simultaneous output timing CH7 to CH12 simultaneous output timing CH1 to CH12 simultaneous output timing CH1 to CH6 simultaneous output timing CH7 to CH12 simultaneous output timing – 13 – CXA3562R 4. Timing generator (TG) block The internal timing generator operates by one pair of differential clock inputs (MCLK, MCLKX) and a horizontal sync signal input (SHST), and generates the timing pulses needed by the demultiplexer block, dot inversion control pulse and output deviation cancel circuit. The various operating modes can be designated by the pin settings. The SHST and FRP inputs should satisfy the relationship shown in the figure below with the MCLK and MCLKX input period as 1clk. SHST FRP 30clk or more 1µs or more The CXA3562R can select various operating modes according to the timing generator block settings. These settings are described below. • SL_DAT (Pin 72) Digital input selection. Single input from only the A port is selected when set to high level, and parallel input from both the A and B ports is selected when set to low level. When inputting a 2-parallel processed digital video signal in parallel input mode, input the earlier time series data to the A port and the later time series data to the B port. Input a master clock having the same period as the input data rate to MCLK in both modes. This pin is low level (2-parallel input mode) when left open. • DIRC (Pin 71), SL_SCN (Pin 73) Scan direction settings. Output is ascending order when DIRC is set to high level, and inverted to descending order (SH_OUT1 to SH_OUT12) when set to low level. At this time if SL_SCN is set to high, the A and B port data can be switched by switching DIRC between high and low. When SL_SCN is set to low, the A port data is output from the odd-numbered SH_OUT and the B port data is output from the even-numbered SH_OUT regardless of the DIRC setting. Set SL_SCN to high when SL_DAT is high. D_A[9:0] D_B[9:0] A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 DIRC: L SH_OUT1: A6, SH_OUT2: B6, SH_OUT3: A5, SH_OUT4: B5, SH_OUT5: A4, SH_OUT6: B4, SH_OUT7: A3, SH_OUT8: B3, SH_OUT9: A2, SH_OUT10: B2, SH_OUT11: A1, SH_OUT12: B1 SH_OUT1: B6, SH_OUT2: A6, SH_OUT3: B5, SH_OUT4: A5, SH_OUT5: B4, SH_OUT6: A4, SH_OUT7: B3, SH_OUT8: A3, SH_OUT9: B2, SH_OUT10: A2, SH_OUT11: B1, SH_OUT12: A1 – 14 – DIRC: H SH_OUT1: A1, SH_OUT2: B1, SH_OUT3: A2, SH_OUT4: B2, SH_OUT5: A3, SH_OUT6: B3, SH_OUT7: A4, SH_OUT8: B4, SH_OUT9: A5, SH_OUT10: B5, SH_OUT11: A6, SH_OUT12: B6 SH_OUT1: A1, SH_OUT2: B1, SH_OUT3: A2, SH_OUT4: B2, SH_OUT5: A3, SH_OUT6: B3, SH_OUT7: A4, SH_OUT8: B4, SH_OUT9: A5, SH_OUT10: B5, SH_OUT11: A6, SH_OUT12: B6 SL_SCN: L SL_SCN: H CXA3562R • SL_INV (Pin 74) Dot inversion and line inversion selection. When set to low level, all SH_OUT channels are output at the same polarity as shown by the solid line in the figure below. When set to high level, the odd-numbered and evennumbered SH_OUT outputs are output at inverse polarities. At this time the odd-numbered outputs are inverted when the FRP pulse is high, and non-inverted when the FRP pulse is low. Conversely, the evennumbered outputs are inverted when the FRP pulse is low, and non-inverted when the FRP pulse is high. SH_OUT GND FRP • F/H_CNT (Pin 70) SH_OUT output timing phase setting. When set to low level, all SH_OUT outputs are output at the same timing. When set to high level, SH_OUT1 to SH_OUT6 and SH_OUT7 to SH_OUT12 are output at phases offset by 1/2 clock period from each other. SH_OUT7 to 12 SH_OUT7 to 12 SH_OUT1 to 6 SH_OUT1 to 6 GND GND F/H_CNT: L F/H_CNT: H • Output phase setting The phase of each SH_OUT output can be adjusted in MCLK period units when SL_DAT is high or in 1/2 MCLK period units when SL_DAT is low by POSCTR[3:0] (Pins 6 to 9). The phase can be set in 16 ways by 4-bit digital input. The output phase shifts backward by the above unit each time this setting is increased by one bit. – 15 – CXA3562R 5. Calibration level generator block The CXA3562R generates the offset cancel circuit reference with a calibration level generator in order to minimize the deviation between channels at the center level. The 200h output level is generated at both the AC output high and low sides, and these levels are DC output from CAL_OH and CAL_OL, respectively. At the same time, 200h data is forcibly inserted into the video signal while the video blanking period SHST pulse is low level, and feedback is applied so that the output levels of all SH_OUT channels conform to CAL_IH and CAL_IL during this period. SHST Video signal replacement period FRP 200ns CAL_PLS (internal pulse) Offset cancel operation 200h SH_OUT Signal center 200h 000h 000h Delayed by sample-and-hold 6. SID signal generator block This circuit generates the precharge signal waveform used by the LCD panel. The voltage input from PRG_LV (Pin 58) and SID_LV (Pin 59) is switched by the PRG pulse (Pin 60). The PRG_LV voltage is selected when PRG is high, and the SID_LV voltage is selected when PRG is low. This signal is then further amplified by a factor of two times and folded by the FRP pulse. The folded center voltage is the SH_OUT center voltage (voltage set by the SIG.C pin). SID_OUT (Pin 57) is inverted when FRP is high, and non-inverted when FRP is low. Conversely, SID_OUTX (Pin 56) is inverted when FRP is low, and noninverted when FRP is high. SID_OUT and SID_OUTX cannot directly drive the precharge signal input of the LCD panel, so they should be connected via a buffer having sufficient current supply capability. 7. VCOM potential generator block This block sets the DC common potential for the LCD panel. VCOM_OFST (Pin 54) sets the deviation relative to the SH_OUT center potential, which is set by SIG.C. – 16 – CXA3562R Example of Representative Characteristics (VCC = 15.5V, VDD = 5.0V, Ta = 25°C) VREF_I voltage vs. SH_OUT voltage white-black amplitude 4.8 14 SIG.C = 3.75V SIG_OFST = 3.6V 12 Input data vs. SH_OUT voltage SH_OUT white-black amplitude voltage [V] 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 3.9 3.8 2.7 FRP = High SH_OUT voltage [V] 10 8 6 FRP = Low 4 2 0 000h SIG.C = 3.75V SIG_OFST = 3.6V 100h 200h 300h 3FFh 2.8 2.9 3.0 3.1 3.2 3.3 VREF_I voltage [V] Input data (10 bits) SIG.C voltage vs. SH_OUT center voltage 9.0 8.5 12 11 SIG_OFST = 3.6V 10 SIG_OFST voltage vs. SH_OUT voltage SH_OUT center voltage [V] 8.0 7.5 7.0 6.5 6.0 5.5 5.0 2.5 SH_OUT voltage [V] FRP = High 9 8 7 6 5 4 3 SIG.C = 3.75V FRP = Low DATA = 200h 3.0 3.5 SIG.C voltage [V] 4.0 4.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SIG_OFST voltage [V] VCOM_OFST voltage vs. VCOM_OUT voltage 6.00 SIG.C = 3.75V 5.95 VCOM_OUT voltage [V] 5.90 5.85 5.80 5.75 5.70 2.8 2.9 3.0 3.1 3.2 VCOM_OFST voltage [V] – 17 – CXA3562R SID_LV voltage vs. SID_OUT voltage 16 14 12 SIG.C = 3.75V 16 14 12 PRG_LV voltage vs. SID_OUT voltage SIG.C = 3.75V SID_OUT voltage [V] SID_OUT voltage [V] FRP = High 10 8 6 FRP = Low 4 2 0 0 1 2 SID_LV voltage [V] 3 4 FRP = High 10 8 6 FRP = Low 4 2 0 0 1 2 PRG_LV voltage [V] 3 4 – 18 – CXA3562R Application Circuit 1 (to XGA Panel) VDD 20kΩ VDD 0.1µF Buffer 1 Psig VDD 10Ω 10Ω VDD VDD 1µF 0.1µF VDD 10kΩ SID_OUTX SID_OUT F/H_CNT VREF_O SL_SCN PRG_LV SL_DAT VREF_I SL_INV SID_LV 20kΩ DSD CXD3511Q PRG 161 RGT 136 VDD 0.1µF 47µF 20kΩ 1Ω 31 COM 1Ω VCOM_OFST VDD VCOM_OUT 3 Vsig1 SH_OUT1 TEST DIRC GND GND GND GND GND PRG VDD VCC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R1OUT9 122 R1OUT8 121 R1OUT7 120 R1OUT6 119 R1OUT5 118 R1OUT4 117 R1OUT3 116 R1OUT2 113 R1OUT1 112 R1OUT0 111 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω D_A9 D_A8 D_A7 D_A6 D_A5 D_A4 D_A3 D_A2 D_A1 D_A0 GND GND GND GND GND D_B9 D_B8 D_B7 D_B6 D_B5 D_B4 D_B3 D_B2 D_B1 D_B0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 TEST NC PS 50 49 48 47 46 45 44 43 42 41 40 39 PVCC SH_OUT2 NC SH_OUT3 NC SH_OUT4 NC SH_OUT5 NC SH_OUT6 GND GND PGND GND GND SH_OUT7 NC SH_OUT8 NC SH_OUT9 NC SH_OUT10 NC SH_OUT11 PVCC 0.1µF VCC 47µF 1Ω 13 Vsig11 1Ω 12 Vsig10 1Ω 11 Vsig9 1Ω 10 Vsig8 1Ω 9 Vsig7 1Ω 8 Vsig6 1Ω 7 Vsig5 1Ω 6 Vsig4 1Ω 5 Vsig3 1Ω 4 Vsig2 CXA3562R 38 37 36 35 34 33 32 31 30 29 28 27 26 LCD Panel LCX023 2 MCLK 3 MCLKX 4 FRP 5 SHST 6 POSCTR0 7 POSCTR1 8 POSCTR2 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 POSCTR3 SIG_OFST SH_OUT12 DCFBOFF CAL_OL CAL_OH CAL_IH SHTEST CAL_IL SIG.C GND GND GND GND GND GND NC 10kΩ 1Ω 14 Vsig12 VDD VDD FRP 157 SHST 159 10Ω 10Ω VDD VCC VDD OPEN 20kΩ 0.1µF 1µF 1µF CXA3266Q 82Ω CLKH 32 CLKL 31 130Ω 130Ω 82Ω 20kΩ 0.1µF 15.5V 5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 19 – CXA3562R Application Circuit 2 (to SXGA Panel) VDD 20kΩ VDD 0.1µF Buffer 1 Psig VDD 10Ω 10Ω VDD VDD 1µF 0.1µF VDD 1Ω 10kΩ VDD 0.1µF 21 COML 47µF 1Ω 32 COM 20kΩ 2 COMR 20kΩ DSD CXD3511Q PRG 161 RGT 136 VCOM_OFST 3 Vsig1 VCOM_OUT SID_OUTX 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R1OUT9 122 R1OUT8 121 R1OUT7 120 R1OUT6 119 R1OUT5 118 R1OUT4 117 R1OUT3 116 R1OUT2 113 R1OUT1 112 R1OUT0 111 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω D_A9 D_A8 D_A7 D_A6 D_A5 D_A4 D_A3 D_A2 D_A1 D_A0 GND GND GND GND GND R2OUT9 110 R2OUT8 109 R2OUT7 108 R2OUT6 107 R2OUT5 106 R2OUT4 105 R2OUT3 104 R2OUT2 103 R2OUT1 99 R2OUT0 98 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω D_B9 D_B8 D_B7 D_B6 D_B5 D_B4 D_B3 D_B2 D_B1 D_B0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 PVCC SH_OUT2 NC SH_OUT3 NC SH_OUT4 NC SH_OUT5 NC SH_OUT6 GND GND PGND GND GND SH_OUT7 NC SH_OUT8 NC SH_OUT9 NC SH_OUT10 NC SH_OUT11 PVCC 0.1µF VCC 47µF 1Ω 13 Vsig11 1Ω 12 Vsig10 1Ω 11 Vsig9 1Ω 10 Vsig8 1Ω 9 Vsig7 1Ω 8 Vsig6 1Ω 7 Vsig5 1Ω 6 Vsig4 1Ω 5 Vsig3 1Ω 4 Vsig2 SH_OUT1 SID_OUT F/H_CNT VREF_O SL_SCN PRG_LV SL_DAT VREF_I SL_INV SID_LV TEST DIRC GND GND GND GND GND PRG VDD VCC NC PS CXA3562R 38 37 36 35 34 33 32 31 30 29 28 27 26 LCD Panel LCX028 SIG_OFST DCFBOFF SIG.C CAL_OL CAL_OH CAL_IH NC SH_OUT12 SHTEST MCLKX POSCTR0 POSCTR1 POSCTR2 POSCTR3 CAL_IL GND GND GND GND GND MCLK SHST TEST GND FRP 10kΩ 1Ω 14 Vsig12 VDD VDD FRP 157 SHST 159 10Ω 10Ω VDD VCC VDD OPEN 20kΩ 0.1µF 1µF 1µF CXA3266Q 82Ω CLK/2H 30 CLK/2L 29 130Ω 130Ω 82Ω 20kΩ 0.1µF 15.5V 5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 20 – CXA3562R Application Circuit 3 (to WXGA Panel) Another CXA3562R SID_OUTX 56 57 SID_OUT Buffer 2 Psig1 3 Psig2 4 Psig3 5 Psig4 VDD VDD 10Ω VDD VDD 1µF 0.1µF VDD 10kΩ VDD VDD 1Ω VDD 20kΩ 47µF 0.1µF 25 COML 1Ω 34 COM 20kΩ 6 COMR DSD CXD3511Q RGT 136 VCOM_OFST 7 Vsig-a1 VCOM_OUT SID_OUTX 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R1OUT9 122 R1OUT8 121 R1OUT7 120 R1OUT6 119 R1OUT5 118 R1OUT4 117 R1OUT3 116 R1OUT2 113 R1OUT1 112 R1OUT0 111 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω D_A9 D_A8 D_A7 D_A6 D_A5 D_A4 D_A3 D_A2 D_A1 D_A0 GND GND GND GND GND R2OUT9 110 R2OUT8 109 R2OUT7 108 R2OUT6 107 R2OUT5 106 R2OUT4 105 R2OUT3 104 R2OUT2 103 R2OUT1 99 R2OUT0 98 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω D_B9 D_B8 D_B7 D_B6 D_B5 D_B4 D_B3 D_B2 D_B1 D_B0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 PVCC SH_OUT2 NC SH_OUT3 NC SH_OUT4 NC SH_OUT5 NC SH_OUT6 GND GND PGND GND GND SH_OUT7 NC SH_OUT8 NC SH_OUT9 NC SH_OUT10 NC SH_OUT11 PVCC 0.1µF VCC 47µF 1Ω 17 Vsig-b5 1Ω 16 Vsig-b4 1Ω 15 Vsig-b3 1Ω 14 Vsig-b2 1Ω 13 Vsig-b1 1Ω 12 Vsig-a6 1Ω 11 Vsig-a5 1Ω 10 Vsig-a4 1Ω 9 Vsig-a3 1Ω 8 Vsig-a2 SH_OUT1 SID_OUT F/H_CNT VREF_O SL_SCN PRG_LV SL_DAT VREF_I SL_INV SID_LV TEST DIRC GND GND GND GND GND PRG VDD VCC NC PS CXA3562R 38 37 36 35 34 33 32 31 30 29 28 27 26 LCD Panel LCX037 FRP GND GND GND GND GND MCLK SHST TEST MCLKX SIG.C CAL_OL CAL_OH GND CAL_IH SHTEST CAL_IL NC POSCTR0 POSCTR1 POSCTR2 POSCTR3 SIG_OFST DCFBOFF SH_OUT12 10kΩ 1Ω 18 Vsig-b6 VDD VDD FRP 157 SHST 159 10Ω 10Ω VDD VCC VDD OPEN 20kΩ 0.1µF 1µF 1µF CXA3266Q 82Ω CLK/2H 30 CLK/2L 29 130Ω 130Ω 82Ω 20kΩ 0.1µF 15.5V 5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 21 – CXA3562R Application Circuit 4 (to UXGA Panel) VDD 0.1µF 20kΩ VDD 0.1µF DSD CXD3511Q PRG 161 10Ω 20kΩ RGT 136 10Ω VDD VDD 0.47µF VDD Buffer 1 Psig1 2 Psig2 VDD 47µF 0.1µF VDD VDD VCOM_OFST VCOM_OUT 1Ω 11 Vsig1 SH_OUT1 SID_OUTX 10kΩ SID_OUT F/H_CNT VREF_O SL_SCN SL_DAT VREF_I SL_INV PRG_LV SID_LV TEST DIRC GND GND GND GND GND VDD PRG VCC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R1OUT9 122 R1OUT8 121 R1OUT7 120 R1OUT6 119 R1OUT5 118 R1OUT4 117 R1OUT3 116 R1OUT2 113 R1OUT1 112 R1OUT0 111 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω D_A9 D_A8 D_A7 D_A6 D_A5 D_A4 D_A3 D_A2 D_A1 D_A0 GND GND GND GND GND D_B9 D_B8 D_B7 D_B6 D_B5 D_B4 D_B3 D_B2 D_B1 D_B0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 TEST NC PS 50 49 48 47 46 45 44 43 42 41 40 39 PVCC SH_OUT2 NC SH_OUT3 NC SH_OUT4 NC SH_OUT5 NC SH_OUT6 GND GND PGND GND GND SH_OUT7 NC SH_OUT8 NC SH_OUT9 NC SH_OUT10 NC SH_OUT11 PVCC 0.1µF VCC 47µF 1Ω 31 Vsig21 1Ω 29 Vsig19 1Ω 27 Vsig17 1Ω 25 Vsig15 1Ω 23 Vsig13 1Ω 21 Vsig11 1Ω 19 Vsig9 1Ω 17 Vsig7 1Ω 15 Vsig5 1Ω 13 Vsig3 CXA3562R 38 37 36 35 34 33 32 31 30 29 28 27 26 LCD Panel LCX036 2 MCLK 3 MCLKX 4 FRP 5 SHST 6 POSCTR0 7 POSCTR1 8 POSCTR2 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CAL_OL CAL_IH CAL_IL SH_OUT12 SIG.C SIG_OFST CAL_OH NC POSCTR3 DCFBOFF SHTEST GND GND GND GND GND GND 10kΩ 1Ω 33 Vsig23 VDD FRP 157 SHST 159 10Ω 10Ω OPEN VDD 0.47µF 0.47µF 20kΩ 0.1µF Buffer 4 Psig4 82Ω 82Ω 3 Psig3 VDD 130Ω 130Ω VDD VDD 0.1µF 20kΩ VDD VDD 0.47µF 0.1µF VDD 10kΩ SID_OUTX SID_OUT F/H_CNT VREF_O SL_SCN PRG_LV SL_DAT VREF_I SL_INV SID_LV 20kΩ 0.1µF 56 COM1 57 COM2 47µF 1Ω VDD VCOM_OFST VCOM_OUT 1Ω 12 VSig2 SH_OUT1 TEST DIRC GND GND GND GND GND PRG VDD VCC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 R2OUT9 110 R2OUT8 109 R2OUT7 108 R2OUT6 107 R2OUT5 106 R2OUT4 105 R2OUT3 104 R2OUT2 103 R2OUT1 99 R2OUT0 98 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω 10Ω D_A9 D_A8 D_A7 D_A6 D_A5 D_A4 D_A3 D_A2 D_A1 D_A0 GND GND GND GND GND D_B9 D_B8 D_B7 D_B6 D_B5 D_B4 D_B3 D_B2 D_B1 D_B0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 10Ω TEST NC PS 50 49 48 47 46 45 44 43 42 41 40 39 PVCC SH_OUT2 NC SH_OUT3 NC SH_OUT4 NC SH_OUT5 NC SH_OUT6 GND GND PGND GND GND SH_OUT7 NC SH_OUT8 NC SH_OUT9 NC SH_OUT10 NC SH_OUT11 PVCC 0.1µF VCC 47µF 1Ω 32 Sig22 1Ω 30 Sig20 1Ω 28 Sig18 1Ω 26 Sig16 1Ω 24 Sig14 1Ω 22 Sig12 1Ω 20 Sig10 1Ω 18 Sig8 1Ω 16 Sig6 1Ω 14 Sig4 CXA3562R 38 37 36 35 34 33 32 31 30 29 28 27 26 2 MCLK 3 MCLKX 4 FRP 5 SHST 6 POSCTR0 7 POSCTR1 8 POSCTR2 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SIG_OFST SIG.C CAL_OL CAL_OH CAL_IH CAL_IL NC DCFBOFF SH_OUT12 POSCTR3 SHTEST GND GND GND GND GND GND XFRP 158 10kΩ 1Ω 34 Sig24 CXA3266Q VDD OPEN VDD 0.47µF 0.47µF VCC VDD CLK/2H 30 CLK/2L 29 15.5V 20kΩ 0.1µF 0.1µF 5V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 22 – CXA3562R Notes on Operation The CXA3562R has high power consumption, so be sure to take the following radiation measures. • Use four-layer substrate. • GND lines connected between Pins 11 to 15, Pins 36 to 40, Pins 61 to 65 and Pins 86 to 90 should be as thick as possible. – 23 – CXA3562R Package Outline Unit: mm 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 14.0 ± 0.1 75 76 51 50 B A 100 1 0.5 b 25 26 (0.22) 0.13 M + 0.2 1.5 – 0.1 0.1 ± 0.1 b = 0.18 ± 0.03 0.5 ± 0.2 0.1 DETAIL B : PALLADIUM EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.7g (15.0) 0˚ to 10˚ 0.5 ± 0.2 NOTE: Dimension " ∗" does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-100P-L01 P-LQFP100-14x14-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS 0.125 ± 0.04 – 24 – Sony Corporation