CXA3796N

Digital CCD Camera Head Amplifier CXA3796N Description The CXA3796N is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the following functions: correlated double sampling, AGC for the CCD signal, A/D sample and hold, blanking, A/D reference voltage, and an output driver. (Applications: CCD cameras) Features High sensitivity made possible by a high-gain AGC amplifier Blanking function provided for the purpose of calibrating the CCD output signal black level Regulator output pin provided for A/D converter reference voltage Built-in sample-and-hold circuits for camera signals required by external A/D converters Selectable maximum gain of AGC amplifier (MAXGAIN mode) Minus gain setting of AGC amplifier (GAINSHIFT mode) CCDLEVEL output blanking function Input dynamic range expansion Noise characteristics improvement Package 24-pin SSOP (Plastic) Structure Bipolar silicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E07Z39-CR CXA3796N Absolute Maximum Ratings Supply voltage Operating temperature Storage temperature Allowable power dissipation VCC Topr Tstg PD 5.5 –20 to +75 –65 to +150 417 V °C °C mW Operating Conditions Supply voltage VCC1, 2, 3 3.0 to 3.6 V -2- CXA3796N Block Diagram and Pin Configuration CCDLEVEL AGCCONT 24 23 22 21 20 19 18 17 16 15 14 13 BUF SH1 SH2 AGC DC SHIFT OB SW SH3 DMSW2 CDS CLP2 DMSW1 CDS CLP1 OFFSET VREF CAM SH AGC CLP VRT DRV VRT VRB DRV VRB BLK SW DRV 1 GND2 2 GAINSHIFT 3 GND3 4 DRVOUT 5 VCC3 6 MAXGAIN 7 VRB 8 VRT 9 OFFSET 10 PBLK 11 XRS 12 CLPOB -3- AGCCLP CLPDM ICONT GND1 VCC2 VCC1 SHD SHP DIN PIN CXA3796N Pin Description (VCC1, 2, 3 = 3.3V) Pin No. Symbol I/O — Pin voltage GND Equivalent circuit Description Ground. 1 GND2 3 GND3 19 GND1 2 GAINSHIFT Gain shifted according to the following setting. I VCC to 0.7VCC: 0dB OPEN: –3dB 0.3VCC to GND: –6dB 120k 2k 2 120k 7p 1k 11µA 1k 80k 40k 2.2V 40k Gain shift. 80k 11µA 40k IOFFSET 0 to 55µA 27.5µA 220µA 27.5µA 2k VRB = 1.485V 55µA 55µA 4 DRVOUT O VRB to VRB + 110mV ICONT 3.52 to 7.04mA 2k 4 CAM signal Driver output for A/D converter capable of direct DC coupling capacitor. Dynamic range = 1.07Vp-p. 6 5 VCC3 16 VCC1 23 VCC2 — VCC Power supply. 6 MAXGAIN VCC to 0.7VCC: 34dB OPEN: 26dB I 0.3VCC to GND: 30dB * AGCCONT = 3.0V 120k 2k 6 120k 7p 1k 11µA 1k 80k 40k 2.2V 40k MAXGAIN. 80k 11µA 40k -4- CXA3796N Pin No. Symbol I/O Pin voltage Equivalent circuit Description 100 16.5k 300 1.485V 1k 200 1.485V regulator output. Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7μF) 7 VRB O 1.485V (0.45VCC) 300 7 1.3k 13.5k 110µA 4k 12 2.585V regulator output. 1k 6.5k 300 2.58V 300 8 16k 12 8 VRT O 2.585V (0.783VCC) 23.5k 55µ 55µ 220µ 200 Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7μF) 50k 1k 50k 1k 200 2k 60k 1.65V VRB Controls the output offset. When 3.3V: VRB + 0mV When 1.65V: VRB + 110mV When 0V (preset mode): VRB + 40mV 9 OFFSET I 1.65 to 3.3V & 0V 1.5k 3k 24k 55µA 1k 55µA 55µA 2k 9 60k VTH = 1.65V 60k 60k 1k Camera signal preblanking pulse input. Active when Low. Calibrates the black level of the AGC output waveform. When PBLK is Low, the DRVOUT potential is forced to VRB. 10 PBLK I Active: Low 2k 1.65V 10 60k 27.5µA VTH = 0.74V 24k 50µA 440µA 1k 145 11 11 XRS I Sampling 0.74V 7k 1k Camera signal sampleand-hold pulse input. 98µA -5- CXA3796N Pin No. Symbol I/O Pin voltage Equivalent circuit Description VTH = 1.65V 16k 60k 1k 12 CLPOB I Active: Low 2k 1.65V 12 60k 55µA Clamp pulse input used to clamp the optical black portion of the camera signal after it passes through the AGC amplifier. 1k 5k 5k 145 13 AGCCLP O Approximately1.4V 145 1k 50k 1.9V 1k 13 AGC clamp capacitor. (Recommended value: 0.1μF) 1k 1k 500 14 3.4k 3.18V 3.4k 3.4k 2.475V 220µA 3.4k 500k 220µA AGC gain control input. When 1.65V: –1 dB (Minimum gain) When 3.3V: 31.5 dB (Maximum gain) MAXGAIN = OPEN GAINSHIFT = VCC * Gain values can be changed by setting two pins shown above. 14 AGCCONT I 1.65 to 3.3V (0.5VCC to 1.0VCC) 3k 3k ICONT 110µA 110µA 110µA 110µA -6- CXA3796N Pin No. Symbol I/O Pin voltage Equivalent circuit Description 220µA 15 CCDLEVEL O CCD signal black level of DIN input Approximately2.5V 15 500 500 Enables monitoring output of the SH3 output camera signal. 250 250 17 SHP I VTH = 0.74V 36k 55µA 440µA 1k 145 17 Preset level sample-andhold pulse input. Sampling 0.745V 10.5k 1k 1k 18 18 SHD I Data level sample-andhold pulse input. VTH = 1.65V 1.65V 60k 1k 2k 20 CLPDM I Active: Low 20 Clamp pulse input used to clamp the dummy pixel portion of the input CCD signal. 60k 55µA 500 145 500 1k 11µA 11µA 49k 500 21 PIN 22 DIN I Black level Approximately2.5V 21 22 145 CCD signal input. 1k 1k 330µA 27.5µA 22k 1k 11k 15k 2.475V 6k 45k 1k 2k DRVOUT output waveform rise time control input. 24 24 ICONT I 1.65 to 3.3V 6k 110µA When 1.65V: Maximum rise time When 3.3V: Minimum rise time -7- CXA3796N Electrical Characteristics (Ta = 25°C, VCC1, 2, 3 = 3.3V) Item VCC = 3.3V Current consumption VCC = 3.0V IDC30 IDC Symbol Conditions Min. Typ. Max. Unit 45.7 65.6 mA 59 VAGCCONT = 1.65V, open between VRT and VRB 33 MAXGAIN = OPEN, GAINSHIFT = VCC ICONT = 3.3V, SHP, SHD = Duty75% (H:L = 3:1) VAGCCONT = 1.5V, open between VRT and VRB 29.5 41.3 MAXGAIN = OPEN, GAINSHIFT = VCC ICONT = 3.0V, SHP, SHD = Duty75% (H:L = 3:1) 31 34 MAXGAIN1 DIN = 1μs, 15 mVp-p pulse A CONT max.1 VAGCCONT = 3.0V, ICONT = 3.3V MAXGAIN = VCC, GAINSHIFT = VCC DIN = 1μs, 20 mVp-p pulse A CONT max.2 VAGCCONT = 3.0V, ICONT = 3.3V MAXGAIN = GND, GAINSHIFT = VCC DIN = 1μs, 30 mVp-p pulse A CONT max.3 VAGCCONT = 3.0V, ICONT = 3.3V MAXGAIN = OPEN, GAINSHIFT = VCC 37 MAXGAIN2 27 30 33 MAXGAIN3 23 26 29 DIN = 1μs, 500 mVp-p pulse GAINSHIFT1 A CONT min.1 VAGCCONT = 1.65V, ICONT = 3.3V MAXGAIN = OPEN, GAINSHIFT = VCC DIN = 1μs, 500 mVp-p pulse GAINSHIFT2 A CONT min.2 VAGCCONT = 1.65V, ICONT = 3.3V MAXGAIN = OPEN, GAINSHIFT = OPEN DIN = 1μs, 500 mVp-p pulse GAINSHIFT3 A CONT min.3 VAGCCONT = 1.65V, ICONT = 3.3V MAXGAIN = OPEN, GAINSHIFT = GND AGC Gain variable AGC G1 width 1 Gain variable AGC G2 width 2 Gain variable AGC G3 width 3 Gain variable AGC G4 width 4 Gain variable AGC G5 width 5 Gain variable AGC G6 width 6 Gain variable AGC G7 width 7 Gain variable AGC G8 width 8 Gain variable AGC G9 width 9 A CONT max.1 – A CONT min.1 A CONT max.2 – A CONT min.1 A CONT max.3 – A CONT min.1 A CONT max.1 – A CONT min.2 A CONT max.2 – A CONT min.2 A CONT max.3 – A CONT min.2 A CONT max.1 – A CONT min.3 A CONT max.2 – A CONT min.3 A CONT max.3 – A CONT min.3 — –0.8 1.4 — –3.6 –1 — –6.5 –3.5 — — — — — — — — — dB 29.6 34.8 25.6 30.8 21.6 26.8 32 28 24 37.6 33.6 29.6 34.5 40.5 30.5 36.5 26.5 32.5 -8- CXA3796N Item Dynamic range Max. AGC Dynamic range Typ. Offset High DRV Offset Low Symbol AGCmax.D Conditions Min. Typ. Max. Unit — V VAGCCONT = 3.3V MAXGAIN = OPEN, GAINSHIFT = VCC At the 0.88 1.07 level when DRVOUT output signal is saturated VAGCCONT = 2.2V MAXGAIN = OPEN, GAINSHIFT = VCC At the 0.88 1.07 level when DRVOUT output signal is saturated OFFSET = 1.65V OFFSET = 3.3V OFFSET = 0V 400Ωload 400Ωload 400Ωload BLKOF (PBLK = 3.3V) – BLKOF (PBLK = 0V) ICONT = 3.3V DIN = 1μs, 1.1Vp-p pulse 88 — 30 115 3 41 AGCtyp.D CAOF high CAOF low — — 10 55 V mV Offset Preset CAOF pre VRTDC level VRTO REF VRBDC level VRBO VRT – VRB BLK SH3 Offset Dynamic range ΔVR BLKOF1 SH3 D 2535 2585 2635 1435 1485 1535 mV 1045 1087 1155 –15 0.9 2 1 30 — mV V -9- CXA3796N Electrical Characteristics Measurement Circuit CCDLEVEL CLPDM ICONT GND1 VCC2 24 23 22 21 20 19 18 17 16 VCC1 SHD SHP DIN PIN 15 14 13 BUF SH1 SH2 AGC DC SHIFT OB SW SH3 DMSW2 CDS CLP2 DMSW1 CDS CLP1 OFFSET VREF CAM SH AGC CLP VRT DRV VRT VRB DRV VRB BLK SW DRV 1 GND2 2 GAINSHIFT 3 GND3 4 DRVOUT 5 VCC3 6 MAXGAIN 7 VRB 8 VRT 9 OFFSET 10 PBLK 11 XRS 12 CLPOB PL4 GND L OPEN SW1 H R2 22 VCC3 3.3V L OPEN SW2 R1 400 C5 4.7µ V7 3.3V C4 4.7µ SW2 H R3 10k V6 3.3V V5 2.03V C6 40pF V4 0 to 3.3V PL6 PL5 SW1 H OPEN L GAINSHIFT 0dB mode –3dB mode –6dB mode SW2 H OPEN L MAXGAIN 34dB (VAGCCONT = 3.0V) 26dB (VAGCCONT = 3.0V) 30dB (VAGCCONT = 3.0V) - 10 - AGCCLP C1 1µF C2 1µF AGCCONT V1 1.65 to 3.3V VCC2 3.3V AC V2 PL1 PL2 PL3 VCC1 3.3V V3 1.65 to 3.3V C3 0.1µF CXA3796N Measurement Timing Chart 1H 2µs 2.5V PL4 (CLPOB) 1H 2µs 2.5V PL1 (CLPDM) GND GND 2.5V PL6 (PBLK) GND 1H V2 (DIN) Different for each test Equivalent to CCD signal black level PL2 (SHD) PL3 (SHP) PL5 (XRS) 2.5V GND - 11 - CXA3796N Application Circuit CCD VICONT 1.65 to 3.3V ICONT VCC CLPDM 1µF VCC2 DIN 1µF PIN SHD SHP VCC VAGCCONT 1.65 to 3.3V CCDLEVEL 0.1µF AGCCONT AGCCLP 13 12 CLPOB CLPOB GND 4.7µ CLPDM GND1 24 23 22 21 20 19 18 17 16 VCC1 SHD SHP 15 14 BUF SH1 SH2 AGC DC SHIFT OB SW SH3 DMSW2 CDS CLP2 DMSW1 CDS CLP1 OFFSET VREF CAM SH AGC CLP VRT DRV VRT BLK SW VRB DRV VRB DRV 1 GND2 2 GAINSHIFT 3 GND3 4 DRVOUT 5 VCC3 6 MAXGAIN 7 VRB 8 VRT 9 OFFSET 10 PBLK 11 XRS XRS 22 VCC PBLK OPEN 3.3V OPEN 3.3V VOFFSET 0 to 3.3V A/D IN A/D VRB 4.7µ VRT SW1 H OPEN L GAINSHIFT 0dB mode –3dB mode –6dB mode SW2 H OPEN L MAXGAIN 34dB (VAGCCONT = 3.0V) 26dB (VAGCCONT = 3.0V) 30dB (VAGCCONT = 3.0V) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 12 - CXA3796N Description of Operation Refer to the Block Diagram. Timing Chart (when VCC = 3.3 V) Signal interval Precharge level CCD output OPB interval Idle transfer interval Signal interval Signal level SHP SHD SH1 output SH2 output SH3 output CLPDM (2µ dummy bit portion during the idle transfer interval) AGC output SH3 output − SH2 output × (–N) [∗3] XRS CLPOB (2µ during the OPB interval) 2.5V [∗1] [∗2] 2.5V 2µs Basic black level 0.715V Black level 2µs CAMSH output 0.715V PBLK (10µ during the idle transfer interval) 10µs BLK SW output 1.485V [∗4] DRVOUT output [∗5] Approx. VRB + 40mV when OFFSET = 0V Approx. VRB + 110mV when OFFSET = 1.65V Approx. VRB when OFFSET = 3.3V - 13 - CXA3796N CDS (SH1, SH2, SH3): The CCD signal from the CCD image sensor is input to PIN and DIN where correlated double sampling (CDS) is performed by SH1, SH2 and SH3. The precharge level of the CCD output signal is sampled, held and output by the SH2 output, and the signal level is sampled, held and output by the SH3 output. SH1 and SH2 are the sample-and-hold circuits for the precharge level; SH3 is the sample-and-hold circuit for the signal level. CDSCLP 1, 2: CDSCLP1 and 2 stabilize the input signal DC level, clamp (CLPDM) the input signal during the idle transfer interval for the purpose of eliminating the AGC input offset, and adjust the DC level ([*1], [*2]) of SH2 and SH3 in line with VREF. CDSCLP1 is the clamp circuit for the precharge level, and CDSCLP2 is the clamp circuit for the signal level. AGC: AGC is the gain control amplifier for the camera signal. The gain can be varied from –1 to +31dB (when MAXGAIN = OPEN, GAINSHIFT = VCC) by adjusting the AGCCONT voltage control VAGCCONT from 1.65 to 3.3V. * Gain width can be changed by MAXGAIN = VCC/OPEN/GND, GAINSHIFT = VCC/OPEN/GND setting. CAM SH: CAM SH is the sample-and-hold circuit for synchronizing the data read-in timing for the external A/D. Sampling is possible according to the approximately 10ns sampling pulse width input to XRS. AGCCLP: The basic black level is set ([*3]) by clamping the AGC output waveform with the CLPOB clock during the OPB interval. When PBLK is High and CLPOB is Low, the clamping circuit operates, adjusting the AGCCLP current so that the DRVOUT potential equals the OFFSET potential (which is determined by the voltage applied to the OFFSET pin), thus setting the AGCCLP potential. The AGCCLP capacitance is connected to the AGCCLP pin. DC SHIFT: This circuit functions when AGCCLP operates, following the AGCCLP potential and forcing a DC shift of the AGC output waveform OPB interval to the basic black level. When AGCCLP is not operating, the basic black level is maintained at its previous setting. BLK SW: The black level is calibrated by blanking the black level signal of the AGC output waveform so that it does not fall below the basic black level and replacing the DC potential with VRB. ([*4]) The signal is blanked when PBLK is Low. OFFSET: OFFSET controls the DRV output waveform black level offset. The offset of the DRVOUT camera signals can be adjusted when a voltage is applied to OFFSET. ([*5]) The voltage controlled by OFFSET is output as the DRV output DC offset via AGCCLP, DCSHIFT, CAMSH and BLKSW. When the OFFSET voltage is 1.65 to 3.3V, DRVOUT DC can vary in a linear fashion from VRB + 110mV to VRB. In addition, when the OFFSET voltage is 0V, DRVOUT DC is preset to VRB + 40mV. DRV: DRV drives the external A/D. The current that flows to the last-stage amplifier in DRV is controlled by applying voltage to the ICONT pin, making it possible to adjust the rise time of the output waveform, which affects the external A/D load capacitance. The variable range is 1.65 to 3.3V, with 1.65V yielding the maximum and 3.3V yielding the minimum. The optimum rise time for the external A/D input capacitance can be selected. - 14 - CXA3796N VRT DRV, VRB DRV: These are the external A/D reference voltage drivers. These circuits are connected to A/D VRT and VRB, supplying 2.585V and 1.485V, respectively, when VCC is 3.3V. The IC's internal primary voltage is also generated on the basis of the VRT and VRB voltage. GAINSHIFT: AGC gain curve can be shifted by setting GAINSHIFT as follows. 0dB shift When applying VCC When OPEN –3dB shift When GND –6dB shift MAXGAIN: AGC MAX gain can be changed by setting MAXGAIN as follows. 34dB * when VAGCCOUNT = 3.0V When applying VCC When OPEN 26dB * when VAGCCOUNT = 3.0V When GND 30dB * when VAGCCOUNT = 3.0V CCDLEVEL BUF: This is buffer to monitor SH3 output camera signal and output from CCDLEVEL. SH3 output is output to CCDLEVEL when PBLK = High and internal generation voltage (Vref) is output when PBLK = Low. - 15 - CXA3796N Example of Representative Characteristics AGCCONT control supply voltage characteristics VAGCCONT vs. Gain 40 35 30 25 20 15 10 5 0 −5 0.5 40 35 30 25 Gain [dB] Gain [dB] Gain [dB] 40 GAINSHIFT = VCC (0dB) MAXGAIN = VCC (34dB mode) MAXGAIN = GND (30dB mode) MAXGAIN = OPEN (26dB mode) 25 20 15 10 5 0 −5 0.6 0.7 0.8 VAGCCONT/VCC 0.9 1 −10 0.5 0.6 0.7 0.8 VAGCCONT/VCC 0.9 1 GAINSHIFT = OPEN (−3dB) 35 30 MAXGAIN = VCC (34dB mode) MAXGAIN = GND (30dB mode) MAXGAIN = OPEN (26dB mode) GAINSHIFT = GND (−6dB) MAXGAIN = VCC (34dB mode) MAXGAIN = GND (30dB mode) MAXGAIN = OPEN (26dB mode) 20 15 10 5 0 −5 −10 0.5 0.6 0.7 0.8 VAGCCONT/VCC 0.9 1 - 16 - CXA3796N AGCCONT control supply voltage characteristics VAGCCONT vs. Gain 35 Tc = 27˚C 30 25 Gain [dB] 20 15 10 5 0 −5 1.5 VCC = 3.0V VCC = 3.3V VCC = 3.6V OFFSET [mV] 120 100 80 60 40 20 0 2 2.5 VAGCCONT [V] 3 3.5 0 140 OFFSET control supply voltage characteristics VOFFSET vs. OFFSET Tc = 27˚C VCC = 3.0 VCC = 3.3 VCC = 3.6 1 2 VOFFSET [V] 3 AGCCONT control temperature characteristics AGCCONT vs. Gain 35 30 25 Gain [dB] 20 15 10 5 0 −5 1.65 VCC = 3.3V −20˚C +27˚C +75˚C OFFSET [mV] 140 120 100 80 60 40 20 0 2.15 2.65 VAGCCONT [V] 3.15 0 OFFSET control temperature characteristics VOFFSET vs. OFFSET VCC = 3.3V Tc = −20˚C Tc = +27˚C Tc = +75˚C 1 2 VOFFSET [V] 3 4 - 17 - CXA3796N Maximum signal amplitude temperature characteristics (Max. gain) Tc vs. Vout 1.4 VCC = 3.3V, AGCCONT = 3.3V 1.3 Input amplitude DIN = 28mVpp Input amplitude DIN = 24mVpp Input amplitude DIN = 21mVpp Maximum signal amplitude temperature characteristics (Min. gain) Tc vs. Vout 1.4 VCC = 3.3V, AGCCONT = 1.65V Input amplitude DIN = 700mVpp Input amplitude DIN = 800mVpp Input amplitude DIN = 1Vpp Input amplitude DIN = 1.1Vpp Input amplitude DIN = 1.2Vpp Input amplitude DIN = 1.25Vpp DIN = 1250mVpp 1.3 1.2 1.2 1.1 VOUT [Vpp] 31.23dB 1 VOUT [Vpp] DIN = 28mVpp +0 31.23 –0.18 dB 31.23dB DIN = 24mVpp +0 31.29 –0.16 dB 31.29dB 1.1 31.06dB 1 DIN = 1200mVpp DIN = 1100mVpp DIN = 1000mVpp 0.9 31.29dB 31.13dB 0.9 0.8 31.35dB 0.7 31.35dB DIN = 21mVpp 31.17dB +0 31.235 –0.17 dB 0.8 DIN = 800mVpp 0.7 DIN = 700mVpp 0.6 –20 0 30 Tc [˚C] 80 130 0.6 –20 0 30 Tc [˚C] 80 130 VRT, VRB, VRT − VRB temperature characteristics Tc vs. VRT, VRB, VRT − VRB 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 –40 –20 0 20 40 Tc [˚C] 60 80 100 VRB VCC = 3.3V VRT VRT, VRB, VRT − VRB [V] VRT – VRB - 18 - CXA3796N Package Outline (Unit: mm) 24PIN SSOP (PLASTIC) + 0.2 1.25 – 0.1 ∗7.8 ± 0.1 24 13 0.1 A ∗5.6 ± 0.1 7.6 ± 0.2 1 b 12 0.13 M B 0.65 b = 0.22 ± 0.03 0.1 ± 0.1 0.5 ± 0.2 DETAIL B : PALLADIUM 0˚ to 10˚ NOTE: Dimension "∗" does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.1g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS SONY CODE EIAJ CODE JEDEC CODE SSOP-24P-L01 P-SSOP24-7.8x5.6-0.65 - 19 - + 0.03 0.15 – 0.01 Sony Corporation