CXB1567Q

CXB1567Q Limiting Amplifier for Optical Fiber Communication Receiver For the availability of this product, please contact the sales office. Description The CXB1567Q achieves the 2R optical-fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is also equipped with the signal interruption alarm output function, which is used to discriminate the existence of data input. Features • Auto-offset canceller circuit • Signal interruption alarm outputs • Single 5V power supply Applications • SONET/SDH: 622.08Mb/s • Fiber channel: 531.25Mb/s Absolute Maximum Ratings • Power supply VCC – VEE • Storage temperature Tstg • Input voltage difference: | VD – VD | Vdif • Input voltage Vi • Output current (Continuous) IO (Surge current) Recommended Operating Conditions • Supply voltage VCC – VEE • Operating temperature Ta • Termination resistor (Q/Q) RT1 • Termination resistor (SD/SD) RT2 • Termination voltage VCC – VTT Structure Bipolar silicon monolithic IC 48 pin QFP (Plastic) –0.3 to +7.0 –65 to +150 0.0 to +2.5 –0.3 to VCC 0 to 50 0 to 100 V °C V V mA mA 5.0 ± 0.5 –40 to +85 45 to 55 45 to 55 1.8 to 2.2 V °C Ω Ω V Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94709A63-ST CXB1567Q Block Diagram and Pin Configuration VEED VEED N.C. N.C. VCCDA N.C. N.C. 26 36 VEE 37 35 34 33 32 31 Q 30 29 28 27 25 24 N.C. VEE 23 N.C. 22 VEED 21 VEED 20 VEED 19 VEED SD SD VEED 39 VCCD 40 VEED 41 VCCD 42 UP 43 DOWN 44 VCCA 45 VEEA 46 Alarm Block Peak Hold2 Peak Hold1 Output Buffer Block Limiting Amplifier Block N.C. 38 Q 18 VEED 17 VEED 16 CAP1 15 CAP1 14 N.C. R1 R1 N.C. 47 N.C. 48 R2 13 VEE R2 1 2 3 4 5 6 7 8 9 R3 R3 11 12 10 CAP2 VCCA N.C. VEEA VEEA CAP3 –2– VEEA N.C. N.C. VEE D D CXB1567Q Pin Description Pin No. 1 2 3 4 Typical pin Symbol voltage (V) DC AC VEE N.C. VCCA VEEA 0V –5V –5V Description Negative power supply pin. No connection. Positive power supply pin for analog block. Negative power supply pin for analog block. 5 6 VCCA Equivalent circuit 5 CAP3 –1.8V 80 80 Capacitance connection pins for alarm block peak hold circuit. Connect each pin to VCC in 2000pF. CAP2 pin → Peak hold capacitance connection pin for the limiting amplifier signal CAP3 pin → Peak hold capacitance connection pin for the alarm level setting block Negative power supply pin for analog block. 10p 40µA 10p 40µA VEEA 6 CAP2 –1.8V 7 VEEA –5V –0.9V to –1.7V 100 8 9 10 11 12 13 14 15 16 D N.C. D VEEA N.C. VEE N.C. CAP1 CAP1 –1.3V VCCA Limiting amplifier input pins Ensure that these inputs are AC-coupled. –1.3V –5V 8 10 100 1K 7.5k 130p 200 7.5k 200 16 15 Negative power supply pin for analog block. No connection. Negative power supply pin. –5V 1K VEEA No connection. Capacitance connection pins to determine the cut-off frequency for feedback block. Negative power supply pin for digital block. No connection. –1.8V –1.8V –5V 17 to 22 VEED 23, 24 25 N.C. VEE –5V Negative power supply pin. –3– CXB1567Q Pin No. 26 27 Typical pin Symbol voltage (V) DC N.C. VCCDA 0V AC Equivalent circuit Description No connection. Positive power supply pin for output buffer. 28 Q –0.9V to –1.7V VCCDA 28 Data signal output pins. Terminate these pins in 50Ω at VTT = –2V. 29 Q –0.9V to –1.7V 29 VEED 30 31, 32 N.C. VEED –5V No connection. Negative power supply pin for digital block. 33 SD –0.9V to –1.7V VCCDA 33 Alarm signal output pins. Terminate these pins in 50Ω at VTT = –2V. 34 SD –0.9V to –1.7V 34 VEED 35, 36 37 38 39 40 41 42 N.C. VEE N.C. VEED VCCD VEED VCCD –5V 0V –5V 0V –5V No connection. Negative power supply pin. No connection. Negative power supply pin for digital block. Positive power supply pin for digital block. Negative power supply pin for digital block. Positive power supply pin for digital block. –4– CXB1567Q Pin No. Typical pin Symbol voltage (V) DC AC Equivalent circuit Description VCCA 43 UP –4.7V 100 5k 43 44 1k 100 5k 44 DOWN –5V VEEA Resistor connection pins for alarm level setting. UP pin → When the resistance connected to this pin is increased, the alarm level becomes higher. DOWN pin → Normally connect this pin to VEE. Positive power supply pin for analog block. Negative power supply pin for analog block. No connection. 45 46 47, 48 VCCA VEEA N.C. 0V –5V –5– CXB1567Q Electrical Characteristics • DC characteristics (VCC = VCCA = 0V, VEED= VEEA= VEE = –5V±10%, Ta = –40°C to +85°C, RT = 50Ω, VTT = –2V) Item Supply current Q/Q High output voltage Q/Q Low output voltage SD/SD High output voltage SD/SD Low output voltage Input offset voltage D/D input resistance Symbol IEE VOH VOL VOHS VOLS VOFF Rin 0.75 Ta = 0 to 85°C Conditions Min. –93 –1.03 –1.81 –1.25 –1.95 Typ. –59 –0.95 –1.70 –0.95 –1.76 70 1.0 1.25 –0.88 –1.62 –0.70 –1.57 µV kΩ V Max. Unit mA • AC characteristics (VCC = VCCA = 0V, VEED= VEEA= VEE = –5V±10%, Ta = –40°C to +85°C, RT = 50Ω, VTT = –2V) Item Maximum input data rate Maximum input voltage Limiting amplifier gain Q/Q rise time Q/Q fall time Identification maximum voltage amplitude of alarm level Hysteresis width Alarm response assert time Alarm response deassert time Symbol B VMAX GL TTLH TTHL VMIN Hys TAS TDAS Electrically tested Low → High ∗1 (SD) High → Low ∗2 (SD) Single-ended input voltage at D IC internal amplitude 400mVpp 20% to 80% 20 4 0 2.5 6 8 100 100 Conditions Min. 622.08 1000 66 240 240 450 450 Typ. Max. Unit Mbps mVpp dB ps mVpp dB µs ∗1 CAP2, CAP3 pin capacitance = 2000pF, REX = 400Ω, Vin = 20mVpp (single ended) ∗2 CAP2, CAP3 pin capacitance = 2000pF, REX = 400Ω, Vin = 60mVpp (single ended) –6– CXB1567Q DC Electrical Characteristics Measurement Circuit VTT –2V 51 51 VTT –2V 51 51 V V V V 36 37 35 34 33 32 31 30 29 28 27 26 25 24 39 40 41 Output Buffer Block 38 23 22 21 P/H 2 P/H 1 20 19 42 43 REX 44 45 46 47 48 Alarm Block Limiting Amplifier Block 18 17 16 C2 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 A VEE –5V C3 C3 C1 V VD C1 –7– CXB1567Q AC Electrical Characteristics Measurement Circuit Z0 = 50 Z0 = 50 Z0 = 50 Oscilloscope 50Ω Input Z0 = 50 36 37 35 34 33 32 31 30 29 28 27 26 25 24 39 40 41 Output Buffer Block 38 23 22 21 P/H 2 P/H 1 20 19 42 43 REX 44 45 46 47 48 Alarm Block Limiting Amplifier Block 18 17 16 0.047µF 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 2000pF VEE –3V VCC +2V 2000pF RD VD 1000pF 1000pF RD –8– CXB1567Q Application Circuit VTT –2.0V 51 51 51 51 36 37 35 34 33 32 31 30 29 28 27 26 25 24 39 40 41 Output Buffer Block 38 23 22 21 P/H 2 P/H 1 20 19 42 43 273 44 45 46 47 48 Alarm Block Limiting Amplifier Block 18 17 16 0.047µF 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 2000pF VEE –5.0V 2000pF 1000pF 50 1000pF 50 VD Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –9– CXB1567Q Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceller circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2, as shown in Fig. 2. Similarly, external capacitor C2 and internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 values so as to avoid the occurrence of peaking characteristics. The typical values of R1,R2, C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 10 to a capacitor which has the same capacitance as capacitor C1. RD is the resistor for impedance matching. The same level of output impedance as for the signal source should be applied to Pin 10. R1 (internal) : 1kΩ f2: 160kHz C1 (external) : 1000pF C2 (external) : 0.047µF R2 (internal) : 7.5kΩ f1: 450Hz D C1 RD 8 To IC interior 10 C1 R1 15 C2 16 R2 R1 R2 Fig. 1 Feedback frequency responce Amplifier frequency responce Gain f1 f2 Frequency Fig. 2 – 10 – CXB1567Q 2. Alarm block As shown in Fig. 3, the alarm block requires external resistor REX1 for alarm level setting and peak hold capacitor C3. When the resistance value provided for resistor REX1 is increased, the alarm setting level rises. When the resistance value provided for REX2 is increased, the alarm setting level lowers. However, the voltage of Pin 43 should always be higher than that of Pin 44. Normally, short-circuit Pin 44 to VEE (REX2 = 0). See Fig. 5 for the alarm setting level. In the relationship between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6dB) as shown in Fig. 4. External capacitors C3 are used for input signal and alarm level peak hold capacitance. The C3 capacitance value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The deassert time becomes smaller by connecting resistor R10 between VEE and Pin 5 and resistor R11 between VEE and Pin 6. The REX1 and C3 typical values are indicated below. (A capacitance of approximately 10pF is built in Pins 5 and 6 respectively.) REX1: C3: 273Ω (VDAS = 3mVpp) 2000pF VCCA R7 1k From Limiting amplifier 100 Peak hold Peak hold R8 R7, R8, and R9 values are typical values. 100 R8 SD SD 10p R9 IC interior 43 IC exterior REX1 REX2 R10 C3 44 5k R9 5k VccA 6 5 10p VccA C3 R11 VEE VEE VEE Vcc Vcc VEE Fig. 3 SD output 24 VAS, VDAS (mVpp) High level VDAS → deassert level VAS → assert level 20 VAS 16 Low level 12 VDAS 8 VDAS 0 Hysteresis width VAS Input amplitude 4 0 20 log ( VAS ) = 6.0 dB VDAS 0 200 400 600 REX1 (Ω) 800 1000 1200 Fig. 4 – 11 – Fig. 5 CXB1567Q Example of Representative Characteristics Bit error rate vs. Data input level for each data rate 10–6 VEE = –5.0V, Ta = 27°C, pattern : PRBS223–1 10–7 Bit error rate 10–8 1062.5Mbps 10–9 622.08Mbps 265.5Mbps 10–10 10–11 2 3 4 5 Data input level [mVp-p] Output RMS jitter vs. Data input level 50 40 Output RMS jitter [ps] VEE = –5.0V Ta = 27°C D = 622.08Mbps pattern : PRBS223–1 30 20 10 0 1 10 100 Data input level [mVp-p] 1000 – 12 – CXB1567Q VEE = –5.0V Ta = 27°C D = 265.5Mbps pattern = PRBS223–1 Y Axis = 300mV/div X Axis = 1300ps/div Q VDIN = 2.0Vp-p Q 26.1040ns 32.6040ns 39.1040ns Q VDIN = 500mVpp Q 26.1040ns 32.6040ns 39.1040ns Q VDIN = 2.5mVpp Q 26.1040ns 32.6040ns 39.1040ns – 13 – CXB1567Q VEE = –5.0V Ta = 27°C D = 622.08Mbps pattern = PRBS223–1 Y Axis = 300mV/div X Axis = 500ps/div Q VDIN = 2.0Vp-p Q 23.7300ns 26.2300ns 28.7300ns Q VDIN = 500mVpp Q 23.6600ns 26.1600ns 28.6600ns Q VDIN = 3.0mVpp Q 23.7500ns 26.2500ns 28.7500ns – 14 – CXB1567Q VEE = –5.0V Ta = 27°C D = 1062.5Mbps pattern = PRBS223–1 Y Axis = 300mV/div X Axis = 300ps/div Q VDIN = 2.0Vp-p Q 26.4900ns 27.9900ns 29.4900ns Q VDIN = 500mVpp Q 26.4900ns 27.9900ns 29.4900ns Q VDIN = 10mVpp Q 16.3740ns 17.8740ns 19.3740ns – 15 – CXB1567Q Package Outline Unit: mm 48PIN QFP (PLASTIC) 15.3 ± 0.4 + 0.4 12.0 – 0.1 + 0.1 0.15 – 0.05 36 25 0.15 37 24 48 13 + 0.2 0.1 – 0.1 1 + 0.15 0.3 – 0.1 12 0.8 ± 0.12 M + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 ∗QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g – 16 – 0.9 ± 0.2 13.5