CXB1573R

CXB1573R Post-Amplifier for Optical Fiber Communication Receiver Description The CXB1573R achieves the 2R optical-fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is equipped with the signal detection function, which is used to enable TTL/ECL outputs. Also, the output disable function performs the output shutdown. Features • Output disable function (TTL input) • Signal detection function (TTL/ECL output) Applications • SONET/SDH: • Fibre Channel: : • Gigabit-Ethernet: 32 pin LQFP (Plastic) 622.08Mbps 531.25Mbps 1.062Gbps 1.25Gbps Absolute maximum Ratings • Supply voltage • Storage temperature • Input voltage difference | VD – VD | • SW input voltage • ECL output current • TTL output current (High level) • TTL output current (Low level) • D/DB input voltage • ODIS input voltage Recommended Operating Conditions • Supply voltage • Termination voltage (for data) • Termination voltage (for alarm 1,alarm 2) • Termination resistance (for data) • Termination resistance (for alarm 1) • Termination resistance (for alarm 2) • Operating temperature Structure Bipolar silicon monolithic IC VCC – VEE Tstg Vdif Vi IOQ/SD-ECL IOH SD-TTL IOL SD-TTL –0.3 to +6 –65 to +150 0 to +2 VEE to VCC –30 to 0 –20 to 0 0 to 20 Vcc – 2 to Vcc VEE – 0.5 to VEE + 5.5 V °C V V mA mA mA V V VCC – VEE VCC – VTD VTA RTD RTA1 RTA2 Ta 3.3 ± 0.2 1.8 to 2.2 VEE 46 to 56 240 to 300 460 to 560 –40 to +85 V V V Ω Ω Ω °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98401-PS CXB1573R Block Diagram and Pin Configuration CAP3 CAP2 VEE4 VccZ VEE2 VEEI DN 24 23 22 21 20 19 18 17 VCC4 25 UP 16 VCC2 ∆V SD-TTL 26 peak hold SDB-TTL 27 peak hold 15 VEE1 14 D 13 DB SD-ECL 28 12 CAP1 SDB-ECL 29 11 CAP1B Q 30 10 VccY QB 31 VCC3 32 9 VCC1 1 2 3 4 5 6 7 8 VEE3 SW VCC2 ODIS –2– VccX VEE2 VEE1 TM CXB1573R Pin Description Pin No. 1 Typical pin voltage (V) DC VEE3 0 VCC2 10k Symbol Equivalent circuit Description Negative power supply for ECL output buffer. AC 2 ODIS 0 or 3.3 (Open) 2 300 10k VREF Controls the output shutdown function. High voltage when open; the Q output is fixed to Low. Low voltage when connected to VEE; the D input results in the Q output with ECL level. TTL level is also available. VEE2 VCC2 3 SW 0 or 3.3 (Open) 60k 3 40k Switches the identification maximum voltage amplitude. High voltage when open; the identification maximum voltage amplitude becomes 40mVp-p. Low voltage when connected to VEE; the amplitude becomes 20mVp-p. VEE2 4 5 6 7 VCC2 VccX VEE2 VEE1 3.3 3.3 0 0 Positive power supply for digital block. Positive power supply for digital block. Negative power supply for digital block. Negative power supply for analog block. 7 8 8 TM 1.6 VEE1 Chip temperature monitor. 9 VCC1 3.3 Positive power supply for analog block. –3– CXB1573R Pin No. 10 11 12 Symbol Typical pin voltage (V) DC AC Equivalent circuit Description Positive power supply for analog block. VCC1 VccY CAP1B CAP1 3.3 14 7.5k 200 12 100p 11 13 DB 2 1.6 to 2.4 1.6 to 2.4 13 1k 1k 7.5k 200 VEE1 Pins 11 and 12 connect a capacitor which determines the cut-off frequency for DC feedback block. Pins 13 and 14 are input pins for limiting amplifier block. Input the signal with AC coupled. 14 D 2 15 16 VEE1 VCC2 0 3.3 Negative power supply for analog block. Positive power supply for digital block. Connects a resistor for alarm level setting. Default voltage can be generated without an external resistor by shorting the VEEI pin to VEE. Generates the default voltage between UP and DOWN. The voltage (8.0mV for input conversion) can be generated between UP and DOWN (Pins 17 and 18) as alarm setting level by connecting this pin to VEE. Negative power supply for digital block. 17 UP 986 140.9 VCC2 18 DN 17 18 140.9 100 100 VCS SW SW 19 VEEl 0 19 VEE2 20 VEE2 0 –4– CXB1573R Pin No. Symbol Typical pin voltage (V) DC AC Equivalent circuit Description 21 80 10p VCC2 21 CAP2 1.5 5µA 200 VEE2 22 80 10p VCC2 Connects a peak hold circuit capacitor for alarm block. 470pF should be connected to Vcc each. CAP2 pin connects a peak hold capacitor for alarm level setting block. CAP3 pin connects a peak hold capacitor for limiting amplifier signal. 22 CAP3 1.5 5µA 200 VEE2 23 24 25 VccZ VEE4 VCC4 3.3 0 3.3 VCC4 Positive power supply for ECL output buffer. Negative power supply for TTL output buffer. Positive power supply for TTL output buffer. 26 SD-TTL VEE or 2.2 40k 26 Alarm signal TTL level output. VEE4 –5– CXB1573R Pin No. Symbol Typical pin voltage (V) DC AC Equivalent circuit Description VCC4 27 SDB-TTL VEE or 2.2 40k 27 Alarm signal TTL level output. VEE4 28 SD-ECL 1.6 or 2.4 VCC3 28 29 Alarm signal ECL level output. Terminate this pin in 270Ω to VEE. 29 SDB-ECL 1.6 or 2.4 VEE3 30 Q 1.6 or 2.4 VCC3 30 31 Data signal output. Terminates this pin in 50Ω to VTT = Vcc – 2V. 31 QB 1.6 or 2.4 VEE3 32 VCC3 3.3 Positive power supply for ECL output buffer. –6– CXB1573R Electrical Characteristics DC Characteristics Item Supply current Q/QB High output voltage Q/QB Low output voltage Symbol IEE VOH VOL 50Ω to VTT 270Ω to VEE IOH = –0.4mA Ta = 0 to +85°C IOL = 2mA Ta = 0 to +85°C at SW pin Open: High VCC – 0.5 0 VCC = 3.3 ± 0.2V, VEE = GND, Ta = –40 to +85°C Conditions Min. –74 VCC – 1100 VCC – 1860 VCC – 1100 VCC – 1900 2.2 0.5 VCC 0.5 10 –100 at ODIS pin Open: High 2.0 0 VIH = Vcc VIL = VEE –400 765 Iin = 1mA 1.2 1020 1275 2.0 VCC + 0.5 0.8 20 µA V Typ. –51 VCC – 860 VCC – 1620 VCC – 860 VCC – 1620 mV Max. Unit mA SD-ECL/SDB-ECL High output voltage VOH-E SD-ECL/SDB-ECL Low output voltage SD-TTL/SDB-TTL High output voltage SD-TTL/SDB-TTL Low output voltage SW High input voltage SW Low input voltage SW High input current SW Low input current ODIS High input voltage ODIS Low input voltage ODIS High input current ODIS Low input current D/DB input resistance TM voltage VOL-E VOH-T VOL-T VIHSW VILSW IIHSW IILSW VIHOD VILOD IIHOD IILOD Rin VTM V µA Ω V –7– CXB1573R AC Characteristics Item Maximum input voltage amplitude Symbol Vmax VCC = 3.3 ± 0.2V, VEE = GND, Ta = –40 to +85°C Conditions single-ended input Min. 1600 52 SW: Low, single-ended input 20 mVp-p 40 3 3 6 6 7 dB 7 Typ. Max. Unit mVp-p dB Amplifier gain (excluding the output buffer) GL Identification maximum voltage amplitude of alarm level VmaxA1 SW: Open High, VmaxA2 single-ended input ∆P1 SW: Low, at default alarm level SW: Open High, at default alarm level SW: Open High, VEEI = VEE, fin = 100Mbps Differential voltage input 20% to 80% 50Ω to VTT 0.6V to 2.2V CL = 10pF 20% to 80% 510Ω to VEE SD/SDB hysteresis width ∆P2 Alarm setting level for default Q/QB rise time Q/QB fall time SD-TTL/SDB-TTL rise time SD-TTL/SDB-TTL fall time SD-ECL/SDB-ECL rise time SD-ECL/SDB-ECL fall time Propagation delay time SD response assert time SD response deassert time SD response assert time for alarm level default SD response deassert time for alarm level default Vdef TrQ TfQ TrSDT TfSDT TrSDE TfSDE TPD Tas Tdas Tasd Tdasd 6.6 8.0 230 230 9.3 350 350 10 10 1.6 1.6 mV ps ns 0.4 ∗1 ∗2 ∗3 ∗4 0 2.3 0 2.3 1.9 100 100 100 100 µs ∗1 VUP – VDOWN = 100mV, Vin = 100mVp-p (single ended), SW: High, peak hold capacitance (CAP2, CAP3 pins) of 470pF, VEEI: Open. ∗2 VUP – VDOWN = 100mV, Vin = 1Vp-p (single ended), SW: High, peak hold capacitance (CAP2, CAP3 pins) of 470pF, connect VEEI: Open. ∗3 Vin = 50mVp-p (single ended), SW: Low, peak hold capacitance of 470pF, connect VEEI to VEE. ∗4 Vin = 1Vp-p (single ended), SW: Low, peak hold capacitance of 470pF, connect VEEI to VEE. –8– CXB1573R DC Electrical Characteristics Measurement Circuit C3 C3 CAP3 CAP2 VccZ VEE4 VEE2 VEEI DN 24 23 22 21 20 19 18 UP 17 VCC4 25 16 VCC2 VEE1 ∆V SD-TTL 26 peak hold SDB-TTL 27 SD-ECL 270 SDB-ECL 29 270 Q 30 51 QB 51 VTT 1.3V VCC3 32 9 31 VCC1 10 VccY 11 28 12 CAP1B C2 peak hold DB 13 CAP1 14 C1 15 C1 VD D 1 2 3 4 5 6 7 8 VCC2 VEE3 VEE2 SW ODIS VccX VEE1 TM 3.3V VODIS VSW –9– CXB1573R AC Electrical Characteristics Measurement Circuit 470p 470p REX1 CAP3 CAP2 VccZ VEE4 VEE2 VEEI DN 24 23 22 21 20 19 18 UP 17 VCC4 25 16 VCC2 VEE1 ∆V SD-TTL 26 Oscilloscope Hi-Z input peak hold SDB-TTL 27 SD-ECL Z0 = 50 SDB-ECL Z0 = 50 Oscilloscope 50Ω input Z0 = 50 QB Z0 = 50 VCC3 32 9 31 VCC1 Q 30 10 29 11 VccY 28 12 CAP1B 1µF peak hold DB 13 CAP1 0.047µF 14 15 D 0.047µF 1 2 SW ODIS VCC2 VccX VEE3 VEE2 VCC +2V VEE –1.3V – 10 – VEE1 TM 3 4 5 6 7 8 CXB1573R Application Circuit VEE 470p 470p VccZ CAP3 VEE4 CAP2 VEE2 REX1 VEEI DN 24 23 22 21 20 19 18 VCC4 25 UP 17 16 VCC2 51Ω 0.047µF Signal Generator 51Ω VIN ∆V SD-TTL 26 TTL Output peak hold SDB-TTL 27 SD-ECL 28 ECL Output SDB-ECL 29 51Ω ECL Output 51Ω VCC –2V QB 31 Q 30 peak hold 15 VEE1 VTT D 14 DB 13 CAP1 12 CAP1B 11 0.047µF 51Ω VTT VTT 1µF 51Ω 10 VccY VCC3 32 9 VCC1 1 2 3 4 5 6 7 8 ODIS SW VccX VEE1 VCC2 VEE3 TTL Input VEE Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 11 – VEE2 TM CXB1573R Notes on Operation 1. Limiting amplifier block The limiting amplifier block is equipped with the auto-offset canceler circuit. When external capacitors C1 and C2 are connected as shown in Fig. 1, the DC bias is set automatically in this block. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 as shown in Fig. 2. Similarly, external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 values so as to avoid the occurrence of peaking characteristics. The target values of R1 and R2 and the typical values of C1 and C2 are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 13 to a capacitor which has the same capacitance as capacitor C1. R1 (internal): 1kΩ f2: 3.4kHz C1 (external): 0.047µF C2 (external): 1µF R2 (internal): 7.5kΩ f1: 21Hz D C1 14 To IC interior 13 C1 R1 R1 R2 12 C2 11 R2 Fig. 1 Feedback frequency response Amplifier frequency response Gain f1 f2 Frequency Fig. 2 – 12 – CXB1573R 2. Alarm block In order to operate the alarm block, give the voltage difference between Pins 17 and 18 to set an alarm level and connect the peak hold capacitor C3 shown in Fig. 3. This IC has two setting methods of alarm level; one is to connect Pin 19 to VEE and leave Pins 17 and 18 open to set an alarm level default value (8mV for input conversion). The other is to connect Pin 19 to VEE and set a desired alarm level using the external resistors REX1, REX2 and REX3 shown in Fig. 3. Connect REX1 between Pins 17 and 18 or connect REX3 between Pin 18 and Vcc when less alarm level is desired to be set than its default value; connect REX2 between Pin 17 and Vcc when more alarm level is desired to be set than its default value. However, the Pin 17 voltage must be higher than that of Pin 18. This IC also features two-level setting of identification maximum voltage amplitude. The amplitude is set to 40mVp-p when Pin 3 is left open (High level) and it is set to 20mVp-p when Pin 3 is Low level. Therefore, the noise margin can be increased by setting Pin 3 to Low level when the small signal is input. The relation of input voltage and peak hold output voltage is shown in Fig. 5. In the relation between the alarm setting level and hysteresis width, the hysteresis width is designed to maintain a constant gain (design target value: 6dB) as shown in Fig. 4. This IC is designed to externally have the capacitor C3, and the C3 value should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The electrical characteristics for the SD response assert and deassert times are guaranteed only when the waveforms are input as shown in the timing chart of Fig. 6. REX1: 100Ω (when the alarm level is set to 4mV for input conversion.) REX2: 8kΩ (when the alarm level is set to 10mV for input conversion.) REX3: 4kΩ (when the alarm level is set to 4mV for input conversion.) C3: 470pF The table below shows the alarm logic. Optical signal input state Signal input Signal interruption SD High level Low level SD Low level High level The table below shows the output disable function logic. Optical signal input state ODIS: Open High ODIS: Low Q Fixed Low Data Q Fixed High Data Ra1, Ra2A and Ra2B values are typical values. VCCA Ra1 986 Ra2A 141 Ra2B 141 From limiting amplifier Peak Hold SD-TTL SDB-TTL Peak Hold SD-ECL SDB-ECL VCCA VCS ∆V 3 IC interior 17 18 19 19 17 18 21 22 10p 10p VCCA VEEI UP DN IC exterior REX2 VEE REX1 C3 REX3 VCC VCC C3 VCC VCC Fig. 3 – 13 – CXB1573R VDAS → Deassert level VAS → Assert level High level SD output Peak hold output voltage Low level SW → Low VDAS Small 3dB 3dB Alarm setting input level Hysteresis Input electrical signal amplitude VAS Large SW → Open High 0 20 40 Input voltage [mVp-p] Fig. 4 Fig. 5 Data input (D) Hysteresis width Alarm setting level Data output (Q) Alarm output (SD) Assert time Deassert time Fig. 6 – 14 – CXB1573R Example of Representative Characteristics 1. Q/QB output waveform Q VCC = 3.3V VEE = GND VTT = 1.3V Ta = 27°C D = 622Mbps Vin = 5mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 500ps/div Fig. 7 Q VCC = 3.3V VEE = GND VTT = 1.3V Ta = 27°C D = 622Mbps Vin = 10mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 500ps/div Fig. 8 Q VCC = 3.3V VEE = GND VTT = 1.3V Ta = 27°C D = 1.25Gbps Vin = 5mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 200ps/div Fig. 9 – 15 – CXB1573R Q VCC = 3.3V VEE = GND VTT = 1.3V Ta = 27°C D = 1.25Gbps Vin = 10mVp-p Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT QB Ch. 1 = 400mV/div OFFSET = –1330mV, Ch. 2 = 400mV/div OFFSET = –1330mV, Timebase = 200ps/div Fig. 10 2. Bit error rate Bit error rate vs. Data input level 10 –3 10 –4 10 –5 622Mbps 1.0Gbps 1.25Gbps VCC = 3.3V VEE = GND VTT = 1.3V Ta = 27°C Single input pattern: PRBS223-1 Q/QB = 50Ω to VTT Bit error rate 10 –6 10 –7 10 –8 10 –9 10 –10 1.5 2 2.5 3 3.5 Data input level [mVp-p] 4 4.5 3. Alarm level Alarm level vs. REX1 9 8 7 SW = H SW = L Fig. 11 Alarm level vs.Temperature 6.0 5.5 5.0 SW = H SW = L Alarm level [mV] Alarm level [mV] fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C Differential input 103 UP-DOWN (REX1) [Ω] 104 4.5 4.0 3.5 3.0 2.5 2.0 –40 –20 0 20 40 Ta [°C] 60 80 100 fin = 100Mbps VCC – VEE = 3.3V Up-Down = 200Ω (REX1) 6 5 4 3 2 102 Fig. 12 Fig. 13 – 16 – CXB1573R Alarm level vs. Supply voltage 6.0 5.5 5.0 SW = H SW = L 16 15 14 Alarm level vs. REX2 fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C Differential input Alarm level [mV] Alarm level [mV] fin = 100Mbps Ta = 27°C Up-Down = 200Ω (REX1) 3.1 3.2 3.4 3.3 VCC – VEE [V] 3.5 3.6 4.5 4.0 3.5 3.0 2.5 2.0 3.0 13 12 11 10 9 8 103 SW = H SW = L 104 VCC-UP (REX2) [Ω] 105 Fig. 14 Alarm level vs. Temperature 15.0 14.5 14.0 SW = H SW = L 15.0 14.5 14.0 SW = H SW = L Fig. 15 Alarm level vs. Supply voltage Alarm level [mV] 13.5 13.0 12.5 12.0 11.5 11.0 –40 –20 0 20 40 Ta [°C] 60 80 100 fin = 100Mbps VCC – VEE = 3.3V VCC-UP = 5kΩ (REX2) Alarm level [mV] 13.5 12.0 12.5 12.0 11.5 11.0 3.0 fin = 100Mbps Ta = 27°C VCC-UP = 5kΩ (REX2) 3.1 3.2 3.4 3.3 VCC – VEE [V] 3.5 3.6 Fig. 16 Alarm level vs. REX3 9 SW = H SW = L 8 6.0 5.5 5.0 SW = H SW = L Fig. 17 Alarm level vs. Temperature fin = 100Mbps VCC – VEE = 3.3V VCC-Down = 3kΩ (REX3) Alarm level [mV] Alarm level [mV] fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C Differential input 104 VCC-DOWN (REX3) [Ω] 105 7 4.5 4.0 3.5 3.0 2.5 –40 –20 0 20 40 Ta [°C] 60 80 100 6 5 4 3 103 Fig. 18 Fig. 19 – 17 – CXB1573R Alarm level vs. Supply voltage 6.0 5.5 5.0 SW = H SW = L fin = 100Mbps Ta = 27°C VCC-Down = 3kΩ (REX3) 8.0 7.0 6.0 5.0 Hysteresis width vs. Alarm level SW = H SW = L Alarm level [mV] 4.5 4.0 3.5 3.0 2.5 2.0 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 3.6 HYS [dB] 4.0 3.0 2.0 1.0 0 2.0 fin = 100Mbps VCC – VEE = 3.3V Ta = 27°C 4.0 6.0 10.0 8.0 Alarm level [mV] 12.0 14.0 Fig. 20 Hysteresis width vs. Temperature 8.0 7.0 6.0 5.0 SW = H SW = L 8.0 7.0 6.0 5.0 SW = H SW = L Fig. 21 Hyteresis width vs. Supply voltage HYS [dB] 4.0 3.0 2.0 1.0 0 –40 –20 0 20 40 Ta [°C] 60 80 fin = 100Mbps VCC – VEE = 3.3V Up, Down = Open VEEI = VEE HYS [dB] 4.0 3.0 2.0 1.0 0 3.0 fin = 100Mbps Ta = 27°C Up, Down = Open VEEI = VEE 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 3.6 Fig. 22 Alarm level vs. Data rate 16 14 12 SW = H SW = L 10 12 SW = H SW = L Fig. 23 Hysteresis width vs. Data rate Alarm level [mV] 8 10 8 6 4 2 0 200 400 600 800 fin [Mbps] 1000 1200 1400 VCC – VEE = 3.3V Ta = 27°C Up, Down = Open VEEI = VEE 2 VCC – VEE = 3.3V Ta = 27°C Up, Down = Open VEEI = VEE 0 200 400 600 800 fin [Mbps] 1000 1200 1400 HYS [dB] 6 4 0 Fig. 24 Fig. 25 – 18 – CXB1573R 4. DC voltage SD-ECL "H" level vs. Supply voltage –860 SD-ECL SDB-ECL –900 Ta = 27°C –900 –860 SD-ECL SDB-ECL VCC – VEE = 3.3V SD-ECL "H" level vs. Temperature "H" level [mV] –980 "H" level [mV] 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 3.6 –940 –940 –980 –1020 –1020 –1060 –1060 –1100 –1100 –40 –20 0 20 40 Ta [°C] 60 80 100 Fig. 26 SD-ECL "L" level vs. Supply voltage –1640 –1680 SD-ECL SDB-ECL Ta = 27°C –1680 –1640 SD-ECL SDB-ECL Fig. 27 SD-ECL "L" level vs. Temperature VCC – VEE = 3.3V –1720 –1720 "L" level [mV] –1760 "L" level [mV] 3.0 3.1 3.2 3.4 3.3 VCC – VEE [V] 3.5 3.6 –1760 –1800 –1800 –1840 –1840 –1880 –1880 –40 –20 0 20 40 Ta [°C] 60 80 100 Fig. 28 SD-TTL "H" level vs. Supply voltage 3.4 Ta = 27°C 3.2 3.2 3.4 Fig. 29 SD-TTL "H" level vs. Temperature VCC – VEE = 3.3V 3.0 3.0 "H" level [V] 2.8 "H" level [V] 3.1 3.2 3.4 3.3 VCC – VEE [V] 3.5 3.6 2.8 2.6 2.6 2.4 2.4 2.2 3.0 2.2 –40 –20 0 20 40 Ta [°C] 60 80 100 Fig. 30 Fig. 31 – 19 – CXB1573R SD-TTL "L" level vs. Supply voltage 400 Ta = 27°C 400 SD-TTL "L" level vs. Temperature VCC – VEE = 3.3V 350 350 "L" level [mV] 300 "L" level [mV] 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 3.6 300 250 250 200 200 –40 –20 0 20 40 Ta [°C] 60 80 100 Fig. 32 Q "H" level vs. Supply voltage –860 Q-H QB-H –900 Ta = 27°C –900 –860 Q-H QB-H Fig. 33 Q "H" level vs. Temperature VCC – VEE = 3.3V "H" level [mV] –980 "H" level [mV] 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 3.6 –940 –940 –980 –1020 –1020 –1060 –1060 –1100 –1100 –40 –20 0 20 40 Ta [°C] 60 80 100 Fig. 34 Q "L" level vs. Supply voltage –1620 Q-L QB-L –1660 Ta = 27°C –1660 –1620 Q-L QB-L Fig. 35 Q "L" level vs. Temperature VCC – VEE = 3.3V –1700 –1700 "L" level [mV] –1740 "L" level [mV] 3.0 3.1 3.3 3.2 3.4 VCC – VEE [V] 3.5 3.6 –1740 –1780 –1780 –1820 –1820 –1860 –1860 –40 –20 0 20 40 Ta [°C] 60 80 100 Fig. 36 Fig. 37 – 20 – CXB1573R Package Outline Unit: mm 32PIN LQFP (PLASTIC) 7.0 1.7MAX 5.0 B 24 17 B A 25 16 A S 0.08 S 32 9 1 X4 0.2 S AB 0.5 8 X4 0.2 0.08 M S S AB AB 0.25 0.1 ± 0.05 0.2 ± 0.03 (0.2) 0° to 8° (0.5) DETAIL A DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-32P-L01 LQFP032-P-0505 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.1g NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). – 21 – (0.125) 0.125 ± 0.02 0.6 ± 0.15 (0.5)