CXB1582Q

CXB1582Q Fibre Channel Receiver Description The CXB1582Q is a receiver IC with a built-in PLL clock recovery circuit for high-speed serial data reception. It can be used together with the transmitter IC CXB1581Q as a chip set, and 1062.5Mbaud, 20bit or 531.25Mbaud, 10-bit operation can be selected. Features • Conforms to ANSI X3T11 Fibre channel standard • Supports GLM (Gigabaud Link Module) interface • Built-in low-jitter PLL clock recovery circuit • Single 3.3V power supply or dual 3.3V/5V power supply (for 5V TTL interface) operation can be selected. • Low power consumption: 910mW (Typ.) when operating with a single 3.3V power supply • 1062.5Mbaud, 20-bit or 531.25Mbaud, 10-bit operation can be selected. • PLL lock detection circuit • Power-on reset signal output circuit 80 pin QFP (Plastic) Applications Fibre channel 1062.5Mbaud and 531.25Mbaud communications Structure Bipolar silicon monolithic IC TJMON SOUT∗ PTEST LPF_B EXCLK LPF_A VEEP2 VEEP1 SDIN SDIN∗ SOUT REXT LBIN LBIN∗ Pin Configuration VCCG VCCE VCCE 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VEEG 61 VCCG 62 LBEN 63 SHD 64 LCKREF∗ 65 SYNCEN 66 SDRSEL 67 PPSEL 68 REFCLK 69 RTCAP 70 POR∗ 71 VCCT5 72 VCCT3 73 VEET 74 VEEG 75 VCCG 76 VCCG 77 RX19 78 RX18 79 RX17 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 ECLKSEL∗ 39 PDTEST 38 SSEL0 37 SSEL1 ∗ 36 LKDT 35 SYNC 34 RBC1 33 RBC0 32 VEET 31 VCCT5 30 VCCT3 29 VEET 28 RX0 27 RX1 26 VEEG 25 VCCG 24 VCCT5 23 VCCT3 22 RX2 21 RX3 VCCP VCCT3 RX16 RX12 RX13 VEET VCCT5 VCCT3 RX10 RX14 VEET Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– VCCT5 RX15 RX11 VEET RX8 RX9 RX7 RX6 RX5 RX4 VEEG VEEE E95930-ST CXB1582Q Absolute Maximum Ratings (VEEE, VEET, VEEG, VEEP = 0V) Item Supply voltage (excluding VCCT5) Supply voltage for TTL output TTL DC input voltage ECL DC input voltage ECL differential input voltage TTL output current (High level) TTL output current (Low level) ECL output current Operating ambient temperature Storage temperature Symbol VCC VCCT5 VI_T VI_E VIS_E IOH_T IOL_T IO_E Ta Tstg Min. –0.3 VCCG – 2, or –0.3 –0.5 VCC – 2 –2 –20 0 –30 –55 –65 Typ. Max. 4 VCCG + 5, or 5.5 5.5 VCC 2 0 20 0 70 150 Unit V V V V V mA mA mA °C °C Recommended Operating Conditions (VEEE, VEET, VEEG, VEEP = 0V) During single 3.3V power supply operation Item Supply voltage (including VCCT5) Ambient temperature Symbol VCC Ta Min. 3.135 0 Typ. 3.3 Max. 3.465 70 Unit V °C During dual 3.3V/5V power supply operation (VCCT3 open) Item Supply voltage (excluding VCCT5) Power supply for TTL output Ambient temperature Symbol VCC VCCT5 Ta Min. 3.135 4.75 0 Typ. 3.3 5 Max. 3.465 5.25 70 Unit V V °C –2– CXB1582Q Block Diagram ECL Output Selector PPSEL SSEL0 SSEL1 LBEN SHD SOUT/SOUT∗ 53.125Mbaud Data Output Controll 10 10 53.125Mbaud RX10 to 19 RX00 to 09 SDIN/SDIN∗ LBIN/LBIN∗ 0 1 DFF S/P Converter 531.25 or 1062.5MHz 20 Byte Sync SYNC 53.125MHz REFCLK LPF_A PLL LPF_B REXT 1 0 Parallel Clock Generator 53.125MHz RBC0 RBC1 LKDT∗ EXCLK LCKREF∗ ECLKSEL∗ SYNCEN SDRSEL Power On Reset Output Generator POR∗ RTCAP –3– CXB1582Q Pin Description Pin No. Symbol Type Power supply Typical pin I/O voltage 0V Equivalent circuit Description Negative power supplies for TTL output. VCCT5 1, 10, 19, 29, VEET 32, 74 78 to 80, 2 to 4, 7 to 9, 11 RX19 to RX17, RX16 to RX14, RX13 to RX11, RX10 — VCCT3 TTL output TTL level RX10 to 19 Parallel data outputs (Byte_1). VEET VCCT5 12 13, 16 to 18, 20 to 22, 27 28 RX09, RX08, RX07 to RX05, RX04 to RX02, RX01, RX00 VCCT3 TTL output TTL level RX00 to 09 Parallel data outputs (Byte_0). The first data of the serial data is RX00 and the last data is RX19 (RX09 during 531Mbaud mode). VEET VCCT5 5, 14, 23, 30 VCCT3 73 Power 3.3V or open supply VCCG VCCT3 VEET VCCT5 Positive power supply for TTL output. Set to 3.3V when using the IC with a single 3.3V power supply; leave open when using the IC with a dual 3.3V/5V power supply. 6, 15, 24, 31 VCCT5 72 Power supply VCCT5 3.3V or 5V VCCG VEET Positive power supply for TTL output. Set to 3.3V when using the IC with a single 3.3V power supply; to 5V when using the IC with a dual 3.3V/5V power supply. –4– CXB1582Q Pin No. Symbol Type Power supply Power supply Typical pin I/O voltage 3.3V Equivalent circuit Description Positive power supplies for internal logic gate. Negative power supplies for internal logic gate. VCCT5 25, 42, 62, 76, VCCG 77 26, 41, VEEG 61, 75 — 0V — VCCT3 33 RBC0 TTL output TTL level RBC0 Receive byte clock 0 output. This clock is used when loading parallel data (RX00 to RX19) using the system in the next stage. VEET VCCT5 VCCT3 34 RBC1 TTL output TTL level RBC1 Receive byte clock 1 output. Inverse of the RBC0 clock. VEET VCCT5 VCCT3 35 SYNC TTL output TTL level SYNC Byte sync output. This pin outputs high level when +Comma (0011111) or –Comma (1100000) is detected in the serial data. (See the Timing Charts.) VEET –5– CXB1582Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit VCCT5 Description VCCT3 36 LKDT∗ TTL output TTL level LKDT∗ PLL lock detection signal output. This pin outputs low level when the PLL is locked to the serial data and high level when the PLL becomes unlocked. VEET VCCG 37 38 SSEL1 SSEL0 TTL input TTL level SSEL0 SSEL1 SOUT/SOUT∗ output signal selection. (See Table 1.) VEET VEET VCCG 39 PDTEST TTL input 0V PDTEST Test. Connect to VEEG. VEET VEET VCCG 40 TTL ECLKSEL∗ input TTL high level or 3.3V ECLKSEL∗ External clock selection. When this pin is set to low level, the clock input to EXCLK is used as the bit rate clock. VEET VEET –6– CXB1582Q Pin No. Symbol Type Typical pin I/O voltage VCCE Equivalent circuit VCCG Description 43 44 SDIN∗ SDIN ECL input (differen -tial) SDIN ECL level SDIN∗ VCCE – 1.3V Serial data inputs. These input pins are enabled when SHD is set to low level. VEEE VEEG 45, 58 VCCE Power supply 3.3V VCCE — VCCG Positive power supplies for ECL I/O. 46 47 LBIN∗ LBIN ECL input (differen -tial) LBIN ECL level LBIN∗ VCCE – 1.3V Serial data inputs for loop-back test. These input pins are enabled when LBEN is set to high level. VEEE VCCE VEEG VCCG EXCLK VCCE – 1.3V 48 EXCLK ECL input ECL level VEEE VEEG External clock input. When ECLKSEL∗ is set to low level, the clock input to this pin is used as the bit rate clock. This pin is biased to become low level when left open. Positive power supply for internal PLL. 49 VCCP Power supply 3.3V — VCCP 50 REXT External part connec -tion pin — REXT VEEP2 Connects the resistor which determines the VCO center frequency. Connect a 4.7kΩ resistor between this pin and VEEP1. (See Notes on Operation and Fig. 1.) Negative power supply for internal PLL. Negative power supply for internal PLL. 51 VEEP1 Power supply Power supply 0V — 52 VEEP2 0V –7– — CXB1582Q Pin No. Symbol Type Typical pin I/O voltage VCCP Equivalent circuit Description 53 LPF_A External part connec -tion pin LPF_A LPF_B — External loop filter connection. (See Notes on Operation and Fig. 1.) VEEP2 VEEP1 VCCP 54 LPF_B External part connec -tion pin LPF_A LPF_B — External loop filter connection. (See Notes on Operation and Fig. 1.) VEEP2 VEEP1 VCCE VCCG TJMON 55 PTEST TTL input 0V PTEST Test. Connect to VEEP1. VEEE VEEG VCCE VCCG TJMON 56 TJMON Test pin 0V PTEST Junction temperature measurement. Connect to VEEP. VEEE VEEG 57 VEEE Power supply 0V — Negative power supply for ECL I/O. –8– CXB1582Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCE 59 60 SOUT∗ SOUT ECL output (differen -tial) SOUT ECL level SOUT∗ High-speed signal monitor. The monitored signal can be selected with SSEL0/1. (See Table 1.) VEEE VCCG 63 LBEN TTL input TTL level LBEN Loop-back enable. When this pin is set to high level, LBIN functions as a serial data input. VEET VEET VCCG 64 SHD TTL input TTL level SHD Serial data input shutdown. When this pin is set to high level, the serial data is fixed to low level regardless of the signal input to SDIN. VEET VEET VCCG 65 LCKREF∗ TTL input TTL level LCKREF∗ Lock-to-reference signal input. Setting this pin to low level forcibly locks the PLL to REFCLK. VEET VEET –9– CXB1582Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description Byte sync enable signal input. When this pin is set to high level, +Comma (0011111) or –Comma (1100000) is detected and the parallel data is synchronized to this byte. (See the Timing Charts.) When this pin is set to low level, byte synchronization is not performed. VCCG 66 SYNCEN TTL input TTL level SYNCEN VEET VEET VCCG 67 SDRSEL TTL input TTL level SDRSEL Serial data rate selection. Setting this pin to low level selects 531.25Mbaud mode and to high level selects 1.0625Gbaud mode. VEET VEET VCCG 68 PPSEL TTL input TTL level PPSEL VEET VEET Ping-Pong mode selection. When this signal is set to high level during 1.0625Gbaud mode (SDRSEL = high), parallel data is output during PingPong mode. In other words, byte 0 is output in sync with the rise of RBC0, and byte 1 with the rise of RBC1. (See the Timing Charts.) – 10 – CXB1582Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description Reference clock input. This pin is used for PLL frequency pull-in. Input the clock with 1/20 frequency of the serial data rate during 1.0625Gbaud mode or with 1/10 frequency of the serial data rate during 531.25Mbaud mode (around 53.125MHz in either case). VCCG 69 REFCLK TTL input TTL level REFCLK VEET VEET VCCG VCCT5 70 RTCAP External part connec -tion pin RTCAP — Connects the capacitor which determines the POR∗ (power-on reset signal) low time. (See Notes on Operation and Fig. 4.) VEEG VEET VCCT5 VCCT3 71 POR∗ TTL output TTL level POR∗ Power-on reset signal output. When the power is turned on, POR∗ maintains low level for approximately 100ns and then goes to high level. (See Notes on Operation and Fig. 4.) VEET – 11 – CXB1582Q SSEL0 0 1 0 1 SSEL1 0 0 1 1 SOUT/SOUT∗ Non Retimed Serial Data. Retimed Serial Data. Recovered Bit Rate Clock Testing output. Fixed to low. Table 1. Monitor Output (SOUT) Selection Table – 12 – CXB1582Q Timing Charts VTH_H 1.5V VTH_L RBC0 Tof_T Tor_T Tskew RBC1 Ts Th Ts Th VTH_H COMMA CHARACTER Valid 1.5V VTH_L RX00 to 19 or RX00 to 09 during Ping-Pong mode Tof_T Tor_T VTH_H 1.5V VTH_L SYNC Ts Th VTH_H Valid Valid 1.5V VTH_L RX10 to 19 during Ping-Pong mode Tof_T Tor_T During single 3.3V power supply operation: VTH_L = 0.8V, VTH_H = 2.0V During dual 3.3V/5.0V power supply operation: VTH_L = 0.6V, VTH_H = 2.2V – 13 – CXB1582Q Electrical Characteristics DC Characteristics (under the recommended operating conditions) Item TTL high level input voltage TTL low level input voltage TTL high level input current TTL low level input current TTL high level output voltage Single 3.3V power supply Dual 3.3V/5V power supply TTL low level output voltage Single 3.3V power supply Dual 3.3V/5V power supply ECL high level input voltage ECL low level input voltage VIH_E VIL_E VCC – 1.17 VCC – 1.81 200 VCC – 1.05 VCC – 1.81 650 VOL_T 0.5 0.5 VCC – 0.88 VCC – 1.48 1000 VCC – 0.81 VCC – 1.55 V V V V mV V V mV AC coupling input 50Ω terminated to VCC – 2V 50Ω terminated to VCC – 2V 50Ω terminated to VCC – 2V Output pins open ICC 274 182 99 343 228 124 mA mA mA 3.3V power supply 5V power supply (VCCT5) Output pins open PD 0.91 1.10 1.19 1.44 W W IOL = 2mA IOL = 4mA VOH-T 2.2 2.6 V V IOH = –0.4mA IOH = –0.4mA Symbol VIH_T VIL_T IIH_T IIL_T –400 Min. 2 0 Typ. Max. 5.5 0.8 20 Unit V V µA µA VIH = VCC VIL = 0 Conditions ECL differential input voltage VIS_E ECL high level output voltage VOH_E ECL low level output voltage VOL_E ECL output amplitude Current consumption Single 3.3V power supply Dual 3.3V/5V power supply Power consumption Single 3.3V power supply Dual 3.3V/5V power supply VOS_E – 14 – CXB1582Q AC Characteristics (under the recommended operating conditions) Item REFCLK rise time REFCLK fall time TTL output rise time Single 3.3V power supply Dual 3.3V/5V power supply TTL output fall time Single 3.3V power supply Dual 3.3V/5V power supply ECL output rise time ECL output fall time SDIN data rate 531.25Mbaud mode 1062.5Mbaud mode REFCLK cycle tolerance RBC0/1 skew RBC duty cycle RX setup time RX hold time Jitter tolerance Bit sync time Frequency acquisition time Ttol_RC Tskew DC_RBC Ts Th JT Tbs Tfa R_SDIN 500 1000 –100 –1 40 3 7.53 0.7 2500 500 531.25 1062.5 0 550 Mbaud Tor_E Tof_E Tof_T 3.5 3.2 400 400 ns ns ps ps 2.0 to 0.8V, CL = 10pF 2.2 to 0.6V, CL = 10pF 20 to 80%, CL ≤ 2pF 20 to 80%, CL ≤ 2pF Tor_T 3.5 3.2 ns ns 0.8 to 2.0V, CL = 10pF 0.6 to 2.2V, CL = 10pF Symbol Tir_RC Tif_RC Min. Typ. Max. 4.8 4.8 Unit ns ns 0.8 to 2.0V 2.0 to 0.8V Conditions 1100 Mbaud 100 1 60 ppm ns % ns ns UI bit µs FC Idle Pattern Loop Damping Capacitor C1 = 0.01µF RBC reference RBC reference Using the SDIN cycle as a reference – 15 – CXB1582Q Electrical Characteristics Measurement Circuit (See Fig. 3 Power Supply Circuits regarding the power supply.) II_T Measurement device TTL_IN TTL_OUT Io_T A VI_T V Vo_T (a) TTL I/O DC characteristics measurement circuit Measurement device Pulse generator TTL_IN TTL_OUT CL Probe Oscilloscope CL = 10pF (including the probe capacitance) (b) TTL I/O AC characteristics measurement circuit II_E Measurement device ECL_IN ECL_OUT 50Ω VCCE – 2V A VI_TE V VO_E (c) ECL I/O DC characteristics measurement circuit VCCE – 2V 50Ω Pulse generator 50Ω 50Ω Transmission Line VCCE – 2V VCCE – 2V 50Ω Oscilloscope 50Ω VCCE – 2V Measurement device ECL_IN ECL_IN∗ ECL_OUT ECL_OUT∗ CL ≤ 2pF (input capacitance of the measurement instrument and floating capacitance) (d) ECL I/O AC characteristics measurement circuit 26.5625MHz Measurement device VCCE – 2V 50Ω Triger Pulse pattern generator 1.0625Gbps SDIN SDIN∗ SOUT 1.0625Gbps SOUT∗ 50Ω VCCE – 2V Oscilloscope (e) Jitter characteristics measurement circuit – 16 – CXB1582Q Notes on Operation 1. Clock synthesizer (PLL) The CXB1582Q has a built-in PLL-based clock recovery circuit which recovers the clock from the serial data. This clock recovery circuit requires an external loop filter and an external resistor which determines the VCO center frequency. The external part circuit and recommended constant values are shown in the figure below. The parasitic capacitance attached to the IC pins (Pins 50, 53 and 54) which are used to connect external parts should be kept as small as possible in order to obtain the good PLL characteristics. In addition, resistor R3 should have a small temperature coefficient to reduce the temperature dependence of the VCO oscillation frequency. 50 R3 51 52 R1 53 54 R2 C1 R1: 200Ω R2: 200Ω R3: 4.7kΩ C1: 0.01µF Fig. 1. External Part Circuit and Recommended Constants – 17 – CXB1582Q 2. ECL input circuit The ECL differential input pins of the CXB1582Q are biased to VBB (Vcc – 1.3V) via an 18kΩ resistor in the IC. See the figures below for ECL differential input methods. VCC = 3.3V, VEE = GND VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 18kΩ 18kΩ 160Ω 3.3V ECL output buffer 160Ω ECL differential input buffer (a) ECL differential signal from 3.3V ECL output buffer VCC = GND, VEE = –4.5V 0.01µF VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 18kΩ 0.01µF 330Ω ECL100K output buffer 330Ω VEE 18kΩ ECL differential input buffer (b) ECL differential signal from ECL100K output buffer VCC = 3.3V, VEE = GND 0.01µF 18kΩ VBB (VCC – 1.3V) 50Ω TRANS. LINE 50Ω 50Ω 0.01µF 18kΩ VTT (VCC – 2V) ECL differential input buffer (c) ECL differential signal from 50Ω transmission line VCC = 3.3V, VEE = GND VBB (VCC – 1.3V) 0.01µF 50Ω TRANS. LINE 50Ω VTT (VCC – 2V) ECL differential input buffer 18kΩ 0.01µF 18kΩ (d) ECL single signal from 50Ω transmission line Fig. 2. ECL Input Circuits – 18 – CXB1582Q 3. Power supply Power can be supplied to the CXB1582Q by either a single 3.3V power supply or a dual 3.3V/5V power supply. When a TTL output high level of 2.2V is sufficient (for example, when only interfacing with a 3.3V CMOS), use a single 3.3V power supply. When a TTL output high level of greater than 2.2V is required (for example, when interfacing with a 5V TTL/CMOS), use a dual 3.3V/5V power supply. VCCT5 VCCT3 VCCE VCCG VCCP 3mH 3mH 3.3V 22µF 0.1µF 22µF 0.1µF 22µF 0.1µF VEET VEEE VEEG VEEP1 VEEP2 (a) Single 3.3V power supply VCCT5 VCCE VCCG VCCP 3mH 5.0V 22µF 0.1µF 3.3V 22µF 0.1µF 22µF 0.1µF VEET VEEE VEEG VEEP1 VEEP2 (b) Dual 3.3V/5V power supply Fig. 3. Power Supply Circuits – 19 – CXB1582Q 4. Power-on reset signal (POR∗) The CXB1582Q has a power-on reset signal output (POR∗). As shown in figure (a) below, this signal is output at low level for approximately 100ns after the power is turned on, after which it goes to high level and can be used as the system reset signal. The low level time Tpor can be adjusted by capacitance Crt connected to the RTCAP pin as shown in figure (b) below. Tpor conforms roughly to the following equation. Tpor = 90ns × (1 + Crt/10pf) POR∗ 71 POR∗ Output Tpor RTCAP 70 Crt Power ON (a) (b) Fig. 4. Power-on Reset Signal Setting – 20 – CXB1582Q Example of Representative Characteristics Jitter transfer (1.0625GHz operation) 5 R1 = R2 = 300Ω 0 R1 = R2 = 200Ω Jitter transfer [dB] –5 R1 = R2 = 100Ω –10 –15 C1 = 0.01µF, R3 = 4.7kΩ, Ta = 27°C Pattern: Fibre Channel Idle Pattern (Transition Density = 80%) –20 103 104 105 106 107 108 Modulation frequency [Hz] Bit sync time (1.0625GHz operation) 5000 C1 = 0.01µF, R1 = R2 = 200Ω, R3 = 4.7kΩ, Ta = 27°C SDIN: Fibre Channel Idle Pattern (1.0625Gbps) 4000 Bit sync time [ns] 3000 2000 1000 0 52 52.5 53 REFCLK [MHz] 53.5 54 – 21 – CXB1582Q Example of RJ measurement (recovery clock, 1.0625GHz operation) C1 = 0.01µF, R1 = R2 = 200Ω, R3 = 4.7kΩ, Ta = 27°C SDIN: Fibre Channel Idle Pattern (Transition Density = 80%) RJ = 9.5ps (RMS) [50ps/div] Eye pattern (retimed data, 1.0625GHz operation) [200mV/div] C1 = 0.01µF, R1 = R2 = 200Ω, R3 = 4.7kΩ, Ta = 27°C SDIN: Fibre Channel Idle Pattern (Transition Density = 80%) [200ps/div] – 22 – CXB1582Q Package Outline Unit: mm 80PIN QFP (PLASTIC) + 0.35 1.5 – 0.15 + 0.1 0.127 – 0.05 0.1 41 40 16.0 ± 0.4 + 0.4 14.0 – 0.1 60 61 80 1 0.65 20 21 + 0.15 0.1 – 0.1 ± 0.12 M 0° to 10° PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L03 LQFP080-P-1414 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 0.6g – 23 – 0.5 ± 0.2 + 0.15 0.3 – 0.1 (15.0)