CXB1828ER

CXB1828ER 2.5Gbps Laser Diode Driver Description The CXB1828ER is a high-speed monolithic laser diode driver. This IC can drive the data rate of 2.5Gbps and the modulation current of up to 50mA. The bias current of up to 50mA can be supplied and it is controlled by the built-in APC (automatic power control). The modulation current and bias current are designed to be linearly controlled by the voltage input to the control pin. This IC has a built-in DFF, and through mode or DFF mode can be selected. In through mode the signal goes as it is, and in DFF mode the input signal is retimed by the external clock. The data input pin and the clock input pin can accept the differential input of PECL and CML, and the 50Ω termination resistors are provided in the IC. The shutdown function which shuts down the modulation current and bias current, the activity error detect circuit which detects that the signal has no input, and the alarm output power-on reset circuit. Furthermore, the duty cycle control circuit which corrects the modulation output signal duty is included in this IC. The CXB1828ER employs the 4.8mm × 4 .8mm of 32-pin plastic package, contributing to the miniaturization of the optical mode. Features • Direct laser diode drive • Maximum data rate of 2.5Gbps • Power-on reset function • Automatic power control (APC) for bias current • Alarm function and shutdown function • Differential PECL and CML inputs or AC coupled input • Internal duty cycle correction circuit • Activity error detector function for laser safety • Typical rise time is 80ps. • Built-in 50Ω input termination resistor • Compact package size: 4.8mm × 4.8mm • Single +3.3V supply voltage Applications • Gigabit ethernet: 1.25Gbps • SONET/SDH: 622Mbps, 2.5Gbps 32 pin VQFN (Plastic) Absolute Maximum Ratings • Supply voltage Vcc – VEE –0.3 to +6.0 V • Data and clock input voltage difference |VD – VDN| 2.5 V • Bias output current 100 mA • Modulation output current 100 mA • Storage temperature Tstg –65 to +150 °C Recommended Operating Conditions • Supply voltage Vcc – VEE 3.14 to 3.46 • Operating ambient temperature Ta –40 to +85 Important Notes The IC requires SLOW turning power on and off. See Vcc rise and fall time in AC characteristics. Electrostatic Strength This IC has a very sensitive electrostatic strength, so care should be taken for handling. V °C Typical Transmit Block Diagram Transmit Path Sony CXB1828ER Laser Diode Sony SerDes Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E01Y22A2Z-PS CXB1828ER THRUMODE MOD_MON Vcc – 1.4V 10kΩ DIN 50Ω 50Ω DINB Vcc – 1.4V 10kΩ CKIN 50Ω 50Ω CKINB Activity Error Detector AED_CAP AED_DISABLE 1.8V WCVH WCVL High Vref Gen. Low 0.3V Vcc Voltage Error Det. Time Stretcher S Q 4kΩ R Q Vref 1.1V 50:1 kill Q D Q 50:1 kill 1 MUX 0 Duty Control BIAS_MON Block Diagram DUTY QB Q BIAS BIAS_SET OP_OUT TIME_CAP OP_IN to Modulation/Bias Control 15kΩ 60kΩ Vref Gen 1.9V SHUTDOWN SHUTDOWNB VREF ALARM MOD_SET AED_DISABLE Pin Assignment THRUMODE MOD_MON 24 23 22 21 20 19 18 17 DIN 25 DINB 26 VEE1 27 VCC1 28 CKIN 29 CKINB 30 WCVH 31 WCVL 32 1 VCC2 BIAS_MON TIME_CAP AED_CAP DUTY VEE2 16 VCCO 15 QB 14 Q 13 VEEO1 12 VEEO2 11 BIAS 10 OP_IN 9 2 SHUTDOWNB OP_OUT 3 SHUTDOWN 4 ALARM 5 RREF 6 VREF 7 MOD_SET 8 BIAS_SET –2– RREF CXB1828ER Pin Description Pin No. 1 Symbol Vcc2 Typical pin voltage (V) I/O DC 3.3 Equivalent circuit Description Positive power supply. 2 SHUTDOWNB 0 or Vcc I Vcc2 10kΩ 2 3 TTL input. The modulation current and bias current is shut down by inputting the Low voltage to this pin. High level when open. 10kΩ 3 SHUTDOWN 0 or Vcc I VEE2 TTL input. The modulation current and bias current is shut down by inputting the High voltage to this pin. High level when left open. Vcc2 4 ALARM O 4 TTL output. High when the abnomality is detected from the OP_IN pin voltage. The abnormal voltage of OP_IN is Vop < 0.3V or Vop > 1.8V. VEE2 Vcc2 5 5 RREF Connect an external resistor of 18kΩ between this pin and Vcc. VEE2 –3– CXB1828ER Pin No. Symbol Typical pin voltage (V) I/O DC Equivalent circuit Description Vcc2 6 VREF 1.9 O 26.4KΩ 6 Reference voltage output. GND reference 1.9V. VEE2 Vcc2 7 MOD_SET 0.2 to 2.0 I 7 8 Modulation current control. The modulation current is controlled by this pin voltage. 8 BIAS_SET 0.2 to 2.0 I VEE2 Vcc2 Bias current control. The bias current is controlled by the voltage of this pin. 150kΩ 4kΩ 9 9 OP_OUT O Internal operational amplifier output. Used for the bias current automatic power control (APC). The OP_OUT pin is connected to the BIAS_SET pin. Connect a 0.1µF capacitor between this pin and GND. VEE2 Vcc2 10 10 OP_IN 0.3 to 1.8 I The internal operational amplifier input for the bias current automatic power control (APC). VEE2 –4– CXB1828ER Pin No. Symbol Typical pin voltage (V) I/O DC Equivalent circuit Description VCC1 11 11 BIAS O Current Source VEEO2 Laser bias current output. 12 13 VEEO2 VEEO1 0 0 VCCO 14 Negative power supply for the modulation and bias output. Negative power supply for the modulation output. 14 Q O 15 Laser modulation current output. Open collector output. 15 QB O VEEO1 Current Source VEEO1 Complementary current output. Connect the laser diode not to this pin, but to the Q pin. Positive power supply for the modulation output. 16 VccO 3.3 VCC1 17 BIAS_MON O 17 18 Bias current monitor. 1/50 of the bias current flows to this pin. This pin is connected to Vcc either through a resistor 1kΩ or directly. Current Source 18 MOD_MON O VEE1 (MOD_MON) VEEO2 (BIAS_MON) Modulation current monitor. 1/50 of the modulation current flows to this pin. This pin is connected to Vcc either through a resistor 1kΩ or directly. –5– CXB1828ER Pin No. Symbol Typical pin voltage (V) I/O DC Equivalent circuit Description Vcc2 30pF 19 AED_CAP 19 500Ω Capacitor connection for the activity error detector. If the active detector function is not required, this pin can be left open. When a capacitor is connected between the AED_CAP pin and Vcc, the time till the error is detected can be extended. VEE2 Vcc2 20 TIME_CAP 20 500Ω 30pF Capacitor connection for the alarm power-on reset. The period of the power-on reset time is controlled by a capacitor (recommended value is 0.01µF) connected between the TIME_CAP pin and GND. If the ALARM function is not required, this pin can be left open. VEE2 Vcc2 10kΩ 21 10kΩ 21 AED_DISABLE I TTL input. This pin controls the activity error detector circuit. When High (open or connected to Vcc), the activity error detector function is disabled. When Low (connected to GND), the activity error detector function is enabled. VEE2 Vcc2 10kΩ 22 10kΩ 22 THRUMODE I TTL input. When High (open or connected to Vcc), the input data goes not through the D flip-flop. When Low (connected to GND), the serial input data goes through the D flip-flop within the chip. VEE2 –6– CXB1828ER Pin No. Symbol Typical pin voltage (V) I/O DC Equivalent circuit Description Vcc1 23 DUTY 300Ω 23 300Ω Resistor connection for the duty cycle control. When an external resistor is connected between the DUTY pin and GND, the modulation pulse width can be expanded. VEE1 24 VEE2 0 Vcc1 Negative power supply. 25 DIN PECL or CML 25 50Ω 50Ω 26 10kΩ I 26 DINB VEE1 Differential PECL and CML data inputs. These two inputs are internally connected by 100Ω and biased by 10kΩ to Vcc – 1.4V. 27 28 VEE1 Vcc1 0 3.3 Vcc1 Negative power supply. Positive power supply. 29 CKIN PECL or CML 29 50Ω 50Ω 30 10kΩ I Differential PECL and CML clock inputs. These two inputs are internally connected by 10kΩ and biased by 10kΩ to Vcc – 1.4V. 30 CKINB VEE1 Vcc2 31 WCVH 1.8 31 36kΩ VEE2 Window comparator's higher threshold voltage for ALARM. The default high alarm assert voltage for the comparator is 1.8V. –7– CXB1828ER Pin No. Symbol Typical pin voltage (V) I/O DC Equivalent circuit Description Vcc2 32 WCVL 0.3 31 8kΩ Window comparator's lower threshold voltage for ALARM. The default low alarm assert voltage for the comparator is 0.3V. 6kΩ VEE2 –8– CXB1828ER Electrical Characteristics DC Characteristics Item DC power supply voltage Supply current (DATA THRU MODE) Supply current (D-FF MODE) Maximum modulation output current Minimum modulation output current Modulation output voltage range Maximum bias output current Minimum bias output current Bias output voltage range Modulation shutdown current Bias shutdown current DIN, CKIN input High voltage (PECL) DIN, CKIN input Low voltage (PECL) DIN, CKIN differential input voltage (CML) Internal resistance between DIN and DINB, CKIN and CKINB Internal input reference voltage at DIN, DINB, CKIN, CKINB TTL input High voltage TTL input Low voltage TTL input current High TTL input current Low ALARM output High voltage ALARM output Low voltage VREF output voltage WCVH output voltage WCVL output voltage Vcc voltage error detect voltage Symbol VDC (Vcc – VEE = 3.14 to 3.46V, Ta = –40 to +85°C) Conditions Vcc – VEE Min. 3.14 Typ. 3.3 62 65 50 7 Vcc – 2 50 3 Vcc – 2 Vcc 100 100 ∗1 ∗1 ∗2 Vcc – 1.17 Vcc – 1.84 400 70 Vcc – 1.37 2.0 –0.3 –250 Iin = –0.4mA Iin = 2.0mA Iout = 0 to 500µA Open voltage Open voltage 2.4 0 1.80 1.70 0.28 2.59 Vcc 0.5 2.05 2.05 0.37 3.08 Vcc + 0.3 0.8 5 Vcc – 0.81 Vcc – 1.48 2000 130 Vcc Max. 3.46 84 88 Unit V mA mA mA mA V mA mA V µA µA V V mVp-p Ω V V V µA µA V V V V V V ICC_THRU IQ = 0mA, IB = 0mA ICC_DFF IQMAX IQMIN VQ IBMAX IBMIN VB IQSHD IBSHD VEIH VEIL VIN RDI, RCK VEIR VTIH VTIL ITIH ITIL VTOH VTOL VREF VWH VWL Vcc_err IQ = 0mA, IB = 0mA ∗1 Since the internal input reference voltage may become lower than the Low level of ECL, input the signal into DIN and CKIN by AC coupling at the time of a single phase input. –9– CXB1828ER ∗2 Min.: 200mV for each input Max.: 1000mV for each input VIN AC Characteristics Item Maximum data rate Maximum variable High pulse width by duty cycle control Rise time (20 to 80%) Fall time (80 to 20%) DIN – CKIN setup time DIN – CKIN hold time Vcc rise time Vcc fall time ∗3 DIN ts CKIN th (Vcc – VEE = 3.14 to 3.46V, Ta = –40 to +85°C) Symbol fdmax Conditions Min. 2.488 Data rate = 2.5Gbps IQ = 50mA, RL = 25Ω IQ = 50mA, RL = 25Ω Rise and fall time of input = 130ps∗3 Rise and fall time of input = 130ps∗3 10 to 90% 90 to 10% 30 50 5 5 100 80 90 Typ. Max. Unit Gbps ps ps ps ps ps ms ms tdelay tr tf ts th tvccr tvccf Setup time, Hold time DC/AC Characteristics for the APC Circuit Item OP_IN input voltage range OP_OUT output maximum voltage OP_OUT output minimum voltage Minimum OP_OUT output voltage at shutdown condition OP_IN input current OP_OUT output source current OP_OUT output sink current APC operational amplifier gain Monitor photodiode current range Symbol VI_OP VO_OPMAX VO_OPMIN VO_OPSDN II_OP IO_OPSORC IO_OPSINK AV IMPD (Vcc – VEE = 3.14 to 3.46V, Ta = –40 to +85°C) Conditions Min. Typ. Fig. 15 2.0 0.2 0.2 –2.0 1 4 4 12 10 1000 Max. Unit V V V V µA µA µA dB µA – 10 – CXB1828ER Functional Block Description APC (Automatic power control) The APC loop consists of the laser driver and APC operational amplifier. The APC operational amplifier is configured as an inverting integrator. It is the input voltage that is derived from the monitor current by the monitor photodiode and an external resistor RPD to OP_IN. The input voltage is inverted and the output from OP_OUT. The bias current is controlled by inputting the output to the BIAS_SET pin. The bias current is set by RPD. A capacitor CPD with a value of 1000pF works for stability and reduces the noise. Use CAPC (recommended value 0.1µF) between the OP_OUT pin and VEE. CAPC controls the rapid rise of the OP_OUT pin when the shutdown is cancelled, and suppresses the excess current flowing to the laser diode. CXB1828ER LD Modulation Current Q Bias Current BIAS OP_IN Vcc Monitor PD APC Operational Amplifier Vref_1.1V 15kΩ CPD 1000pF RPD 60kΩ 4kΩ OP_OUT CAPC 0.1µF CXB1828ER Fig.1. APC Function Block Diagram Alarm function This circuit is for the APC operation. When the input OP_IN is provided with an excess voltage or minimal voltage, the window comparator output goes High, and this signal is latched resulting in the output of alarm signal. The WCVH and WCVL pin voltages are the upper and the lower threshold values of the window comparator for ALARM. The default value of WCVH is 1.8V and that of WCVL is 0.3V. If the voltage of OP_IN is lower than WCVL or higher than WCVH, ALARM signal is asserted High. This alarm signal returns to Low only by the Vcc power-on reset function. Power-on reset time (TTIME) is set by the external capacitor put between the TIME_CAP pin and VEE. (Refer to Fig. 8.) It is necessary for the alarm signal output to be Low forcibly because the excess voltage or minimal voltage may be applied to the OP_IN pin till the APC operation completes. The recommended value of the capacitor is 0.01µF. SHUTDOWN/SHUTDOWNB Activity Error Detector Vcc Voltage Error Detector Monitor PD OP_IN OUT Modulation/Bias Current OFF SQ Time Stretcher R RS-FF IN ALARM Vcc < 2.9V Vcc Voltage Error Detector AED_DISABLE SHUTDOWN SHUTDOWNB Vcc > 2.9V Window Comparator 1.8V L L H RPD 0.3V Operational Amplifier for APC Modulation/Bias Current OFF APC Settling Alarm Reset TIME_CAP CTIME 0.01µF TTIME ALARM ENABLE Fig.2. Alarm Function Block Diagram – 11 – Fig.3. Timing Chart of Alarm Function CXB1828ER Data input The PECL/CML signal is input to the data buffer at a maximum data rate of 2.5Gbps. This input pin is biased by the reference bias voltage (Vcc – 1.4V) for the AC coupling input. An on-chip 100Ω resistor is put between the DIN and DINB pins. The data buffer has the frequency detector and input amplitude voltage detector for the Activity Error Detector (AED). Clock input The PECL/CML clock is input to the clock buffer at a maximum data rate of 2.5GHz. This input pin is biased by the reference bias voltage (Vcc – 1.4V) for the AC coupling input. An on-chip 100Ω resistor is put between the CKIN and CKINB pins. Signal duty cycle correction The output pulse width can be extended as shown in Fig.9 by connecting an external resistor between the DUTY pin and VEE, and setting its resistor value from 0Ω to 4kΩ. The output pulse width can be extended up to 100ps (min.). Short the DUTY pin to VEE when not want to vary the duty. 23 DUTY MOD_SET 0 to 4kΩ Fig.4. Duty Cycle Control Bias current and modulation current control The bias current and modulation current can be controlled linearly by the voltage input to the BIAS_SET and MOD_SET pins as shown in Figs.10 and 11. The voltage applied to the BIAS_SET and MOD_SET pins can be set by the external resistor between the VREF pin and VEE. Refer to Fig.5. BIAS_SET VREF 6 7 8 10kΩ 10kΩ RMOD RBIAS Fig.5. Modulation/Bias Control Bias current and modulation current monitor This circuit monitors the bias and modulation current. The BIAS_MON and the MOD_MON pins should be connected to VCC either directly or through a resistor. The modulation current and monitor current are in the rate of approximately 50:1. (Refer to Fig.12 and Fig.13.) Thru-mode When this pin is High or connected to Vcc, the input data goes not through the internal flip-flop. If this pin is grounded the input data goes through the D flip-flop. – 12 – CXB1828ER Shutdown function This circuit disables the output current, that is, the bias and modulation current is turned off and used to shut off the laser. And the voltage of OP_OUT is set to VEE. The function block diagram for all of the shutdown mechanism for the circuit is shown in Fig.6. The shutdown functions when one of the following conditions is met. 1) SHUTDOWN is High. 2) SHUTDOWNB is Low. 3) The activity error detector detects an error of the DIN/DINB input signal. 4) The voltage error detector detects Vcc is below 2.59 to 3.08V.∗ (∗ The bias current may flow at approximately Vcc = 2.0V.) Modulation/Bias Current OFF, The voltage of OP_OUT is set to VEE. SHUTDOWN SHUTDOWNB Input Buffer DIN/DINB Activity Error Detector Vcc Voltage Error Detector Time Stretcher Alarm Reset AED_CAP AED_DISABLE Fig.6. Shutdown Function Block Diagram Activity error detect function The activity error detect circuit monitors the DIN/DINB input signal, and shuts down the output current when this circuit determines that the input data signal has no input. The conditions where the input signal is determined to be no signal are when the input data signal logic is not varied over a period of the time set by the user and when the voltage swing is too small (< 100mVpp-diff). Either of these conditions is met, the shutdown circuit is enabled and the modulation current and laser bias current are shut down. If needed, the time till the activity error detect can be extended. Fig.14 shows the graphs of the activity error detection time (TAED) vs. CAED. When the activity error detect function is not required, connect the AED_DISABE pin to VCC or leave it the pin open. Signal Loss IN DIN/DINB AED_DISABLE L Active Error Detector TAED OUT Fig.7. Timing Chart of AED Function – 13 – TIME_CAP CXB1828ER DC Electrical Characteristics Measurement Circuit A 24 23 A 22 A 21 20 19 A 18 A 17 16 Vcc – 1.4V 10kΩ 25Ω 15 14 1 MUX 0 Duty Control 13 A 25 50Ω 50Ω A A 26 27 28 Vcc – 1.4V 10kΩ D Q 50:1 kill Q Activity Error Detector 12 A 29 50Ω 50Ω 11 A A 30 50:1 1.8V kill S Q V V 31 32 High Vref Gen. Low 0.3V Vcc Voltage Error Det. Time Stretcher R Q Vref 1.1V 10 15kΩ to Modulation/Bias Control A 60kΩ 4kΩ Vref Gen 1.9V 9 6 7 8 V 1 2 3 4 5 A A V 0.4mA or –2.0mA 18kΩ A V 0 to 500µA A A 3.3V – 14 – CXB1828ER AC Electrical Characteristics Measurement Circuit 0 to 4kΩ 24 23 22 21 20 19 18 17 16 51Ω 0.1µF 25 51Ω 0.1µF 26 27 Vcc – 1.4V 10kΩ 50Ω 50Ω 1 MUX 0 Duty Control 25Ω 15 14 51Ω 13 Z0 = 50Ω Oscilloscope 50Ω input 28 Vcc – 1.4V 51Ω 0.1µF 29 0.1µF 30 10kΩ 50Ω 50Ω D Q 50:1 kill Q 12 51Ω Activity Error Detector 11 50:1 1.8V 31 32 High Vref Gen. Low 0.3V Vcc Voltage Error Det. Time Stretcher S Q kill R Q Vref 1.1V 10 15kΩ to Modulation/Bias Control 60kΩ 4kΩ Vref Gen 1.9V 9 6 7 8 1 2 3 4 5 10kΩ 0 to 100kΩ 18kΩ 10kΩ 0 to 100kΩ Oscilloscope 3.3V – 15 – CXB1828ER Application Circuit RDUTY 0 to 4kΩ THRUMODE MOD_MON BIAS_MON DUTY Laser Diode Monitor Photodiode RQB Vcc – 1.4V 10kΩ DIN 50Ω 50Ω DINB Vcc – 1.4V 10kΩ CKIN 50Ω 50Ω CKINB Activity Error Detector Q BIAS D Q 50:1 kill Ferrite Bead 1 MUX 0 Duty Control RPD QB Q RQ CPD 1000pF Vcc CAED AED_CAP AED_DISABLE 1.8V WCVH WCVL High Vref Gen. Low 0.3V TIME_CAP CTIME 0.01µF SHUTDOWN SHUTDOWNB 50:1 kill S Q 4kΩ Vcc Voltage Error Det. Time Stretcher R Q Vref 1.1V 15kΩ 60kΩ Vref Gen 1.9V VREF RVREF 10kΩ OP_OUT OP_IN BIAS_SET CAPC 0.1µF to Modulation/Bias Control MOD_SET ALARM RMOD_SET Vcc 18kΩ RRREF Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 16 – RREF CXB1828ER Example of Representative Characteristics 60 Amount of increases in pulse width time [ps] 160 140 120 100 80 60 40 20 0 Ta = –40˚C Ta = +40˚C Ta = +85˚C 0 1 2 RDUTY [kΩ] 3 4 50 40 TTIME [ms] 30 20 10 0 0 0.02 0.04 0.06 0.08 0.10 CTIME [µF] Fig. 8. Power-on reset time (TTIME) vs. CTIME 90 80 70 Modulation current [mA] Fig. 9. Increment of output pulse width vs. RDUTY 80 70 60 Bias current [mA] 60 50 40 30 20 10 0 0 500 1000 1500 Ta = –40˚C Ta = +40˚C Ta = +85˚C 2000 2500 50 40 30 20 10 0 Ta = –40˚C Ta = +40˚C Ta = +85˚C 0 500 1000 1500 2000 2500 MOD_SET input voltage [mV] BIAS_SET input voltage [mV] Fig. 10. Modulation current vs. MOD_SET input voltage 80 70 Ratio of modulation current and modulation monitor current [mA] Fig. 11. Bias current vs. BIAS_SET input voltage Ratio of bias current and bias monitor current [mA] 80 70 60 50 40 30 20 10 0 Ta = –40˚C Ta = +40˚C Ta = +85˚C 0 500 1000 1500 2000 2500 60 50 40 30 20 10 0 Ta = –40˚C Ta = +40˚C Ta = +85˚C 0 500 1000 1500 2000 2500 MOD_SET input voltage [mV] BIAS_SET input voltage [mV] Fig. 12. Ratio of modulation current (IQ) and modulation monitor current vs. MOD_SET input voltage Fig. 13. Ratio of bias current (IB) and bias monitor current vs. BIAS_SET input voltage – 17 – CXB1828ER 100 90 TAED (AED error detection time) [µs] OP_OUT output voltage [V] 80 70 60 50 40 30 20 10 0 0 200 400 600 Ta = –40˚C Ta = +40˚C Ta = +85˚C 800 100 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 Ta = –40˚C Ta = +40˚C Ta = +85˚C Vcc = 3.3V 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OP_IN input voltage [V] CAED [pF] Fig. 14. Activity error detect time (TAED) vs. CAED Fig. 15. OP_OUT output voltage vs. OP_IN input voltage RL = 25Ω Ta = 25˚C IQ = 30mA Pattern = PRBS23 – 1 Data Rate = 2.5Gbps Time base: 100.0ps/div 250mV/div Fig. 16. Electrical Output Waveform 2 FP LD (λ = 1310nm) Ta = 25˚C Pattern = PRBS23 – 1 Data Rate = 2.5Gbps Filter Mask: OC-48 1 3 Time base: 100.0ps/div Fig. 17. Optical Output Waveform – 18 – CXB1828ER Foot Print Unit: mm 0. 15 0.8 2.3 0.6 ± 0.2 Via hole in PWB Package outline VEE in PWB VEE or solder resist in PWB 0.14 (This area is VEE in IC) 0.2 0.4 IC pin size Foot pattern recommended 4.8 39 0. – 19 – CXB1828ER Package Outline Unit: mm 32PIN VQFN (PLASTIC) 4.8 4.4 24 C 0.7 17 0.9 ± 0.1 0.05 S 2.3 0.6 ± 0.1 0. 3 4R 9) .3 (0 0.2 ± 0.01 0.23 ± 0.02 25 A 16 B PIN1 INDEX 32 9 0. 6 (0 .1 5) 4 5˚ 0.4 x4 0.1 S A-B C x4 0.1 S A-B C S 0.03 ± 0.03(∗1) (Stand Off) C 1 8 1.4 0.05 M S A-B C Solder Plating 0.13 ± 0.025 + 0.09 0.14 – 0.03 TERMINAL SECTION NOTE: 1) The dimensions of the terminal section apply to the ranges of 0.1mm and 0.25mm from the end of a terminal. 2) The dimension of ( ∗1) is apply to DiePad and the lead. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VQFN-32P-04 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.05g 32PIN VQFN (PLASTIC) 4.8 4.4 24 C 0.7 17 0.9 ± 0.1 0.05 S 2.3 0.6 ± 0.1 25 A 16 B PIN1 INDEX 4(0 .3 45˚ 32 9 R 0. 9) .1 5) 0.4 x4 0.1 S A-B C x4 0.1 S A-B C S C 1 8 0. 6 1.4 0.03 ± 0.03(∗1) (Stand Off) 0.05 M S A-B C Solder Plating 0.13 ± 0.025 + 0.09 0.14 – 0.03 TERMINAL SECTION NOTE: 1) The dimensions of the terminal section apply to the ranges of 0.1mm and 0.25mm from the end of a terminal. 2) The dimension of ( ∗1) is apply to DiePad and the lead. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE VQFN-32P-04 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING COPPER ALLOY 0.05g LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. COPPER ALLOY Sn-Bi Bi:1-4wt% 5-18µm 0.2 ± 0.01 0.23 ± 0.02 (0 3 – 20 – Sony Corporation