CXD1171M

CXD2302Q 8-bit 50MSPS Video A/D Converter with Clamp Function Description The CXD2302Q is an 8-bit CMOS A/D converter for video with synchronizing clamp function. The adoption of 2 step-parallel method achieves low power consumption and a maximum conversion rate of 50MSPS. Features • Resolution: 8 bit ± 1/2LSB (DL) • Maximum sampling frequency: 50MSPS • Low power consumption: 125mW (at 50MSPS typ.) (reference current excluded) • Synchronizing clamp function • Clamp ON/OFF function • Reference voltage self-bias circuit • Input CMOS/TTL compatible • 3-state TTL compatible output • Single 5V power supply or dual 5V/3.3V power supply • Low input capacitance: 15pF • Reference impedance: 370Ω (typ.) Applications Wide range of applications that require high-speed A/D conversion such as TV and VCR. Structure Silicon gate CMOS IC 32 pin QFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 7 V • Supply voltage VDD • Reference voltage VRT,VRB VDD + 0.5 to Vss – 0.5V • Input voltage VIN VDD + 0.5 to Vss – 0.5V (Analog) • Input voltage VI VDD + 0.5 to Vss – 0.5V (Digital) • Output voltage VO (Digital) • Storage temperature Tstg VDD + 0.5 to Vss – 0.5V –55 to +150 °C Recommended Operating Conditions • Supply voltage AVDD, AVss 4.75 to 5.25 V DVDD, DVss 3.0 to 5.5 V | DVss – AVss | 0 to 100 mV • Reference input voltage VRB 0 and above V VRT 2.7 and below V • Analog input VIN 1.7Vp-p above • Clock pulse width TPW1, TPW0 9ns (min) to 1.1µs (max) • Operating ambient temperature Topr –40 to +85 °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E94102E78-PS CXD2302Q Block Diagram DVss 28 OE 30 Reference supply DVss D0 (LSB) D1 D2 D3 D4 D5 D6 D7 (MSB) DVDD TEST (OPEN) 31 24 1 23 2 3 4 5 6 7 8 16 10 11 Clock generator AVDD Upper data latch Lower encoder (4 BIT) Lower sampling comparator (4 BIT) 20 19 18 17 AVDD AVDD VRT VRTS Lower data latch Lower encoder (4 BIT) Lower sampling comparator (4 BIT) 22 21 AVss AVss VIN VRB 25 VRBS Upper encoder (4 BIT) Upper sampling comparator (4 BIT) CLK 12 TEST (OPEN) 9 D-FF 15 14 13 29 CLE 27 CCP 26 VREF CLP NC NC NC 32 –2– CXD2302Q Pin Description Pin No. Symbol Equivalent circuit Description DVDD Di 1 to 8 D0 to D7 D0 (LSB) to D7 (MSB) output DVSS DVDD 9 TEST 9 Leave open for normal use. DVSS 10 11 DVDD TEST AVDD Digital power supply +5V or +3.3V Leave open for normal use. Pull-up resistor is built in. Input the clamp pulse. Clamps the signal voltage during Low interval. Pull-up resistor is built in. The clamp function is enabled when CLE = Low. The clamp function is set to off and the converter functions as a normal A/D converter when CLE = High. Pull-up resistor is built in. 15 CLP 11 15 29 29 CLE AVSS AVDD 12 CLK 12 Clock input. Set to Low level when no clock is input. AVSS 13, 14, 32 NC 16, 19, 20 AVDD Analog power supply +5V –3– CXD2302Q Pin No. 17 Symbol VRTS Equivalent circuit AVDD Description Generates approximately +2.5V when shorted with AVDD. 18 VRT 17 18 RT Rref RB 24 25 Reference voltage (top) 24 VRB Reference voltage (bottom) Generates approximately +0.6V when shorted with AVSS. 25 VRBS AVDD AVSS 21 VIN 21 Analog input AVSS 22, 23 AVSS AVDD Analog ground 26 VREF 26 Clamp reference voltage input. Clamps so that the reference voltage and the input signal during clamp interval are equal. AVSS AVDD 27 CCP 27 Integrates the clamp control voltage. The relationship between the changes in CCP voltage and in VIN voltage is positive phase. AVSS 28, 31 DVSS AVDD Digital ground 30 OE 30 Data is output when OE = Low. Pins D0 to D7 are at high impedance when OE = High. Pull-down resistor is built in. AVSS –4– CXD2302Q Digital output The following table shows the relationship between analog input voltage and digital output code. Input signal voltage VRT : : : : VRB Timing Chart I TPW1 TPW0 Step 0 : 127 128 : 255 Digital output code MSB LSB 11111 : 10000 01111 : 00000 111 000 111 000 Clock 1.3V Analog input N N+1 N+2 N–1 N+3 N N+4 N+1 Data output N–3 N–2 O: Analog signal sampling point Timing Chart I-1. tr 4ns tf 4ns 90% Clock 1.3V 10% 0V 3V Data output 0.7DVDD 0.3DVDD tpLH, tpHL Timing Chart I-2. tr = 4.5ns tf = 4.5ns 90% OE input 1.3V 10% tpLZ tpZL 0V VOH Output 1 10% tpHZ tpZH 90% Output 2 1.3V VOL VOH (≠ DVDD) 1.3V VOL (≠ DVSS) 3V Timing Chart I-3. –5– CXD2302Q Electrical Characteristics Analog characteristics Item Max. conversion rate Min. conversion rate Analog input band width Differential non-linearity error Integral non-linearity error Offset voltage∗1 Differential gain error Differential phase error Sampling delay (Fc = 50MHz, AVDD = 5V, DVDD = 3 to 5.5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C) Symbol Fc max. Fc min. BW ED EL EOT EOB DG DP Potential difference to VRT Potential difference to VRB NTSC 40 IRE mod ramp Fc =14.3MSPS –70 20 Conditions AVDD = 4.75 to 5.25V Ta = –40 to +85°C, VIN = 0.5 to 2.5V fIN = 1kHz triangular wave Envelope RIN = 33Ω End point –1dB –3dB Min. 50 Typ. 65 MSPS 0.5 60 100 ±0.3 +0.7 –50 40 3 1.5 0 VIN = DC VREF = 0.5V CIN = 10µF tpcw = 2.75µs Fc = 14.3MHz VREF = 2.5V Fclp = 15.75kHz FIN = 100kHz FIN = 500kHz Signal-to-noise ratio SNR FIN = 1MHz FIN = 3MHz FIN = 10MHz FIN = 25MHz FIN = 100kHz FIN = 500kHz Spurious free dynamic range FIN = 1MHz FSDR FIN = 3MHz FIN = 10MHz FIN = 25MHz 0 0 20 20 45 44 44 43 38 32 51 46 49 46 45 45 dB dB 40 mV 40 ±0.5 ±1.5 –30 60 % deg ns mV LSB MHz Max. Unit tsd Clamp offset voltage∗2 EOC ∗1 The offset voltage EOB is a potential difference between VRB and a point of position where the voltage drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”. EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to 1/2LSB of the voltage when the output data changes from “11111111” to “11111110”. ∗2 Clamp offset voltage varies individually. When using with R, G, B 3 channels, color sliding may be generated. –6– CXD2302Q DC characteristics Item Supply current (Fc = 50MHz, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C) Symbol IAD + IDD Conditions NTSC ramp wave input CLE = 0V DVDD = 5V DVDD = 3.3V 4.1 260 Shorts VRTS and AVDD Shorts VRBS and AVSS Fc = 50MHz 0.52 1.80 Min. Typ. 25 23 2 5.4 370 0.56 1.92 13 16 30 15 11 11 11 11 2.2 V 0.8 –240 –240 –40 240 40 240 –2 mA 4 –1.2 mA 2.4 –40 –40 40 µA 40 VOH = DVDD – 0.8V µA pF pF kΩ Max. 36 33 3 7.7 480 0.60 2.04 mA Ω V mA Unit Analog Digital IAD IDD IREF RREF VRB VRT – VRB Reference current Reference resistance (VRT – VRB) Self-bias voltage Analog input resistance RIN VIN Fc = 35MHz Fc = 20MHz CAI1 Input capacitance CAI2 CDIN Output capacitance CAO CDO Digital input voltage VIH VIL VIN, VIN = 1.5V + 0.07Vrms VRTS, VRT, VRB, VRBS, VREF TEST, CLK, CLP, CLE, OE CCP D0 to D7, TEST AVDD = 4.75 to 5.25V DVDD = 3 to 5.5V Ta = –40 to +85°C CLK Digital input current IIH IIL VI = 0V to AVDD TEST, OE Ta = –40 to +85°C CLP, CLE IOH IOL IOH Digital output current IOL IOZH IOZL OE = 0V DVDD = 5V VOH = DVDD – 0.8V Ta = –40 to +85°C VOL = 0.4V OE = 0V DVDD = 3.3V Ta = –40 to +85°C VOL = 0.4V VOH = DVDD OE = 3V DVDD = 3 to 5.5V Ta = –40 to +85°C VOL = 0V Note) The voltage of up to (AVDD + 0.5V) can be input when DVDD = 3.3V. But the output pin voltage is less than the DVDD voltage. When the digital output is in the high impedance mode, the IC may be damaged by applying the voltage which is more than the (DVDD + 0.5V) voltage to the digital output. –7– CXD2302Q Timing Item (Fc = 50MHz, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C) Symbol Conditions DVDD = 5V CL = 15pF OE = 0V DVDD = 3.3V 4.3 Min. 5.5 Typ. 9.5 8.5 11.8 7.6 RL = 1kΩ CL = 15pF OE = 3V → 0V DVDD = 5V 2.5 4.5 6.0 DVDD = 3.3V DVDD = 5V DVDD = 3.3V 3.0 3.5 2.5 1.75 7.0 5.0 RL = 1kΩ CL = 15pF OE = 0V → 3V 5.5 5.5 2.75 7.5 ns 8.0 3.75 µs 9.0 8.0 ns 16.3 Max. 12.0 ns Unit Output data delay Tri-state output enable time Tri-state output disable time Clamp pulse width∗ tpLH tpHL tpLH tpHL tpZH tpZL tpZH tpZL tpHZ tpLZ tpHZ tpLZ tCPW Fc = 14.3MHz, CIN = 10µF for NTSC wave ∗ The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75kHz for NTSC) for other processing systems to equal the values for NTSC. Electrical Characteristics Measurement Circuit Output data delay measurement circuit Tri-state output measurement circuit Measurement point To output pin Measurement point RL DVDD CL To output pin CL RL Note) CL includes capacitance of probes. –8– CXD2302Q Integral non-linearity error Differential non-linearity error Offset voltage +V } S2 S1 Analog input resistance test circuit test circuit +5V 2.5V VDD VRT S1: ON IF A < B S2: ON IF B > A VIN VRB CLK –V AB COMPARATOR A8 B8 to to A1 B1 A0 B0 0.5V GND 8 VIN 8 DUT CXD2302Q "0" CLK (50MHz) BUFFER DVM "1" 8 CONTROLLER 000 · · · 00 TO 111 · · · 10 Differential gain error Differential phase error } test circuit CX20202A-1 TTL ECL NTSC SIGNAL SOURCE 100 VIN AMP 40 IRE MODULATION BURST 0 SYNC 0.5V 2.5V CXD 2302Q 8 8 620 –5.2V 10bit D/A VECTOR SCOPE CLK D.G D.P. IAE –40 S.G. (CW) FC TTL ECL 620 –5.2V Digital output current test circuit 2.5V 0.5V VDD VRT D0 VIN to VRB D7 CLK OE GND VOL IOL 2.5V 0.5V + – VDD VRT VIN D0 to VRB D7 CLK OE GND VOH IOH + – –9– CXD2302Q Timing Chart II Vi (1) Vi (2) Vi (3) Vi (4) Analog input External clock (1) (2) (3) (4) Upper comparators block S (1) C (1) S (2) C (2) S (3) C (3) S (4) C (4) Upper data MD (0) MD (1) MD (2) MD (3) Lower reference voltage RV (0) RV (1) RV (2) RV (3) Lower comparators A block S (1) H (1) C (1) S (3) H (3) C (3) Lower data A LD (–1) LD (1) Lower comparators B block H (0) C (0) S (2) H (2) C (2) S (4) H (4) Lower data B LD (–2) LD (0) LD (2) Digital output Out (–2) Out (–1) Out (0) Out (1) Operation (See Block Diagram and Timing Chart II) 1. The CXD2302Q is a 2-step parallel system A/D converter featuring a 4-bit upper comparator block and 2 lower comparator blocks of 4-bit each. The reference voltage that is equal to the voltage between VRT – VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through the reference supply to the lower 4-bit comparator block. VRTS and VRBS pins serve for the self generation of VRT (Reference voltage top) and VRB (Reference voltage bottom), and they are also used as the sence pins as shown in the Application Circuit examples I-4 and I-5. – 10 – CXD2302Q 2. This IC uses an offset cancel type comparator which operates synchronously with an external clock. It features the following operating modes which are respectively indicated on the timing chart II with S, H, C symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode. 3. The operation of respective parts is as indicated in the Timing Chart II. For instance input voltage Vi (1) is sampled with the falling edge of the external clock (1) by means of the upper comparator block and the lower comparator A block. The upper comparator block finalizes comparison data MD (1) with the rising edge of the external clock (2). Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the upper results. The lower comparator A block finalizes comparison data LD (1) with the rising edge of the external clock (3). MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the external clock (4). Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output. Operation Notes 1. VDD, VSS To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass to the respective GND’s. 2. Analog input Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When driving with an amplifier of low output impedance, parasitic oscillation may occur. That may be prevented by insetting a resistance of about 33Ω in series between the amplifier output and A/D input. When the VIN signal of pin No. 21 is monitored, the kickback noise of clock is. However, this has no effect on the characteristics of A/D conversion. 3. Clock input The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. Reference input Voltage VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VDD and VRTS, VSS and VRBS respectively, the self-bias function that generates VRT=about 2.5V and VRB=about 0.6V, is activated. 5. Timing Analog input is sampled with the falling edge of CLK and output as digital data synchronized with a delay of 2.5 clocks and with the following rising edge. The delay from the clock rising edge to the data output is about 9ns (DVDD = 5V). 6. OE pin Pins 1 to 8 (D0 to D7) are in the output mode by leaving OE open or connecting it to DVSS, and they are in the high impedance mode by connecting it to DVDD. – 11 – CXD2302Q Application Circuit I. Single +5V Power Supply I-1. When clamp is used (self-bias used) +5V (Digital) ACO4 CLOCK IN CLAMP PULSE IN 0.01µ +5V (Analog) 17 18 19 VIDEO IN 10µ 33Ω 0.1µ 10p 20 21 22 23 24 +5V (Analog) 0.01µ 25 26 27 28 0.01µ GND (Digital) GND (Analog) 29 30 31 32 16 15 14 13 12 11 10 OPEN 9 8 7 6 5 4 3 2 1 D7 D6 D5 D4 D3 D2 D1 D0 0.1µ VREF 20K I-2. Digital clamp (self-bias used) +5V (Digital) ACO4 CLOCK IN OPEN 16 0.01µ +5V (Analog) 17 18 19 VIDEO IN 10µ 33Ω 0.1µ 10p 20 21 22 23 24 0.01µ 25 26 27 28 29 30 31 32 DAC · PWM · etc. ← Information other than that for clamp interval is at high impedance. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Subtracter · Comparator · etc. Clamp level setting data 0.1µ ∗ The relationship between the changes in CCP voltage (Pin 27) and in VIN voltage is positive phase. ∗ ∆Vin/∆Vccp = 3.0 (fs = 20MSPS) GND (Analog) GND (Digital) – 12 – CXD2302Q I-3. When clamp is not used (self-bias used) +5V (Digital) ACO4 CLOCK IN 16 0.01µ +5V (Analog) 17 18 19 VIDEO IN 20 33Ω 21 0.1µ 10p 22 23 24 0.01µ 25 26 27 28 29 30 31 32 15 14 13 12 11 10 OPEN 9 8 7 6 5 4 3 2 1 D7 D6 D5 D4 D3 D2 D1 D0 0.1µ GND (Digital) GND (Analog) I-4. When clamp is used (self-bias not used) +5V (Digital) ACO4 CLOCK IN CLAMP PULSE IN 17 VRT +5V (Analog) 0.01µ 18 19 VIDEO IN 20 10µ 33Ω 21 0.1µ 10p 0.01µ 24 VRB +5V (Analog) VREF 20K 25 26 27 28 0.01µ GND (Digital) GND (Analog) 29 30 31 32 1 D0 22 23 16 15 14 13 12 11 10 OPEN 9 8 7 6 5 4 3 2 D7 D6 D5 D4 D3 D2 D1 0.1µ – 13 – CXD2302Q I-5. When clamp is not used (self-bias not used) +5V (Digital) ACO4 CLOCK IN 16 17 VRT +5V (Analog) 19 VIDEO IN 20 33Ω 21 0.1µ 10p 0.01µ 24 VRB 25 26 27 28 29 30 31 32 1 D0 22 23 0.01µ 18 15 14 13 12 11 10 OPEN 9 8 7 6 5 4 3 2 D7 D6 D5 D4 D3 D2 D1 0.1µ GND (Digital) GND (Analog) II. Dual +5V/+3.3V Power Supply II-1. When clamp is used (self-bias used) +3.3V (Digital) ACO4 CLOCK IN CLAMP PULSE IN 0.01µ +5V (Analog) 17 18 19 VIDEO IN 10µ 33Ω 0.1µ 10p 20 21 22 23 24 +5V (Analog) 0.01µ 25 VREF 20K 26 27 28 0.01µ GND (Digital) GND (Analog) 29 30 31 32 16 15 14 13 12 11 10 OPEN 9 8 7 6 5 4 3 2 1 D7 D6 D5 D4 D3 D2 D1 D0 0.1µ – 14 – CXD2302Q Example of Representative Characteristics Ambient temperature vs. Supply current Supply current [mA] 26 Supply voltage vs. Supply current Supply current [mA] 27 Fc = 50MHz NTSC ramp wave input AVDD = DVDD = 5V 25 25 Fc = 50MHz NTSC ramp wave input AVDD = DVDD Ta = 25°C 4.75 5 Supply voltage [V] 5.25 24 23 –20 0 25 50 75 Ambient temperature [°C] Sampling frequency vs. Supply current Supply current [mA] Supply current [mA] 25 35 Input frequency vs. Supply current Fc = 50MHz Sine wave 1.9Vp-p AVDD = DVDD = 5V Ta = 25°C 20 NTSC ramp wave input AVDD = DVDD = 5V Ta = 25°C 10 20 30 40 50 30 15 25 0.01 0.1 1 10 25 Sampling frequency [MSPS] Input frequency [MHz] Ambient temperature vs. Maximum operating frequency Maximum operating rate [MSPS] Maximum operating rate [MSPS] Supply voltage vs. Maximum operating frequency Fc = 50MHz NTSC ramp wave input AVDD = DVDD 70 Fc = 50MHz fin = 1kHz, triangular wave input AVDD = DVDD = 5V 67 65 65 60 63 –20 0 25 50 75 4.75 5 Supply voltage [V] 5.25 Ambient temperature [°C] Ambient temperature vs. Sampling delay Sampling delay [ns] 1 Fc = 50MHz AVDD = DVDD = 5V 0 –1 Analog input band Fc = 50MHz Sine wave 1Vp-p input AVDD = DVDD = 5V Ta = 25°C 0 –1 Output level [dB] –3 –20 0 25 50 75 0.1 1 10 100 Ambient temperature [°C] Analog input frequency [MHz] – 15 – CXD2302Q Analog input frequency vs. SNR, effective bit 8 7 6 5 50 Fc = 50MHz AVDD = DVDD = 5V VIN = 2Vp-p Ta = 25°C 60 Analog input frequency vs. FSDR Fc = 50MHz AVDD = DVDD = 5V VIN = 2Vp-p Ta = 25°C Effective bit [bit] 40 FSDR [dB] SNR [dB] 50 40 30 30 0.01 0.1 1 10 0.01 0.1 1 10 Analog input frequency [MHz] Analog input frequency [MHz] Ambient temperature vs. Output data delay Output data delay [ns] Output data delay [ns] Fc = 10MHz AVDD = DVDD = 5V CL = 15pF tpLH Ambient temperature vs. Output data delay 12 10 8 tpHL 6 –20 0 12 10 8 6 tpLH Fc = 10MHz AVDD = 5V DVDD = 3.3V CL = 15pF tpHL –20 0 25 50 75 25 50 75 Ambient temperature [°C] Ambient temperature [°C] Load capacitance vs. Output data delay Output data delay [ns] Output data delay [ns] Fc = 10MHz AVDD = DVDD = 5V Ta = 25°C tpLH 14 12 Load capacitance vs. Output data delay 12 10 tpLH 10 8 tpHL 6 0 5 10 15 20 25 Fc = 10MHz AVDD = 5V DVDD = 3.3V Ta = 25°C tpHL 8 6 0 5 10 15 20 25 Load capacitance [pF] Load capacitance [pF] DVDD supply voltage vs. Output data delay Output data delay [ns] tpLH Fc = 10MHz AVDD = 5V CL = 15pF Ta = 25°C Analog input voltage vs. Input current Analog input current IAI [µA] 80 12 10 8 0 tpHL 6 3 3.5 4.5 5 5.5 –80 Fc = 50MHz AVDD = DVDD = 5V VRT = 2.5V VRB = 0.5V Ta = 25°C 0.5 1.5 Analog input voltage VIN [V] 2.5 DVDD supply voltage [V] – 16 – CXD2302Q 8-bit 50MSPS ADC and DAC Evaluation Board Evaluation boards are available for the high speed, low power consumption CMOS converters CXD2302Q (8-bit 50MHz A/D) and CXD1171M (8-bit 40MHz D/A). The evaluation boards are composed of a main board, CXD2302Q sub board and CXD1171M sub board. The each board is connected with sockets. An input interface, clock buffer and latches are mounted on the main board. The CXD2302Q and CXD1171M are mounted on each of the sub boards. Those ICs are mounted according to recommended print patterns designed to provide maximum performance to the A/D and D/A converters. Block Diagram V OUT ANALOG CIRCUIT MOUNT PORTION DAC SOCKET 8 V REF V IN ANALOG INPUT INTERFACE ADC SOCKET 8 4 CLOCK BUFFER DATA LATCH DIGITAL CIRCUIT MOUNT PORTION ANALOG CIRCUIT MOUNT PORTION OSC SW GND +5V –5V CLOCK OE SEL SYNC CLE Unnecessary at self bias use BLK Characteristics • Resolution • Maximum conversion rate • Digital input level • Supply voltage Supply voltage Item +5V –5V Clock input CMOS compatible Pulse width TCW1 TCW0 Min. 8bit 50MHz CMOS level ±5.0V (Single +5V power supply possible at self bias use) Typ. Max. 185 20 Unit mA 10ns (min) 10ns (min) – 17 – CXD2302Q Analog Output (CXD1171M) Item Analog output Min. 1.8 Typ. 2.0 (RL > 10kΩ) Max. 2.1 Unit V Output Format (CXD2302Q) The table shows the output format of AD Converter. Analog input voltage VRT : : : : VRB Step 0 : 127 128 : 255 Digital output code MSB LSB 111 100 011 000 11 : 00 11 : 00 1 0 1 0 1 0 1 0 1 0 1 0 Timing Chart Analog input External clock Tpw1 AD clock Tdc Tpw0 tPD (AD) AD output tDD Latch output DA input ts DA clock th DA output tPD (DA) Item Clock High time Clock Low time Clock Delay Data delay AD Data delay (latch) Settling time Hold time Data delay DA Symbol TPW1 TPW0 Tdc Min. 10 10 Typ. Max. Unit ns ns 24 9 17 5 10 10 ns ns ns ns ns ns tPD (AD) tDD tS th tPD (DA) – 18 – CMOS ADC/DAC Peripheral Circuit Board (Main Board) DVDD DVSS 13 NC NC 12 0.01µ CLK 9 8 7 6 5 4 3 2 1 0.01µ CLK 9 8 7 6 5 4 3 2 74S174 (LATCH) 16 0.01µ DVSS 8 9 10 11 12 DVDD 13 14 7 6 5 4 3 2 1 BLK OSC SWITCH EXT/INT R9 75 SYNC EXTERNAL CLOCK INPUT 1 CLEAR OSC out 8 DVDD 14 0.01µ 1 DVSS 7 10 14 13 CLK 12 DVDD 11 14 DVDD 15 D7 10 D6 9 D5 8 D4 7 D3 D2 5 D1 4 D0 3 6 13 12 11 SW1 15 CLP 16 NC SW2 18 VRT 19 20 AVDD 21 AVDD 22 VIN 23 AVSS 24 AVSS 25 SW3 27 VREF DVSS 2 28 CLE OE 1 26 VRB 17 NC DVSS CLEAR 74S174 (LATCH) 10 11 12 13 14 DVDD 16 15 DVSS DVSS 11 CLK 10 BLK 9 D7 8 D6 7 D5 6 D4 5 D3 4 D2 3 D1 2 D0 1 14 NC 15 AVSS R8 3.3k 17 IREF (16R) 18 VREF 19 AVDD R7 200 21 IO (R) 22 IO 23 NC 24 DVDD V out 20 AVDD 16 AVSS OUTPUT GAIN ADJUST VR4 20k C5 0.1 VRB ADJUST VRT ADJUST AVDD R4 510 VR1 2k VR2 2k Q1 Q2 R6 510 R5 510 74S04 OR 74HC04 (INV BUFFER) –5V +5V GND AVDD DVDD – 19 – 0.01 DVDD DVSS AVSS VIDEO INPUT AVDD C3 0.01 Q3 C2 R3 10µ 33 R1 100k C1 470µ R2 75 AVSS C4 0.01 CLAMP VOLTAGE ADJUST VR3 20k 47µ (RIN = 75Ω) SYNC INT OE SEL CLE 47µ VR5 20k R10 75 CXD2302Q CXD2302Q CMOS ADC/DAC Peripheral Circuit Board (Sub Board) CLP 15 NC 16 NC 17 18 VRT 19 AVDD 20 AVDD 21 VIN 22 AVSS 23 AVSS 24 VRB 25 26 VREF 27 CLE 28 C1 0.01µ C4 JB C5 C3 0.1µ 16 15 JT 17 18 19 20 CXD2302Q 21 22 23 24 25 26 27 28 29 30 31 32 4 3 2 1 C2 0.1µ 8 7 6 5 14 13 12 11 10 9 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CLK DVDD D7 D6 D5 D4 D3 D2 D1 D0 DVSS OE NC 13 NC 14 AVSS 15 AVSS 16 IREF 17 VREF 18 AVDD 19 AVDD 20 IO 21 IO 22 NC 23 DVDD 24 C3 C2 13 14 15 16 17 18 CXD1171M 19 20 21 22 23 24 12 11 10 9 8 7 6 5 4 3 2 1 C4 12 11 10 9 8 7 6 5 4 3 2 1 NC DVSS CLK BLK D7 D6 D5 D4 D3 D2 D1 D0 C1 – 20 – CXD2302Q List of Parts resistance R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 VR1 VR2 VR3 VR4 VR5 100K 75Ω 75Ω 510Ω 510Ω 510Ω R = 200 18R ≈ 3.3K 75Ω 75Ω 2K 2K 20K 20K 20K transistor Q1 2SC2785 Q2 2SC2785 Q3 2SC2785 IC IC1 IC2 IC3 oscillator OSC others connector BNC071 SW AT1D2M3 74S174 74S174 74S04 capacitance C1 470µF/6.3V (chemical) C2 10µF/16V (chemical) C3 0.01µF C4 0.01µF C5 0.1µF C6 0.1µF C7 0.1µF C8 0.1µF C9 0.1µF C10 0.1µF C11 47µF/10V (chemical) C12 47µF/10V (chemical) C13 47µF/10V (chemical) C14 0.1µF Adjustment 1. Vref adjustment (VR1, VR2) Adjustment of A/D converter reference voltage. VRB is adjusted through VR1 and VRT through VR2. When self bias is used, there is no need for adjustment. Reference voltage is set through self bias delivery. 2. Setting of clamp reference voltage (VR3) Clamp reference voltage is set. 3. DAC output full scale adjustment (VR4) Full scale voltage of D/A converter output is adjusted at the PCB shipment, the full scale voltage is adjusted to approx. 2V. 4. Sync (clamp) pulse interface (VR5) This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is performed to obtain a threshold of approx. 2.5V to an H sync of 0 to 5V. – 21 – CXD2302Q 5. OE, SEL, Sync, BLK, CLE, Sync INT The following pins are set on the main board: OE, Sync, CLE, Sync INT (CXD2302Q), BLK (CXD1171M) and SEL (not used). For the pins function, refer to the Pin Description. The difference between Sync pin and Sync INT pin is that a pulse above 3.5Vp-p should be input to Sync INT pin. The pulse threshold is set through VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case cut off the junction line between Sync and Sync INT pin. At the PCB shipment the main board pins are set as follows. • OE : Low (A/D output ON) • SEL : Low • Sync : Line junction Sync INT pin • CLE : Low (Clamp function ON) • BLK : Low (Blanking OFF) 6. Clamp pulse input method Directly input the clamp pulse as shown in Application Circuit example I-1. As SW1 is set to direct input at the PCB shipment, use it in this position. Points on the PCB Pattern Layout 1. Set the layout not to have Digital current flow into Analog GND (For 1, see p.24 “Component side diagram”.). 2. The C2 and C3 capacitors for the CXD2302Q sub board serve the important role of bringing out ICs full performance. Connect over 0.1µF (ceramic) capacitors with good high frequency characteristics as close to the IC as possible. 3. Analog GND (AVSS) and Digital GND (DVSS) are on a common voltage supply source. Keeping ADC’s DVSS (For 2, see p.24 “Component side diagram”.) as close to the voltage supply source as possible will provide better characteristics. That is, a layout where ADC is close to the voltage supply source, is recommended. 4. ADC samples analog signals at the clock falling edge. Accordingly it is important that clocks supplied to ADC do not have any jitter. 5. The PCB layout shows ADC and DAC’s Analog GND independently from the voltage supply source. The layout aims at providing an independent evaluation of ADC and DAC, as much as possible. On the actual board, common use will not cause any problems. – 22 – CXD2302Q Notes on Operation 1. Reference voltage Shorting AVDD and VRTS, AVSS and VRBS will activate the self-bias function that generates VRT = about 2.6V and VRB=about 0.5V. On the PCB, either self bias or the external reference voltage can be selected depending on the junction method of the jumper line. At shipment from the factory, reference voltage is provided in self bias. Also, to provide external reference voltage, adjust the dynamic range (VRT – VRB) to above 1.8Vp-p. 2. Clock input There are 2 modes for the PCB clock input 1) Provided from the external signal generator. (External clock) 2) Using the crystal oscillator (built-in clock driver). (Internal clock) The 2 modes are selected using the switch on the PCB. 3. The 2 Latch ICs (74S174) are not absolutely necessary for the evaluation of ADC and DAC. That is, operation will still be normal if ADC output data is directly input to DAC input. However, as ADC output data is hardly ever D/A converted without executing Digital signal processing, it was mounted to indicate an example layout of Digital signal processing IC. Use the Latch IC output when the ADC output data is used. 4. When clamp is not used Turning CLE to H will set OFF the clamp function. In this case, the DC element is cut off by means of C2 on the main board and DC voltage on the ADC side of C2 turns to about (VRT+VRB)/2. To transfer DC elements of input signals, short C2. At that time, it is necessary to bias input signals, but keeping R2 open, Q3 can also be used as buffer. Use the open space for the bias circuit. 5. Clamp pulse latch On the evaluation board, the clamp pulse is latched with ADC sampling CLK and then input to CLP pin. However, the latch is incorporated in CLP pin of the CXD2302Q, so that the external latch is not required. 6. Peripheral through hole There is a group of through holes on the Analog input, output and Logic. There are to be used when mounting additional circuits to the PCB. Use when necessary. The connector hole on DAC part is used to mount the test chassis mount jack. – 23 – CXD2302Q Silk Side Component Side Soldering Side (Diagram seen from the component side) – 24 – CXD2302Q Package Outline Unit: mm 32PIN QFP (PLASTIC) 9.0 ± 0.2 + 0.3 7.0 – 0.1 24 17 + 0.35 1.5 – 0.15 0.1 25 16 32 9 + 0.2 0.1 – 0.1 1 0.8 + 0.15 0.3 – 0.1 8 + 0.1 0.127 – 0.05 0° to 10° ± 0.12 M PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 ∗QFP032-P-0707-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g – 25 – 0.50 (8.0)