CXD1217M

CXD1217M Synchronizing Signal Generator for Video Camera Description The CXD1217M is a synchronizing signal generator for color video cameras. Features • Compatible with the respective systems, NTSC, PALM, PAL and SECAM • Output is synchronized with the clock of 910fH or 908fH • 25Hz offset processing by PAL system • Color framing by the respective systems, NTSC, PALM and PAL • Possible external synchronization by H reset, V reset and line alternate reset pins Applications Synchronizing signal generator for color video cameras Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 4.5 to 5.5 • Operating temperature Topr –20 to +75 28 pin SOP (Plastic) V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E89626A79-PS CXD1217M Block Diagram and Pin Configuration 4fscIN 10 1/4 PALM INT-NTSC 4fscOUT 9 1/9 CLOCK ELIMINATION 1/101 fH 2fH 1/81 1/2 PAL fH PAL 1/625, 1/525 PALM INTNTSC 19 OSC 1/7 VDD 28 fH 1/625 1/525 PAL PALM fv/2 PAL 1/4 VSS 14 fv/8 SC RESET PHASE COMPARISON 24 HCOMOUT TEST 16 CLIN 26 1/4 FIELD 1 RESET SC RESET CLOUT 25 1/454, 1/455 MODE1 21 MODE2 22 EXT 20 LALTRI 15 LINE ALTERNATE RESET HORIZONTAL RESET VERTICAL RESET DECODE 2fH fH 1/625, 1/525 1/2 2 5 7 OFLD1 OFLD OLALT OBF/COLB OBLK OSYNC OUTPUT F.F. COMPOSITE SIGNAL CONTROL F.F. 3 6 4 HRI 23 12 OVD 8 OHD VRI 1 27 OFH 17 O2FH Note) Pin 19 output is (a) a signal based on Pin 26 in INT mode at NTSC. (b) each signal is based on Pin 10 in other modes. –2– CXD1217M Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol VRI OFLD1 OBF/COLB OSYNC OFLD OBLK OLALT OHD 4fscOUT 4fscIN NC OVD NC VSS LALTRI TEST O2FH NC OSC EXT MODE1 MODE2 HRI HCOMOUT CLOUT CLIN OFH VDD I/O I O O O O O O O O I — O — — I I O — O I I I I O O I O — Sub carrier output Internal and external synchronizing modes switchover L: Internal synchronization H: External synchronization System selecting input 1 System selecting input 2 Horizontal reset input Phase comparator output Clock output Clock input Horizontal frequency output Power supply pin GND pin Line alternate reset input Test input 2fH output (Double the frequency of Pin 27) Vertical drive output Vertical reset signal First field output Burst flag/color blanking output Composite sync output Even and Odd output Composite blanking output Line alternate output Horizontal drive output 4fsc output 4fsc input Description –3– CXD1217M Electrical Characteristics DC characteristics Item Output voltage 1 Output voltage 2∗1 Output voltage 3∗2 Symbol VOH VOL VOH VOL VOH VOL Input voltage Input current∗3 (Pull-down pin) Output leak current∗1 Power current supply Feedback resistance∗4 ∗1 ∗2 ∗3 ∗4 VIH VIL IIH ILZ IDD RFB VIH = VDD At high impedance At output pin in no-load VDD = 5V 250k 20 50 ±30 8 2.5M Conditions IOH = –2mA IOL = 4mA IOH = –4mA IOL = 4mA IOH = –4mA IOL = 8mA 0.7VDD 0.3VDD 120 (VDD = 5V ± 10%, VSS = 0V, Topr = –20 to +75°C) Min. VDD – 0.5 VSS VDD – 0.5 VSS VDD/2 VDD/2 Typ. Max. VDD 0.4 VDD 0.4 Unit V V V V V V V V µA nA mA Ω HCOMOUT pin 4fscOUT and CLOUT pins LALTRI, TEST, EXT, MODE1 and MODE2 pins 4fscOUT, 4fscIN, CLOUT and CLIN pins (VDD = VI = 0V, fM = 1MHz) Symbol CIN COUT Conditions Min. — — Typ. — — Max. 9 11 Unit pF pF I/O capacitance Item Input pin Output pin –4– CXD1217M Description of Operation (See Block Diagram.) The CXD1217 is applicable to four systems; namely, NTSC, PAL, PALM and SECAM. In order to realize them, the following relative equations of Sub-carrier (4fsclN) and Clock (CLIN) are adopted . Sub carrier NTSC PAL PALM SECAM 4fsc = 910fH 4fsc = 1135fH + 2fv 4fsc = 909fH — Clock 910fH 908fH 910fH 908fH As it is obvious from the above equations, the 4fsc and clock frequency do not coincide with each other in the PAL and PALM. Therefore matching of the clock frequency is carried out by providing PLL. 1 . MODE specified input The CXD1217 provides four inputs to specify the respective modes. ∗ EXT input: Set this pin to VDD side, and it becomes into external synchronizing mode. At this time, the counters in connection with the PLL Ioop as shown in the upper part of the block diagram become into stand still state. ∗ MODE1 and MODE2 inputs: These are inputs for the system selection. MODE1 0 0 1 1 MODE2 0 1 0 1 System NTSC SECAM PALM PAL "0" → VSS "1" → VDD ∗ TEST input: An input to be used to measure IC. This input is normally kept opened. (Because it is dropped internally to Vss with MOS resistance.) 2. Reset operation The CXD1217 has three reset inputs ; namely, HRI, VRI, LALTRI, and it works to perform reset operation when it detects falling edge. These three inputs are so designed as to take in synchronization with the IC internal clock. Therefore, it is a prerequisite that both systems should have clock frequencies that are matched as a reset operation to each other (GEN Iocked). • H reset (HRI input) When the HRI input is continuous with H synchronization, resetting is activated with the initial falling edge, and for the subsequent edges they do not have to be reset unless they are deviated more than 2-bit (140ns) against the initial edge in the internal clock. That is, if the jitter of HRI input is less than 140ns, it is absorbed. The minimum resetting pulse width is over 0.3µs. The phase to be reset is the advanced point of 6.3 to 6.37µs (= 90 to 91-bit × 70ns) than the HRI input as shown in the diagram below. HRI input CXD1217 HD OUT output Reset 6.3 to 6.37 [µs] –5– CXD1217M • V reset (VRI input) When the VRI is input as shown in figure below, OSYNC can be reset at the same phase with the SYNC signal. Counter State 1 SYNC Signal Falling edge permitted span VRI CXD1217 internal clock (2fH) (See Timing Chart Diagram) V reset pulse 9 10 11 12 a Rising edge is to be behind from point a 2 3 4 5 6 7 8 9 10 11 12 13 14 15 After reset SYNC OUT 13 14 Reset State Since the falling edge point in the diagram above (marked with ↑) is the boundary of reset, if the falling edge of the VRI input traverses that point, it causes 1/2H deviation to the reset state. Accordingly, if resetting is applied between two similar systems whose frequency are different, the V to which resetting is applied generates jitter of 1/2H. (When the resetting is applied continuously.) • LALT reset (LALTRI input) Phase relation between LALTRI pulse polarity and 2fH is the same as in the case of V resetting. Resetting operation is basically required only in the external synchronizing mode (GEN LOCK mode). However, even in the internal synchronizing mode, it sometimes requires H and V outputs whose phases are deviated against a certain output. In that case, it suffices to use two CXD1217s and conduct the operation as follows: Clock VRI2 CXD1217 OHD1 OVD1 CXD1217 VRI2 OHD2 OVD2 Input Shift Reg. Clock Output Delay ∗ It suffices to set IC-1 and IC-2 into INT mode. By varying the Delay and Shift Reg. of the above diagram, any phases of OHD2 and OVD2 can be provided against the respective OHD1 and OVD1. 3. Color framing In the case of internal synchronization in the individual NTSC, PAL and PALM systems, the phase relationships between SYNC of the 1st field and sub-carrier are kept stable regardless of the power supply being ON or OFF. However, as the PAL and PALM systems are comprised of PLL, the absolute values concerning the phase according to variation of the ambient temperature drifts. –6– CXD1217M Timing Chart Output Timing Chart Diagram CXD1217 NTSC, PALM Field 1 ODD 2 EVEN SYNC OUT 3 ODD 4 EVEN 12H Field 1 BF/COLB OUT (PALM) 2 3 4 Field 1 LALT OUT (PALM) 2 3 4 10H BF/COLB OUT (NTSC) ODD EVEN ODD HD OUT EVEN 20H ODD BLK OUT EVEN 9H VD OUT ODD FLD OUT EVEN FLD1 OUT (fv/4) (NTSC) FLD1 OUT (fv/8) (PALM) CLIN (NTSC) 4fscIN (PALM) SC OUT 3H Field 1 3H Field 1 –7– CXD1217M CXD1217 PAL, SECAM Field 4 EVEN 1 ODD SYNC OUT 2 EVEN 3 ODD 10H Field 4 BF/COLB OUT (PAL) 1 2 3 Field 4 LALT OUT (PAL) 1 2 3 9H BF/COLB OUT (SECAM) 9H 8.5H 7H 9H 7H EVEN ODD EVEN HD OUT ODD 25H EVEN BLK OUT ODD 7.5H OVD EVEN FLD OUT ODD FLD1 OUT (fv/8) (PAL) FLD1 OUT (fv/4) (SECAM) 4fscIN (PAL) SC OUT 2.5H 2.5H –8– CXD1217 fH P96 N96 P315 N315 P169 N154 P66 N68 P32 N36 P78 N76 P420 N423 HD/CBLK fH P139 N140 HBLK HSYNC P22 N22 BF EQ P34 N32 P388 N387 P66 N68 P90 N90 P169 N169 P145 N145 H 1 H 2 P454 N455 P908 N910 –9– VSYNC H. R. 2fH (Internal clock) P140 N141 VD FLD P: PAL SECAM N: NTSC PALM Numerical figures show number of clocks FLD1 CXD1217M LALT CXD1217M Application Circuit Basic connection in individual systems Basic connection in individual systems at internal synchronization mode (EXT input = "0") is as follows. See waveform diagram for each output. • NTSC 14.318MHz ( = 910fH) VDD 19 OSC 26 25 CLOUT CLIN 28 VDD 14 VSS HRI 23 1 1/4 OLALT Synthesizer VRI OSYNC OBF/COLB OLALT O2FH 4fscIN 10 9 4fscOUT OHD OBLK 17 27 8 12 4 6 OFLD 5 OFH OVD OFLD1 2 10k 3 7 ∗ H/2 is output for LALT OUT even in NTSC mode. ∗ MODE1, MODE2, EXT, TEST and LALTRI pins can be kept open. (If noise annoys, connect to Vss by low impedance.) • PAL L. P. F OSC 19 4fsc IN 1/4 24 HCOMOUT 14.187MHz ( = 908fH) VCO VDD 10k 26 CLIN 25 CLOUT 14 VSS 28 VDD 21 22 MODE1 MODE2 10 Phase Comparison HRI f'H 4fsc OUT S. C. Reset 1/8 1/625 Clock Elimination 1/7 1/81 fH 23 1 Synthesizer 9 VRI OSYNC Field OBF/COLB 17.734MHz (4fsc) 1/2 OLALT OHD OFH 17 27 8 12 4 6 OFLD 5 OVD 3 7 ∗ Inverter of CLIN or CLOUT pins are usable as VCO. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – OFLD1 2 O2FH OBLK CXD1217M • PALM 14.318MHz ( = 910fH) L. P. F OSC 19 4fsc IN 1/4 Phase Comparison HRI 9 f'H 4fsc OUT S. C. Reset 1/9 1/101 fH Synthesizer VRI 23 1 24 HCOMOUT 26 CLIN 25 CLOUT 14 VSS 28 VDD VCO VDD 10k 21 MODE1 10 OSYNC OBF/COLB 14.302MHz (4fsc) 1/8 1/525 OLALT OHD 17 27 8 12 4 6 OFLD 5 10k HRI VRI OFH OVD Field 1 3 7 ∗ Internal inverter is usable as VCO. • SECAM 14.187MHz ( = 908fH) VDD 25 CLOUT 4fscIN 10 26 CLIN 14 VSS 28 VDD 22 MODE2 23 1 Synthesizer OSYNC OBF/COLB 9 OVD 17 27 8 12 4 6 3 7 5 OFLD1 OLALT O2FH OBLK OHD OFLD OFH 2 ∗ COLB is output to BF/COLB OUT pin. ∗ SDR and SDB are formed in PLL using 908fH. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 11 – OFLD1 2 O2FH OBLK CXD1217M Package Outline Unit: mm 28PIN SOP (PLASTIC) + 0.4 18.8 – 0.1 28 15 0.15 + 0.2 0.1 – 0.05 + 0.4 2.3 – 0.15 10.3 ± 0.4 + 0.3 7.6 – 0.1 9.3 1 0.45 ± 0.1 14 1.27 + 0.1 0.15 – 0.05 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE SOP-28P-L02 SOP028-P-0375 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.6g – 12 – 0.5 ± 0.2